A robot system based on high-speed LVDS networking and a control method thereof

Abstract

The application belongs to the field of communication networks, and specifically discloses a robot system based on high-speed LVDS networking and a control method thereof. Through the application, the LVDS interface "PCS layer" cache forwarding scheme can improve the signal quality of network communication between multiple joint drive cards, effectively ensuring the stability of the transmission data of a complex robot system; the high-speed LVDS networking communication mode effectively ensures high-bandwidth data transmission and reliable transmission, the differential signal interface mode improves the anti-interference ability and saves FPGA pin IO resources, greatly reduces the network deployment cost, and can effectively ensure the real-time performance and stability of the robot system network communication; each board card adopts an "FPGA+MCU" architecture, the FPGA is responsible for data analysis, transmission and motor drive control, and the MCU is responsible for FOC algorithm calculation, and the architecture can fully exert the respective advantages of the FPGA and the MCU.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of communication networks, and more particularly, relates to a robot system based on high-speed LVDS (Low-Voltage Differential Signaling) networking and a control method thereof. BACKGROUND

[0002] Robot system networking refers to connecting multiple robots and related devices (such as sensor, controller, and other sub-modules) through a communication network to realize data sharing, task cooperation, and centralized management among various sub-modules within the robot system. The traditional networking method of robot systems can be divided into wired communication networks and wireless communication networks. With the development of industrial automation and intelligent manufacturing, the complexity and scale of robot systems are continuously expanding, and the traditional communication methods are difficult to meet the needs of modern robot systems in terms of data transmission rate, anti-interference ability, security, and real-time performance.

[0003] Wired communication networks include Ethernet, RS485, CAN bus, and the like. Ethernet network communication has the advantages of high-bandwidth data transmission, good data stability, long-distance transmission, and the like. The physical interface of Ethernet communication generally uses RJ45 interface and SFP optical module interface to connect sub-devices to realize the networking communication of robot systems. However, the sub-modules of micro robots are generally embedded in the same device, and a networking method suitable for ultra-short distance transmission is required. RS485 asynchronous serial port communication supports multi-node communication, low cost, and easy implementation. However, its data transmission rate is low, and it is only suitable for simple control commands and small amount of data transmission. CAN bus network communication has the advantages of high reliability, real-time performance, support for efficient transmission between multiple nodes, strong anti-electromagnetic interference ability, and the like, and has been widely applied in automobiles and industrial environments. However, the software development cost of CAN bus is high, and the maintenance cost is high, which is not suitable for robot system networking applications.

[0004] Wireless communication networks include: WI-FI network, Bluetooth technology, 5G technology and other communication networks. The WI-FI network has the advantages of wireless connection, high-speed data transmission, extensive signal coverage, support for multi-device connection, easy deployment and the like; but its defects are also quite obvious, such as poor anti-electromagnetic interference ability, limited network capacity, high power consumption and the like, which leads to the fact that WIFI communication mode cannot be used for precise motion control module of robot system. Bluetooth technology has the advantages of low power consumption, short-range wireless communication, high security, stable data transmission and the like; but it has the defects of limited coverage, weak signal penetration, compatibility problems, high initial development cost, low data transmission rate and the like, so it is not suitable for the design of robot system networking. The 5G network communication technology has high-speed data transmission (the theoretical peak of 5G transmission can reach the order of Gbps), low latency, high capacity (supports millions of device connections per square kilometer); but its most obvious disadvantage is its high deployment cost, and its limited coverage, signal attenuation problems and security challenges also limit its popularity and application in robot system networking design. SUMMARY

[0005] In view of the defects of the prior art, the purpose of the present application is to provide a robot system based on high-speed LVDS networking and a control method thereof, aiming to solve the problem that the existing communication mode is difficult to meet the needs of robot system in terms of data transmission rate, anti-interference ability, security and real-time performance.

[0006] To achieve the above-mentioned purpose, in a first aspect, the present application provides an LVDS networking analysis and forwarding control module, comprising: a pcs_rx submodule, an elastic buffer submodule, a pcs_tx submodule and a mac_rx submodule.

[0007] The pcs_rx submodule is used to convert the input LVDS signal from physical layer serial data to transmission layer parallel data, and simultaneously perform CRC check operation on the data code, and write the transmission layer parallel data with successful CRC check into the elastic buffer submodule and output to the mac_rx submodule;

[0008] The elastic buffer submodule located between the pcs_rx submodule and the pcs_tx submodule is used to buffer the transmission layer parallel data written by the pcs_rx submodule;

[0009] The pcs_tx submodule is used to read out the transmission layer parallel data in the elastic buffer submodule, simultaneously perform CRC check, convert the transmission layer parallel data with successful CRC check into physical layer serial data, and send it to the LVDS output interface after packaging;

[0010] the mac_rx submodule is used for converting the physical layer serial data output by the pcs_rx submodule into user data of the current drive board card and user data of other drive board cards, if the current drive board card responds to the control instruction of the host computer, the user data of the current drive board card is first sent to the MCU, then the calculation result fed back by the MCU is received and output to the motion control module, and then the user data processed by the motion control module is received and transmitted to the pcs_tx submodule together with the user data of other drive board cards; if the current drive board card does not respond to the control instruction of the host computer, all the user data is transparently transmitted to the pcs_tx submodule.

[0011] Preferably, the elastic cache submodule realizes data writing / reading in the following way:

[0012] If the writing data clock frequency is lower than the reading data clock frequency, and the number of data cached in the module is lower than the read empty threshold, after inserting the character code at the writing port, the data code parsed out by the pcs_rx submodule is written through the writing port, otherwise, the data code parsed out by the pcs_rx submodule is directly written through the writing port;

[0013] If the reading data clock frequency is lower than the writing data clock frequency, and the number of data cached in the module is higher than the write full threshold, after deleting the character code at the reading port, the data cached in the module is read out from the reading port, otherwise, no additional processing is performed, and the data cached in the module is directly read out from the reading port;

[0014] The write full threshold is greater than the read empty threshold, and the sum of the two is equal to the storage capacity of the elastic cache submodule, and the character code has uniqueness.

[0015] Preferably, the pcs_rx submodule realizes its function in the following way: the LVDS serial differential input signal is obtained from the LVDS input interface; the input LVDS signal is filtered to filter out the glitch signal generated by hardware; the filtered LVDS serial signal is sampled at the double edges of the system clock, and the shift register is used to generate the parallel data of the MII interface with half-byte bit width; the parallel data of the MII interface with half-byte bit width is converted into the transmission layer parallel data with one-byte bit width in the FPGA internal general-purpose; the preamble and delimiter in the transmission layer parallel data with one-byte bit width are deleted; the processed Ethernet frame in the transmission layer format is subjected to CRC check, if the CRC check passes, the transmission layer parallel data is synchronously written into the elastic cache submodule and output to the mac_rx submodule, otherwise, the transmission is interrupted, and a check error alarm is issued.

[0016] Preferably, the mac_rx submodule realizes its functions by the following ways: (1) receiving the physical layer serial data output by the pcs_rx submodule, detecting whether the CRC check field, message length field and message board ID field are correct, if there is any error, discarding the message, and reporting the relevant error state information to the upper layer; otherwise, entering (2); (2) deleting the redundant information in the original message, only keeping the valid data field, the redundant information including the Ethernet source address, destination address and Ethernet type, and the valid data field including motor control instruction, control parameter and calculation data; (3) matching whether the motor control instruction of the valid data field is related to the current drive board card, if related, sending the user data of the current drive board card to the MCU, receiving the calculation result feedback by the MCU and outputting to the motion control module, so that the motion control module transmits the user data processed by the current drive board card and the user data of other drive board cards to the pcs_tx submodule; if not related, directly transmitting all the user data to the pcs_tx submodule.

[0017] In a second aspect, the application provides a robot system based on high-speed LVDS networking, comprising: a CPU master chip, one motor drive board card and one information acquisition board card;

[0018] The first motor drive board card communicates with the CPU master chip through an Ethernet interface;

[0019] One motor drive board card and one information acquisition board card adopt linear connection mode of LVDS interface.

[0020] Each motor drive board card comprises a first FPGA and an MCU, the first FPGA comprising a motion control module and an LVDS networking analysis and forwarding control module as described in the first aspect;

[0021] The information acquisition board card comprises a second FPGA and an MCU, the second FPGA comprising an information acquisition module and an LVDS networking analysis and forwarding control module as described in the first aspect.

[0022] Preferably, the information acquisition board card is used to realize analysis and reporting of data collected by various sensors, according to different sensor interfaces to analyze relevant data, package the data and upload to the Nth motor drive board card through the LVDS structure; the A motor drive board is used to realize driving control of relevant motors according to the control instruction of the CPU master chip and the motor control data transmitted by the MCU module; the collection data message is uploaded level by level until uploaded to the CPU master chip, and the relevant MCU state data is collected before uploading; the CPU master chip is used to make corresponding processing according to the uploaded collection data, MCU state data and control instruction of the upper computer.

[0023] In a third aspect, the application provides a control method of the robot system based on the high-speed LVDS networking of the second aspect, comprising:

[0024] Step 1: complete initialization according to the control instruction of the upper computer;

[0025] Step 2: the information collection module in the information collection board card acquires data of each sensor, and after the MCU completes signal processing work, the processing result is forwarded to the second FPGA, the second FPGA analyzes and forwards the control module through the LVDS networking, and the collected various sensor data is packaged and uploaded to the Nth motor drive board card;

[0026] Step 3: the Nth motor drive board card receives the data uploaded by the lower level through the LVDS interface, and the first FPGA analyzes the motor encoder data, and the data uploaded by the lower level, the motor encoder data and the MCU state data are packaged and uploaded to the upper level through the LVDS networking analysis and forwarding control module, ;

[0027] Step 4: the CPU master chip processes the data uploaded by the first motor drive board card, and after completing data calculation, the calculation result is uploaded to the upper computer through Ethernet, so that after the upper computer receives the calculation result, the corresponding control command is sent to each motor drive board card;

[0028] Step 5: after each motor drive board card receives the control instruction transmitted by the upper computer, the MCU is responsible for FOC algorithm processing of the motor, and the processed data is forwarded to the motion control module through the LVDS networking analysis and forwarding control module, and the motion control module realizes driving of the motor according to the upper computer instruction and MCU calculation data, and the LVDS networking analysis and forwarding control module transmits the upper computer control instruction to the lower level to realize control of the whole robot system.

[0029] Preferably, the control process in the motor drive board card is as follows:

[0030] Step 1: after the LVDS input signal enters the motor drive board card, the pcs_rx submodule converts the high-speed serial LVDS signal into parallel data of the Ethernet frame, and converts the data format into the general data format in the FPGA and sends it to the pcs_rx output port; ​

[0031] Step 2: The data outputted by the pcs_rx submodule is sent to the elastic buffer submodule, and the parallel data read from the transmission layer in the elastic buffer submodule is converted into high-speed LVDS serial signals by the pcs_tx submodule, and then outputted to the lower-level motor drive board card;

[0032] Step 3: The data outputted by the pcs_rx submodule is sent to the mac_rx submodule, and the upper-level data is distributed to the motion control module and MCU for further processing according to the different command sub-packets of the Ethernet frame;

[0033] Step 4: The MCU performs FOC algorithm calculation according to the control parameters issued by the upper computer and the motor encoder data collected by the motor drive board card, and returns the calculation results to the first FPGA; the motion control module in the first FPGA realizes motor drive control according to the control instructions of the upper computer and the calculation results of the MCU.

[0034] Preferably, time synchronization processing of the board cards at each level is performed before data communication: the transmission delay value between the board cards at each level and the CPU master control chip is measured, and the delay data is written into the original message and fed back to the upper level; taking the board card with the largest delay value as the reference, the waiting time required for the response of each board card is calculated; after receiving the control instructions of the CPU master control chip, each board card delays the corresponding waiting time.

[0035] In a fourth aspect, the present application provides a computer readable storage medium, comprising instructions, when the instructions run on an electronic device, make the electronic device execute the control method of the third aspect.

[0036] It can be understood that the beneficial effects of the third aspect to the fourth aspect described above can be referred to the related description in the second aspect, which will not be repeated here.

[0037] Overall, compared with the prior art, the above technical solutions conceived by the present application have the following beneficial effects:

[0038] (1) The present application provides a LVDS networking analysis and forwarding control module, which embeds an elastic buffer submodule between the pcs_rx submodule and the pcs_tx submodule. The input LVDS signal is analyzed by the pcs_rx submodule, cached once by the elastic buffer submodule, packaged by the pcs_tx submodule, and then outputted to the LVDS interface. The internal processing mechanism of the elastic buffer prevents data loss and improves the stability of LVDS serial data.

[0039] (2) The application provides a robot system based on high-speed LVDS networking. First, the LVDS interface "PCS layer" cache forwarding scheme can improve the signal quality of network communication between multiple joint drive cards, effectively ensuring the stability of the transmission data of a complex robot system. Second, the high-speed LVDS networking communication mode effectively ensures high-bandwidth data transmission and reliable transmission, and the differential signal interface mode improves the anti-interference ability and saves FPGA pin IO resources, greatly reduces the network deployment cost, and can effectively ensure the real-time performance and stability of the robot system network communication. Third, each board card adopts an "FPGA + MCU" architecture, the FPGA is responsible for data analysis, transmission and motor drive control, and the MCU is responsible for FOC algorithm calculation. This architecture can fully utilize the advantages of FPGA and MCU, that is, the flexible programmable characteristics of FPGA can realize the adaptation of various network protocol interfaces, and the MCU can realize complex motion control algorithms to make up for the lack of FPGA computing resources. BRIEF DESCRIPTION OF DRAWINGS

[0040] Figure 1 is a structural schematic diagram of a robot system based on high-speed LVDS networking provided by an embodiment of the application.

[0041] Figure 2 is a control method flowchart of a robot system based on high-speed LVDS networking provided by an embodiment of the application.

[0042] Figure 3 is one of structural schematic diagrams of an LVDS networking analysis forwarding control module provided by an embodiment of the application.

[0043] Figure 4 is another structural schematic diagram of an LVDS networking analysis forwarding control module provided by an embodiment of the application. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical scheme and advantages of the application clearer, the application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the application and not to limit the application.

[0045] In the application, the term "and / or" is used to describe the association relationship between the associated objects, which means that there can be three relationships, for example, A and / or B, which means that there are three cases of A alone, A and B together, and B alone. In the application, the symbol " / " represents the relationship of or, for example, A / B represents A or B.

[0046] The terms "first" and "second" and the like in the present application are used to distinguish different objects, rather than to describe a specific order of the objects. For example, the first response message and the second response message are used to distinguish different response messages, rather than to describe a specific order of the response messages.

[0047] The term "electrical connection" in the present application can be direct circuit connection or signal transmission through a communication protocol.

[0048] In the embodiments of the present application, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration, in any non-limiting and non-exhaustive sense. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or advantageous than other embodiments or design solutions. Rather, the use of terms such as "exemplary" or "for example" is merely intended to present concepts in a concrete manner.

[0049] In the description of the embodiments of the present application, unless otherwise specified, "a plurality of" means two or more, for example, a plurality of processing units means two or more processing units, and the like; a plurality of elements means two or more elements, and the like.

[0050] The embodiments of the present application will be described below in conjunction with the accompanying drawings in the embodiments of the present application.

[0051] As shown in Figure 1 The present application proposes a robot system based on high-speed LVDS networking, which mainly comprises a CPU master chip, N motor drive board cards (containing a motion control module), and an information acquisition board card.

[0052] The communication between the CPU master chip and the first electrode drive board card is completed through an Ethernet interface, and the communication between the board cards adopts a high-speed LVDS interface, specifically, a linear connection mode of the high-speed LVDS interface. The rate of the LVDS interface is 100 Mbps, which can effectively ensure the rapid and stable transmission of data between the robot systems, and greatly save the pin resources of each module chip.

[0053] Each board card adopts an "FPGA + MCU" architecture, the FPGA is responsible for the driving control of the motor and the networking data transceiving control, and the MCU is responsible for the implementation of the motor driving algorithm; the communication between the FPGA and the MCU adopts a user-defined parallel bus. Since the expansion interface of the FPGA is rich, and the encoding and decoding of the LVDS interface signal are implemented at the FPGA end, the data forwarding delay can be effectively reduced, and the real-time performance of the current board card for the data transmission of the upper and lower modules can be ensured.

[0054] The network communication protocol of the robot system adopts an Ethernet data standard, and the data format of each module uniformly adopts an Ethernet data frame.

[0055] According to different application scenarios, different motor drive board cards can be responsible for the movement, lifting, rotation and other functions of different parts of the robot. Specifically, the motion control module in the motor drive board realizes the driving control of the related motor according to the control instruction of the CPU main control chip and the motor control data transmitted by the MCU.

[0056] The information acquisition board card is used for analyzing and reporting the data collected by various sensors, analyzing the relevant data according to different sensor interfaces, and finally packaging the data and uploading it to the upper module through the LVDS structure. The collected data messages are uploaded level by level (after passing through each level of board card, the relevant state data will be collected), and finally uploaded to the CPU main control chip.

[0057] The CPU main control chip is used to make corresponding processing according to the reported collection data, state data and control instruction of the upper computer, and complex algorithms are generally completed by the CPU main control chip, such as image processing algorithms.

[0058] As shown in Figure 2 The present application proposes a control method of a robot system based on high-speed LVDS networking, and the specific steps are as follows:

[0059] Step 1: The upper computer sends initialization instructions to the CPU main control chip and each module to complete the initialization operation of the robot system.

[0060] Step 2: The information acquisition board card acquires the data collected by each sensor, and the MCU part will be responsible for completing some signal processing work (voice recognition) and then forwarding to the FPGA. Finally, the FPGA transmits the control module through the LVDS networking analysis, and uploads the collected various sensor data to the upper level.

[0061] Step 3: The motor drive board card receives the data uploaded by the next level through high-speed LVDS, and the FPGA will analyze and acquire the motor encoder data. Finally, the data uploaded by the next level, the motor encoder data and the MCU state data are packaged and uploaded to the upper level through the LVDS networking analysis and forwarding control module.

[0062] Step 4: The CPU main control chip is responsible for processing the sensor collection data and board card state data uploaded by the next level, and at the same time processes these reported data through corresponding algorithms. Finally, the results of the algorithm processing are uploaded to the upper computer through the gigabit Ethernet.

[0063] Step 5: After the upper computer receives the results calculated by the CPU main control chip, it sends corresponding control commands to different board cards. The control command is referenced to the standard Ethernet frame, and the internal data format (motion control data, sensor collection data, board card state data) can be defined by the user.

[0064] Step 6: After receiving the control instructions transmitted by the host computer, the MCU is responsible for the FOC algorithm processing of the motor and transmits the processed data to the motion control module through the LVDS network analysis forwarding control module. The motion control module drives the motor according to the host computer instructions and MCU calculation data, and the LVDS network analysis forwarding control module transmits the host computer control instructions to the next level to realize the control of the entire robot system.

[0065] FOC algorithm (Field-Oriented Control, magnetic field oriented control) is an advanced motor control technology, mainly used for the control of alternating current motor (such as permanent magnet synchronous motor and asynchronous motor). Its core idea is to control the magnetic field direction of the motor to realize the accurate control of the motor torque and speed. Its working principle is as follows: FOC algorithm decomposes the stator current of the motor into two perpendicular components: one is the excitation current (d-axis current), which is used to generate magnetic field; the other is the torque current (q-axis current), which is used to generate torque. Through coordinate transformation (such as Clarke transformation and Park transformation), three-phase alternating current is converted into two-phase direct current, realizing decoupling control of current. In this way, excitation current and torque current can be controlled independently, so as to realize accurate control of the motor.

[0066] According to the design architecture diagram of the robot system, the complexity of the robot system is related to the number of motor drive board cards. The more the number of motor drive board cards, the more complex the robot system, and the stability of LVDS interface signal will decrease. Therefore, the design of LVDS network analysis forwarding control module in FPGA is very important, which relates to the communication quality of high-speed LVDS network. The present application designs two kinds of LVDS network analysis forwarding control schemes for different number of motor drive board cards.

[0067] The first LVDS network analysis forwarding control scheme

[0068] As shown in Figure 3 , when the number of motor drive board cards required by the robot system is small (2-5), LVDS point-to-point "wired" direct forwarding is adopted. The idea of this forwarding control scheme is: the LVDS input interface is directly connected with the output interface, and the high-speed data transmitted to the lower level or reported to the upper level does not need to pass through the PCS layer, which can reduce the delay time of communication between the upper and lower modules. The biggest advantage of this method is that it can achieve almost zero delay. The specific steps are as follows:

[0069] Step 1: The LVDS signal of the upper module is directly transmitted to the lower module through FPGA logic primitive IBUFDS without any analysis processing, which ensures that the data is transmitted to the lower module through high-speed LVDS interface without delay.

[0070] Step 2: The current motor drive board card replicates the LVDS signal of the transparent transmission, carries out the double-edge sampling of the FPGA logic primitive IDDR module, so as to ensure the input signal quality, and then further parses the received LVDS signal through pcs_rx and mac_rx.

[0071] Step 3: The data parsed through the mac_rx is in the data format processed by the user terminal, the data parsed through the mac_rx is distributed to the motion control module and the MCU in the FPGA according to the user-defined message data format in the Ethernet frame.

[0072] The second LVDS networking parsing and forwarding control scheme

[0073] When there are many motor drive board cards in the robot system, scheme one can ensure zero delay in transmission between systems, but the scheme has a signal attenuation problem, and the circuit noise between each board card in the step-by-step transmission will cause the LVDS signal quality to decrease, so scheme one is not suitable for the robot system with multiple motor drive board cards.

[0074] When the number of required drive cards in the robot system is large (more than 5), the LVDS interface "PCS layer" buffering and forwarding is adopted. The idea of the forwarding control scheme is that the input LVDS signal is parsed through the pcs_rx submodule, then the PCS data is buffered once, and finally the data is packaged and sent to the LVDS interface output through the pcs_tx submodule, so as to ensure the high-quality transmission of data between each subsystem.

[0075] The characteristic of the scheme adopting the LVDS interface "PCS layer" buffering and forwarding design is that the elastic buffering submodule (hereinafter referred to as Elastic Buffer) is embedded between the receiving and sending modules in the PCS layer. The advantage is that the signal quality is guaranteed and will not deteriorate step by step, which can greatly improve the stability of the robot system.

[0076] As shown in Figure 4 The application provides an LVDS networking parsing and forwarding control module, which comprises a pcs_rx submodule, an Elastic Buffer, a pcs_tx submodule and a mac_rx submodule. The layered transmission idea is adopted in the FPGA chip communication, and the advantages are that the logic code is reusable and maintainable.

[0077] The pcs_rx submodule is used for converting the input LVDS signal from the physical layer serial data into the transmission layer parallel data, and simultaneously performing the CRC check operation of the data code. The transmission layer parallel data with the CRC check success is synchronously written into the elastic buffering submodule and output to the mac_rx submodule.

[0078] An elastic buffer submodule between the pcs_rx submodule and the pcs_tx submodule, used to buffer the transport layer parallel data written by the pcs_rx submodule.

[0079] The pcs_tx submodule is used to read the transport layer parallel data in the elastic buffer submodule, perform CRC check, convert the transport layer parallel data with successful CRC check into physical layer serial data, and send the physical layer serial data to the LVDS output interface after packaging.

[0080] The mac_rx submodule is used to convert the physical layer serial data output by the pcs_rx submodule into user data of the current drive board card and user data of other drive board cards. If the current drive board card responds to the control instruction of the upper computer, the user data of the current drive board card is first sent to the MCU, and then the calculation result fed back by the MCU is output to the motion control module. Then, the user data processed by the motion control module is received and transmitted to the pcs_tx submodule together with the user data of other drive board cards. If the current drive board card does not respond to the control instruction of the upper computer, all user data is transparently transmitted to the pcs_tx submodule.

[0081] The Elastic Buffer is used for elastic buffering of data between pcs_rx and pcs_tx, and enhances the stability of data transmission. The Elastic Buffer is coded by a hardware description language verilog, and finally synthesized into a logic circuit by an EDA tool. First, the character code to be inserted and deleted needs to be selected. At the write port, if the write clock is faster than the read clock, the character code needs to be inserted according to the data in the Buffer. At the read port, if the read clock is faster than the write clock, the character code needs to be selectively deleted according to the number of data in the Buffer. The key and difficult point of the design of the Elastic Buffer lies in the selection of the character code (the character code cannot be the same as the data) and the internal processing mechanism of the Elastic Buffer, which is used to prevent data loss and improve the stability of LVDS serial data.

[0082] CRC (Cyclic Redundancy Check) is an algorithm used to detect errors in data transmission or storage. It calculates the redundancy code (check code) of the data and verifies these redundancy codes at the receiving end to detect the integrity of the data. CRC is widely used in communication systems, storage devices and file systems to ensure the accuracy and reliability of data.

[0083] Preferably, the elastic buffer submodule realizes data writing / reading in the following way:

[0084] If the write data clock frequency is lower than the read data clock frequency, and the number of data buffered in the module is lower than the read empty threshold, after inserting the character code in the write port, the data code parsed by the pcs_rx submodule is written through the write port, otherwise, the data code parsed by the pcs_rx submodule is directly written through the write port.

[0085] If the read data clock frequency is lower than the write data clock frequency, and the number of data buffered in the module is higher than the write full threshold, after deleting the character code in the read port, the data buffered in the module is read out from the read port, otherwise, no additional processing is performed, and the data buffered in the module is directly read out from the read port.

[0086] The write full threshold is greater than the read empty threshold, and the sum of the two is equal to the storage capacity of the elastic buffer submodule. The character code has uniqueness.

[0087] Preferably, the pcs_rx submodule realizes its function by the following way: obtaining an LVDS serial differential input signal from an LVDS input interface; filtering the input LVDS signal to filter out the glitch signal generated by hardware; double-edge sampling the filtered LVDS serial signal by a system clock, and generating half-byte bit width MII interface parallel data by using a shift register; converting the half-byte bit width MII interface parallel data into one-byte bit width transmission layer parallel data in the FPGA internal general-purpose; deleting the preamble and delimiter in the one-byte bit width transmission layer parallel data; performing CRC check on the processed transmission layer format Ethernet frame, if the CRC check passes, synchronously writing the transmission layer parallel data into the elastic buffer submodule and outputting to the mac_rx submodule, otherwise, interrupting the transmission and issuing a check error alarm.

[0088] MII (Media-Independent Interface) is an interface standard for Ethernet devices, used to connect the Ethernet MAC (Media Access Control) layer and the PHY (Physical Layer) device. The MII interface makes the communication between the MAC layer and the PHY layer independent of the specific transmission medium, that is, "media independent".

[0089] Preferably, the mac_rx submodule realizes its function by the following way:

[0090] (1) receiving the physical layer serial data output by the pcs_rx submodule, detecting whether the CRC check field, the message length field and the message board ID field are correct, if there is any error, discarding the message and reporting the related error state information to the upper layer; otherwise, entering (2);

[0091] (2) delete the redundant information in the original message, only keep the valid data field, the redundant information includes Ethernet source address, destination address and Ethernet type, the valid data field includes motor control instruction, control parameter and calculation data;

[0092] (3) match the motor control instruction of the valid data field with the current drive board card, if it is related, send the user data of the current drive board card to the MCU, receive the calculation result feedback by the MCU and output to the motion control module, so that the motion control module transmits the user data processed by the current drive board card and the user data of other drive board cards to the pcs_tx submodule; if it is not related, directly transmit all the user data to the pcs_tx submodule.

[0093] The control process in the motor drive board card is as follows:

[0094] Step 1: after the LVDS input signal enters the motor drive board card, the pcs_rx submodule converts the high-speed serial LVDS signal into parallel data of Ethernet frame, and converts the data format into the general data format inside the FPGA and sends it to the pcs_rx output port;

[0095] Step 2: the pcs_rx submodule outputs data to send to the elastic cache submodule, and the pcs_tx submodule converts the parallel data read from the transmission layer in the elastic cache submodule into high-speed LVDS serial signal and outputs to the next level of the motor drive board card;

[0096] Step 3: send the data output by the pcs_rx submodule to the mac_rx submodule, and the mac_rx submodule distributes the upper level data to the motion control module and MCU for further processing according to the different command sub-packet of Ethernet frame;

[0097] Step 4: the MCU performs FOC algorithm calculation according to the control parameters issued by the upper computer and the motor encoder data collected by the motor drive board card, and returns the calculation result to the first FPGA; the motion control module in the first FPGA realizes motor drive control according to the control instruction of the upper computer and the calculation result of the MCU.

[0098] Time synchronization processing

[0099] Because the main clock of each FPGA is a non-synchronous clock, there is a certain phase difference, which causes the problem of time lag in the response of each level of subsystem to the control instruction. Therefore, before data communication, system time synchronization processing must be performed.

[0100] The CPU master chip sends instructions to motor drive board cards at all levels. In order to ensure that the board cards at all levels (including information acquisition board cards) respond to the control instructions at the same time, the motor drive board cards at all levels need to obtain the transmission delay value from the CPU master chip to the current module.

[0101] To solve the above problems, the application provides a time synchronization technology. First, the transmission delay value between the sub-board cards at all levels and the master chip is measured, and the delay data is written into the original message and fed back to the upper module. The waiting time required by the board cards at all levels to respond is calculated based on the drive board card with the largest delay value (the last motor drive control card). After receiving the control instruction of the master chip, the board cards at all levels delay the corresponding waiting time, so that the drive control of the motor can be completed at the same time.

[0102] The specific steps for implementing the technical solution are as follows:

[0103] (1) When the CPU master chip sends an Ethernet message to the lower module, the time stamp generated by the local clock of the master chip is latched, and the sending time stamp is embedded in the sent message;

[0104] (2) When the motor drive board cards at all levels receive the system message from the upper module, the receiving time stamp of the board cards at all levels is latched and embedded in the received message; when the motor drive board cards at all levels send a message to the upper system, the sending time stamp is latched and embedded in the sent message; wherein, the receiving time stamp of the motor drive board card and the sending time stamp are generated by the local clock of the current motor drive board card, is the number of different motor drive board cards;

[0105] (3) The original Ethernet message is sent from the CPU master chip, passes through all drive board cards, and is returned to the CPU master chip. After receiving the returned message, the CPU master chip immediately latches the time stamp of the current receiving time . At this time, the CPU master chip can calculate the transmission delay time of data between the CPU master chip and a certain drive board card according to the time stamp generated by itself and , and the time stamp and of a certain drive board card. At the same time, the instruction delay waiting time required by the first block drive board card is calculated , wherein, represents the data transmission delay time from the CPU master chip to the last drive board card, which is also the largest transmission delay value.

[0106] (4) After the CPU master chip calculates the instruction waiting delay value of each level of drive board card, it writes it into the sending message and assigns it to the corresponding drive board card. After each level of drive board card obtains the corresponding delay waiting value, it will respond to the drive control instruction issued according to the corresponding delay waiting value. At this time, the CPU master chip has completed the synchronous control of all drive board cards.

[0107] Embodiments

[0108] In order to prove that the signal quality of the "PCS layer" cache forwarding scheme is better than that of the point-to-point "wired" direct forwarding scheme, multiple motor drive control cards are prepared for the test, and the data communication of the two schemes on different numbers of motor drive cards is studied. Whether the data packets sent can be normally received at the master chip end is checked, and the packet loss of the two is compared. This test uses 1 to 9 motor drive control cards for cascade communication, and the specific experimental results are shown in Table 1, where "√" indicates normal data transmission, and "×" indicates data transmission interruption (packet loss).

[0109] Table 1 Data packet loss in "wired" forwarding and "PCS layer" forwarding schemes

[0110]

[0111] As can be seen from Table 1, when the number of motor drive board cards in the robot system is 5 or more, the point-to-point "wired" direct forwarding scheme will cause the master chip to interrupt the reception of data and cause packet loss; when the number of cascade drive control cards is the maximum of 9, the "PCS layer" cache forwarding scheme can still guarantee normal data transmission and no packet loss occurs. Therefore, it can be proved that in a robot system with multiple levels of motor drive control cards in cascade, the "PCS layer" cache forwarding data transmission scheme can guarantee high-quality transmission of LVDS signals.

[0112] It should be understood that the above device is used to execute the method in the above embodiment, and the corresponding program module in the device has similar implementation principles and technical effects to the description in the above method. The working process of the device can refer to the corresponding process in the above method, which will not be described here.

[0113] Based on the method in the above embodiment, an electronic device is provided, which can include a processor, a communications interface, a memory, and a communications bus. The processor, the communications interface, and the memory can communicate with each other through the communications bus. The processor can invoke the logical instructions in the memory to execute the method in the above embodiment.

[0114] In addition, the logic instructions in the memory described above can be implemented in the form of a software function unit and sold or used as an independent product, and can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or say the part that contributes to the prior art or part of the technical solutions can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the method described in various embodiments of the present application.

[0115] Based on the method in the above embodiments, the embodiments of the present application provide a computer readable storage medium, which stores a computer program, and when the computer program runs on a processor, the processor executes the method in the above embodiments.

[0116] Based on the method in the above embodiments, the embodiments of the present application provide a computer program product, and when the computer program product runs on a processor, the processor executes the method in the above embodiments.

[0117] It can be understood that the processor in the embodiments of the present application can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The general-purpose processor can be a microprocessor or any conventional processor.

[0118] The method steps in the embodiments of the present application can be implemented by means of hardware, or by means of a processor executing software instructions. The software instructions can be composed of corresponding software modules, which can be stored in a Random Access Memory (RAM), a flash memory, a Read-only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically EPROM (EEPROM), a register, a hard disk, a mobile hard disk, a CD-ROM, or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor, so that the processor can read information from the storage medium, and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC.

[0119] In the above embodiments, all or part of the embodiments can be implemented by means of software, hardware, firmware, or any combination thereof. When implemented by means of software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted by means of the computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center by means of a wire (such as coaxial cable, optical fiber, Digital Subscriber Line (DSL)) or wireless (such as infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that includes one or more available media sets. The available media can be magnetic media (such as floppy disk, hard disk, magnetic tape), optical media (such as DVD), or semiconductor media (such as Solid State Disk (SSD)), etc.

[0120] It can be understood that the various numerical numbers involved in the embodiments of the present application are only for the convenience of differentiation, and do not limit the scope of the embodiments of the present application.

[0121] Those skilled in the art can easily understand that the above description is only the preferred embodiment of the present application, and is not used to limit the present application, and any modification, equivalent replacement and improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A LVDS networking parsing and forwarding control module, characterized in that, The LVDS networking analysis and forwarding control module is used for network communication between multiple motor drive board cards, and comprises a pcs_rx submodule, an elastic buffer submodule, a pcs_tx submodule and a mac_rx submodule. The pcs_rx submodule is used for converting input LVDS signals from physical layer serial data into transmission layer parallel data, performing CRC check operation on the data code, and synchronously writing transmission layer parallel data with successful CRC check into the elastic buffer submodule and outputting the transmission layer parallel data to the mac_rx submodule. The elastic buffer submodule is located between the pcs_rx submodule and the pcs_tx submodule, and is used for buffering transmission layer parallel data written by the pcs_rx submodule. The pcs_tx submodule is used for reading transmission layer parallel data in the elastic buffer submodule, performing CRC check, converting transmission layer parallel data with successful CRC check into physical layer serial data, and sending the physical layer serial data to an LVDS output interface after being packaged. The mac_rx submodule is used for converting transmission layer parallel data with successful CRC check output by the pcs_rx submodule into user data of a current motor drive board card and user data of other motor drive board cards.

2. The LVDS network resolution forwarding control module of claim 1, wherein, The elastic buffer submodule realizes data writing / reading in the following manner: If the writing data clock frequency is lower than the reading data clock frequency, and the number of buffered data in the module is lower than the reading empty threshold, after inserting character code at the writing port, the data code parsed by the pcs_rx submodule is written through the writing port, otherwise, the data code parsed by the pcs_rx submodule is directly written through the writing port. If the reading data clock frequency is lower than the writing data clock frequency, and the number of buffered data in the module is higher than the writing full threshold, after deleting character code at the reading port, the buffered data in the module is read from the reading port, otherwise, no additional processing is performed, and the buffered data in the module is directly read from the reading port. The writing full threshold is greater than the reading empty threshold, and the sum of the two is equal to the storage capacity of the elastic buffer submodule, and the character code has uniqueness.

3. The LVDS network resolution forwarding control module of claim 1, wherein, The pcs_rx submodule realizes its function in the following manner: LVDS serial differential input signals are acquired from an LVDS input interface; Input LVDS signals are filtered to filter out glitch signals generated by hardware; Filtered LVDS serial signals are sampled at two edges of a system clock, and a shift register is used to generate half-byte bit width MII interface parallel data; Half-byte bit width MII interface parallel data is converted into one-byte bit width transmission layer parallel data in FPGA; Preamble and delimiter in one-byte bit width transmission layer parallel data are deleted; The processed transmission layer format Ethernet frame is subjected to CRC check, if the CRC check is passed, the transmission layer parallel data is synchronously written into the elastic buffer submodule and output to the mac_rx submodule, otherwise, the transmission is interrupted, and a check error alarm is issued.

4. The LVDS network resolution forwarding control module of claim 1, wherein, The mac_rx submodule realizes its function in the following manner: (1) receiving the transmission layer parallel data with passed CRC check output by the pcs_rx submodule, detecting whether the CRC check field, message length field and message board ID field are correct, if any error exists, discarding the message, and reporting the relevant error state information to the upper layer; otherwise, entering (2); (2) deleting the redundant information in the original message, only keeping the valid data field, the redundant information including the Ethernet source address, destination address and Ethernet type, the valid data field including the motor control instruction, control parameter and calculation data; (3) matching whether the motor control instruction of the valid data field is related to the current motor drive board card, if related, sending the user data of the current motor drive board card into the MCU, receiving the calculation result fed back by the MCU and outputting the calculation result to the motion control module, so that the motion control module transmits the user data of the current motor drive board card and the user data of other motor drive board cards processed to the pcs_tx submodule; if not related, directly transmitting all the user data to the pcs_tx submodule.

5. A robot system based on high-speed LVDS networking, characterized by, It comprises: CPU master chip, one motor drive board card and one information acquisition board card; The first motor drive board card communicates with the CPU master control chip through the Ethernet interface; One motor drive board card and one information acquisition board card, linear connection mode of LVDS interface is adopted; Each motor drive board card comprises a first FPGA and an MCU, the first FPGA comprising a motion control module and the LVDS networking analysis and forwarding control module as claimed in any one of claims 1 to 4; The information acquisition board card comprises a second FPGA and an MCU, the second FPGA comprising an information acquisition module and the LVDS networking analysis and forwarding control module as claimed in any one of claims 1 to 4.

6. The robot system of claim 5, wherein The information collection board card is used for realizing analysis and reporting of data collected by various sensors, analyzing relevant data according to different sensor interfaces, packing the data and uploading the data to the motor drive board card through an LVDS structure Motor drive board card The Motor drive board is used to drive and control the relevant motor according to the control instruction of CPU master control chip and the motor control data transmitted by MCU module; the collected data message is uploaded level by level until uploaded to the CPU master control chip, and the relevant MCU state data is collected before uploading. The CPU master control chip is configured to make corresponding processing according to the uploaded acquisition data, MCU state data and control instruction of the upper computer.

7. A control method of a robot system based on a high-speed LVDS network as claimed in claim 5 or 6, characterized by, It comprises: Step 1: completing initialization according to the control instruction of the upper computer; Step 2: In the information acquisition board card, the information acquisition module acquires the data of various sensors, and the MCU completes the signal processing work and forwards the processing result to the second FPGA, and the second FPGA analyzes and forwards the control module through the LVDS networking, and packs the collected various sensor data and uploads it to the Motor drive board card; Step 3: In the motor driver board, data uploaded from the lower level is received via the LVDS interface. Simultaneously, the first FPGA parses the motor encoder data and, through the LVDS networking parsing and forwarding control module, packages the data uploaded from the lower level, the motor encoder data, and the MCU status data and uploads them to the upper level. ; Step 4: the CPU master control chip processes the data uploaded by the first motor drive board card, after completing data calculation, transmits the calculation result to the upper computer through the Ethernet, so that the upper computer receives the calculation result, and sends corresponding control command to each motor drive board card; Step 5: after each motor drive board card receives the control instruction transmitted by the upper computer, the MCU is responsible for the FOC algorithm processing of the motor, and transmits the processed data to the motion control module through the LVDS networking analysis and forwarding control module, the motion control module realizes the driving of the motor according to the instruction of the upper computer and the calculation data of the MCU, and the LVDS networking analysis and forwarding control module transmits the control instruction of the upper computer to the next level, so as to realize the control of the whole robot system.

8. The control method according to claim 7, characterized by, The control process in the motor drive board card is as follows: Step 1: After the LVDS input signal enters the motor drive board card, the pcs_rx sub-module converts the high-speed serial LVDS signal into parallel data of an Ethernet frame and converts the data format into a general data format inside the FPGA and sends the data to the pcs_rx output port; Step 2: The pcs_rx sub-module sends the output data to the elastic buffer sub-module, and the pcs_tx sub-module converts the parallel data read from the transmission layer in the elastic buffer sub-module into a high-speed LVDS serial signal and outputs the signal to the next level of the motor drive board card; Step 3: The pcs_rx sub-module sends the output data to the mac_rx sub-module, and the mac_rx sub-module distributes the data from the upper level to the motion control module and the MCU for further processing according to the sub-packet of different commands of the Ethernet frame; Step 4: The MCU performs FOC algorithm calculation according to the control parameters issued by the upper computer and the motor encoder data collected by the motor drive board card, and returns the calculation results to the first FPGA; the motion control module in the first FPGA realizes motor drive control according to the control instructions of the upper computer and the calculation results of the MCU.

9. The control method according to claim 7, characterized by, Time synchronization processing of each level of board card is performed before data communication: The transmission delay value between each level of board card and the CPU main control chip is measured, and the delay data is written into the original message and fed back to the upper level; Taking the board card with the largest delay value as the reference, the waiting time required by each level of board card to respond is calculated; After receiving the control instruction of the CPU main control chip, each level of board card delays the corresponding waiting time.

10. A computer-readable storage medium, characterized in that, The instructions, when executed on an electronic device, cause the electronic device to perform the control method of any one of claims 7-9. The instructions, when executed on an electronic device, cause the electronic device to perform the control method of any one of claims 7-9.

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