Time synchronization method and equipment

Abstract

The invention provides a time synchronization method executed by slave equipment, and the method comprises the steps: receiving a time synchronization packet from master equipment, and obtaining the packet transmitting time of the master equipment and the packet receiving time of the slave equipment; calculating a clock offset value between the slave device and the master device based on the packet transmitting time of the master device, the packet receiving time of the slave device and the path delay calibration value, and correcting a local clock of the slave device; wherein the path time delay calibration value is related to the distance between the master device and the slave device. The method can correct the clock skew between the master device and the slave device in real time, and improves the time synchronization precision.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, in particular to a time synchronization method and device. BACKGROUND

[0002] With the evolution of the fourth industrial revolution and the development of artificial intelligence technology, more and more automation, intelligentization and unmanned application scenarios are emerging. These new scenarios put forward higher requirements for the cooperation between network device nodes. In order to solve these needs, the industry proposes the concept of Time Sensitive Networking (TSN), and puts forward specific requirements for various sub-directions. Common application scenarios include automated mechanical tools, such as Industrial IoT (IIoT), vehicle and workshop radar, professional audio playback, power system control and other fields.

[0003] Traditional wired network clock synchronization (Network Time Protocol, NTP) protocols, such as those led by Cisco, can only achieve 10 millisecond (10ms) synchronization accuracy, and the synchronization process is slow. IEEE has designed a new generation of Precision Time Protocol (PTP) IEEE 1588, which uses wired mode and can achieve 100 nanosecond (100ns) synchronization accuracy through the UDP protocol layer. However, PTP requires a wired environment, which is complex to lay out and has poor flexibility, making it extremely inconvenient for many application scenarios. The 802.1as protocol enables PTP to be applied in wireless networks, resulting in new technologies such as Fine Timing Measurement (FTM), and the focus of synchronization is placed on the physical layer and MAC layer. Compared with wired PTP, the accuracy of FTM used for node synchronization will decrease.

[0004] In the FTM technology, another problem is the synchronization speed between devices. For one-to-one or one-to-small-number-of-devices, the FTM synchronization speed is in milliseconds or sub-seconds. However, when the network scale expands, the FTM network synchronization speed becomes a problem. In the FTM synchronization process, because of the time drift between devices, a global synchronization is performed every certain period of time to ensure the network synchronization state. In each clock calibration, the master clock device and each slave device need to transmit and receive dozens of FTM data packets back and forth to obtain dozens of clock offset groups for averaging, so as to eliminate the influence of the time point estimation error. When the number of nodes in the network increases, a large amount of time is consumed for transmitting FTM related data packets in each round of global synchronization, which greatly increases the wireless channel overhead, affects other control and data transmission of the system, and causes network congestion. At the same time, because the synchronization time is very long, the crystal oscillator drift between devices accumulates, which causes greater error.

[0005] Although the FTM technology is followed by the evolution of the 802.11az standard, the space-time multiplexing uplink and downlink can be adopted in a one-to-many manner, but the participating devices need to simultaneously support the two latest Wi-Fi standards of 802.11ax and 802.11az, which requires great changes in hardware and software, is not compatible with the current mainstream devices, and the cost is also much higher.

[0006] Therefore, how to use the FTM to realize fast synchronization of a large-scale network and at the same time ensure high synchronization precision is still a technical problem to be solved in the field. SUMMARY

[0007] The present application aims to at least solve one of the technical problems existing in the prior art or related art, and for this purpose, the present application provides a time synchronization method performed by a slave device in a communication network, a time synchronization method performed by a master device, and corresponding slave devices and master devices.

[0008] According to a first aspect of the present application, a time synchronization method is provided, which is performed by a slave device, and includes: receiving a time synchronization packet from a master device, obtaining a packet transmission time of the master device and a packet reception time of the slave device; based on the packet transmission time of the master device, the packet reception time of the slave device, and a path delay calibration value, calculating a clock offset value between the slave device and the master device, and correcting a local clock of the slave device; wherein the path delay calibration value is related to a distance between the master device and the slave device.

[0009] As an example, the path delay calibration value is a ratio of the distance between the master device and the slave device to the signal propagation speed.

[0010] As an example, the method further includes: obtaining a transceiver hardware delay calibration value of the slave device; and using the transceiver hardware delay calibration value of the slave device to compensate the clock offset value.

[0011] As an example, the transceiver hardware delay calibration value of the slave device comprises a loop delay calibration value, which is a local hardware loop delay value obtained by the slave device through loop calibration after power-on; wherein the loop delay calibration value at least comprises: analog and radio frequency path delays; and a clock phase difference between a receive end analog clock and a baseband clock.

[0012] As an example, the transceiver hardware delay calibration value of the slave device further comprises a non-loop delay calibration value, which is a calibration value of a baseband processing delay and a power amplifier delay obtained by the slave device based on a fixed distance calibration before factory shipment; wherein the baseband processing delay is related to the working mode of the slave device; and the power amplifier delay is related to the working state of the power amplifier.

[0013] As an example, the path delay calibration value is obtained in the following ways: through manual measurement of the distance between the slave device and the master device in the network deployment stage; or through a single-sided two-way SS-TW ranging process to measure the distance between the slave device and the master device.

[0014] As an example, the slave device is a movable slave device, and when the slave device moves, the method further comprises performing a path delay calibration process, which comprises the following steps: the slave device sends a ranging request packet to the master device and records a first time when the slave device sends the packet; the slave device receives a reply packet from the master device, wherein the reply packet comprises a second time when the master device receives the packet, a third time when the master device sends the packet, a transceiver hardware delay calibration value of the master device, and records a fourth time when the slave device receives the packet; based on the first time, the second time, the third time, the fourth time, the transceiver hardware delay calibration value of the master device, the transceiver hardware delay calibration value of the slave device, and an estimated value of the crystal oscillator offset between the master device and the slave device, the path delay calibration value is calculated and updated.

[0015] As an example, the path delay calibration process is repeatedly performed to obtain multiple path delay calibration values, and the multiple path delay calibration values are smoothed to obtain a final path delay calibration value.

[0016] As an example, the smoothing process comprises a sliding average, a weighted average, or a Kalman filter smoothing algorithm.

[0017] As an example, the method further comprises: the slave device estimates the crystal oscillator offset between the master device and the slave device each time it receives a synchronization packet from the master device, and stores the estimated value in a memory of a preset length to obtain a crystal oscillator offset tracking value through smoothing.

[0018] As an example, the method further comprises: between two synchronizations, the slave device dynamically corrects the local clock based on the crystal oscillator offset tracking value to compensate for the clock drift between the master device and the slave device.

[0019] As an example, the method further comprises smoothing the clock offset values obtained by the slave device from the multiple synchronization packets.

[0020] As an example, the synchronization packets are broadcast packets or multicast packets.

[0021] According to a second aspect of the present application, there is also provided a slave device for Wi-Fi communication, comprising a receiver, a transmitter, a memory, a processor, and computer executable instructions stored on the memory and executable on the processor, which when executed by the processor implement any of the methods described in the first aspect of the present application.

[0022] According to a third aspect of the present application, there is also provided a time synchronization method, which is performed by a master device, comprising setting a time window for path latency update; within the time window, receiving ranging update request packets from at least one slave device; after the time window ends, sending a reply packet to the at least one slave device; the reply packet comprises at least a sending time of the reply packet and a receiving time of each slave device request packet received by the master device, for each slave device to update its path latency calibration value.

[0023] As an example, the method further comprises grouping the at least one slave device to obtain at least one synchronization group, wherein the synchronization packet sending mode is determined by negotiation within each synchronization group.

[0024] As an example, the synchronization packet sending mode adopts a maximum bandwidth mode.

[0025] As an example, when the at least one master device is a plurality of master devices, the method further comprises selecting one root master device from the plurality of master devices as a master clock reference for the entire network; and the plurality of master devices perform time synchronization based on the root master device.

[0026] According to a fourth aspect of the present application, there is also provided a master device for Wi-Fi communication, comprising a receiver, a transmitter, a memory, a processor, and computer executable instructions stored on the memory and executable on the processor, which when executed by the processor implement any of the methods described in the third aspect of the present application.

[0027] The time synchronization method executed by the slave device provided in the embodiments of the present application can accurately calculate and correct the clock offset between the master device and the slave device in real time by combining one-way time synchronization, path delay calibration, hardware delay compensation and crystal oscillator offset tracking under the condition that the master device periodically broadcasts synchronization packets. This method not only significantly improves the time synchronization accuracy and effectively eliminates the synchronization errors caused by distance changes and hardware differences, but also supports multi-device parallel synchronization and dynamic path delay updating, greatly reducing the channel resource occupation. Thus, efficient, low-delay and high-robustness clock synchronization between movable nodes in a large-scale wireless network is realized, meeting the demand for high-precision clock consistency in complex scenarios such as industrial automation, logistics and power.

[0028] In addition, the time synchronization method executed by the master device provided in the embodiments of the present application further sets a path delay update window, uniformly receives the ranging requests of multiple slave devices, and broadcasts a reply packet at one time after the window ends, thereby realizing efficient synchronization response to the group slave devices. This method supports multi-master device cooperative synchronization, can flexibly group and adapt to different synchronization packet sending modes, and effectively reduces channel occupation and system overhead. The master device can provide a unified and accurate clock reference for the entire network, improving the efficiency and precision of multi-node synchronization in a large-scale wireless network. This scheme is suitable for large-scale and scalable networking environment, significantly enhances the time consistency and real-time collaboration capability of the wireless network, and meets the high-precision synchronization demand in various scenarios such as industry, logistics and power. BRIEF DESCRIPTION OF DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced as follows. The drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0030] Figure 1 A schematic diagram showing that two devices in a communication system adopt a one-way mode for time synchronization according to an embodiment of the present application.

[0031] Figure 2 A schematic diagram showing that two devices in a communication system adopt a one-way mode for time synchronization according to an embodiment of the present application.

[0032] Figure 3 A schematic diagram showing the flow of a time synchronization method executed by a slave device according to an embodiment of the present application.

[0033] Figure 4 A structure and working flowchart of a slave device time synchronization system of a wireless network based on Wi-Fi FTM according to an embodiment of the present application.

[0034] Figure 5 FIG. 1 shows a first schematic diagram of a group distance updating process of a master device and multiple slave devices in an SS-TW mode according to an embodiment of the present application.

[0035] Figure 6 FIG. 2 shows a second schematic diagram of a group distance updating process of a master device and multiple slave devices in an SS-TW mode according to an embodiment of the present application.

[0036] Figure 7 FIG. 3 shows a schematic diagram of a time synchronization method performed by a master device according to an embodiment of the present application.

[0037] Figure 8 FIG. 4 shows a schematic diagram of a slave device according to an embodiment of the present application.

[0038] Figure 9 FIG. 5 shows a schematic diagram of a master device according to an embodiment of the present application. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of the present application.

[0040] To facilitate the understanding of the embodiments of the present application, the invention process and technical concept of the present application will first be described as follows:

[0041] In the art, to solve the FTM network synchronization speed problem, the inventors found that Chinese patent application CN119521368A proposes a high-precision time synchronization method for a wireless environment, which adopts one-to-one uplink of multiple slave devices and one-to-many downlink of a master device using beacon broadcast, and reduces the interaction process from 2N communication frame quantities to (N+1) communication frame quantities. However, the inventors noticed that this application does not consider that this is only one round of interaction in a synchronization process. If the entire network is to achieve the above-mentioned available synchronization accuracy in a synchronization process, the above-mentioned (N+1) communication frame quantity interaction process needs to be performed for dozens of times. The beacon broadcast period is fixed at 100 ms, and 30 interactions require 3 s. If the synchronization period is relatively dense and the device density is also high, the scheme of the application has limited savings in channel overhead.

[0042] In addition, the inventor also noticed that the application has some defects in clock offset calibration and path delay calibration. First, the application defines a concept of adjacent rate ratio to calibrate the crystal oscillator offset of the master and slave devices. However, the so-called adjacent rate ratio is actually the crystal oscillator offset between the master and slave devices, which can be obtained from the physical layer when receiving the frame, and the algorithm of the application is based on the assumption that t3-t1=t3'-t1', that is, the two sets of time differences (t3-t1) and (t3'-t1') are completely equal. This assumption cannot achieve the claimed calibration in a real wireless communication environment. Second, the synchronization calibration of the network clock of the master-slave structure should be based on the master node. In the application, the time of the master node is mapped to the clock of the slave node, that is, based on the slave node, which is obviously wrong, because doing so will let the slave nodes act independently, thereby causing the timing synchronization of the entire network to be chaotic.

[0043] On this basis, the inventor creatively realized that in order to realize fast synchronization of a large-scale network using FTM, it is necessary to greatly reduce the number of frame interactions in each round of synchronization process while ensuring high synchronization accuracy.

[0044] The inventor has creatively found through long-term research on the time synchronization problem of wireless communication systems, especially the master-slave device time synchronization in Wi-Fi networks, that in wireless network device synchronization and ranging applications based on Wi-Fi FTM (Fine Timing Measurement) technology, time synchronization (aligning the clocks of devices) and ranging (calculating the distance between devices) are a two-sided process. To achieve accurate distance measurement, the clocks between devices must be sufficiently aligned, otherwise the ranging calculation will be distorted due to clock errors. For efficient time synchronization, not only the deviation of the clock itself should be eliminated, but also the propagation delay of the wireless signal in space should be compensated, because the flight time of the signal in the air will also affect the synchronization accuracy.

[0045] In actual implementation, both time synchronization and ranging can be implemented in one-way (One-Way, OW) and two-way (Two-Way, TW) modes. The two-way mode is divided into single-sided two-way (Single-Sided Two-Way, SS-TW) mode and double-sided two-way (Double-Sided Two-Way, DS-TW) mode. The double-sided two-way DS-TW mode is suitable for ranging or synchronization systems with ultra-high precision requirements, such as ultra-wideband (UWB) systems, which can achieve centimeter-level or even decimeter-level ranging or synchronization. For FTM systems mainly targeting meter-level and sub-meter-level ranging requirements, the single-sided two-way SS-TW mode can be used under normal interaction intervals.

[0046] Reference Figure 1This illustrates a schematic diagram of two devices synchronizing time in a one-way manner in a communication system according to an embodiment of this application. Figure 1 As shown, the communication system includes a master device Dev1 and a slave device Dev2. In unidirectional mode, the master device Dev1 sends a synchronization signal at time t1, which arrives at the slave device Dev2 after a path delay. The slave device Dev2 receives the signal at time t2. During signal transmission, there is a hardware delay D at the transmitter of the master device Dev1. TX1 There is a hardware delay D at the receiving end of device Dev2. RX2 This one-way process is used by the slave device to synchronize and calibrate its local clock based on the master device's packet transmission time, path delay, and related hardware delays.

[0047] See Figure 2 This illustrates a schematic diagram of two devices in a communication system according to an embodiment of this application performing time synchronization and ranging in a one-sided bidirectional mode. For example... Figure 2 As shown, the communication system also includes a master device Dev1 and a slave device Dev2. In one-way bidirectional mode, the master device Dev1 first sends a signal at time t1, after path delay and related hardware delay (D... TX1 D RX2 After that, the slave device Dev2 receives the signal at time t2. Subsequently, the slave device Dev2 sends the signal back to the master device Dev1 at time t3, and this signal also undergoes path delay and related hardware delay (D). TX2 D RX1 After that, the master device Dev1 receives the data at time t4. By recording the above four key moments (t1, t2, t3, t4) and the related hardware delays, higher precision clock synchronization and distance measurement between the master and slave devices can be achieved.

[0048] In view of this, see Figure 3 This document illustrates a flowchart of a time synchronization method performed by a slave device according to an embodiment of this application. Specifically, this application provides a time synchronization method for a master device and a slave device, which is performed by the slave device and includes the following steps:

[0049] S101: Receive a time synchronization packet from the master device and obtain the packet transmission time of the master device and the packet reception time of the slave device;

[0050] S102: Based on the packet transmission time of the master device, the packet reception time of the slave device, and the path delay calibration value, calculate the clock offset value between the slave device and the master device, and correct the local clock of the slave device.

[0051] The path delay calibration value is related to the distance between the master and slave devices.

[0052] In some embodiments, the path latency calibration value is a ratio of a distance between the master device and the slave device and a signal propagation speed.

[0053] For example, in the SS-TW, the path delay (PD) of the wireless channel is defined as equal to the distance between the two devices divided by the signal propagation speed (generally the speed of light c), i.e., ΔPD = ΔD / c. Where ΔD represents the distance between the two devices; c is the speed of wireless space in the working environment, and there is a slight difference in different transmission media; the path delay ΔPD represents the time (the unit can be seconds, milliseconds, microseconds, nanoseconds, picoseconds, etc.) taken by the electromagnetic wave signal to pass a distance ΔD.

[0054] Thus, in the time synchronization method of the embodiments of the present application, the packet transmission time of the master device and the packet reception time of the slave device are obtained by the slave device receiving the time synchronization packet sent by the master device, and the clock offset between the master device and the slave device is calculated in combination with the path latency calibration value related to the distance between the master device and the slave device, and the local clock of the slave device is corrected accordingly. The embodiments of the present application can effectively eliminate the influence of the signal propagation delay introduced by the physical distance between the master device and the slave device on the accuracy of clock synchronization, and improve the synchronization precision. Further, the slave device of the embodiments of the present application can quickly and automatically correct the local clock after receiving the synchronization packet, without complex multi-round interaction, thereby improving the time synchronization efficiency.

[0055] Back to Figure 2 In the communication system, the processing latency inside the device is divided into the transmission end latency D TX and the reception end latency D RX , and the clock offset between the master device and the slave device is Δclk. By recording and analyzing the four time instants (t1, t2, t3, t4), in combination with the transmission end latency D TX , the reception end latency D RX , and the clock offset between the master device and the slave device Δclk, the following relationships can be obtained:

[0056] t2 = t1 + Δclk + ΔPD + D TX1 + D RX2 (1)

[0057] t4 + Δclk = t3 + ΔPD + D TX2 + D RX1 (2)

[0058] HD1 = D TX1 + D RX1 (3)

[0059] HD2 = D TX2 + D RX2 (4)

[0060] By solving, Δclk and ΔPD are obtained as follows:

[0061]

[0062] In general applications, the clock deviation Δclk is used for network synchronization, and the path delay ΔPD is used for ranging.

[0063] The inventor finds that the above formula does not consider the crystal oscillator deviation between the master and slave devices. In fact, if the crystal oscillator deviation is introduced, for example, continuing with the Chinese patent application CN119521368A, it adopts a mode of multiple uplinks and one downlink in a 100 ms beacon period, and the overall average flow interval T reply = t3-t2 is 50 ms, and in the case of a crystal oscillator deviation of 2ppm between Dev1 and Dev2, the synchronization error caused by the crystal oscillator deviation alone reaches 50 ns. If the crystal oscillator deviation of a conventional Wi-Fi device is considered to be 50ppm, the synchronization error is as high as 1250 ns. Moreover, this synchronization error does not consider other error sources t2, t4, for example, the estimation error at t2, t4 is in the order of 200-1000 nanoseconds, which is generally determined by the specific algorithm implementation.

[0064] Based on this, the inventor realizes that to achieve fast and high-precision time synchronization in the SS-TW mode, it is also necessary to shorten the response time of the master device to the request (such as synchronization or ranging request) initiated by the slave device as much as possible, and to align the crystal oscillator deviation on both sides to a higher side, generally the master clock device, in the synchronization process. Here, the "response time" can refer to the time interval for the master device to respond to the request (such as synchronization or ranging request) initiated by the slave device and send a response packet. The shorter the time interval, the smaller the cumulative clock error between the master and slave devices caused by the crystal oscillator deviation, thereby facilitating high-precision time synchronization.

[0065] In view of this, the present application also conceives that on the basis of using a one-way (OW) time synchronization mechanism, a double calibration method based on crystal oscillator deviation compensation and single-sided two-way (SS-TW) ranging can be introduced, thereby further realizing fast and high-precision clock synchronization between movable nodes in a large-scale wireless network.

[0066] Specifically, in a one-way (OW) synchronization system, if a one-way method is used to calculate the distance between devices, the clocks of both devices need to be completely synchronized, that is, the clock deviation Δclk = 0, otherwise the calculated distance will have a large error. Conversely, if the one-way method is used to align the clocks of the slave device and the master device, the slave device needs to accurately know the physical distance between itself and the master device, that is, to have a high-precision path delay ΔPD value as a calibration value, and a transceiver hardware delay calibration amount, such as DTX1 、D RX2 Moreover, to ensure the accuracy of the one-way mode, the crystal oscillator offset (clock offset) of the device must also be small enough. If the crystal oscillator offset is large, the transmission frequency of the one-way synchronization packet must be very high to prevent clock loss.

[0067] In other words, to achieve high accuracy in the one-way synchronization mode, the following three factors must be considered: first, the clocks of the master and slave devices must be synchronized. Second, the slave device must know the distance (path delay) between itself and the master device and have calibration data for the hardware delay. Third, the crystal oscillator offset of the device must be small enough, otherwise the synchronization must be frequent.

[0068] Generally, one-way ranging and one-way clock synchronization are in the same system and cannot be achieved at the same time. That is, one-way ranging and one-way clock synchronization cannot be achieved at the same time in the same wireless system. The reason is that one-way ranging requires the clocks of the master and slave devices to be completely synchronized, otherwise the measured distance will not be accurate. In addition, one-way clock synchronization requires the slave device to accurately know the distance (signal propagation delay) between itself and the master device and the hardware delays of both parties, that is, the distance must be known before the clock can be synchronized. These two are prerequisites for each other, but cannot be achieved in practice. If the accuracy is guaranteed, the synchronization speed of the one-way mode is the fastest because there is only one-way transmission of the synchronization packet from the master device to the slave device. The formula for calculating the clock offset value is as follows:

[0069] Δclk = t2 - t1 - D TX1 -D RX2 -ΔPD (7)

[0070] Where t1 is the packet transmission time of the master device, t2 is the time when the slave device receives it, D TX1 is the transmission delay of the master device, D RX2 is the reception delay of the slave device, and ΔPD is the path delay.

[0071] The slave device Dev2 only has its own reception and transmission hardware delay calibration value HD2 = D TX2 + D RX2 and does not have information about the transmission delay D TX1 of the master device, and the reception and transmission hardware delays cannot be simply estimated, so the calculation of (7) can only be approximate and there will be errors. If the wireless communication modules of the two devices are of the same type, the reception and transmission hardware delays HD are symmetrical, that is, D TX2 is used instead of D TX1 , the error introduced is limited and the error introduced is relatively small. However, if the master and slave devices are different, the approximation will bring a not inconsiderable synchronization error; therefore, an optimization method for time synchronization that takes into account the reception and transmission hardware delay calibration values needs to be conceived.

[0072] In view of this, the time synchronization method of the embodiments of the present application can further comprise: obtaining a transceiving hardware delay calibration value of the slave device; and compensating the clock offset value by using the transceiving hardware delay calibration value of the slave device.

[0073] In some embodiments, the transceiving hardware delay calibration value of the slave device comprises: a loop delay calibration value, which is a local hardware loop delay value obtained by the slave device through loop calibration after power-on; wherein the loop delay calibration value at least comprises: an analog and radio frequency path delay; and a clock phase difference between a receiving end analog clock and a baseband clock.

[0074] It can be understood that the analog and radio frequency path delay is a fixed value in the same type of chip and is related to the working mode of the device. Generally, the delay can be equally divided between the transceiving sides.

[0075] As for the clock phase difference between the receiving end analog clock and the baseband clock, when the temperature and voltage are constant, the delay is also a fixed value in the same type of chip. Even if the temperature and voltage change greatly, the maximum error is only about one ADC clock period. If the receiver sampling rate is 80MHz, one sampling period is 12.5ns, and the error is at most 12.5ns. If the receiver sampling rate is 160MHz, one sampling period is 6.25ns, and the error is at most 6.25ns. As the maximum error of the hardware delay calibration between devices, it is acceptable in the art.

[0076] After power-on, the slave device can automatically perform loop calibration for all possible working modes. The loop delay calibration value obtained after performing the loop calibration is saved in the first calibration value table. When performing clock synchronization subsequently, the part of the delay can be automatically compensated by searching the first calibration value table, thereby improving the accuracy of time synchronization.

[0077] In some embodiments, the transceiving hardware delay calibration value of the slave device further comprises: a non-loop delay calibration value, which is a calibration value of a baseband processing delay and a power amplifier delay obtained by the slave device before leaving the factory based on fixed distance calibration; wherein the baseband processing delay is related to the working mode of the slave device; and the power amplifier delay is related to the working state of the power amplifier.

[0078] It can be understood that the baseband processing delay refers to the processing time of data in the baseband chip, and the delay is related to the working mode of the device and is fixed in the same working mode.

[0079] Power amplifier delay refers to the delay of a signal when passing through a power amplifier. In some device architectures, the delay is related to the working state (such as an amplification stage) of the power amplifier, and in some device architectures, the delay is irrelevant to the working state of the power amplifier. Therefore, different devices need to prepare general delay calibration values or different delay calibration values for different working states of the power amplifier according to the specific implementation architecture.

[0080] Generally, when the device is shipped, the manufacturer will perform a calibration with a fixed distance to obtain the above-mentioned non-loop delay calibration value and save it in a specific second calibration value table. The second calibration value table needs to store different delay calibration values according to different working modes or according to the combination of working modes and working states of the power amplifier.

[0081] In summary, the first calibration value table and the second calibration value table respectively store various hardware delays of the device in different modes and different power amplifier states. Therefore, as long as the corresponding values are looked up according to the working mode and the amplifier working state in the one-way time synchronization process and are combined, the transceiver hardware delay calibration value of a single device can be obtained.

[0082] It can be understood that, in addition to the calculation error during calibration, the error between different devices of the same type is mainly the error in the clock phase difference between the receiving end analog clock and the baseband clock, which is generally about 10 ns. For a wireless network requiring synchronization accuracy at the level of hundreds of nanoseconds, this error is acceptable.

[0083] Therefore, from the slave device, the hardware delay calibration value in the one-way clock synchronization calibration value formula (7) can be replaced by the sum of the values in the first calibration value table and the second calibration value table of the slave device in the corresponding mode, that is, HD≈D TX1 +D RX2 , and the introduced error is acceptable.

[0084] At this point, the formula (7) still retains the device distance related value, that is, the second term of the one-way synchronization mode calibration value, ΔPD, path delay. In other words, the second term ΔPD in formula (7) is the “path delay” between the master device and the slave device, that is, the signal flight time, which is directly related to the distance between them.

[0085] In some embodiments, the path delay calibration value is obtained by manually measuring the distance between the slave device and the master device during the network deployment stage, or by measuring the distance between the slave device and the master device through the one-sided two-way SS-TW ranging process.

[0086] As an example, for a single slave device, there are two ways to obtain this value. In the first way, if the device is fixed, the known distance can be manually set as the initialization of the path delay calibration value ΔPD at the time of network deployment. In the second way, the distance can also be measured in a single-side two-way (SS-TW) ranging mode at the time of network deployment. This path delay calibration value is stored in the third calibration value table. Each time the clock is synchronized, the time delay caused by signal propagation is automatically compensated by looking up the third calibration value table, ensuring more accurate clock synchronization.

[0087] Subsequently, in the network working period, if the position of the slave device changes, the path delay calibration value in the third calibration value table can be updated to ensure the accuracy of synchronization.

[0088] It can be understood that if the distance is updated in the SS-TW ranging mode, a 30-meter distance change corresponds to a 100-ns path delay calibration value error. For most application scenarios, the position movement of the network wireless node is a relatively slow process. Therefore, the frequency of path delay update using the single-side two-way (SS-TW) ranging mode is very low - much lower than the frequency of time synchronization process. This means that although the number of frames to be transmitted in the SS-TW ranging is more than that in the synchronization, because it is not used frequently, the network pressure is completely acceptable. In other words, as long as the device is not moving violently all the time, occasional path calibration is enough, and fast clock synchronization is mainly done at ordinary times.

[0089] As another example, for multiple slave devices, in the network deployment stage of the wireless network, the path delay calibration value between the master device and each slave device can be manually set in advance; or the path delay calibration value between the master device and each slave device can be automatically measured and obtained by using the FTM ranging process. Similarly, this path delay calibration value will be stored in the third calibration value table of each slave device, and each time the time synchronization is performed subsequently, the time delay caused by signal propagation is automatically compensated by looking up the third calibration value table, ensuring more accurate clock synchronization.

[0090] In actual application, the time synchronization process is as follows: the master device periodically broadcasts a synchronization packet (such as a Wi-Fi AP packet), and all slave devices receive it and correct their own time according to the locally saved first calibration value table, second calibration value table and third calibration value table.

[0091] Further, the application also conceives to use the crystal oscillator offset between the master and slave devices for compensation to improve the time synchronization accuracy.

[0092] In some embodiments, the slave device is a mobile slave device, and after the slave device moves to a new location, the method further comprises performing a path latency calibration procedure, which comprises the following steps: the slave device sends a ranging request packet to the master device, and records a first time when the slave device sends the packet; the slave device receives a reply packet from the master device, wherein the reply packet comprises a second time when the master device receives the packet, a third time when the master device sends the packet, a transceiver hardware delay calibration value of the master device, and records a fourth time when the slave device receives the packet; based on the first time, the second time, the third time, the fourth time, the transceiver hardware delay calibration value of the master device, a transceiver hardware delay calibration value of the slave device, and an estimated value of the crystal oscillator offset between the master device and the slave device, the path latency calibration value is calculated and updated.

[0093] In some embodiments, the path latency calibration procedure is repeatedly performed to obtain a plurality of path latency calibration values, and the plurality of path latency calibration values are smoothed to obtain a final path latency calibration value. Similarly, the final path latency calibration value is stored in the third calibration value table. Through the smoothing, the result is more accurate, thereby ensuring the estimation accuracy.

[0094] In some embodiments, the smoothing comprises a sliding average, a weighted average, or a Kalman filter smoothing algorithm.

[0095] In some embodiments, the slave device estimates the crystal oscillator offset between the master device and the slave device each time the slave device receives a synchronization packet from the master device, and stores the estimated value in a memory with a preset length, and obtains a crystal oscillator offset tracking value through smoothing.

[0096] In some embodiments, between two synchronizations, the slave device dynamically corrects the local clock based on the crystal oscillator offset tracking value to compensate for the clock drift between the master device and the slave device.

[0097] In some embodiments, the slave device smoothes the clock offset values obtained from multiple synchronization packets. The synchronization packet can be a broadcast packet or a multicast packet.

[0098] As an example, back to Figure 2 The slave device performs path latency update in a one-to-one manner, i.e., the slave device moves and performs ranging with the master device once. The slave device that moves to a new location sends a ranging update request to the master device. The request can be loaded on a broadcast packet or any service / control packet in a user-defined IE mode, and the working mode (such as bandwidth, protocol format, etc.) supported by both the master device and the slave device. The local sending time t1 is recorded in the slave device. After the master device receives the request packet loaded with the ranging update request, the packet receiving time estimator of the master device estimates the receiving time t2. Then, the master device sends a reply packet to the slave device within a reasonable T replyThe slave device replies a broadcast packet or any service / control packet within a time period, which is loaded with the transmission time t3 of the reply frame of the master device, and the reception time t'2 of the ranging update request frame of the master device. Wherein:

[0099] t'2 = t2 - HD 主 (8)

[0100] Wherein, HD 主 is the calibration value of the transceiver hardware delay of the master device. That is, formula (8) represents the calibration of t2 by using the calibration value of the transceiver hardware delay of the master device. Similarly, this calibration method can also be applied to t3. In other words, the time t3 of the packet sent by the master device can also be calibrated by hardware delay (i.e. subtracting HD 主 ).

[0101] After the slave device receives the reply frame from the master device, the packet reception time estimator estimates the reception time t4. At this time, the slave device can also obtain the current crystal oscillator offset estimation value (PPM) from the crystal oscillator offset smoothers, and then calculate the path delay ΔPD in the third calibration value table by using the following formula:

[0102]

[0103] Wherein, t1 represents the time when the slave device initiates the ranging request; t4 represents the time when the slave device receives the reply of the master device; HD represents the local hardware delay; t3 represents the packet sending time of the master device, t'2 is the calibration time when the master device receives the request packet; and PPM represents the offset estimation value between the master device and the slave device.

[0104] Therefore, by formula (9), the transceiver hardware delay and the crystal oscillator offset of the master device and the slave device can be eliminated by the embodiments of the present application, and the real signal propagation delay can be obtained. In addition, the path delay is one-to-one corresponding to the distance, that is, the ΔPD to be compensated, and the result is directly stored in the third calibration value table.

[0105] It should be understood that although the slave device corrects the crystal oscillator offset relative to the master device, the offset of the master device relative to the absolute accurate clock still exists. In order to reduce the estimation error of ΔPD caused by the offset, the time T reply needs to be reasonably arranged and cannot be too long.

[0106] In order to make the result more accurate, the above process can be performed multiple times, and the obtained multiple ΔPDs are smoothed to ensure the estimation accuracy. The final ΔPD smoothing value is written into the third calibration value table.

[0107] In order to facilitate the understanding of the technical solutions of the present application, Figure 4 a structure of a slave device time synchronization system of a wireless network based on Wi-Fi FTM according to the embodiments of the present application and a working flowchart thereof are shown. Referring toFigure 4 The slave device time synchronization system of this application embodiment can achieve high-precision synchronization compensation of the slave device to the local clock when the master device periodically broadcasts synchronization packets, which is particularly suitable for the application requirements of large-scale, mobile wireless networks.

[0108] like Figure 4 As shown, the slave device time synchronization system includes: a packet reception time estimator, calibration value table 1, calibration value table 2, calibration value table 3, calibration value table 3 update module, crystal oscillator offset estimator, crystal oscillator offset memory, crystal oscillator offset smoother, clock offset correction value calculator, clock synchronizer, correction value reset signal module, synchronization frame information processing module, and other system control modules.

[0109] Specifically, its workflow includes the following steps:

[0110] 1. Synchronization packet reception and local time estimation

[0111] The master device periodically sends synchronization packets containing synchronization timestamps via broadcast or multicast. After receiving the synchronization packet, the slave device first uses a packet reception time estimator to perform a high-precision estimation of the time when it received the synchronization packet locally, providing a time reference for subsequent calibration.

[0112] 2. Multi-level calibration value lookup compensation

[0113] The device consults the three types of calibration value tables stored locally, based on the current operating mode (such as bandwidth, protocol type, etc.):

[0114] Calibration Value Table 1: Used to store the hardware loop delay (such as RF, analog front end, sampling delay, etc.) of this device in different operating modes. The calibration values ​​are obtained through self-loop calibration after the device is powered on.

[0115] Calibration Value Table 2: Used to store baseband processing delay and power amplifier delay, classified according to different operating modes and power amplifier status, usually the factory calibration values.

[0116] Calibration Value Table 3: Used to store the path delay (i.e., distance / speed of light) between the master device and this device. This calibration value can be set manually or automatically updated based on the one-sided two-way (SS-TW) ranging process, and is especially suitable for device movement scenarios.

[0117] The above three types of calibration values ​​can compensate for time errors caused by hardware differences, environmental changes and node distances by looking up tables, thereby ensuring high accuracy of calibration calculations.

[0118] 3. Clock skew and crystal oscillator skew tracking compensation

[0119] The slave device obtains the frequency offset value (in ppm) between the master and slave devices through the crystal oscillator offset estimator when receiving each frame sent by the master device. The frequency offset estimate is stored in the crystal oscillator offset memory, and the last N frequency offset estimates are maintained in a first-in, first-out manner. The crystal oscillator offset smoother performs smoothing processing (such as sliding average, linear or nonlinear filtering) on the N estimates to obtain a stable master-slave frequency offset tracking value. The clock offset correction value calculator can dynamically compensate the clock cumulative error between two synchronization processes according to the currently accumulated crystal oscillator frequency offset tracking value, to realize real-time tracking and adjustment of the local clock. Through the above mechanism, even if the synchronization packet interval is long, the slave device can still accurately track the master device clock, significantly reducing the synchronization packet sending frequency requirement and improving the system efficiency.

[0120] 4. Multiple synchronization measurements and mean / smoothing processing

[0121] To further reduce accidental errors, the system supports repeating the above calibration estimation multiple times within a single synchronization process, and performing mean or other smoothing processing on the multiple calibration values, which are finally used for correction of the local clock.

[0122] 5. Dynamic update of path delay

[0123] The calibration value table 3 update module supports the slave device to initiate a path delay update request to the master device through a single-sided two-way (SS-TW) ranging process after a position change occurs. The master device can uniformly reply to multiple slave device ranging requests, to realize efficient path delay calibration for one-to-many, and each slave device automatically updates the path delay compensation value in the calibration value table 3 according to this, to ensure that the synchronization accuracy is continuously reliable.

[0124] Based on this, the time synchronization system and method of the slave device in the embodiments of the present application can automatically consult the multi-level calibration value table under the condition that the master device periodically broadcasts synchronization packets, and realize high-precision, low-delay, and low-overhead wireless network time synchronization in combination with frequency offset tracking compensation. At the same time, the system and method of the embodiments of the present application also support dynamic update of the path delay in complex scenarios such as device movement, greatly improving the clock consistency of device cooperation in the wireless network and the real-time performance, reliability of the whole system.

[0125] With reference back to Figure 4, network normal work, in the process of packet transmission and synchronization process of packet transmission process, all from the device in receiving the master device of any frame (frame), in order to correctly receive data frame, will carry out frequency offset estimation, get the current frame of the slave device relative to the master device of the crystal oscillator offset, unit for ppm. From the device has a length of N crystal oscillator offset storage device, every received a master device sent frame, the frame calculated crystal oscillator offset will be stored in the crystal oscillator offset storage device, the oldest will be replaced by the new. Subsequently, the crystal oscillator offset smoother will be with smoothing algorithm (may be simple average, but also can be more advanced linear / nonlinear algorithm), smoothing the N frame of the master device in the storage device between the single frame crystal oscillator offset estimation value, to get a more stable crystal oscillator offset estimation tracking value. The purpose of this tracking value, not only in smoothing crystal oscillator offset estimation error, but also can track the crystal oscillator offset changes with temperature, aging and other factors in real time.

[0126] The slave device will continue to track the master device and its own above-mentioned crystal oscillator offset estimation tracking value, for clock offset correction value calculator. Clock offset correction value calculator is one of the core modules of high-precision synchronization. Between two synchronization processes, clock offset correction value calculator will calculate the cumulative error of clock period between slave device and master device according to the obtained current crystal oscillator offset estimation tracking value, as correction error, to get the time period between two synchronization processes, the correct clock of each moment relative to the master device.

[0127] The next round of synchronization process ends, the new clock offset value is updated, the clock offset correction value calculator is reset, and the cumulative error is cleared. And before the next round of synchronization process, the cumulative error caused by the crystal oscillator offset is accumulated. In other words, after each round of synchronization process, the slave device will update the clock offset with the master device once, and the cumulative error before will be cleared. Next, before the next round of synchronization, the slave device will continuously calculate and correct the clock difference between itself and the master device according to the actual crystal oscillator offset, and track and calibrate the error all the time.

[0128] The calibration of the cumulative error of clock period between slave device and master device greatly guarantees the tracking accuracy of clock between two synchronization processes, reduces the necessity of frequent initiation of synchronization process. Therefore, the system can appropriately increase the synchronization process interval to alleviate the frame interaction pressure of time synchronization between large-scale network nodes, and reduce the channel occupation consumed in synchronization process.

[0129] Each time the master device sends a broadcast or multicast synchronization packet, the packet is loaded with an estimate of the master device's transmission time t1, and this value is not calibrated in any way. The broadcast or multicast packet is sent in a mode commonly supported by each target slave device in the network. For example, BW20, BW40, BW80, and so on in a Wi-Fi system, or HT, VHT, HE, EHT, and so on.

[0130] As another example, if a one-to-many approach is used for path delay updating, the master device can more efficiently simultaneously calibrate the distance for multiple slave devices.

[0131] In this example, the master device sets a path delay update period T reply，tot This period cannot be too long, otherwise the master device's offset relative to the absolute accurate clock will cause the estimate error of ΔPD to be too large, thereby affecting the ranging accuracy. The master device can initiate a path delay update period in various forms, and set T reply，tot During the path delay update period, all slave devices that need to perform path delay updating send one or more ranging update request frames (see Figure 5 and Figure 6 , as described in detail below) to the master device in the same format as in the one-to-one mode. The master device uniformly replies to a broadcast packet (or any service packet / control packet) at the end of the period, and the reply packet is loaded with the master device's reply frame transmission time t3 and the corrected reception time t' of all ranging update request frames at the master device end 2i i represents the i-th slave device. The reply packet also distinguishes different requests using the hardware number of the slave device (such as the wireless synchronization network node number, hardware MAC address, and so on).

[0132] After receiving the uniform reply from the master device, each slave device can independently calculate its own path delay ΔPD according to the timestamps, according to the aforementioned algorithm. In addition, each slave device can participate in ranging multiple times, and after collecting enough ΔPD results, it can no longer participate in subsequent path delay update periods. All ΔPDs are smoothed to obtain a final ΔPD smoothed value, and this smoothed value ΔPD is written into the third calibration value table of the slave device.

[0133] Through this one-to-many approach, the master device only needs to uniformly reply once at the end of the period, greatly saving channel resources. At the same time, multiple slave devices can perform ranging in parallel, greatly improving the ranging and synchronization efficiency of the entire network.

[0134] To facilitate understanding of the technical solutions of the present application, Figure 5 a first schematic diagram of a group distance updating process of a master device and multiple slave devices in an SS-TW mode according to an embodiment of the present application is shown. As shown in Figure 5As shown, the master device and multiple slave devices (including slave device 1, slave device 2, and slave device 3) jointly participate in a group distance update process in the SS-TW mode. In the process, each slave device sends a ranging request frame to the master device in turn, and initiates a ranging request at local time t 11 , t 12 , t 13 . Each request signal is received by the master device after passing through a corresponding transmission end delay (D TX1 , D TX2 , D TX3 ) and path delay (PD1, PD2, PD3). After receiving the request of each slave device, the master device records the reception time t 21 , t 22 , t 23 , respectively, and combines the local reception end delay (D RX# ). After the end of the preset total response window T reply,tot , the master device uniformly broadcasts a reply frame to all slave devices at time t3, and the reply frame carries the master device packet sending time and the reception time information of each ranging request. After receiving the reply frame, each slave device performs reception at local time t 41 , t 42 , t 43 , respectively, and performs dynamic calibration of path delay and clock offset in combination with the local reception end delay (D RX1 , D RX2 , D RX3 ). Through the above process, efficient parallel ranging and path delay update of the master device to multiple slave devices can be achieved, which greatly improves the synchronization and ranging efficiency of the group nodes and reduces the channel occupation.

[0135] Figure 6 A second schematic diagram of a group distance update process of a master device and multiple slave devices in the SS-TW mode according to an embodiment of the present application is shown. As shown, Figure 6 the master device and two slave devices (slave device 1 and slave device 2) participate in a group distance update process in the SS-TW mode. In the process, slave device 1 and slave device 2 initiate ranging requests at local time t 11 , t 21 , respectively, and the signals are received by the master device after passing through their respective transmission end delays (D TX1 , D TX2 ) and path delays (PD1, PD2), and the reception times t 12 , t 22 are recorded, while combining the reception end delay (D RX# ) of the master device. After the end of the preset response window, the master device uniformly broadcasts a reply frame at time t3, and the reply frame carries the master device packet sending time and the reception time of each slave device request packet. Each slave device performs reception at local time t41 , t 42 Receiving the reply frame and combining the local receiving end delay (D RX1 , D RX2 ) to perform subsequent path delay and clock offset calculation and calibration. Through this group process, the master device can realize the synchronous ranging and path delay compensation of multiple slave devices, ensuring high-precision time synchronization and distance estimation of each node in the system.

[0136] Therefore, through the group distance updating process of the master device and multiple slave devices in the SS-TW mode as described above, the application embodiment can effectively realize efficient and parallel distance calibration and time synchronization between multiple slave devices and the master device in a large-scale wireless network, and is suitable for various complex networking and high-synchronization-precision-demand application scenarios.

[0137] In summary, the time synchronization method performed by the slave device provided by the application embodiment can accurately calculate and real-time correct the clock offset between the master device and the slave device by combining one-way time synchronization, path delay calibration, hardware delay compensation, and crystal oscillator offset tracking under the condition that the master device periodically broadcasts synchronization packets. This method not only significantly improves the synchronization accuracy, effectively eliminates the synchronization error caused by distance changes and hardware differences, but also supports multi-device parallel synchronization and dynamic path delay updating, greatly reducing the channel resource occupation. Therefore, efficient, low-delay, and high-robustness clock synchronization between movable nodes in a large-scale wireless network is realized, meeting the demand for high-precision clock consistency in complex scenarios such as industrial automation, logistics, and power.

[0138] Figure 7 A flowchart of a time synchronization method performed by a master device is shown. Referring to Figure 7 , the time synchronization method is performed by the master device and includes the following steps:

[0139] S701: Set a time window for path delay updating;

[0140] S702: In the time window, receive a ranging update request packet from at least one slave device;

[0141] S703: After the end of the time window, send a reply packet to at least one slave device; the reply packet at least includes the sending time of the reply packet and the receiving time of each slave device request packet received by the master device, for each slave device to update the path delay calibration value.

[0142] In some embodiments, the time synchronization method further includes grouping at least one slave device to obtain at least one synchronization group, wherein the synchronization packet sending mode in each synchronization group is determined by negotiation.

[0143] In some embodiments, the synchronization packet transmission mode adopts a maximum bandwidth mode.

[0144] In some embodiments, when the at least one master device is a plurality of master devices, the method further comprises: selecting one root master device from the plurality of master devices as a master clock reference of the entire network; and performing time synchronization among the plurality of master devices based on the root master device.

[0145] It can be understood that in a wireless network, there are usually one or more movable master devices and a plurality of movable slave devices. If the master device is not unique, a root device is defined among the master devices as a time reference of the entire network, and the rest are backup master devices. The master devices need to be aligned in time first, and then broadcast the synchronization signal to all slave devices like a single master device system. The master device can be an AP in a Wi-Fi network.

[0146] The master device can divide the slave devices in the network into different synchronization groups, and each group can determine the synchronization packet transmission mode of the group by negotiation or the like. The entire network can also specify a synchronization packet transmission mode. By default, the highest mode supported by all devices is set, such as in a Wi-Fi system, mainly to specify the bandwidth mode. Because the first and second calibration value tables have different values under different bandwidth modes, only when the master and slave devices set the same mode for transmission and reception, the error compensation is most accurate, which can help to ensure the calibration accuracy. Moreover, the wider the bandwidth, the higher the estimation accuracy of the packet reception time t2 and t4, and the higher the synchronization accuracy of the network. In other words, in a wireless network, under the premise of device support, the larger the bandwidth, the more accurate the network synchronization.

[0147] When the master device sends out a broadcast or multicast synchronization packet, each target slave device receives the broadcast or multicast synchronization packet, and estimates the packet reception time t2 at the packet reception time estimator of each device. Then, the slave device compensates the hardware delay and path delay and other errors into the three aforementioned calibration value tables (Table 1, Table 2, Table 3) according to the current transmission and reception mode. Specifically, according to formula (7), the slave device performs table lookup according to the reception mode from the first, second, and third calibration value tables to obtain the calibration value for calibration, and obtains the respective two-side clock deviation Δclk at the moment.

[0148] In order to eliminate the estimation error of the packet reception time estimator, the above process needs to be repeated multiple times in each synchronization process, and the multiple clock offset values are averaged or other algorithms are used for smoothing processing, so as to effectively reduce the accidental error. In the one-way clock synchronization process, because broadcast packets or multicast packets are used, the master device only sends one packet, all slave devices can receive it, and there is no need to reply one by one ACK frame, so the synchronization efficiency is higher.

[0149] In summary, the time synchronization method executed by the master device provided in the embodiments of the present application further updates the path delay through setting a path delay update window, uniformly receives ranging requests of multiple slave devices, and broadcasts a reply packet at one time after the window ends, thereby realizing efficient synchronization response to the group slave devices. The method supports multi-master device collaborative synchronization, can flexibly group and adapt to different synchronization packet sending modes, and effectively reduces channel occupation and system overhead. The master device can provide a unified and accurate clock reference for the entire network, and improves the efficiency and accuracy of multi-node synchronization in a large-scale wireless network. The scheme is suitable for large-scale and scalable networking environment, significantly enhances the time consistency and real-time collaboration capability of the wireless network, and meets the high-precision synchronization requirements in various scenarios such as industry, logistics and power.

[0150] In order to enable those skilled in the art to further understand the technical solutions of the present application and their application values, the typical applications of the present application are described below in combination with actual scenarios.

[0151] Typical application scenario 1

[0152] In a typical application scenario, the embodiments of the present application are suitable for wireless network node clock synchronization in a large, medium or small automatic production line control system, and are particularly suitable for the case that some nodes move slowly.

[0153] For example, on an automatic production line, there are usually several fixedly installed industrial robots, conveyor controllers, various sensors, and a small number of slowly moving detection trolleys or debugging terminals. All devices are networked through Wi-Fi or similar wireless communication networks.

[0154] The master device (such as a master control cabinet or a wireless access point) is generally arranged in the central area of the production line, serving as a clock reference node of the entire network, periodically broadcasting synchronization packets to each slave device in the network. The fixed devices, as slave devices, can receive the synchronization packets of the master device according to the predetermined synchronization period, and use the one-way time synchronization mechanism proposed in the present application, in combination with the local calibration value table (including hardware delay compensation and path delay compensation) and the crystal oscillator offset tracking compensation, to realize sub-microsecond local clock synchronization correction. For the mobile detection trolley and the debugging terminal, during operation, the path delay calibration value between the master device and the mobile detection trolley or the debugging terminal can be automatically updated through the SS-TW ranging process, thereby ensuring that the clock synchronization accuracy is not affected by movement.

[0155] The technical solutions of the embodiments of the present application can be widely applied to various automatic production line scenarios such as large-scale automobile manufacturing assembly lines, electronic component packaging lines, and food and beverage sorting lines.

[0156] Typical application scenario 2

[0157] In this typical application scenario, the embodiments of the present application are suitable for clock synchronization between nodes of an automatic logistics sorting equipment control system, and have significant advantages especially in the case of a large number of nodes and frequent movement.

[0158] For example, in an intelligent logistics center or an automated warehouse system, a large number of mobile automated guided vehicles (AGVs), sorting mechanical arms, RFID read-write terminals, and intelligent shelves are usually included.

[0159] The master device (such as a wireless base station of a sorting area or a dispatch master server) serves as a clock master node of the entire network, regularly broadcasts a synchronization signal to the network. Various mobile slave devices can receive the synchronization packet in real time, and continuously correct the clock drift caused by node movement and environmental changes through the one-way synchronization method and crystal oscillator offset tracking algorithm of the present application.

[0160] Due to the frequent movement of the above nodes, each mobile device can automatically or on demand initiate a unilateral two-way (SS-TW) ranging request to the master device according to the actual motion state. The master device can efficiently respond in a one-to-many manner, realizing dynamic path delay calibration of a large number of nodes. The calibration value table mechanism supports flexible switching of devices in different partitions and different bandwidth modes, ensuring the accuracy of clock synchronization and path delay compensation.

[0161] In addition, the embodiments of the present application support heterogeneous devices (including different brands or hardware models) to form a network together, and effectively eliminate synchronization errors caused by hardware differences through multi-level calibration tables.

[0162] The technical solutions of the embodiments can also be extended and applied to intelligent express transfer centers, automatic stereoscopic warehouses, airport baggage sorting, port container automatic scheduling, and other automated logistics scenarios.

[0163] Typical application scenario 3

[0164] In this typical application scenario, the embodiments of the present application are directed to node clock synchronization of a power transmission control system, and are particularly suitable for application occasions in which network nodes are basically static and present a tree-shaped topology structure, such as a master control center, a substation, a power distribution cabinet, a remote monitoring terminal, and the like.

[0165] The master control center or the core substation usually serves as a master device, regularly broadcasts a synchronization packet to the entire network through wireless or wired means, and constructs a clock reference of a tree-shaped topology structure. Each subordinate substation, power distribution box, and terminal instrument serves as a slave device, can regularly receive the synchronization signal of the master device, and realizes high-precision clock alignment in the entire network based on the one-way synchronization mechanism of the present application, combined with transmission hardware delay calibration (using the first and second calibration value tables) and path delay compensation (the third calibration value table).

[0166] Since most nodes are fixedly installed, path delay calibration can be obtained by manual setting or one-time ranging at the initial network deployment, and subsequent path delay update is only required at a very low frequency, thereby greatly reducing network load.

[0167] The technical solution of the embodiments of the present application can also be applied to various power automation scenarios such as regional power dispatching, remote power transmission monitoring, intelligent power distribution network, and distributed new energy access.

[0168] The present application also provides a slave device for Wi-Fi communication, which is described below with reference to Figure 8 , which shows a structural schematic diagram of the slave device 8 of the embodiments of the present application, which includes a receiver 801, a transmitter 802, a memory 803, a processor 804, and computer executable instructions 805 stored on the memory and executable on the processor, and the processor executes the computer executable instructions 805 to implement the method steps in the method performed by the slave device in each of the embodiments of the time synchronization method described above.

[0169] The present application also provides a master device for Wi-Fi communication, which is described below with reference to Figure 9 , which shows a structural schematic diagram of the master device 9 of the embodiments of the present application, which includes a receiver 901, a transmitter 902, a memory 903, a processor 904, and computer executable instructions 905 stored on the memory and executable on the processor, and the processor executes the computer executable instructions 905 to implement the method steps in the method performed by the slave device in each of the embodiments of the time synchronization method described above.

[0170] In the present embodiment, each of the above modules can be implemented in whole or in part by software, hardware, and a combination thereof. Each of the above modules can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory in the computer device in software form, so as to be called and executed by the processor to perform the operations corresponding to each of the above modules.

[0171] The embodiments of the present application also provide a computer readable storage medium having computer program instructions stored thereon, and the computer program instructions are executable by the processor to implement the execution steps of the time synchronization method in each of the embodiments.

[0172] The embodiments of the present application also provide a computer program instruction executable by the processor to implement the execution steps of the time synchronization method in each of the embodiments.

[0173] In the above embodiments, the implementation principles and beneficial effects of the slave device, the master device, the computer readable storage medium, and the computer program for Wi-Fi communication can be referred to the description of the time synchronization method in the above, which will not be repeated here.

[0174] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. The non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical storage, high-density embedded non-volatile memory, resistive memory (ReRAM), magneto resistive random access memory (MRAM), ferroelectric memory (FRAM), phase change memory (PCM), graphene memory, etc. The volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration but not limitation, the RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The database involved in the embodiments provided in the present application can include at least one of a relational database and a non-relational database. The non-relational database can include a distributed database based on a block chain, etc., without being limited thereto. The processor involved in the embodiments provided in the present application can be a general-purpose processor, a central processing unit, a graphics processing unit, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., without being limited thereto.

[0175] Although various embodiments of aspects of the present application have been described for the purposes of the present disclosure, it should not be understood that the teachings of the present disclosure are limited to these embodiments. The features disclosed in one specific embodiment are not limited to that embodiment, but can be combined with the features disclosed in different embodiments. For example, one or more features and / or operations of the method according to the present application described in one embodiment can be applied individually, in combination or as a whole in another embodiment. Those skilled in the art should understand that there are more optional implementation manners and variations, and various changes and modifications can be made to the above-mentioned system without departing from the scope defined by the claims of the present application.

Claims

1. A time synchronization method, the method being executed by a slave device, comprising: Receive a time synchronization packet from the master device, and obtain the packet transmission time of the master device and the packet reception time of the slave device; as well as Based on the packet transmission time of the master device, the packet reception time of the slave device, and the path delay calibration value, the clock offset value between the slave device and the master device is calculated, and the local clock of the slave device is corrected. The path delay calibration value is related to the distance between the master device and the slave device.

2. The method according to claim 1, wherein, The path delay calibration value is the ratio of the distance between the master device and the slave device to the signal propagation speed.

3. The method according to claim 1, further comprising: Obtain the transmit / receive hardware latency calibration value of the slave device; as well as The clock offset value is compensated using the transmit / receive hardware delay calibration value of the slave device.

4. The method according to claim 3, wherein, The transmit / receive hardware latency calibration values ​​of the slave device include: The loop delay calibration value is the local hardware loop delay value obtained by the slave device through loop calibration after power-on. The loop delay calibration value includes at least the following: Analog and RF path delays; and The clock phase difference between the analog clock and the baseband clock at the receiving end.

5. The method according to claim 3, wherein, The transmit / receive hardware latency calibration value of the slave device also includes: The non-loop delay calibration value refers to the calibration values ​​of the baseband processing delay and power amplifier delay obtained by the slave device based on fixed-distance calibration before leaving the factory; wherein, The baseband processing delay is related to the operating mode of the slave device; The power amplifier delay is related to the operating state of the power amplifier.

6. The method according to claim 1, wherein, The path delay calibration value is obtained through the following methods: The distance between the slave device and the master device is obtained by manually measuring and inputting the distance during the network deployment phase; or The distance between the slave device and the master device is obtained by measuring the distance using a one-sided bidirectional SS-TW ranging process.

7. The method according to claim 1, wherein, The slave device is a movable slave device. When the slave device moves, the method further includes performing a path delay calibration process, which includes the following steps: The slave device sends a ranging request packet to the master device, and records the first time the slave device sends the packet; The slave device receives a response packet from the master device, wherein the response packet includes a second time when the master device receives the packet, a third time when the master device sends the packet, and the master device's transmit / receive hardware delay calibration value; and records a fourth time when the slave device receives the packet; as well as The path delay calibration value is calculated and updated based on the first time, the second time, the third time, the fourth time, the master device's transmit / receive hardware delay calibration value, the slave device's transmit / receive hardware delay calibration value, and the estimated crystal oscillator offset between the master device and the slave device.

8. The method according to claim 7, wherein, Repeat the path delay calibration process to obtain multiple path delay calibration values, and smooth the multiple path delay calibration values ​​to obtain the final path delay calibration value.

9. The method according to claim 8, wherein, The smoothing process includes moving average, weighted average, or Kalman filter smoothing algorithms.

10. The method according to claim 1, further comprising: Each time the slave device receives a synchronization packet from the master device, it estimates the crystal oscillator offset between the master device and the slave device, stores the estimated value in a memory of a preset length, and obtains the crystal oscillator offset tracking value through smoothing processing.

11. The method of claim 10, further comprising: Between two synchronizations, the slave device dynamically corrects its local clock based on the crystal oscillator offset tracking value to compensate for clock drift between the master device and the slave device.

12. The method according to claim 1, further comprising: The slave device smooths the clock offset values ​​obtained from multiple synchronization packets.

13. The method according to claim 1, wherein, The synchronization packet is a broadcast packet or a multicast packet.

14. A slave device for Wi-Fi communication, comprising: Receiver; transmitter; A memory, a processor, and computer-executable instructions stored on the memory and executable on the processor, wherein the computer-executable instructions, when executed by the processor, implement the method according to any one of claims 1 to 13.

15. A time synchronization method, the method being executed by a master device, comprising: Set the time window for path delay updates; Within the time window, a ranging update request packet is received from the at least one slave device; as well as After the time window ends, a response packet is sent to the at least one slave device. The response packet includes at least the sending time of the response packet and the receiving time when the master device receives each slave device request packet, so that the at least one slave device can update the path delay calibration value.

16. The method of claim 15, further comprising: Grouping is performed on the at least one slave device to obtain at least one synchronization group, wherein a synchronization packet sending mode is determined through negotiation within each synchronization group.

17. The method of claim 16, wherein the synchronization packet transmission mode adopts the maximum bandwidth mode.

18. The time synchronization method according to claim 15, wherein, When the at least one master device is multiple master devices, the method further includes: Select one root master from multiple master devices as the master clock reference for the entire network; and The multiple master devices perform time synchronization based on the root master device.

19. A master device for Wi-Fi communication, characterized in that, include: Receiver; transmitter; A memory, a processor, and computer-executable instructions stored on the memory and executable on the processor, wherein the computer-executable instructions, when executed by the processor, implement the method according to any one of claims 15 to 18.

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