Memory device and method of controlling the same

Abstract

The embodiment of the invention provides a memory device and a control method thereof. The memory device comprises a plurality of first stacked structures which are arranged in a stacked manner; the first stack structure comprises a plurality of first conductive layers and first dielectric layers which are alternately arranged along a first direction; a plurality of first conductive structures, wherein each first conductive structure is connected with one first conductive layer of at least two first stacking structures in the plurality of first stacking structures; a plurality of channel structures; each channel structure penetrates through the plurality of first stack structures; at least one semiconductor layer, at least one second conductive layer; one semiconductor layer and one second conductive layer are located on the two sides of one first stacking structure in the first direction respectively and connected with the channel structure in one first stacking structure; each second conductive layer comprises a plurality of bit lines which are spaced along the second direction and extend along the third direction; and a plurality of second conductive structures, wherein each second conductive structure is connected with one bit line of at least one second conductive layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, in particular to a memory device and a control method thereof. BACKGROUND

[0002] Memory devices, such as NAND flash memory, have become the mainstream products in the memory market due to their high storage density, controllable production cost, suitable programming and erasing speed, and retention characteristics. SUMMARY

[0003] Embodiments of the present application provide a memory device, which comprises: a plurality of first stack structures arranged in a stack; each first stack structure comprises a plurality of first conductive layers and a plurality of first dielectric layers arranged alternately along a first direction; a plurality of first conductive structures, each first conductive structure being connected to one first conductive layer of at least two first stack structures of the plurality of first stack structures; a plurality of channel structures, each channel structure penetrating the plurality of first stack structures; at least one semiconductor layer and at least one second conductive layer, the at least one semiconductor layer and the at least one second conductive layer being respectively located on two sides of one first stack structure along the first direction and connected to the channel structure in the one first stack structure; each second conductive layer comprises a plurality of bit lines arranged in a second direction and extending in a third direction; the second direction and the third direction intersect and are both perpendicular to the first direction; and a plurality of second conductive structures, each second conductive structure being connected to one bit line of the at least one second conductive layer.

[0004] In some embodiments, different bit lines corresponding to different first stack structures penetrated by the same channel structure are all connected to the same second conductive structure.

[0005] In some embodiments, the at least one second conductive layer is located between two adjacent first stack structures and connected to the channel structures in the two adjacent first stack structures.

[0006] In some embodiments, the memory device further comprises a peripheral circuit; the peripheral circuit comprises a page buffer; and the plurality of second conductive structures are connected to the same page buffer.

[0007] In some embodiments, different bit lines corresponding to different first stack structures penetrated by the same channel structure are all connected to different second conductive structures.

[0008] In some embodiments, the size of the second conductive layer corresponding to different first stack structures in the third direction is different; and different second bit lines connected by the second conductive layer corresponding to different first stack structures are arranged in the third direction in sequence.

[0009] In some embodiments, the memory device further comprises a peripheral circuit; the peripheral circuit comprises a plurality of page buffers; the second conductive structures connected to the bit lines of the same second conductive layer are connected to the same page buffer of the plurality of page buffers; the second conductive structures connected to the bit lines of different second conductive layers are connected to different page buffers of the plurality of page buffers.

[0010] In some embodiments, the at least one semiconductor layer is located between two adjacent first stack structures and connected to the channel structures in the two adjacent first stack structures.

[0011] In some embodiments, two adjacent first stack structures of the plurality of first stack structures form a stack group; the memory device comprises a plurality of semiconductor layers; the plurality of semiconductor layers are respectively located between two adjacent first stack structures of the plurality of stack groups; and the plurality of semiconductor layers are connected to each other.

[0012] In some embodiments, a cross-sectional shape of the plurality of first stack structures along the first direction comprises a stepped shape; each step of the stepped shape corresponds to one adjacent first conductive layer and one adjacent first dielectric layer; and the first conductive structures extend along the first direction in the first stack structures and are connected to at least two steps where one first conductive layer of at least two first stack structures is located.

[0013] In some embodiments, the memory device further comprises a second stack structure comprising a plurality of isolation layers and a plurality of second dielectric layers arranged alternately; the first conductive structures comprise a first lead-out portion and a plurality of first connection portions; the first lead-out portion is connected to the plurality of first connection portions in the second stack structure along the first direction; and each first connection portion is located in one isolation layer and connected to one first conductive layer of a corresponding first stack structure of the at least two first stack structures.

[0014] In some embodiments, the first conductive structures are connected to the same first conductive layer of each first stack structure that is away from the semiconductor layer connected to the channel structure of the corresponding first stack structure.

[0015] In some embodiments, the first conductive structures are connected to different first conductive layers of each first stack structure that are away from the semiconductor layer connected to the channel structure of the corresponding first stack structure.

[0016] In some embodiments, the memory device further comprises a peripheral circuit; the peripheral circuit comprises a plurality of word line driving circuits; and one first conductive layer of the at least two first stack structures are connected to each other through the first conductive structures and connected to the same word line driving circuit.

[0017] In some embodiments, the memory device further includes a plurality of third conductive structures; the first conductive layers in the first stack structures include top select gate layers and gate layers; the top select gate layers are located at one end of the respective first stack structures along the first direction, away from the semiconductor layers connected with the channel structures in the respective first stack structures; the third conductive structures extend along the first direction in the first stack structures and are connected with the top select gate layers included in at least one of the first stack structures; the first conductive structures are connected with one gate layer of at least two of the first stack structures.

[0018] In some embodiments, the memory device further includes top select gate isolation structures; the top select gate isolation structures divide the top select gate layers into a plurality of sub-top select gate layers; different sub-top select gate layers included in the same top select gate layer are connected with different third conductive structures.

[0019] In some embodiments, different top select gate layers included in different first stack structures are connected with different third conductive structures; different bit lines corresponding to different first stack structures penetrating the same channel structure are connected with the same second conductive structure.

[0020] In some embodiments, different bit lines corresponding to different first stack structures penetrating the same channel structure are connected with different second conductive structures; different top select gate layers included in different first stack structures are connected with the same third conductive structure.

[0021] In some embodiments, the plurality of first stack structures are stacked to form one memory surface; the memory device includes a first memory surface and a second memory surface; the first memory surface and the second memory surface are arranged side by side along a second direction; the memory device further includes a plurality of word line driving circuits; the first conductive structures are located between the first memory surface and the second memory surface, and are connected with one gate layer of different first stack structures in at least one memory surface; the first conductive layers at the same position in the first direction of the first memory surface and the second memory surface are connected with each other and connected with the same word line driving circuit.

[0022] In some embodiments, different bit lines corresponding to different first stack structures penetrating the same channel structure are connected with different second conductive structures; different top select gate layers included in different first stack structures in the same memory surface are connected with the same third conductive structure; different top select gate layers included in the first stack structures at the same position in the first direction of different memory surfaces are connected with different third conductive structures.

[0023] In some embodiments, the plurality of first stack structures arranged in a stack form a memory module; the memory device comprises a first memory module and a second memory module; the first memory module and the second memory module are arranged in a stack along a first direction; the plurality of first conductive structures are connected to a gate layer of each first stack structure in the first memory module and the second memory module.

[0024] In some embodiments, different bit lines corresponding to different first stack structures through the same channel structure in the same memory module are connected to different second conductive structures; two bit lines corresponding to two first stack structures in different memory modules are connected to each other; different top select gate layers included in different first stack structures in the same memory module are connected to the same third conductive structure; two top select gate layers included in two first stack structures in different memory modules are connected to different third conductive structures.

[0025] In some embodiments, different bit lines corresponding to different first stack structures through the same channel structure in the same memory module are connected to the same second conductive structure; different bit lines corresponding to two first stack structures in different memory modules are connected to different second conductive structures; different top select gate layers included in different first stack structures in the same memory module are connected to different third conductive structures; two top select gate layers included in two first stack structures in different memory modules are connected to the same third conductive structure.

[0026] In some embodiments, the plurality of first stack structures are arranged in the first region, the plurality of first conductive structures are arranged in the second region, the plurality of second conductive structures are arranged in the third region, and the plurality of third conductive structures are arranged in the fourth region; the second region is located in the middle of the first region; or the second region is located on at least one side of the first region along a direction perpendicular to the stacking direction; the third region is located on at least one side of the first region along a third direction; and the fourth region is located between the first region and the second region.

[0027] Embodiments of the present application also provide a control method of a memory device, the memory device comprising a memory device provided by embodiments of the present application, a channel structure being divided into a plurality of sub-channel structures by a semiconductor layer and a second conductive layer; a plurality of first conductive layers in a first stack structure comprising a top select gate layer and a gate layer; the top select gate layer being located at one end of the corresponding first stack structure away from the end of the corresponding first stack structure where the channel structure is connected to the semiconductor layer along a first direction; the control method of the memory device comprising:

[0028] In the process of performing the read operation, a first voltage is applied to the top select gate of the unselected sub-channel structure and / or the bit line coupled thereto, and a second voltage is applied to the top select gate of the selected sub-channel structure and the bit line coupled thereto; a pass voltage is applied to all unselected gate layers, and a read voltage is applied to the selected gate layer.

[0029] In some embodiments, the first voltage includes a cutoff voltage, and the second voltage includes a first conduction voltage; the first voltage is applied to the top select gate of the unselected sub-channel structure and / or the bit line coupled thereto, and the second voltage is applied to the top select gate of the selected sub-channel structure and the bit line coupled thereto, including: applying the cutoff voltage to the top select gate of the unselected sub-channel structure, and applying the first conduction voltage to the top select gate of the selected sub-channel structure.

[0030] In some embodiments, the first voltage includes a program inhibit voltage, and the second voltage includes a program enable voltage; the first voltage is applied to the top select gate of the unselected sub-channel structure and / or the bit line coupled thereto, and the second voltage is applied to the top select gate of the selected sub-channel structure and the bit line coupled thereto, including: applying the program inhibit voltage to the bit line coupled to the unselected sub-channel structure, and applying the program enable voltage to the bit line coupled to the selected sub-channel structure; and a first conduction voltage is applied to all top select gate layers.

[0031] In some embodiments, the plurality of first conductive layers in the first stack structure further includes a bottom select gate layer; the bottom select gate layer is located at one end of the corresponding first stack structure along the first direction, which is closer to the semiconductor layer connected to the channel structure in the corresponding first stack structure; the method further includes: in the process of performing the read operation, a second conduction voltage is applied to all bottom select gate layers.

[0032] The embodiments of the present application also provide a control method of a memory device, the memory device including the memory device provided by the embodiments of the present application, the channel structure being divided into a plurality of sub-channel structures by the semiconductor layer and the second conductive layer; the plurality of first conductive layers in the first stack structure includes a top select gate layer and a gate layer; the top select gate layer is located at one end of the corresponding first stack structure along the first direction, which is away from the semiconductor layer connected to the channel structure in the corresponding first stack structure; the control method of the memory device includes:

[0033] In the process of performing the program operation, a first voltage is applied to the top select gate of the unselected sub-channel structure and / or the bit line coupled thereto, and a second voltage is applied to the top select gate of the selected sub-channel structure and the bit line coupled thereto; a pass voltage is applied to all unselected gate layers, and a program voltage is applied to the selected gate layer.

[0034] In some embodiments, the first voltage comprises a cutoff voltage, and the second voltage comprises a turn-on voltage; the applying the first voltage on the top select gates of the unselected sub-channel structures and / or the bit lines coupled thereto, and the applying the second voltage on the top select gates of the selected sub-channel structures and the bit lines coupled thereto, comprises: applying the cutoff voltage on the top select gates of the unselected sub-channel structures, and applying the turn-on voltage on the top select gates of the selected sub-channel structures.

[0035] In some embodiments, the first voltage comprises a program inhibit voltage, and the second voltage comprises a program enable voltage; the applying the first voltage on the top select gates of the unselected sub-channel structures and / or the bit lines coupled thereto, and the applying the second voltage on the top select gates of the selected sub-channel structures and the bit lines coupled thereto, comprises: applying the program inhibit voltage on the bit lines coupled to the unselected sub-channel structures, and applying the program enable voltage on the bit lines coupled to the selected sub-channel structures; and applying a turn-on voltage on all of the top select gate layers.

[0036] In some embodiments, the plurality of first conductive layers in the first stack structure further comprises a bottom select gate layer; the bottom select gate layer is located at one end of the corresponding first stack structure along the first direction, which is close to the semiconductor layer connected to the channel structure in the corresponding first stack structure; the method further comprises: applying a cutoff voltage on all of the bottom select gate layers during the programming operation.

[0037] Embodiments of the present application provide a memory device and a control method thereof; the memory device comprises: a plurality of first stack structures arranged in a stack; the first stack structure comprises a plurality of first conductive layers and a plurality of first dielectric layers arranged alternately along a first direction; a plurality of first conductive structures, each of which is connected to one first conductive layer of at least two first stack structures; a plurality of channel structures, each of which penetrates the plurality of first stack structures; at least one semiconductor layer and at least one second conductive layer; one semiconductor layer and one second conductive layer are respectively located on both sides of one first stack structure along the first direction and are connected to the channel structure in the one first stack structure; each second conductive layer comprises a plurality of bit lines spaced along a second direction and extending along a third direction; and a plurality of second conductive structures, each of which is connected to one bit line of the at least one second conductive layer.

[0038] In the embodiments of the present application, the memory device includes a plurality of first decks, and each deck is provided with a second conductive layer and a semiconductor layer on both sides along a first direction. In this way, the problem of channel saturation current reduction caused by too many gate layers can be improved. Meanwhile, the first conductive structure as the first conductive layer lead-out structure is connected with one first conductive layer of at least two first decks, that is, the first conductive structure is connected with a plurality of first conductive layers corresponding to a plurality of first decks, so that the plurality of first conductive layers can share the first conductive structure, which can reduce the total number of the first conductive structure and its driving circuit, and reduce the size of the memory device. On the other hand, the sharing of the first conductive structure extending along the first direction provides good technical support for the layer stacking of the plurality of decks along the first direction, and provides a technical basis for the improvement of the storage density brought by the layer stacking of the plurality of decks. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 A schematic diagram of a layout of a peripheral circuit including a word line driving circuit SD provided in an embodiment of the present application is shown;

[0040] Figure 2A A three-dimensional schematic diagram of a memory device architecture provided in an embodiment of the present application is shown Figure 1 ;

[0041] Figure 2B A three-dimensional schematic diagram of a memory device architecture provided in an embodiment of the present application is shown

[0042] Figure 2C A three-dimensional schematic diagram of a memory device architecture provided in an embodiment of the present application is shown

[0043] Figure 2D A three-dimensional schematic diagram of a memory device architecture provided in an embodiment of the present application is shown

[0044] Figure 2E A three-dimensional schematic diagram of a memory device architecture provided in an embodiment of the present application is shown

[0045] Figure 3A A schematic diagram of a memory device architecture forming process provided in an embodiment of the present application is shown Figure 1 ;

[0046] Figure 3B A schematic diagram of a memory device architecture forming process provided in an embodiment of the present application is shown

[0047] Figure 3C A schematic diagram of a memory device architecture forming process provided in an embodiment of the present application is shown

[0048] Figure 4AThe perspective view of the first stack structure and the first conductive structure including the memory device provided by the embodiment of the present application Figure 1 ;

[0049] Figure 4B The perspective view of the first stack structure and the first conductive structure including the memory device provided by the embodiment of the present application

[0050] Figure 4C The perspective view of the first stack structure and the first conductive structure including the memory device provided by the embodiment of the present application

[0051] Figure 5A The perspective view of the first stack structure and the first conductive structure including the memory device provided by the embodiment of the present application

[0052] Figure 5B The perspective view of the first stack structure and the first conductive structure including the memory device provided by the embodiment of the present application

[0053] Figure 5C The perspective view of the first stack structure and the first conductive structure including the memory device provided by the embodiment of the present application

[0054] Figure 5D The perspective view of the first stack structure and the first conductive structure including the memory device provided by the embodiment of the present application

[0055] Figure 6A The cross-sectional view of the specific form of the first conductive structure including the memory device provided by the embodiment of the present application Figure 1 ;

[0056] Figure 6B The cross-sectional view of the specific form of the first conductive structure including the memory device provided by the embodiment of the present application

[0057] Figure 6C The cross-sectional view of the specific form of the first conductive structure including the memory device provided by the embodiment of the present application

[0058] Figure 7A The top view of the layout including the array region and the connection region provided by the embodiment of the present application Figure 1 ;

[0059] Figure 7B The cross-sectional view of the specific form of the first conductive structure including the memory device provided by the embodiment of the present application Figure 7A

[0060] Figure 8A The top view of the layout including the array region and the connection region provided by the embodiment of the present application

[0061] Figure 8B The​Figure 8A Cross-sectional view at X2-X2' in FIG. 2;

[0062] Figure 9A Top view schematic diagram three of layout including array region, connection region provided for embodiments of the present application;

[0063] Figure 9B Provided for embodiments of the present application is a cross-sectional view of the layout including array and peripheral circuit of the memory device; Figure 9A Cross-sectional view at Y1-Y1' in FIG. 3;

[0064] Figure 10A Provided for embodiments of the present application is a perspective view schematic diagram two of layout including array and peripheral circuit of the memory device; Figure 1 ;

[0065] Figure 10B Provided for embodiments of the present application is a top view schematic diagram of the BL and TSG of deck1 of the memory device; Figure 1 ;

[0066] Figure 10C Provided for embodiments of the present application is a top view schematic diagram of the BL and TSG of deck2 of the memory device; Figure 1 ;

[0067] Figure 10D Provided for embodiments of the present application is a cross-sectional view schematic diagram of the BL of the memory device; Figure 1 ;

[0068] Figure 10E Provided for embodiments of the present application is a cross-sectional view schematic diagram of the TSG of the memory device; Figure 1 ;

[0069] Figure 11A Provided for embodiments of the present application is a perspective view schematic diagram two of layout including array and peripheral circuit of the memory device;

[0070] Figure 11B Provided for embodiments of the present application is a top view schematic diagram two of BL of each deck of the memory device;

[0071] Figure 11C Provided for embodiments of the present application is a top view schematic diagram two of BL of each deck of the memory device;

[0072] Figure 11D Provided for embodiments of the present application is a cross-sectional view schematic diagram two of TSG of each deck of the memory device;

[0073] Figure 11E Provided for embodiments of the present application is a cross-sectional view schematic diagram two of TSG of each deck of the memory device;

[0074] Figure 12A Figure 3 is a perspective view of a layout of an array of memory devices and peripheral circuitry, according to embodiments of the present disclosure;

[0075] Figure 12B Figure 4 is a top view of a BL out structure of each deck of memory devices, according to embodiments of the present disclosure;

[0076] Figure 12C Figure 5 is a top view of a BL out structure of each deck of memory devices, according to embodiments of the present disclosure;

[0077] Figure 12D Figure 6 is a cross-sectional view of a TSG out structure of each deck of memory devices, according to embodiments of the present disclosure;

[0078] Figure 12E Figure 7 is a cross-sectional view of a TSG out structure of each deck of memory devices, according to embodiments of the present disclosure;

[0079] Figure 13A Figure 8 is a perspective view of a layout of an array of memory devices and peripheral circuitry, according to embodiments of the present disclosure;

[0080] Figure 13B Figure 9 is a top view of a BL out structure of each deck of memory devices, according to embodiments of the present disclosure;

[0081] Figure 13C Figure 10 is a top view of a BL out structure of each deck of memory devices, according to embodiments of the present disclosure;

[0082] Figure 13D Figure 11 is a top view of a BL and TSG out structure of Model 1 of memory devices, according to embodiments of the present disclosure;

[0083] Figure 13E Figure 12 is a top view of a BL and TSG out structure of Model 2 of memory devices, according to embodiments of the present disclosure;

[0084] Figure 13F Figure 13 is a cross-sectional view of a TSG out structure of each deck of memory devices, according to embodiments of the present disclosure;

[0085] Figure 14A Figure 14 is a layout of functional layers coupled by a one-tunnel structure of memory devices, according to embodiments of the present disclosure; Figure 1

[0086] Figure 14B Figure 15 is a schematic of voltage application to functional layers in a selected sub-tunnel structure during a read operation, according to embodiments of the present disclosure;​Figure 1 ;

[0087] Figure 14C Schematic diagram of applying voltages to functional layers in an unselected sub- channel structure during a read operation according to embodiments of the present disclosure Figure 1 ;

[0088] Figure 14D Schematic diagram of applying voltages to functional layers in a selected sub- channel structure during a program operation according to embodiments of the present disclosure Figure 1 ;

[0089] Figure 14E Schematic diagram of applying voltages to functional layers in an unselected sub- channel structure during a read operation according to embodiments of the present disclosure Figure 1 ;

[0090] Figure 15A Layout diagram of functional layers coupled to a one-channel structure of a memory device according to embodiments of the present disclosure

[0091] Figure 15B Schematic diagram of applying voltages to functional layers in a selected sub- channel structure during a read operation according to embodiments of the present disclosure

[0092] Figure 15C Schematic diagram of applying voltages to functional layers in an unselected sub- channel structure during a read operation according to embodiments of the present disclosure

[0093] Figure 15D Schematic diagram of applying voltages to functional layers in a selected sub- channel structure during a program operation according to embodiments of the present disclosure

[0094] Figure 15E Schematic diagram of applying voltages to functional layers in an unselected sub- channel structure during a read operation according to embodiments of the present disclosure

[0095] Figure 16 Implementation flow diagram of a method of operating a memory device according to embodiments of the present disclosure

[0096] Figure 17 Schematic diagram of an exemplary system including a memory system according to embodiments of the present disclosure

[0097] Figure 18 Schematic diagram of an exemplary memory card including a memory system according to embodiments of the present disclosure

[0098] Figure 19 Schematic diagram of an exemplary solid state drive including a memory system according to embodiments of the present disclosure

[0099] In the drawings, which are not necessarily drawn to scale, like numerals describe similar components throughout the several views. Like numerals having different letter suffixes can represent different instances of the components. The drawings illustrate generally, by way of example, various embodiments discussed herein. DETAILED DESCRIPTION

[0100] Example implementations of the application will be described more thoroughly, with reference to the accompanying drawings, in which example implementations of the application are shown. It should be understood that the application can be implemented in various forms and should not be limited to the specific implementations described herein. Rather, these implementations are provided as examples of implementing the application so that this application can be thoroughly and completely understood and so that it can convey a full appreciation of the scope of the application to others skilled in the art.

[0101] In the following description, numerous specific details are given to provide a thorough understanding of the application. However, it will be apparent that the application can be practiced without one or more of the specific details. In other instances, well-known features are not described in order to avoid obscuring the application. As would be apparent to one of ordinary skill in the art, not all features of a practical implementation are described in detail herein. Also, the features of the practical implementations can be implemented in software, hardware, firmware, or a combination thereof. In the interest of clarity, not all features of an actual implementation are described in detail.

[0102] In the drawings, the size of layers, regions, elements, and the like can be exaggerated for clarity. Like numbers refer to like elements throughout.

[0103] It will be understood that the spatially relative terms "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0104] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of associated items.

[0105] In order to enable a more detailed understanding of the features and technical content of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below with reference to the accompanying drawings, which are only used for reference and do not limit the embodiments of the present application.

[0106] The technical development trend of a three-dimensional (3D) NAND memory is to achieve higher storage density, better performance, and lower cost. Increasing the number of stacked layers of the 3D NAND memory is an effective way to increase the storage density and reduce the cost per unit capacity. However, the increase in the number of stacked layers will gradually increase the area occupied by a string driver (SD), and the increase in the area occupied by the SD will reduce the array efficiency, and ultimately result in low utilization of the 3D NAND memory chip. Meanwhile, as the number of stacked layers increases, the size of the minimum operating unit, a storage block, gradually increases, and the performance of the 3D NAND memory is weakened.

[0107] Based on this, under the premise of increasing the number of stacked layers of the 3D NAND memory, how to improve the array efficiency and / or reduce the size of the storage block is a problem to be solved.

[0108] In some embodiments, the size of the string driver is reduced to reduce the area occupied by the string driver, so as to improve the array efficiency. Meanwhile, the number of fingers included in a single storage block is reduced to reduce the size of the storage block, so as to improve the performance of the 3D NAND memory. However, the reduction in the number of fingers of a single storage block will increase the length of the string driver in the X-axis direction perpendicular to the extension direction of the bit line in the storage block, thereby increasing the area occupied by the string driver, which in turn reduces the array efficiency. Here, each storage block includes a plurality of finger storage areas Fingers parallel in the Y-axis direction along the extension direction of the bit line, which are divided by a gate slit structure GLS.

[0109] Figure 1A schematic diagram showing the layout of the peripheral circuit including the word line driving circuit of the embodiment of the present application. A specific calculation method of the aforementioned array area effective utilization rate and the storage block size is as follows: array area effective utilization rate = BL number / (BL number located in the core area + SD number located in the area); storage block size = WL layer number * string number * BL number * TLC (3) or QLC (4). Here and hereinafter, the array area effective utilization rate can be referred to as array efficiency. Here, each storage block includes a plurality of storage strings (Strings) arranged in parallel along the Y-axis direction of the bit line extension direction, which are divided by the GLS and the top selection gate isolation structure TSGCUT, and the number of Strings included in one storage block is string number.

[0110] It should be noted that, for the convenience of description, the directions involved in the present application are uniformly defined herein. In the embodiment of the present application, the first direction can be the direction in which the gate layers and the dielectric layers are stacked in the stack structure, the second direction can be the direction in which the bit lines are arranged at intervals, and the third direction can be the direction in which the bit lines extend. The second direction and the third direction are both perpendicular to the first direction. In some specific embodiments, the second direction and the third direction are perpendicular. Exemplarily, the first direction can be the extension direction of the Z-axis shown in the drawing, the first direction can be the extension direction of the Z-axis shown in the drawing; the second direction can be the extension direction of the X-axis shown in the drawing; and the third direction can be the extension direction of the Y-axis shown in the drawing.

[0111] Figure 2A A schematic diagram showing the embodiment of the present application including the memory device architecture Figure 1 In some embodiments, as Figure 2A , the memory device includes a memory array and a peripheral circuit, wherein the memory array includes an array area GB and a connection area SS, exemplarily, the connection area is located in the middle of the array area; the array area is provided with a stack structure and a channel structure (not shown in Figure 2A ) penetrating through the stack structure, the stack structure includes alternately stacked gate layers and dielectric layers; the connection area is provided with a plurality of first conductive structures (first conductive structures or word line connection structures, first conductive structures or word line lead-out structures), one first conductive structure is connected with one gate layer, and is used to lead out the gate layer (or word line WL) to connect with the peripheral circuit, specifically to connect with the word line driving circuit SD in the peripheral circuit. In the embodiment of the present application, the number of gate layers is the same as the number of SDs, as Figure 2A shown, both are N*l. In the embodiment of the present application, the stack structure is provided with a bit line layer and a source line layer (not shown in Figure 2A ) on the opposite sides along the first direction.

[0112] Figure 2B to Figure 2E A schematic diagram showing the embodiment of the present application including the memory device architectureFigure 3A to Figure 3C A schematic diagram illustrating the formation process of a storage device architecture according to an embodiment of this application. Figure 1 To the third.

[0113] In some embodiments, such as Figure 2B The storage device includes a memory array and peripheral circuitry. The memory array comprises N stacked structures arranged along a first direction, each stack ( Figure 2B (The diagram in the image uses a deck) includes one gate layer ( Figure 2B (WL diagram). Each stacked structure has bit line layers on both sides along the first direction. Figure 2B (Illustrated by BL in Chinese) and source layer ( Figure 2B (Illustrated by ACS in the diagram), two adjacent stacked structures along the first direction can share the same BL or ACS. The memory array may also include multiple first conductive structures, each of which is connected to a gate layer of at least two stacked structures (such as N decks), so that these connected gate layers are led out to connect to the SD in the peripheral circuit.

[0114] like Figure 3A , Figure 2B The storage device architecture shown can be obtained by dividing a stacked structure into N parts along the Y-axis (third direction), and then stacking these N parts along the Z-axis. It should be noted that... Figure 2B The architecture of the storage device shown only illustrates the array region, omitting the connection region. Furthermore, Figure 2B The total number of gate layers is also N*l. Figure 2B and Figure 3A The architecture of the storage device shown is referred to below as the array Y-axis folding architecture.

[0115] In some embodiments, such as Figure 2C The storage device includes a memory array and peripheral circuitry. The memory array comprises N stacked structures arranged along a first direction, each stack ( Figure 2C (Illustrated by deck) includes l gate layers ( Figure 2C (WL diagram). Each stacked structure has bit line layers on both sides along the first direction. Figure 2C (Illustrated by BL in Chinese) and source layer ( Figure 2C (Illustrated by ACS in the diagram), two adjacent stacked structures along the first direction can share the same BL or ACS. The memory array can also have multiple first conductive structures, each of which is connected to a gate layer of at least two stacked structures (such as N decks), so that these connected gate layers are led out to connect to the SD in the peripheral circuit.

[0116] like Figure 3B ,Figure 2C The storage device architecture shown can be obtained by dividing a stacked structure into N parts along the X-axis (the second direction), and then stacking these N parts along the Z-axis. It should be noted that... Figure 2C The architecture of the storage device shown only illustrates the array region, omitting the connection region. Furthermore, Figure 2C The total number of gate layers is also N*l. Figure 2C and Figure 3B The architecture of the storage device shown is referred to below as the array X-axis folding architecture.

[0117] It is understandable that if the total number of array bit lines in an undivided stacked structure is Q KB (where Q is a positive integer, such as 16KB), then Figure 2B In the example, the total number of array bit lines is still Q KB (e.g., 16KB), while Figure 2C In the example, the total number of array bit lines is Q / N KB (e.g., 16 / N KB).

[0118] In some embodiments, such as Figure 2D The storage device includes a memory array and peripheral circuitry. The memory array includes M memory modules stacked along a first direction, each memory module ( Figure 2D (Illustrated by Model) includes N stacked structures, each of which can be... Figure 2B The illustrated array has N stacked structures in the Y-axis folding architecture. Each N stacked structure can also be... Figure 2C The diagram shows N stacked structures in a folded architecture along the X-axis. The memory array can also have multiple first conductive structures, each first conductive structure being connected to a gate layer of at least two stacked structures (such as N decks), so that these connected gate layers are led out to the SD connection in the peripheral circuitry. It should be noted that... Figure 2D The architecture of the storage device shown in the figure only illustrates the array region, while the connection region is ignored. Figure 2D The architecture of the storage device shown is referred to below as the array X-axis + Y-axis folding architecture.

[0119] The array folding structure in the X-axis + Y-axis direction can be formed in at least two ways.

[0120] In some specific embodiments, such as Figure 3C First, fold N stacked structures along the X-axis to obtain a storage module, and then fold M storage modules along the Y-axis to obtain M storage modules. This scheme is referred to as X-axis + Y-axis folding scheme 1.

[0121] In some specific embodiments, N stacked structures are first folded along the Y-axis to obtain a storage module, and M storage modules are obtained accordingly. The M storage modules are then folded along the X-axis to obtain M storage modules. This scheme is referred to as X-axis + Y-axis folding scheme 2.

[0122] It is understandable that the folding order differs between the two array X-axis + Y-axis folding architectures described above. Taking the generation of two storage modules as an example, Scheme 1 divides an undivided stacked structure into 4*2=8 parts along the X-axis and Y-axis, while Scheme 2 divides an undivided stacked structure into 2*4=8 parts along the X-axis and Y-axis. Although both involve dividing into 8 parts and stacking the 8 parts along the Z-axis, if the dimensions of the undivided stacked structure itself are different along the X-axis and Y-axis, the final dimensions of each part in Scheme 1 and Scheme 2 may differ.

[0123] In some embodiments, such as Figure 2E The storage device includes a memory array and peripheral circuitry. The memory array includes two storage surfaces arranged side-by-side along the X-axis, i.e., the second direction. Figure 2E (Plane 0 and Plane 1 are shown). Each storage plane can be... Figure 2B The stacked structure of the array Y-axis folding architecture is shown (in this case, the total number of bit lines per memory plane is QKB, such as 16KB); each memory plane can also be Figure 2C The stacked structure of the array X-axis folding architecture is shown (in this case, the total number of bit lines per memory plane is Q / N KB, such as 16 / N KB); each memory plane can also be Figure 2D The stacked structure of the array X-axis + Y-axis folding architecture is shown (for the X-axis folding followed by the Y-axis folding, the total number of bit lines per storage plane is Q / N KB, such as 16 / N KB).

[0124] The memory array also includes a connection region located between the two memory surfaces. This connection region contains multiple conductive structures shared by the two memory surfaces. One of these conductive structures can be connected to a gate layer of each of the multiple stacked structures (e.g., N decks) in the two memory surfaces, for leading the gate layer out to connect to the SD (Signal Deposit) circuitry in the external circuitry, thereby enabling... Figure 2D The number of SDs in the middle can be l. Figure 2E The architecture of the storage device shown is referred to as the memory plane merging architecture in the following text.

[0125] Understandable Figure 2BIn the illustrated array Y-axis folding architecture, the N deck line lead-out structures (i.e., the first conductive structures) share an SD area reduction by N times, thereby improving the effective utilization of the array area under the premise of increasing the number of stacked layers. Figure 2C In the illustrated array X-axis folding architecture, the total number of BLs is reduced to 1 / N before folding, and the folding and the line lead-out structure (i.e., the first conductive structure) are shared, achieving an SD area reduction by N times, and the storage block area is also reduced by 1 / N. Figure 2D In the illustrated array X-axis + Y-axis folding architecture, the advantages of the two architectures are combined, which can improve the effective utilization of the array area and reduce the storage block area. Figure 2E The illustrated storage surface merging architecture further shares the line lead-out structure, further improving the effective utilization of the array area. That is, the above four kinds of storage device architectures successfully solve Figure 2A In the illustrated architecture, reducing the number of fingers to reduce the storage block area will cause the contradiction of increasing the SD area.

[0126] For the above-described four kinds of storage device architectures, the implementation details of these architectures will be described in detail below. It should be noted that the implementation details described below can be applied to the above four kinds of storage device architectures.

[0127] Embodiments of the present application provide a storage device, which comprises: a plurality of first stacked structures arranged in layers; the first stacked structure comprises a plurality of first conductive layers and first dielectric layers arranged alternately along a first direction; a first conductive structure, the first conductive structure extends along the first direction and is connected to one of the first conductive layers of at least two of the plurality of first stacked structures; a plurality of channel structures; the channel structure penetrates the plurality of first stacked structures; at least one semiconductor layer, one semiconductor layer is connected to the channel structure in at least one first stacked structure.

[0128] In the embodiments of the present application, the first stacked structure can be understood as the stacked structure (deck) in the embodiments of the above four kinds of storage device architectures. In some embodiments, the material of the first conductive layer can include a conductive material, which includes but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each first conductive layer includes a metal layer, for example, a tungsten layer. In some embodiments, each first conductive layer includes a doped polysilicon layer. In some embodiments, the material of the first dielectric layer can include an oxide. In some embodiments, the material of the first dielectric layer includes silicon oxide.

[0129] In some embodiments, the channel structure throughout each of the plurality of first stack structures can include a gate dielectric layer, a charge storage layer, a tunneling layer, and a channel layer. In some specific embodiments, the channel structure can have a cylindrical shape (e.g., a column shape). In some implementations, the channel layer, the tunneling layer, the charge storage layer, and the gate dielectric layer are arranged radially from a center of the column toward an outer surface of the column in this order. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The charge storage layer can include silicon nitride, silicon oxynitride, or any combination thereof. The gate dielectric layer can include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In some implementations, the tunneling layer, the charge storage layer, and the gate dielectric layer can be collectively referred to as a memory film, which can include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0130] In embodiments of the present application, the semiconductor layer can be used as a source layer, which is connected with the channel layer in the channel structure. In some embodiments, the material of the semiconductor layer can include various semiconductor materials. In some implementations, the material of the semiconductor layer includes polysilicon.

[0131] In some embodiments, the memory device can further include at least one second conductive layer, one second conductive layer being connected with the channel structure of the at least one first stack structure; one second conductive layer including a plurality of bit lines spaced apart along a second direction and extending along a third direction; the second direction and the third direction both being perpendicular to the first direction. In embodiments of the present application, one semiconductor layer and one second conductive layer connected with the channel structure in the same first stack structure are respectively arranged on both sides of the first stack structure along the first direction.

[0132] In some embodiments, one of the at least one semiconductor layer is located between two adjacent first stack structures and connected with the channel structure in the two adjacent first stack structures.

[0133] In some implementations, as shown in Figure 4A , one second conductive layer (illustrated by BL in Figure 4A ) and one semiconductor layer (illustrated by ACS in Figure 4A ) are respectively arranged on both sides of the first stack structure along the first direction, and between two adjacent first stack structures along the first direction, one second conductive layer and one semiconductor layer are arranged.

[0134] In some implementations, as shown in Figure 4B and 4C , one second conductive layer (illustrated by BL in Figure 4B , Figure 4C ) and one semiconductor layer (illustrated by ACS in Figure 4B , Figure 4CThe second conductive layers or the semiconductor layers are respectively arranged on both sides of the first stack structures along the first direction, and one common second conductive layer or one common semiconductor layer is arranged between two first stack structures adjacent along the first direction. It should be noted that the common second conductive layer or the common semiconductor layer is connected with the channel layers of the channel structures in the first stack structures on both sides thereof and is shared by the channel structures on both sides thereof.

[0135] In some other embodiments, if the second semiconductor layers and the semiconductor layers are not shared, two second conductive layers or two common semiconductor layers can be arranged between two first stack structures adjacent along the first direction, and each of the two second conductive layers or each of the two common semiconductor layers respectively belongs to the first stack structures on both sides.

[0136] In some embodiments, the first conductive layers in each first stack structure include a plurality of gate layers or word lines. In some embodiments, the first conductive layers in each first stack structure further include a top selection gate layer and a bottom selection gate layer. The gate layer far away from the semiconductor layer in each first stack structure can serve as a top selection gate layer of the corresponding stack structure, the gate layer close to the semiconductor layer in each stack structure can serve as a bottom selection gate layer of the corresponding stack structure, and the gate layer between the top selection gate layer and the bottom selection gate layer can serve as a word line.

[0137] In the embodiments of the present application, the first conductive structure can include a word line lead-out structure, and one first conductive structure is connected with one gate layer of each of at least two first stack structures, for leading out the gate layer (or word line WL) to be connected with a peripheral circuit, specifically a word line driving circuit SD in the peripheral circuit. In some embodiments, the first stack structure includes N first stack structures, and one first conductive structure is connected with one first conductive layer in each of M first stack structures of the N first stack structures, that is, one first conductive structure is connected with M first conductive layers corresponding to M first stack structures. Here, M and N are positive integers, and N≥M≥2.

[0138] In some embodiments, the first conductive structure can be connected with one gate layer of each of two first stack structures adjacent to each other, or one gate layer of each of first stack structures spaced apart, or one gate layer of each of all first stack structures. The first conductive structure can be connected with one gate layer of one deck and penetrate through the deck, and be connected with one gate layer of another deck adjacent to the one deck. The first conductive structure can also penetrate through all decks and be connected with the gate layers of all decks.

[0139] In some embodiments, the first conductive structure is connected to one first conductive layer of each of the plurality of first stack structures.

[0140] In some specific embodiments, the first conductive layers connected to the same first conductive structure in different first stack structures are at the same distance from the semiconductor layer connected to the channel structure in the corresponding first stack structure.

[0141] In some embodiments, one first conductive structure is connected to one first conductive layer of each of the plurality of first stack structures, and the first conductive layers connected in each of the first stack structures are at the same distance from the semiconductor layer or the second semiconductor layer connected to the channel structure in the corresponding first stack structure.

[0142] For example, as Figure 4A , 4C each first stack structure includes l gate layers, for example, l = 5, and each first stack structure has gate layers WL1, WL2, WL3, WL4, and WL5 from the second conductive layer (BL) to the semiconductor layer (ACS). When the first conductive structure CT1 is connected to the gate layers of multiple decks, the first conductive structure CT1 can be connected to the same gate layer of different decks, such as one first conductive structure CT1 in the plurality of first conductive structures CT1 connected to the WL2 of all first stack structures, and another first conductive structure CT2 in the plurality of first conductive structures CT1 connected to the WL4 of all stack structures.

[0143] In some specific embodiments, the first conductive layers connected to the same first conductive structure in different first stack structures are at different distances from the semiconductor layer connected to the channel structure in the corresponding first stack structure.

[0144] In some embodiments, one first conductive structure is connected to one first conductive layer of each of the plurality of first stack structures, and the first conductive layers connected in at least two first stack structures are at different distances from the semiconductor layer or the second semiconductor layer connected to the channel structure in the corresponding first stack structure.

[0145] For example, as Figure 4BEach first stack structure includes l gate layers, for example, l = 5, each first stack structure from the second conductive layer (BL) to the semiconductor layer (ACS) gate layers are WL1, WL2, WL3, WL4, WL5 respectively, when the first conductive structure CT1 connects the gate layers of multiple decks, the first conductive structure CT1 can be connected to different gate layers of different decks, for example, one of the first conductive structures CT1-3 in the plurality of first conductive structures CT1 connects WL2 of deck 1, and CT1-3 connects WL4 of deck 2, another first conductive structure CT1-4 in the plurality of first conductive structures CT1 connects WL4 of deck 1, and CT2 connects WL2 of deck 2.

[0146] In some embodiments, the first conductive structure is connected to one first conductive layer of each of the plurality of first stack structures, and the number of first conductive layers connected by the first conductive structure is equal to the number N of decks.

[0147] In some embodiments, different first conductive layers of the first stack structure are connected to different first conductive structures. That is, different gate layers of the deck are led out through different first conductive structures.

[0148] In some embodiments, the number of first conductive structures is the same as the number of first conductive layers contained in the first stack structure; the total number of first conductive layers contained in the plurality of first stack structures is greater than twice the number of first conductive structures.

[0149] In the embodiments of the present application, the positional relationship between the first region where the plurality of first stack structures are arranged and the second region where the first conductive structures are arranged can include a plurality of types.

[0150] In some embodiments, the plurality of first stack structures are arranged in the first region S1, and the first conductive structures are all arranged in the second region S2, and the second region S2 is located in the middle of the first region S1.

[0151] In some embodiments, the plurality of first stack structures are arranged in the first region S1, and the first conductive structures are all arranged in the second region S2, and the second region S2 is located on at least one side of the first region S2 along a direction perpendicular to the first direction.

[0152] Here, the first region can be understood as the array region GB described above, and the second region can be understood as the connection region SS described above.

[0153] In some embodiments, along the X-axis direction, i.e., the second direction, one second region S2 is located on one side of one first region S1 (for example, the right side as shown), and all the first conductive structures are located on the same side of the first region, and the area of the second region S2 is smaller, and the area utilization rate is higher. Figure 5A The first conductive structure is connected to one first conductive layer of each of the plurality of first stack structures, and the number of first conductive layers connected by the first conductive structure is equal to the number N of decks.

[0154] In some implementations, along the X direction (the second direction), two second regions S2 are located on opposite sides of a first region S1. A portion of the first conductive structure is located on the left side of the first region S1, and a portion of the first conductive structure is located on the right side of the first region S1. Furthermore, the first conductive structures connected to all gate layers of the same deck are located on the same side of the array region, and the first conductive structures corresponding to any adjacent decks are located on different sides of the first region S1. For example, such as… Figure 5B As shown, when N=4, the first conductive structures connected to the gate layers of deck1 and deck3 are all located on the right side of the first region S1, and the first conductive structures connected to the gate layers of deck2 and deck4 are all located on the left side of the first region S1.

[0155] In some embodiments, along the X direction (the second direction), two second regions S2 are located on opposite sides of a first region S1. A portion of the first conductive structure is located on the left side of the first region S1, and a portion of the first conductive structure is located on the right side of the first region S1. Furthermore, the first conductive structures connected to all gate layers of the same deck are located on the same side of the first region S1. At least two adjacent decks may have their corresponding first conductive structures located on the same side of the first region S1. For example, as... Figure 5C As shown, when N=4, the first conductive structure connected to all gate layers of deck1 is located on the right side of the first region S1, and the first conductive structure connected to all gate layers of deck3 is located on the left side of the first region S1.

[0156] In some embodiments, along the X direction (the second direction), two second regions S2 are located on opposite sides of a first region S1, with a portion of the first conductive structure located on the left side of the first region S1 and a portion of the first conductive structure located on the right side of the first region S1. Furthermore, the first conductive structures connected to all gate layers of the same deck are located on different sides of the first region S1. For example, as... Figure 5D When N=4, the first conductive structure connected to part of the gate layer of deck1 is located on the left side of the first region S1, and the other first conductive structure connected to another part of the gate layer of deck1 is located on the right side of the first region S1. Thus, the area of ​​the second region S2 is smaller and the area utilization rate is higher.

[0157] It should be noted that in other embodiments of this application, the arrangement of the first conductive structure in the second region may also be a combination of the above-mentioned arrangement methods.

[0158] In some embodiments, the first conductive structure at least partially penetrates all the first stack structures and is connected to a gate layer of each of the first stack structures, respectively. In some embodiments, the first conductive structure can completely penetrate all the first stack structures and be connected to a gate layer of each of the first stack structures, respectively. In the embodiments of the present application, the first conductive structure can include various structural forms, some of which are described below.

[0159] In some embodiments, the cross-sectional shape of the plurality of first stack structures along the first direction includes a stepped shape; each step in the stepped shape corresponds to an adjacent first conductive layer and a first dielectric layer; and the first conductive structure extends along the first direction in the first stack structure and is connected to at least two steps where a first conductive layer of at least two first stack structures is located.

[0160] In the embodiments of the present application, the connection of the gate layers of different decks can be achieved by the stepped form, as shown in Figure 6A In the embodiments of the present application, the first conductive structure can be located in the first stack structure, that is, the second region is in the first stack structure.

[0161] It should be noted that in the embodiments of the present application, each step corresponds to a gate layer, and the arrangement form of the stepped structure is not limited and can be regular or irregularly arranged in an increasing or decreasing manner. In the embodiments of the present application, the first conductive structure can be located in the first stack structure, that is, the second region is in the first stack structure.

[0162] In some embodiments, the memory device further includes a second stack structure, the second stack structure including isolation layers and second dielectric layers arranged alternately along the first direction; the first conductive structure including a first lead-out portion and a plurality of first connection portions; the first lead-out portion extending along the first direction in the second stack structure and connected to the plurality of first connection portions; and each of the first connection portions being located in an isolation layer and connected to a first conductive layer of a corresponding first stack structure of at least two first stack structures.

[0163] In some embodiments, the material of the isolation layer includes but is not limited to silicon nitride, and the material of the second dielectric layer includes but is not limited to silicon oxide. In the embodiments of the present application, the first conductive layer and the isolation layer are arranged in the same layer, and the first dielectric layer and the second dielectric layer are arranged in the same layer. The first conductive structure can be located in the second stack structure, that is, the second region is in the second stack structure. The second stack structure can be located in the middle or on both sides of the first stack structure.

[0164] In this embodiment, the first lead-out portion may penetrate all the first stacked structures along the first direction or only penetrate to the first conductive layer that needs to be connected to the corresponding first stacked structure; the first lead-out portion may be solid or hollow; the first lead-out portion may have the same aperture or a varying aperture along the first direction.

[0165] In some embodiments, the first lead-out portion includes a dielectric structure extending along a first direction and a peripheral conductive layer surrounding the dielectric structure; the peripheral conductive layer is connected to a plurality of the first connection portions.

[0166] In this embodiment, the WL connection between different decks is achieved through a sleeve-like structure. For example, as shown... Figure 6B The first lead-out portion CT1-A can be a segmented structure. Taking three first stacked structures as an example, each first stacked structure has a gate layer connected to the same first lead-out portion CT1-A. The first lead-out portion CT1-A includes a first sub-segment, a second sub-segment, and a third sub-segment. The first sub-segment is located above the gate layer corresponding to the uppermost first stacked structure. The second sub-segment is located between the gate layer corresponding to the uppermost first stacked structure and the gate layer corresponding to the middle first stacked structure. The third sub-segment is located between the gate layer corresponding to the middle first stacked structure and the gate layer corresponding to the lowermost first stacked structure. The dimension of the first sub-segment along the second direction is larger than that of the second sub-segment along the second direction, and the dimension of the second sub-segment along the second direction is larger than that of the third sub-segment along the second direction. The gate layer corresponding to each first stacked structure is connected to a first connection portion CT1-B extending along the second direction, and is connected to the first lead-out portion CT1-A through the corresponding first connection portion CT1-B.

[0167] In some embodiments, the first lead-out portion includes a conductive post.

[0168] In this embodiment, the WL connection between different decks is achieved through SCT (Single Cross-Connect). For example, as shown... Figure 6C The first lead-out portion CT1-A includes conductive pillars extending through a plurality of second stacked structures. A gate layer of each first stacked structure is connected to a conductive pillar via a first connection portion CT1-B extending in a second direction. The conductive pillars are filled with a conductive material, such as tungsten.

[0169] In some embodiments, the memory device further includes peripheral circuitry; the peripheral circuitry includes word line driving circuitry; at least two first conductive layers of the first stacked structures are interconnected through the first conductive structures and connected to the same word line driving circuitry SD.

[0170] In the embodiments of the present application, the peripheral circuit can include a plurality of word line driving circuits, and the first conductive layers of at least two decks are interconnected in the first direction and connected to the same SD, that is, the same first conductive structure connects the interconnected plurality of gate layers in different decks to the same SD, and the interconnected plurality of gate layers can share one SD. It can be understood that the plurality of gate layers can share one SD can reduce the total number of SDs.

[0171] In some embodiments, the area where the word line driving circuit is arranged is aligned with the area where the first conductive structure is arranged in the first direction. In this way, the wiring distance between the two can be reduced, so that the resistivity between the word line driving circuit and the corresponding gate layer is smaller, the power consumption loss is smaller, and the delay is smaller.

[0172] In some embodiments, the memory device has a first number of first stack structures, and each first stack structure has a second number of first conductive layers; the memory device has a third number of word line driving circuits, and the third number is less than the product of the first number and the second number.

[0173] Here, the first number is the number of first stack structures, the second number is the number of first conductive layers contained in each first stack structure, and the third number is the number of SDs. In the embodiments of the present application without deck stacking (as shown in Figure 2A ), the number of SDs is the same as the number of WLs (gate layers). In the embodiments of the present application with deck stacking (as shown in Figure 2B , 2C , 2D), the number of SDs can be the same as the number of first conductive structures, and the number of SDs is smaller than the total number of WLs. In some embodiments, the first conductive layer is a WL, and the total number of WLs = N*SD number (the first number is the number of decks).

[0174] In some embodiments, at least one second conductive layer and a plurality of second conductive structures; one second conductive layer is connected to the channel structure of at least one first stack structure; one second conductive layer includes a plurality of bit lines spaced apart in a second direction and extending in a third direction; the second direction and the third direction are both perpendicular to the first direction; the second conductive structure extends in the first direction in the first stack structure and is connected to one bit line of the at least one second conductive layer.

[0175] In some embodiments, the plurality of first stack structures are arranged in a first region, and the plurality of second conductive structures are all arranged in a third region, and the third region is located on at least one side of the first region in the third direction.

[0176] Here, the second conductive structure is the lead-out structure corresponding to the bit line, and the structure and arrangement of the second conductive structure will be further described below.

[0177] In some embodiments, the memory device further includes a third conductive structure; the first conductive layers in the first stack structures include a top select gate layer and a gate layer; the top select gate layer is located at an end of the respective first stack structure along the first direction that is away from the semiconductor layer connected with the channel structure in the respective first stack structure; the third conductive structure extends along the first direction in the first stack structure and is connected with the top select gate layer included in at least one of the first stack structures; the first conductive structure is connected with one gate layer of at least two of the first stack structures.

[0178] In some embodiments, the first stack structures are arranged in a first region, the first conductive structures are arranged in a second region, and the third conductive structures are arranged in a fourth region; the fourth region is located between the first region and the second region.

[0179] In some embodiments, the third conductive structure includes a second lead-out portion, a second connecting portion, and a contact portion; the second lead-out portion extends along the first direction and is connected with the second connecting portion; the second connecting portion extends along a second direction and is connected with the contact portion; the contact portion extends along the first direction and is connected with the top select gate layer; the second direction is perpendicular to the first direction.

[0180] Here, the third conductive structure is a lead-out structure corresponding to the top select gate layer, and the structure and arrangement of the third conductive structure will be further described below.

[0181] In some embodiments, the first stack structures arranged in a stack form a memory surface; the memory device includes at least two memory surfaces; two of the at least two memory surfaces are arranged side by side along a second direction; the second direction is perpendicular to the first direction; the first conductive structure is located between the two memory surfaces and is connected with one first conductive layer of different first stack structures in at least one memory surface.

[0182] In the embodiments of the present application, the first conductive structure is located between the two memory surfaces, but it is not limited whether the two memory surfaces share the first conductive structure, that is, one first conductive structure can be connected with different deck-specific first conductive layers of one memory surface, and one first conductive structure can also be connected with different deck-specific first conductive layers of each memory surface in two side-by-side memory surfaces.

[0183] In some embodiments, the memory device further includes a peripheral circuit; the peripheral circuit includes a plurality of word line driving circuits; the first conductive layers of different memory surfaces at the same position along the first direction are connected with each other and connected with the same word line driving circuit.

[0184] Here, the memory surface can refer to the foregoing Figure 2EThe first conductive layers in different storage surfaces at the same position along the first direction can be understood as the first conductive layers in different storage surfaces at the same layer, the first conductive layers at the same layer are connected with the same first conductive structure, and are connected with the same SD through the same first conductive structure.

[0185] As mentioned above, each first stack structure is provided with a corresponding semiconductor layer (source layer) and a second conductive layer (a layer formed by a plurality of bit lines, hereinafter, the second conductive layer can also be referred to as a bit line layer). In the embodiments of the present application, the semiconductor layer or the second conductive layer can be shared between two first stack structures adjacent along the first direction.

[0186] In some embodiments, one of the at least one semiconductor layer is located between two adjacent first stack structures and is connected with the channel structures in the two adjacent first stack structures.

[0187] In some embodiments, one of the at least one second conductive layer is located between two adjacent first stack structures and is connected with the channel structures in the two adjacent first stack structures.

[0188] In some embodiments, as shown in Figure 7A to Figure 7B The memory device includes first stack structures located in the array region GB (the first region) and second stack structures located in the connection region SS (the second region), the first stack structures include first conductive layers and first dielectric layers stacked alternately, and the second stack structures include isolation layers and second dielectric layers stacked alternately. The first conductive layers and the isolation layers are arranged at the same layer, and the first dielectric layers and the second dielectric layers are arranged at the same layer. The memory device includes a plurality of first stack structures stacked along the first direction (deck Figure 7B 4 decks are shown in the figure), the bit line layers can be shared between two adjacent decks (such as the bit line layers between deck 2 and deck 3), the bit lines of all decks along the first direction (all bit lines connected with the same channel structure) can be interconnected, and the connection mode of the bit lines can be connected through a conductive column Figure 7A 、 Figure 7B (not shown in the figure), which can be referred to as the dashed line in Figure 6C (not shown in the figure), which can be referred to as the dashed line in

[0189] In some embodiments, the source layers ACS can be shared between two decks adjacent along the first direction, and the source layers of all decks can be interconnected or not. The source layers of all decks can be interconnected through the channel layers in the channel structures.

[0190] In some embodiments, as shown in Figure 8A to Figure 8BAs shown, the memory device includes a plurality of channel structures CH located in the array region GB (first region), the channel structure CH can extend through two adjacent deck structures, the channel structure can include a channel layer and a functional layer surrounding the channel layer, the functional layer includes a tunneling layer, a charge trapping layer and a charge blocking layer arranged from inside to outside. In some embodiments, the two ends of the channel structure are connected to a bit line BL respectively, and a common source layer ACS is provided between the two adjacent first deck structures (such as ACS between deck1 and deck2, ACS between deck3 and deck4). The material of the common source ACS includes but is not limited to polysilicon.

[0191] In some embodiments, the functional layer of the channel structure can be a discontinuous structure, the functional layer includes a first functional layer located above the common source ACS and a second functional layer located below the common source ACS, and the first functional layer and the second functional layer are isolated by the common source layer.

[0192] In some embodiments, as shown, Figure 8A to Figure 8B The bit lines BL connected to the two ends of the channel structure can be respectively led out and then connected to the peripheral circuit CMOS, or can be connected first and then led out from one side of the bit line and then connected to the peripheral circuit, or can be other ways to realize the bit line and the peripheral circuit. In some embodiments, a connection structure J is further provided between the bit line connected to the channel structure and away from the peripheral circuit and the corresponding channel structure, and the material of the connection structure can include doped polysilicon or other materials for realizing ohmic contact between the channel structure and the bit line.

[0193] In some embodiments, as shown, Figure 9A to Figure 9B As shown, the memory device further includes a plurality of second deck structures and a plurality of third deck structures on the basis of the first deck structure, the second deck structure and the third deck structure are arranged along the Y-axis direction and located in the connection region SS, the third deck structure includes a third conductive layer and a third dielectric layer stacked alternately, and the second deck structure includes an isolation layer and a second dielectric layer stacked alternately; wherein the first conductive layer, the second conductive layer and the isolation layer are in the same layer, and the first dielectric layer, the second dielectric layer and the third dielectric layer are in the same layer. The memory device can further include a gate slit structure GLS extending along the X-axis direction, and the gate slit structure extends through the third deck structure along the Z-axis direction. The memory device can further include a virtual channel structure DCH located on both sides of the GLS, and the DCH can be the same material as the CH or a different material, such as being filled with a dielectric layer.

[0194] In some embodiments, as shown, Figure 9A to Figure 9BAs shown, the first conductive structure CT1 can be connected to one first conductive layer of each of the plurality of first stack structures and one third conductive layer of each of the plurality of third stack structures. In some embodiments, the first conductive structure CT1 is further provided with an insulating medium, such that the first conductive structure CT1 is connected to one first conductive layer / third conductive layer of the first stack structure / third stack structure and is isolated from other conductive layers of the first stack structure / third stack structure.

[0195] The embodiment of the present application provides a memory device, which comprises: a plurality of first stack structures arranged in a stack; each first stack structure comprises a plurality of first conductive layers and a plurality of first dielectric layers arranged alternately along a first direction; a plurality of channel structures; each channel structure penetrates through the plurality of first stack structures; at least one semiconductor layer; each semiconductor layer is connected to a channel structure in at least one first stack structure; at least one second conductive layer; each second conductive layer is located between two adjacent first stack structures and connected to a channel structure in at least one first stack structure; each semiconductor layer and each second conductive layer connected to a channel structure in the same first stack structure are arranged on two sides of the first stack structure along the first direction respectively.

[0196] Here, the first stack structure, the first conductive layer, the first dielectric layer, the channel structure, the semiconductor layer and the second conductive layer can be understood with reference to the corresponding structures in the foregoing embodiments, which will not be described herein again.

[0197] In some embodiments, the second conductive layer comprises a plurality of bit lines spaced along a second direction and extending along a third direction; the second direction and the third direction intersect and are both perpendicular to the first direction; a plurality of second conductive structures; each second conductive structure extends along the first direction in the first stack structure and is connected to one bit line of the at least one second conductive layer.

[0198] In some embodiments, the second conductive structure comprises a conductive column extending along the first direction.

[0199] Here, the second conductive layer can be understood as a bit line layer, which can comprise a plurality of bit lines spaced along an X-axis direction and extending along a third direction, and the second conductive structure is a bit line corresponding lead-out structure. In some embodiments, the bit line lead-out structure can penetrate through one or more first stack structures in the bit line lead-out direction, that is, the bit line can be led out in the form of a through silicon contact (TSC), which penetrates through a plurality of first stack layers and is connected to a common bit line region (such as the region between deck2 and deck3 shown in Figure 7B and Figure 8B ).

[0200] In some embodiments, different bit lines connected by different first stack structures passing through the same channel structure are connected to the same second conductive structure.

[0201] Here, the same channel structure can be understood as a channel structure extending along the first direction and passing through all the first stack structures, and different bit lines connected by the same channel structure are connected to the same second conductive structure. This case can be applied to the Y-axis folding and X-Y-axis folding architectures of the memory device described in the foregoing Figure 2B and Figure 2D will be further described in the following examples.

[0202] In some specific embodiments, at least one of the plurality of second conductive layers is located between two adjacent first stack structures and connected to the channel structures in the two adjacent first stack structures.

[0203] In the embodiments of the present application, when the bit lines BL in different first stack structures are interconnected and led out, the bit line layers between two adjacent first stack structures can be shared.

[0204] In some specific embodiments, the memory device further comprises a peripheral circuit; the peripheral circuit comprises a page buffer; and the plurality of second conductive structures are connected to the same page buffer PB.

[0205] In the embodiments of the present application, when different bit lines connected by different first stack structures passing through the same channel structure are connected to the same second conductive structure, the bit lines of different decks are respectively led out to the same page buffer, and the Y-axis folding memory device architecture described in the foregoing Figure 2B can connect the plurality of second conductive structures to the same PB.

[0206] In some embodiments, different bit lines connected by different first stack structures passing through the same channel structure are connected to different second conductive structures.

[0207] Here, the same channel structure can be understood as a channel structure extending along the first direction and passing through all the first stack structures, and different bit lines connected by the same channel structure are connected to different second conductive structures. This case can be applied to the array Y-axis folding architecture and the storage surface merging architecture shown in the foregoing Figure 2C and Figure 2E will be further described in the following examples.

[0208] In some specific embodiments, the second conductive layers corresponding to different first stack structures have different sizes along the third direction; and different second conductive structures connected by the second conductive layers corresponding to different first stack structures are arranged in sequence along the third direction.

[0209] In the embodiments of the present application, when the bit lines of different first stack structures are led out respectively, the different second conductive structures connected by the second conductive layers corresponding to the different first stack structures are arranged in sequence along the third direction (i.e., the direction in which the bit lines extend). That is, the regions in which the plurality of second conductive structures corresponding to each first stack structure along the first direction are arranged are arranged in sequence along the third direction.

[0210] In some embodiments, the memory device further includes a peripheral circuit; the peripheral circuit includes a plurality of page buffers; the second conductive structures connected to the bit lines of the same second conductive layer are connected to the same page buffer in the plurality of page buffers; and the second conductive structures connected to the bit lines of different second conductive layers are connected to different page buffers in the plurality of page buffers.

[0211] In some embodiments, the regions in which the page buffers are arranged are aligned with the regions in which the plurality of first stack structures are arranged along the first direction.

[0212] In the embodiments of the present application, when the different bit lines connected by the different first stack structures that pass through the same channel structure are all connected to the same second conductive structure, the bit lines of different decks are led out to different page buffers, as described above Figure 2C In the array X-axis direction folding architecture shown in the embodiments of the present application, the plurality of second conductive structures can be connected to different PBs. At this time, the number of PBs can be the same as the number of decks, and the bit lines of the same deck are led out to the same PB.

[0213] In some embodiments, the plurality of first stack structures are arranged in the first region, and the plurality of second conductive structures are arranged in the third region, and the third region is located on at least one side of the first region along the third direction.

[0214] In the embodiments of the present application, the region in which the first stack structures are arranged is the first region, the region in which the second conductive structures (i.e., the bit line leading-out structures) are arranged is the third region, and the second region in which the first conductive structures (i.e., the word line leading-out structures) are arranged is the second region. The second region and the third region are located on different sides of the first region, specifically, the second region is located on at least one side of the first region along the second direction, and the third region is located on at least one side of the first region along the third direction.

[0215] It can be understood that, for Figure 2B In the array Y-axis direction folding architecture shown in the embodiments of the present application, compared with the non-folding memory device architecture shown in Figure 2A In the array Y-axis direction folding architecture shown in the embodiments of the present application, compared with the non-folding memory device architecture shown in Figure 2C In the array X-axis direction folding architecture shown in the embodiments of the present application, compared with the non-folding memory device architecture shown in Figure 2AThe unfolded memory device architecture is shown, and the number of BLs becomes 1 / N (e.g., the number of BLs is (130K-160K) / N, where N is the number of decks. For Figure 2D The array X-axis+Y-axis folding architecture is shown, and the number of BLs is the same as Figure 2C The array X-axis folding architecture is shown, and the number of BLs is the same, but the lead-out structures corresponding to the bit lines and the lead-out structures corresponding to the top selection gate layers are different.

[0216] In some embodiments, the plurality of first stack structures arranged in a stack constitute a memory module; the memory device includes at least two memory modules; two of the at least two memory modules are arranged in a stack along a first direction; the memory device further includes fourth conductive structures; different bit lines corresponding to different first stack structures passing through the same channel structure are connected to different second conductive structures; and the plurality of second conductive structures corresponding to the specified first stack structures in different memory modules passing through the same channel structure are connected to each other through the fourth conductive structures.

[0217] Here, the description of the memory module can refer to the foregoing Figure 2D description of the memory module. In the embodiments of the present application, in the same memory module, different bit lines corresponding to a channel structure in different decks are led out respectively, and in different memory modules, different bit lines corresponding to a channel structure in a specified deck are led out together.

[0218] Here, the specified deck is related to the folding rule. Taking the folding in the X-axis direction first and then in the Y-axis direction as an example, referring to the left half of Figure 3C , in Model 1 and Model 2, different bit lines corresponding to a channel structure in different decks are led out respectively, the deck corresponding to the left one in Model 1 and the deck corresponding to the left one in Model 2 are two decks from which the specified bit lines are led out together, the deck corresponding to the left two in Model 1 and the deck corresponding to the left two in Model 2 are two decks from which the specified bit lines are led out together, the deck corresponding to the left three in Model 1 and the deck corresponding to the left three in Model 2 are two decks from which the specified bit lines are led out together, and the deck corresponding to the left four in Model 1 and the deck corresponding to the left four in Model 2 are two decks from which the specified bit lines are led out together.

[0219] In the embodiments of the present application, the second conductive structures of the two decks from which the specified bit lines are led out together are connected through the fourth conductive structures, and the fourth conductive structures are on any one side of the plurality of first stack structures along the first direction.

[0220] In some embodiments, at least one of the plurality of semiconductor layers is located between two adjacent first stack structures and connected to the channel structure in each of the two adjacent first stack structures.

[0221] In some embodiments, two adjacent first stack structures form a stack structure group; the memory device includes a plurality of semiconductor layers; the plurality of semiconductor layers are respectively located between two adjacent first stack structures in a plurality of stack structure groups; and the plurality of semiconductor layers are connected to each other.

[0222] Here, the semiconductor layers can be understood with reference to the structural features of the semiconductor layers in the foregoing embodiments, which will not be described herein again.

[0223] In some embodiments, the memory device further includes a first conductive structure; the first conductive structure extends along the first direction and is connected to one of the first conductive layers in each of at least two of the plurality of first stack structures.

[0224] Here, the first conductive structures can be understood with reference to the structural features of the first conductive structures in the foregoing embodiments, which will not be described herein again.

[0225] In some embodiments, the memory device further includes a third conductive structure; the plurality of first conductive layers in the first stack structure include a top select gate layer and a gate layer; the top select gate layer is located at one end of the corresponding first stack structure along the first direction, which is away from the semiconductor layer connected to the channel structure in the corresponding first stack structure; the third conductive structure extends along the first direction in the first stack structure and is connected to the top select gate layer included in at least one of the plurality of first stack structures; and the first conductive structure is connected to one of the gate layers in each of at least two of the plurality of first stack structures.

[0226] Here, the third conductive structure is an extraction structure corresponding to the top select gate layer, and the structural form and setting position of the third conductive structure will be further described below.

[0227] The embodiment of the present application provides a memory device, which comprises: a plurality of first stack structures arranged in a stack; the first stack structure comprises a plurality of first conductive layers and a plurality of first dielectric layers arranged alternately in a first direction; the plurality of first conductive layers in the first stack structure comprise a top selection gate layer and a gate layer; the top selection gate layer is located at one end of the corresponding first stack structure in the two ends in the first direction, and the one end is far away from a semiconductor layer connected with a channel structure in the corresponding first stack structure; a plurality of channel structures; the channel structure penetrates the plurality of first stack structures; at least one semiconductor layer; one semiconductor layer is connected with the channel structure in at least one first stack structure; a third conductive structure, the third conductive structure extends in the first direction in the first stack structure and is connected with the top selection gate layer included in at least one first stack structure in the plurality of first stack structures.

[0228] Here, the first stack structure, the first conductive layer, the first dielectric layer, the channel structure, the semiconductor layer, and the like can be understood with reference to the corresponding structure in the foregoing embodiment, and details are not described herein.

[0229] In the embodiment of the present application, the third conductive structure is a lead-out structure corresponding to the top selection gate layer, and the top selection gate layer in the first stack structure can comprise one layer or multiple layers; when comprising multiple layers, the multiple layers can be led out together or separately. In the embodiment of the present application, the third conductive structure penetrates the plurality of first stack structures deck, and the third conductive structure is electrically connected with the TSG layer of at least one deck.

[0230] In some embodiments, the memory device further comprises a top selection gate isolation structure; the top selection gate isolation structure divides the top selection gate layer into a plurality of sub-top selection gate layers; different sub-top selection gate layers included in the same top selection gate layer are connected with different third conductive structures.

[0231] Here, the extension direction of the top selection gate isolation structure TSGCUT is similar to that of the gate slit structure GLS shown in the foregoing Figure 9A , Figure 9B More specifically, the top isolation structure penetrates the top selection gate layer in the first conductive layer of each first stack structure. Exemplarily, the top selection gate layer comprises one layer or three layers.

[0232] In the embodiment of the present application, the top selection gate isolation structure divides the top selection gate layer into a plurality of sub-top selection gate layers, and a channel structure corresponding to each sub-top selection gate layer forms a storage string. Different sub-top selection gate layers connected with different storage strings are connected with different third conductive structures.

[0233] It should be noted that the bit line and the top selection gate layer are connected to the channel structure, and the selection and cancellation of the connected channel structure can be realized. The difference between the two is that the bit line extends along the third direction and connects a channel structure column, and the channel structure column includes a plurality of channel structures arranged along the third direction; the top selection gate connects a plurality of channel structure rows, and each channel structure row includes a plurality of channel structures arranged along the second direction. Based on the selection function of the channel structure of the bit line and the top selection gate layer, in order to save the layout area of the corresponding lead-out structure of the two, the corresponding lead-out structure of the two can be considered to be comprehensively laid out under different storage architectures.

[0234] It should be noted that the top selection gate layer is used to select the string, and the bottom selection gate layer can actually play the same role. Based on this, the top selection gate layer in the embodiment of the application can be replaced by the bottom selection gate layer without conflict. In some embodiments, different top selection gate layers included in different first stack structures are connected with different third conductive structures. In the embodiment of the application, the top selection gate layers of different decks are led out respectively. It should be noted that the top selection gate layers of different decks can be led out respectively for the four storage device architectures described above. The lead-out structures corresponding to the bit lines of different decks are connected together, such as the above-mentioned Figure 2B The array Y-axis direction folding architecture shown must lead out the top selection gate layers of different decks respectively to realize the selection and cancellation of the sub-channel structures in different decks. Here, the number of first stack structures is N, and the channel structure includes N sub-channel structures corresponding to N first stack structures.

[0235] In some embodiments, the storage device further includes a plurality of second conductive layers and a plurality of second conductive structures; one second conductive layer is connected with the channel structure of at least one first stack structure; one second conductive layer includes a plurality of bit lines, and each bit line is connected with a column of channel structures; the second conductive structure extends in the first direction in the first stack structure and is connected with one bit line of at least one second conductive layer.

[0236] Here, the second conductive layer can be understood as a bit line layer, and the bit line layer can include a plurality of bit lines spaced along the X-axis direction and extending along the third direction, and the second conductive structure is the lead-out structure corresponding to the bit line. The specific features of the second conductive layer and the second conductive structure can be understood with reference to the description in the foregoing embodiments, which will not be repeated here.

[0237] In some specific embodiments, the different bit lines corresponding to the different first stack structures through the same channel structure are connected with different second conductive structures; and the different top selection gate layers included in the different first stack structures are connected with the same third conductive structure.

[0238] In the embodiments of the present application, the bit lines of different decks are led out respectively (as described above Figure 2C In the illustrated array X-axis folding architecture, the top selection gate layers of different decks can be led out together. In this way, the sub-channel structures in different decks can be selected and deselected respectively, and the layout area of the corresponding leading-out structure of the top selection gate layer can be saved compared with the separate leading-out of the top selection gate layers of different decks.

[0239] In some embodiments, the plurality of first stack structures arranged in layers constitutes one storage surface; the memory device includes at least two storage surfaces; the two storage surfaces in the at least two storage modules are arranged side by side along a second direction; the second direction is perpendicular to the first direction; the memory device further includes a first conductive structure; the first conductive structure is located between the two storage surfaces, and the first conductive structure is connected to one gate layer of each of the different first stack structures in the at least one storage surface.

[0240] In the embodiments of the present application, the first conductive structure is located between the two storage surfaces, but it is not limited whether the two storage surfaces share the first conductive structure, that is, one first conductive structure can connect the different deck first conductive layers of one storage surface, and one first conductive structure can also connect the different deck first conductive layers of each storage surface in the two storage surfaces arranged side by side.

[0241] In some embodiments, the memory device further includes a peripheral circuit; the peripheral circuit includes a plurality of word line driving circuits; the first conductive layers of different storage surfaces at the same position in the layering direction of the first stack structures are connected to each other and connected to the same word line driving circuit.

[0242] Here, the description of the storage surface can refer to the foregoing Figure 2E The first conductive layers of different storage surfaces at the same position in the first direction can be understood as the first conductive layers at the same layer in different storage surfaces, the first conductive layers at the same layer are connected to the same first conductive structure, and are connected to the same SD through the same first conductive structure.

[0243] In some embodiments, the different bit lines corresponding to the different first stack structures penetrated by the same channel structure are connected to different second conductive structures; the different top selection gate layers included in the different first stack structures in the same storage surface are connected to the same third conductive structure; and the different top selection gate layers included in the first stack structures at the same position in the first direction of different storage surfaces are connected to different third conductive structures.

[0244] In the embodiments of the present application, the top selection gate layers of different decks in the same storage surface are led out together; the top selection gate layers of different storage surfaces are led out respectively, and the top selection gate layers of different storage surfaces in the same layer are also led out respectively.

[0245] It should be noted that the above leading-out schemes of the bit lines and the top selection gate layers are applicable to the array X-axis direction folding architecture in each storage surface. When the array Y-axis direction folding architecture is used in each storage surface, the top selection gate layers of different decks in the same storage surface are led out respectively; the top selection gate layers of different storage surfaces are led out respectively.

[0246] In some embodiments, the plurality of first stack structures arranged in layers form one storage module; the memory device includes at least two storage modules; the at least two first storage modules are arranged in layers in a first direction; the memory device further includes a first conductive structure; the first conductive structure is connected to one gate layer of each first stack structure in the two storage modules.

[0247] Here, the description of the storage module can be referred to the foregoing description of the storage module in the foregoing Figure 2D The first conductive structure can be understood with reference to the structural features of the first conductive structure in the foregoing embodiments, which will not be described herein again.

[0248] In some embodiments, the memory device further includes a fourth conductive structure; different bit lines corresponding to different first stack structures passing through the same channel structure in the same storage module are connected to different second conductive structures; two bit lines corresponding to two first stack structures in different storage modules are connected to each other through the fourth conductive structure; different top selection gate layers included in different first stack structures in the same storage module are connected to the same third conductive structure; two top selection gate layers included in two first stack structures in different storage modules are connected to different third conductive structures.

[0249] In the embodiments of the present application, the array X-axis direction folding and then Y-axis direction folding architecture is applicable. In the same storage module, different bit lines corresponding to different decks of one channel structure are led out respectively, and different top selection gate layers corresponding to different decks are led out together; in different storage modules, different bit lines corresponding to different decks of one channel structure are led out together, and different top selection gate layers corresponding to different decks are led out respectively.

[0250] Here, the specified deck is related to the folding rule. For example, the X-axis direction folding and then Y-axis direction folding, which can be referred to the foregoing Figure 3CThe left half of the figure, the channel structure in Model 1 and Model 2 is respectively led out in different decks corresponding to different bit lines. The left one in Model 1 corresponds to the deck in Model 2, and the two decks are led out together with the specified bit line. The left two in Model 1 corresponds to the deck in Model 2, and the two decks are led out together with the specified bit line. The left three in Model 1 corresponds to the deck in Model 2, and the two decks are led out together with the specified bit line. The left four in Model 1 corresponds to the deck in Model 2, and the two decks are led out together with the specified bit line.

[0251] In some embodiments, the fourth conductive structure is located on one side of the region where the second conductive structure is located along the first direction; the two second conductive structures corresponding to the two first stack structures of the specified two in different storage modules are connected to each other through the fourth conductive structure.

[0252] In the embodiments of the present application, the second conductive structures of the two decks led out together with the specified bit line are connected through the fourth conductive structure, and the fourth conductive structure is located on any one side of the two sides of the plurality of first stack structures along the first direction.

[0253] In some embodiments, the different bit lines corresponding to the different first stack structures penetrated by the same channel structure in the same storage module are all connected to the same second conductive structure; the different bit lines corresponding to the two first stack structures in different storage modules are all connected to different second conductive structures; the different top selection gate layers included in the different first stack structures in the same storage module are connected to different third conductive structures; and the two top selection gate layers included in the two first stack structures in different storage modules are connected to the same third conductive structure.

[0254] In the embodiments of the present application, the array is folded in the Y-axis direction first and then in the X-axis direction. In the same storage module, the different bit lines corresponding to the channel structure in different decks are led out together, and the different top selection gate layers corresponding to the channel structure in different decks are led out respectively; in different storage modules, the different bit lines corresponding to the channel structure in different decks are led out respectively, and the different top selection gate layers corresponding to the channel structure in different decks are led out together.

[0255] It should be noted that, for the same array X direction + Y direction folding architecture, X axis direction folding first and then Y axis direction folding and Y axis direction folding first and then X axis direction folding are different due to different folding modes, and the corresponding bit line and top selection gate layer lead-out modes are also different. The bit line and top selection gate layer lead-out modes are related to the folding rule. Specifically, when X axis direction folding is performed, the number of bit lines of each deck after folding does not change compared to before folding, at this time, the one-channel structure needs to be respectively led out at the bit lines of different decks, and the top selection gate layers of different decks can be respectively led out; when Y axis direction folding is performed, the number of bit lines of each deck after folding changes to 1 / N (N is the number of decks) compared to before folding, at this time, the one-channel structure can be led out together at the bit lines of different decks, and the top selection gate layers of different decks need to be respectively led out.

[0256] In some embodiments, the plurality of first stack structures are disposed in the first region, the first conductive structures are each disposed in the second region, and the third conductive structures are each disposed in the fourth region; the fourth region is located between the first region and the second region.

[0257] Here, the first region and the second region can be understood with reference to the first region and the second region in the foregoing embodiments, and the fourth region where the third conductive structure, i.e., the top selection gate layer, is located is between the first region and the second region. In some embodiments, the second region is located in the middle of the first region, and then the fourth region can be divided into two parts, which are both located at positions close to the second region on both sides of the second region along the second direction.

[0258] In some embodiments, the third conductive structure includes a second lead-out part, a second connection part, and a contact part; the second lead-out part extends along the first direction and is connected with the second connection part; the second connection part extends along a direction perpendicular to the first direction and is connected with the contact part; and the contact part extends along the first direction and is connected with the top selection gate layer.

[0259] Here, the third conductive structure is a lead-out structure corresponding to the top selection gate layer, and the structure form of the third conductive structure will be further described below.

[0260] In some embodiments, each first stack structure includes a plurality of top selection gate layers, and a cross-sectional shape of the plurality of top selection gate layers along the first direction includes a stepped shape; each step in the stepped shape corresponds to one top selection gate layer; and one contact part is connected to the step where one top selection gate layer is located.

[0261] In this embodiment, each first stacked structure comprises multiple top-select gate layers. If the voltage strategies applied to these multiple layers are the same, the multiple layers can be brought out together; if the voltage strategies applied to these multiple layers are different, the multiple layers can be brought out separately. In one embodiment, the multiple layers can form a stepped structure, the stepped structure being step-like, each step including a top-select gate layer, and a third conductive structure can be connected to each step.

[0262] In some embodiments, at least one semiconductor layer is located between two adjacent first stacked structures and is connected to the channel structures in both adjacent first stacked structures.

[0263] Here, the semiconductor layer can be understood with reference to the structural features of the semiconductor layer in the foregoing embodiments, and will not be repeated here.

[0264] In some embodiments, the memory device further includes a first conductive structure; the first conductive structure extends along a first direction and is connected to a gate layer of at least two of the plurality of first stacked structures.

[0265] Here, the first conductive structure can be understood with reference to the structural features of the first conductive structure in the aforementioned embodiments, and will not be repeated here.

[0266] Figure 10A A layout diagram of the array of storage devices and peripheral circuitry provided for embodiments of this application. Figure 1 ; Figure 10B A top view of the lead-out structure of the deck 1 including the storage device, BL, and TSG, provided in an embodiment of this application. Figure 1 ; Figure 10C A top view of the BL and TSG lead-out structure of the deck 2, which includes the storage device, provided in an embodiment of this application. Figure 1 ; Figure 10D A cross-sectional view of the lead-out structure of the BL including the storage device provided in the embodiments of this application. Figure 1 ; Figure 10E A cross-sectional view of the lead-out structure of a TSG including a storage device provided in an embodiment of this application. Figure 1 .

[0267] Figure 11A A second schematic diagram showing the layout of an array of storage devices and peripheral circuitry provided for an embodiment of this application; Figure 11B A top view of the BL lead-out structure of each deck including the storage device, provided for an embodiment of this application; Figure 11C A top view schematic diagram 2 of the lead-out structure of the BL of each deck including the storage device provided in the embodiments of this application; Figure 11DFIG. 2 is a cross-sectional view of the lead-out structure of the TSG of each deck including the memory device according to an embodiment of the disclosure; Figure 11E FIG. 2 is a cross-sectional view of the lead-out structure of the TSG of each deck including the memory device according to an embodiment of the disclosure.

[0268] Figure 12A FIG. 4 is a layout diagram of the array and the peripheral circuit including the memory device according to an embodiment of the disclosure; Figure 12B FIG. 5 is a top view of the BL lead-out structure of each deck including the memory device according to an embodiment of the disclosure; Figure 12C FIG. 5 is a top view of the BL lead-out structure of each deck including the memory device according to an embodiment of the disclosure. Figure 12D FIG. 6 is a cross-sectional view of the lead-out structure of the TSG of each deck including the memory device according to an embodiment of the disclosure; Figure 12E FIG. 6 is a cross-sectional view of the lead-out structure of the TSG of each deck including the memory device according to an embodiment of the disclosure.

[0269] Figure 13A FIG. 4 is a layout diagram of the array and the peripheral circuit including the memory device according to an embodiment of the disclosure; Figure 13B FIG. 5 is a top view of the BL lead-out structure of each deck including the memory device according to an embodiment of the disclosure; Figure 13C FIG. 5 is a top view of the BL lead-out structure of each deck including the memory device according to an embodiment of the disclosure. Figure 13D FIG. 5 is a top view of the BL lead-out structure of each deck including the memory device according to an embodiment of the disclosure. Figure 13E FIG. 5 is a top view of the BL lead-out structure of each deck including the memory device according to an embodiment of the disclosure. Figure 13F FIG. 6 is a cross-sectional view of the lead-out structure of the TSG of each deck including the memory device according to an embodiment of the disclosure.

[0270] The following will be described in detail with reference to Figure 10A to Figure 10E , Figure 11A to Figure 11E , Figure 12A to Figure 12E , Figure 13A to Figure 13F The implementation of the BL lead-out structure (second conductive structure) and the TSG lead-out structure (third conductive structure) will be described in detail with reference to the following embodiments.

[0271] The memory device according to an embodiment of the disclosure is provided for the array Y-axis folding architecture as described above, and the BL lead-out structure (second conductive structure) and the TSG lead-out structure (third conductive structure) are as follows. Figure 10A to Figure 10EIn this embodiment, the original array is divided along the Y-axis and stacked to form a memory array Array by sharing a gate layer WL. This Array includes an array region GB and a connection region SS. In some embodiments, along the X-axis, the connection region is located in the middle of the memory array Array, or between two array regions. Figure 10A (This is illustrated in the image). In some implementations, along the X direction, the connection region can be located at the edge of the array, on one side of the array region, such as at the left or right edge of the array structure.

[0272] In this embodiment, the Array may include multiple first conductive structures CT1, which may be located in the connection region, i.e., the second region S2. Each deck has a gate layer WL that can be connected to a first conductive structure CT1. The second region S2 may include a stepped structure, or it may not have a stepped structure, or other connection structures that can lead out the gate layer WL.

[0273] In this embodiment, the memory device further includes peripheral circuitry CMOS. The array and CMOS can be combined through bonding or other methods. The peripheral circuitry may include word line driver circuitry SD and page cache PB; wherein, SD may include multiple circuits, each SD as follows: Figure 10A A small cuboid ( Figure 10A The diagram illustrates two SDs. Each first conductive structure CT1 can be connected to one SD, and the setting area of ​​the SD can be located directly above the connection area SS, while the setting area of ​​PB can be located above the array area GB. This reduces the need for wiring and lowers the difficulty of manufacturing.

[0274] In this embodiment of the application, the Array includes a storage block, which includes a plurality of first stacked structures decks stacked along the Z-axis direction. Figure 10A The diagram illustrates N decks (deck1-deckN), each first stacked structure including a top selected gate layer (TSG). Each structure includes at least one top selected gate isolation (TSG CUT) extending along the X-axis. The TSG CUT extends along the Z-axis through the TSG, dividing it into multiple sub-top selected gate layers. Each top selected gate layer corresponds to a memory chip string. Figure 10B , Figure 10C The diagram illustrates P strings, i.e., string1-stringP. The material of the TSG CUT includes, but is not limited to, silicon oxide.

[0275] In the embodiments of this application, such as Figure 10B , Figure 10CAs shown, the memory device includes a plurality of bit lines BL extending along the Y-axis direction and spaced along the X-axis direction, each bit line BL being connected with each channel structure in a column of channel structures CH. The lead-out structure corresponding to the bit line, i.e., the second conductive structure CT2, is arranged in the third region S3, and each bit line is further extended along the direction in which it extends, and the further extended part is connected with the second conductive structure CT2. In the embodiment of the application, the different bit lines connected with one channel structure in different decks are led out together, i.e., connected to the page buffer PB in the peripheral circuit through the same second conductive structure. One memory block in the embodiment of the application can include one page buffer PB.

[0276] In the embodiment of the application, as shown in Figure 10D , the second conductive structure CT2 connects the different bit lines connected with one channel structure in different decks through the conductive structure similar to the channel structure morphology, and is connected to the part of the PB not embodied in the PB Figure 10D . It should be noted that Figure 10D , only the case where the memory device includes two decks is shown, and the case of multiple decks can be analogized according to the figure.

[0277] In the embodiment of the application, as shown in Figure 10B , Figure 10C , the TSGs of different decks are led out through different third conductive structures CT3. The third conductive structure CT3 includes a second lead-out part TSGTSC, a second connection part B, and a contact part TSGCT; the second lead-out part TSGTSC extends along the Z-axis direction and is connected with the second connection part B; the second connection part B extends along a direction perpendicular to the Z-axis direction and is connected with the contact part TSGCT; the contact part TSGCT extends along the Z-axis direction and is connected with the top select gate layer. The second lead-out part TSGTSC extends along the Z-axis direction through all the decks, and the TSGCTs of each deck can be arranged in alignment along the first direction, and the projections of all the TSGCTs of the decks in the same string on a plane perpendicular to the Z-axis direction overlap. The TSGCTs are connected with the second lead-out part TSC through the conductive structure extending along the X-axis direction, and the TSGCTs of different decks in the same string are connected with the same TSGTSC. The materials of the TSGCT, B, and TSGTSC include but are not limited to tungsten. The number of TSGTSCs is greater than or equal to the number of decks.

[0278] In the embodiment of the application, as shown in Figure 10B , taking deck1 as an example, deck1 can include a plurality of sub-TSGs, and the plurality of sub-TSGs can correspond to connect different TSGCTs respectively, different TSGCTs connect the same TSGTSC, or different TSGCTs can also connect different TSGTSCs Figure 10E , which is shown in the embodiment of the application.Figure 10E for Figure 10B (Cross-sectional view corresponding to X3-X3′). In other embodiments, deck 1 further includes a TSG connected to a TSGCT, which is connected to the TSGSC via a second connecting part B.

[0279] In the example of the facilities in this application, such as Figure 10C As shown, taking deck2 as an example, deck2 can include several sub-TSGs, and these sub-TSGs can be connected to different TSGCTs. Different TSGCTs can be connected to the same TSG SC, or different TSGCTs can be connected to different TSG SCs. Figure 10E (This situation is illustrated in the diagram). In other embodiments, deck 1 further includes a TSG connected to a TSGCT, which is connected to the TSGSC via a second connection part B.

[0280] It should be noted that, in Figure 10B and Figure 10C In this embodiment, the TSGCT is connected to different TSGTSCs via a second connecting portion B extending in the opposite direction (B along the X-axis + in deck 1, B along the X-axis - in deck 2). It can be understood that, for deck 3, the TSGCT is connected to different TSGTSCs via a second connecting portion B extending along the Y-axis + direction. The specific extension direction of the second connecting portion B mentioned above is not intended to limit the extension direction of the second connecting portion B in this embodiment, but only to illustrate that in different decks, the TSGCT can be connected to different TSGTSCs via second connecting portions B extending in different directions.

[0281] This application provides a storage device for the aforementioned array X-axis folding architecture, such as... Figure 11A to Figure 11E In this embodiment, the original array is divided along the X-axis and stacked to form a memory array Array by sharing a gate layer WL. This Array includes an array region GB and a connection region SS. In some embodiments, along the X-axis, the connection region is located in the middle of the memory array Array, or between two array regions. Figure 11A (This is illustrated in the image). In some implementations, along the X direction, the connection region can be located at the edge of the array, on one side of the array region, such as at the left or right edge of the array structure.

[0282] In the embodiments of the present application, the array can include a plurality of first conductive structures CT1, the first conductive structures CT1 can be located in the connection region, i.e., the second region S2, and each deck has a gate layer WL which can be commonly connected to a first conductive structure CT1. The second region S2 can include a stepped structure or can not include a stepped structure, or other connection structures which can realize the leading-out of the gate layer WL.

[0283] In the embodiments of the present application, the memory device further includes a peripheral circuit CMOS, and the array and the CMOS can be combined by bonding or other manners. The peripheral circuit can include a word line driving circuit SD and a page buffer PB; wherein the PB and the SD can include a plurality of, such as PB1 to PBN, and the bit lines of each deck in the N decks are respectively connected to a PB; each SD such as Figure 11A is a small cuboid Figure 11A Two SDs are schematically shown in FIG. 1. Each first conductive structure CT1 can correspond to connect one SD, and the setting region of the SD can be located directly above the connection region SS, and the setting region of the PB can be located above the array region GB, so that the wire winding can be reduced, and the process manufacturing difficulty can be reduced.

[0284] In the embodiments of the present application, as shown in FIG. 2, the array includes a plurality of first stacked structures decks stacked along the Z-axis direction Figure 11A In the embodiments of the present application, as shown in FIG. 2, the array includes a plurality of first stacked structures decks stacked along the Z-axis direction Figure 11A N decks, i.e., deck1-deckN, are schematically shown in FIG. 2, and each deck corresponds to connect a second conductive layer, i.e., a bit line layer BL1-BLN, and the PB can include a plurality of, such as PB1-PBN. The bit lines BL of different stacked structures are respectively led out to the corresponding PB, such as the bit line layer BL1 of deck1 is connected with PB1, and the bit line BLN of deckN is connected with PBN. It should be noted that Figure 11A In the embodiments of the present application, as shown in FIG. 2, the array includes a plurality of first stacked structures decks stacked along the Z-axis direction

[0285] In the embodiments of the present application, as shown in FIG. 2, the array includes a plurality of first stacked structures decks stacked along the Z-axis direction Figure 11B As shown in FIG. 2, the lengths of the bit line layers BL1-BLN corresponding to each deck along the extension direction thereof can be different, and based on this, from the top view shown in FIG. 2 along the Y-axis direction, the adjacent two bit line layers are disconnected. Figure 11B As shown in FIG. 2, the lengths of the bit line layers BL1-BLN corresponding to each deck along the extension direction thereof can be different, and based on this, from the top view shown in FIG. 2 along the Y-axis direction, the adjacent two bit line layers are disconnected. Figure 11CBL1-BL4 in FIG. 1 can see the length change of the bit line in the bit line layer corresponding to different decks from another perspective. In this way, the leading out of the second conductive structure can be facilitated. It should be noted that the bit line of deck 1 can be located at the top layer of all first stack structures, and it can not be necessary to set the second conductive structure to lead it out. Based on this, in the embodiment of the present application, the second conductive structure CT2 is set to extend through all decks between the top of the bit line BL and the structure, and the bit line of deck 1 is led out from the top of the first stack structure. Figure 11B In the embodiment of the present application, the bit line in BL1 is connected to the channel structure CH, and the bit line in BL2-BLN is connected to the second conductive structure CT2.

[0286] As shown in FIG. 1, the bit line of deck 1 is led out from the top of the first stack structure, and the second conductive structure CT2 connected to the bit line of deck 1 extends through all decks between the top of the bit line BL and the structure. Figure 11C As shown in FIG. 1, the bit line of deck 1 is led out from the top of the first stack structure, and the second conductive structure CT2 connected to the bit line of deck 1 extends through all decks between the top of the bit line BL and the structure.

[0287] As shown in FIG. 1, the bit line of deck 1 is led out from the top of the first stack structure, and the second conductive structure CT2 connected to the bit line of deck 1 extends through all decks between the top of the bit line BL and the structure. Figure 11D As shown in FIG. 1, the bit line of deck 1 is led out from the top of the first stack structure, and the second conductive structure CT2 connected to the bit line of deck 1 extends through all decks between the top of the bit line BL and the structure.

[0288] As shown in FIG. 1, the bit line of deck 1 is led out from the top of the first stack structure, and the second conductive structure CT2 connected to the bit line of deck 1 extends through all decks between the top of the bit line BL and the structure. Figure 11D As shown in FIG. 1, the bit line of deck 1 is led out from the top of the first stack structure, and the second conductive structure CT2 connected to the bit line of deck 1 extends through all decks between the top of the bit line BL and the structure.

[0289] As shown in FIG. 1, the bit line of deck 1 is led out from the top of the first stack structure, and the second conductive structure CT2 connected to the bit line of deck 1 extends through all decks between the top of the bit line BL and the structure. Figure 11D , Figure 11E As shown in FIG. 1, the bit line of deck 1 is led out from the top of the first stack structure, and the second conductive structure CT2 connected to the bit line of deck 1 extends through all decks between the top of the bit line BL and the structure. Figure 11E As shown in FIG. 1, the bit line of deck 1 is led out from the top of the first stack structure, and the second conductive structure CT2 connected to the bit line of deck 1 extends through all decks between the top of the bit line BL and the structure. Figure 11DThe TSGs of different decks are led out through the same third conductive structure CT3. The third conductive structure CT3 includes a second leading-out part TSGTSC, a second connecting part B, and a contact part TSGCT; the second leading-out part TSGTSC extends along the Z-axis direction and is connected with the second connecting part B; the second connecting part B extends along a direction perpendicular to the Z-axis direction and is connected with the contact part TSGCT; the contact part TSGCT extends along the Z-axis direction and is connected with the top select gate layer. The second leading-out part TSGTSC extends along the Z-axis direction through all the decks, and the TSGCTs of each deck can be arranged in alignment along the first direction, and the projections of the TSGCTs of all the decks in the same string on a plane perpendicular to the Z-axis direction overlap. The TSGCT is connected with the second leading-out part TSGTSC through a conductive structure extending along the X-axis direction, and the TSGCTs of different decks in the same string are connected with the same TSGTSC. The materials of the TSGCT, B, and TSGTSC include but are not limited to tungsten. The number of TSGTSCs is greater than or equal to the number of decks.

[0290] In the facility example of the present application, as shown in FIG. 1, for deck1-deckN, each deck can include one TSG, and the TSGs of different decks can be connected with different TSGCTs. Figure 11D In other embodiments, each deck can also include one TSG, and the TSG is connected with the TSGCT, and the TSGCT is connected with the TSGTSC through the second connecting part B.

[0291] In the facility example of the present application, as shown in FIG. 1, for deck1-deckN, each deck can include one TSG, and the TSGs of different decks can be connected with different TSGCTs. Figure 11E In other embodiments, each deck can also include one TSG, and the TSG is connected with the TSGCT, and the TSGCT is connected with the TSGTSC through the second connecting part B.

[0292] The storage device provided in the embodiments of the present application is for the aforementioned storage face merging architecture. As described above, each of the two merged storage faces can be an array X-axis direction folding architecture, an array Y-axis direction folding architecture, or an array X-axis direction+Y-axis direction folding architecture. Hereinafter, only an example in which each of the two merged storage faces is an array X-axis direction folding architecture is described.

[0293] As shown in FIG. 1, the TSGs of different decks are led out through the same third conductive structure CT3. The third conductive structure CT3 includes a second leading-out part TSGTSC, a second connecting part B, and a contact part TSGCT; the second leading-out part TSGTSC extends along the Z-axis direction and is connected with the second connecting part B; the second connecting part B extends along a direction perpendicular to the Z-axis direction and is connected with the contact part TSGCT; the contact part TSGCT extends along the Z-axis direction and is connected with the top select gate layer. The second leading-out part TSGTSC extends along the Z-axis direction through all the decks, and the TSGCTs of each deck can be arranged in alignment along the first direction, and the projections of the TSGCTs of all the decks in the same string on a plane perpendicular to the Z-axis direction overlap. The TSGCT is connected with the second leading-out part TSGTSC through a conductive structure extending along the X-axis direction, and the TSGCTs of different decks in the same string are connected with the same TSGTSC. The materials of the TSGCT, B, and TSGTSC include but are not limited to tungsten. The number of TSGTSCs is greater than or equal to the number of decks. Figure 12A to Figure 12EIn this embodiment of the application, the memory device includes a memory array Array, which includes two memory surfaces and a connection region SS located between the two memory surfaces. The two memory surfaces share a gate WL. Each memory surface includes multiple first stacked structures deck. Each deck has a bit line layer BL (i.e., a second semiconductor layer) and a source layer ACS respectively disposed on both sides along a first direction. In some embodiments, two adjacent decks along the Z-axis alternately share the bit line layer BL and the source layer ACS.

[0294] In the embodiments of this application, such as Figure 12A The array can include multiple first conductive structures CT1, which can be located in the connection region, i.e., the second region S2. Each deck has a gate layer WL that can be connected to a first conductive structure CT1. The second region S2 can include a stepped structure, or it can be without a stepped structure, or other connection structures that can lead out the gate layer WL.

[0295] In this embodiment, the memory device further includes peripheral circuitry CMOS. The array and CMOS can be combined through bonding or other methods. The peripheral circuitry may include word line driver circuitry SD and page caches PB; wherein, PB and SD may include multiple PBs, such as PB1 to PBN, with the bit lines of each of the N decks connected to one PB; each SD, such as... Figure 12A A small cuboid ( Figure 12A The diagram illustrates two SDs. Each first conductive structure CT1 can be connected to one SD, and the setting area of ​​the SD can be located directly above the connection area SS. The setting area of ​​PB can be located above the storage surface. This reduces the need for wiring and lowers the difficulty of manufacturing.

[0296] Figure 12B , Figure 12C You can refer to this. Figure 11B , Figure 11C The details are not elaborated here.

[0297] In this embodiment, the Array includes a storage block, which includes multiple first stacked structures decks stacked along the Z-axis. Each first stacked structure includes a top selected gate layer (TSG). The structure includes at least one top selected gate isolation structure (TSG CUT) extending along the X-axis through the top selected gate layer (TSG), dividing the TSG into multiple sub-top selected gate layers. Each top selected gate layer corresponds to a memory string. Figure 12D The diagram illustrates P strings, i.e., string1-stringP. The material of the TSG CUT includes, but is not limited to, silicon oxide.

[0298] In some embodiments of the application, as shown in Figure 12D , Figure 12E Figure 12E As shown in the cross-sectional view of X5-X5' in Figure 12D , the TSGs of different decks are led out through the same third conductive structure CT3. The third conductive structure CT3 includes a second leading-out portion TSGTSC, a second connecting portion B, and a contact portion TSGCT; the second leading-out portion TSGTSC extends along the Z-axis direction and is connected with the second connecting portion B; the second connecting portion B extends along a direction perpendicular to the Z-axis direction and is connected with the contact portion TSGCT; the contact portion TSGCT extends along the Z-axis direction and is connected with the top select gate layer. The second leading-out portion TSGTSC extends along the Z-axis direction through all the decks, and the TSGCTs of each deck can be arranged in alignment along the first direction, and the projections of the TSGCTs of all the decks in the same string on a plane perpendicular to the Z-axis direction overlap. The TSGCT is connected with the second leading-out portion TSGTSC through a conductive structure extending along the X-axis direction, and the TSGCTs of different decks in the same string are connected with the same TSGTSC. The materials of the TSGCT, B, and TSGTSC include but are not limited to tungsten. The number of TSGTSCs is greater than or equal to the number of decks.

[0299] In some embodiments of the application, as shown in Figure 12E , for deck1-deckN, each deck can include one sub-TSG, and the plurality of sub-TSGs form a ladder structure, and the cross-sectional shape of the ladder structure along the first direction is step-shaped; each step in the ladder structure corresponds to one top select gate layer; one contact portion TSGCT is connected to the step where the top select gate layer is located. The plurality of sub-TSGs can correspond to different TSGCTs respectively, and the plurality of TSGCTs in the same string can be connected to the same second leading-out portion TSGTSC, or can be connected to different second leading-out portions TSGTSC (as shown in Figure 12D , three contact portions TSGCTs in the same string are connected to different second leading-out portions TSGTSCs respectively).

[0300] It should be noted that the second connecting portion B for connecting the contact portion TSGCT and the second leading-out structure TSGTSC is shown in Figure 12D , and the second connecting portion B is not shown in Figure 12E due to the problem of cross-sectional view angle.

[0301] ​Embodiments of the present application provide a memory device, for the array X-axis direction + Y-axis direction folding architecture as described above, the array X-axis direction + Y-axis direction folding architecture can be X-axis direction folding first and then Y-axis direction folding, or Y-axis direction folding first and then X-axis direction folding. Hereinafter, only the case of X-axis direction folding first and then Y-axis direction folding is taken as an example for description.

[0302] As Figure 13A to Figure 13F , in the embodiments of the present application, the memory array Array is formed by stacking the original array after being divided along the X-axis direction and the Y-axis direction, and sharing the gate layer WL, the Array includes the array region GB and the connection region SS. In some embodiments, along the X-axis direction, the connection region is located in the middle of the memory array Array, and the connection region is located between the two array regions (as shown in the figure). Figure 13A In some embodiments, along the X-axis direction, the connection region can be located at the edge of the Array, and the connection region is located on one side of the array region, such as the left edge or the right edge of the array structure.

[0303] In the embodiments of the present application, as Figure 13A , the Array includes a plurality of storage modules Model (Model1-ModelM are shown in the figure, M is a positive integer greater than or equal to 2), each Model includes a plurality of first stacked structures deck (N decks are shown in the figure, each Model includes N decks, N is a positive integer greater than or equal to 2). Figure 13A Each deck is provided with a bit line layer BL (BL1-BLN are shown in the figure, the bit line layers of the N decks included in each Model) on both sides along the first direction, that is, the second semiconductor layer and the source layer ACS, in some embodiments, two decks adjacent along the Z-axis direction alternately share the bit line layer BL and the source layer ACS. Each deck is connected with a second conductive layer, that is, a bit line layer. Figure 13A Figure 13A In the embodiments of the present application, as , the Array can also include a plurality of first conductive structures CT1, the first conductive structure CT1 can be located in the connection region, that is, the second region S2, and each deck has a gate layer WL which can be commonly connected to a first conductive structure CT1. The second region S2 can include a stepped structure, or can not include a stepped structure, or other connection structures that can realize the lead-out of the gate layer WL.

[0304] Figure 13A

[0305] ​​In the embodiments of the present application, the memory device further comprises a peripheral circuit CMOS, and the Array and the CMOS can be combined by bonding or other means. The peripheral circuit can comprise a word line driving circuit SD and a page buffer PB; wherein the PB and the SD can comprise a plurality of, such as PB1 to PBN, and the bit lines of each deck of the N decks of each memory module are respectively connected to a corresponding PB, for example, the bit line layer BL1 of deck1 is connected to PB1, and the bit line BLN of deckN is connected to PBN. The bit lines of the same deck of different memory modules Model are connected in parallel to the corresponding PB, for example, the bit line layer BL1 of deck1 of Model1 and the bit line layer BL1 of deck1 of Model1 are both connected to PB1. The bit lines of deckN of each memory module are all connected to PBN. Each SD is as follows Figure 13A A small cuboid is shown in the middle Figure 13A Two SDs are shown in the middle. Each first conductive structure CT1 can correspond to connect one SD, and the setting area of the SD can be located directly above the connection area SS, and the setting area of the PB can be located above the storage surface, so that the winding can be reduced, and the process manufacturing difficulty can be reduced.

[0306] In the embodiments of the present application, in the same memory module, a channel structure in different decks corresponds to different bit lines respectively; in different memory modules, a channel structure in a specified deck corresponds to different bit lines together.

[0307] In the embodiments of the present application, as shown in Figure 13B The lengths of the bit line layers BL1-BLN corresponding to each deck in each Model along the extension direction thereof can be different, and based on this, from the top view shown in Figure 13B The adjacent two bit line layers are disconnected along the Y-axis direction. Figure 13C The lengths of the bit lines in the bit line layers corresponding to different decks in Model1 and Model2 in Figure 13B The bit lines in BL1 of Model1 are connected to the channel structure CH, and the bit lines in the other bit line layers (BL2-BLN) of Model1 and the bit lines in all bit line layers (BL1-BLN) of Model2 are connected to the second conductive structure CT2.

[0308] In the embodiments of the present application, as shown in Figure 13CAs shown, the bit lines of all decks are drawn from the same side, such as from the top of the first stack structure, and the second conductive structures CT2 connected to the bit lines of the decks extend through all the decks between the bit lines BL and the top of the structure. For example, in Model 1, the second conductive structure CT2 connected to the bit line layer BL2 of deck 2 extends through deck 2 and deck 1, and the second conductive structure CT2 connected to the bit line layer BL4 of deck 4 extends through all the decks; in Model 2, the second conductive structure CT2 connected to the bit line layer BL1 of deck 1 extends through all the decks of Model 1, and the second conductive structure CT2 connected to the bit line layer BL4 of deck 4 extends through all the decks of Model 1 and all the decks of Model 2. In other embodiments, the bit lines of all the decks can also be drawn from the bottom of the first stack structure, and the bit lines BL and the second conductive structures CT2 can also have other drawing manners.

[0309] In the embodiments of the present application, as shown in Figure 13C The Array can also include a plurality of fourth conductive structures CT4, each of which is arranged at the top of all the first stack structures, and each of which is used to connect the second conductive structures CT2 of the specified two decks in two different Models, such as a CT4 connecting the second conductive structures CT2 of deck 1 of Model 1 and the second conductive structures CT2 of deck 1 of Model 2. In some embodiments, the fourth conductive structure CT4 can include a combination of a plurality of conductive structures extending in different directions. In other embodiments, the plurality of fourth conductive structures CT4 can also be arranged at the bottom of all the first stack structures.

[0310] In the embodiments of the present application, the Array includes a storage block Block, which includes a plurality of first stack structures decks stacked along the Z-axis direction, each of which includes a top selection gate layer TSG, and the structure includes at least one top selection gate isolation structure TSG CUT extending along the X direction, which extends through the top selection gate layer TSG along the Z-axis direction to divide the TSG into a plurality of sub-top selection gate layers, each of which corresponds to a storage string (string) Figure 13D 、 Figure 13E P strings, i.e. string1-stringP, are shown in the middle). The material of the TSG CUT includes but is not limited to silicon oxide.

[0311] In the embodiments of this application, in the same memory module, the different top selected gate layers corresponding to a channel structure in different decks are led out together; in different memory modules, the different top selected gate layers corresponding to a channel structure in different decks are led out separately.

[0312] In the example of the facilities in this application, such as Figure 13D , Figure 13E As shown, TSGs from different decks are led out through the same third conductive structure CT3. The third conductive structure CT3 includes a second lead-out portion TSGTSC, a second connection portion B, and a contact portion TSGCT. The second lead-out portion TSGTSC extends along the Z-axis and is connected to the second connection portion B. The second connection portion B extends along a direction perpendicular to the Z-axis and is connected to the contact portion TSGCT. The contact portion TSGCT extends along the Z-axis and is connected to the top select gate layer. The second lead-out portion TSGTSC extends along the Z-axis through all decks. The TSGCTs of each deck can be aligned along a first direction, and the projections of the TSGCTs of all decks in the same string overlap on a plane perpendicular to the Z-axis. The TSGCTs are connected to the second lead-out portion TSGTSC through conductive structures extending along the X-axis. The TSGCTs of different decks in the same string are connected to the same TSGTSC. The materials of TSGCT, B, and TSGTSC include, but are not limited to, tungsten. The number of TSGTSCs is greater than or equal to the number of decks.

[0313] In the example of the facilities in this application, such as Figure 13D As shown, taking Model 1 as an example, each deck in deck 1-deck N of Model 1 can include several sub-TSGs. Multiple sub-TSGs can be connected to different TSGCTs, and different TSGCTs can be connected to the same TSG SC, or different TSGCTs can be connected to different TSG SCs. Figure 13D (This situation is illustrated in the diagram). In other embodiments, deck 1 further includes a TSG connected to a TSGCT, which is connected to the TSGSC via a second connection part B.

[0314] In the example of the facilities in this application, such as Figure 13E As shown, taking Model 2 as an example, each deck in deck 1-deck N of Model 2 can include several sub-TSGs. Multiple sub-TSGs can also be connected to different TSGCTs. Different TSGCTs can be connected to the same TSG GTSC, or different TSGCTs can be connected to different TSG GTSCs. Figure 13EIn some embodiments, deck1 further comprises a TSG connected to TSGCT, and TSGCT is connected to TSGTSC through a second connection B.

[0315] It should be noted that, in Figure 13D and Figure 13E , TSGCT is connected to different TSGTSC through second connection B extending in opposite directions (B along X axis + in Model 1, and B along X axis - in Model 2). It can be understood that, for different Models, TSGCT is connected to different TSGTSC through second connection B extending in different directions. The specific extension directions of the above-mentioned second connection B are not used to limit the extension directions of the second connection B in the embodiments of the present application, but only to illustrate that, in different Models, TSGCT can be connected to different TSGTSC through second connection B extending in different directions.

[0316] In the embodiments of the present application, as Figure 13F ( Figure 13F As shown in the cross-sectional view corresponding to X6-X6' in Figure 13D , for deck1-deckN in Model 1, different decks can be connected to the same second lead-out TSGTSC through different contact TSGCT and different second connection B; for deck1-deckN in Model 2, different decks can be connected to the same second lead-out TSGTSC through different contact TSGCT and different second connection B; wherein the second lead-out TSGTSC in Model 1 can be different from the second lead-out TSGTSC in Model 2, the second lead-out TSGTSC in Model 1 can only pass through each deck in Model 1, or pass through each deck in Model 1 and Model 2; the second lead-out TSGTSC in Model 2 passes through each deck in Model 1 and Model 2.

[0317] The embodiments of the present application provide a memory device, which comprises:

[0318] a plurality of first stack structures arranged in a stack; each of the first stack structures comprises a plurality of first conductive layers and a plurality of first dielectric layers arranged alternately along a first direction; a plurality of first conductive structures, each of the first conductive structures is connected to one of the first conductive layers of at least two of the first stack structures; a plurality of channel structures, each of the channel structures penetrates through the plurality of first stack structures; at least one semiconductor layer and at least one second conductive layer; the semiconductor layer and the second conductive layer are located on two sides of one of the first stack structures along the first direction respectively and are connected to the channel structures in the one of the first stack structures; each of the second conductive layers comprises a plurality of bit lines arranged in a second direction and extending in a third direction; the second direction and the third direction are perpendicular to the first direction; a plurality of second conductive structures, each of the second conductive structures is connected to one of the bit lines of the at least one second conductive layer.

[0319] In some embodiments, different bit lines corresponding to different first stack structures penetrated by the same channel structure are connected to the same second conductive structure.

[0320] In some embodiments, the at least one semiconductor layer is located between two adjacent first stack structures and connected to the channel structures in the two adjacent first stack structures.

[0321] In some embodiments, the memory device further comprises a peripheral circuit; the peripheral circuit comprises a page buffer; the plurality of second conductive structures are connected to the same page buffer.

[0322] In some embodiments, different bit lines corresponding to different first stack structures penetrated by the same channel structure are connected to different second conductive structures.

[0323] In some embodiments, the size of the second conductive layer corresponding to different first stack structures along the third direction is different; different second bit lines connected by the second conductive layer corresponding to different first stack structures are arranged in sequence along the third direction.

[0324] In some embodiments, the memory device further comprises a peripheral circuit; the peripheral circuit comprises a plurality of page buffers; the second conductive structure connected to the bit line of the same second conductive layer is connected to the same page buffer in the plurality of page buffers; the second conductive structure connected to the bit line of different second conductive layers is connected to different page buffers in the plurality of page buffers.

[0325] In some embodiments, the at least one semiconductor layer is located between two adjacent first stack structures and connected to the channel structures in the two adjacent first stack structures.

[0326] In some embodiments, two adjacent first stack structures in the plurality of first stack structures form a stack structure group; the memory device includes a plurality of semiconductor layers; the plurality of semiconductor layers are respectively located between two adjacent first stack structures in the plurality of stack structure groups; and the plurality of semiconductor layers are connected to each other.

[0327] In some embodiments, a cross-sectional shape of the plurality of first stack structures along the first direction comprises a stepped shape; each step in the stepped shape corresponds to one adjacent first conductive layer and one adjacent first dielectric layer; and the first conductive structure extends along the first direction in the first stack structure and is connected to at least two steps in which one first conductive layer of at least two first stack structures is located.

[0328] In some embodiments, the memory device further includes a second stack structure including a plurality of isolation layers and a plurality of second dielectric layers alternately arranged; the first conductive structure includes a first lead-out portion and a plurality of first connection portions; the first lead-out portion is connected to the plurality of first connection portions in the second stack structure along the first direction; and each first connection portion is located in one isolation layer and connected to one first conductive layer of a corresponding first stack structure in the at least two first stack structures.

[0329] In some embodiments, the first conductive structure is connected to one first conductive layer in each first stack structure that is the same distance from a semiconductor layer connected to a channel structure of the corresponding first stack structure.

[0330] In some embodiments, the first conductive structure is connected to one first conductive layer in each first stack structure that is a different distance from a semiconductor layer connected to a channel structure of the corresponding first stack structure.

[0331] In some embodiments, the memory device further includes a peripheral circuit; the peripheral circuit includes a plurality of word line driving circuits; and one first conductive layer of the at least two first stack structures is connected to each other through the first conductive structure and connected to the same word line driving circuit.

[0332] In some embodiments, the memory device further includes a plurality of third conductive structures; the first conductive layer in the first stack structure includes a top select gate layer and a gate layer; the top select gate layer is located at one end of the corresponding first stack structure along the first direction that is away from the semiconductor layer connected to the channel structure in the corresponding first stack structure; the third conductive structure extends along the first direction in the first stack structure and is connected to the top select gate layer included in at least one first stack structure in the plurality of first stack structures; and the first conductive structure is connected to one gate layer of at least two first stack structures in the plurality of first stack structures.

[0333] In some embodiments, the memory device further comprises a top select gate isolation structure; the top select gate isolation structure divides the top select gate layer into a plurality of sub-top select gate layers; different sub-top select gate layers included in a same top select gate layer are connected with different third conductive structures.

[0334] In some embodiments, different top select gate layers included in different first stack structures are connected with different third conductive structures; different bit lines corresponding to different first stack structures penetrating a same channel structure are connected with a same second conductive structure.

[0335] In some embodiments, different bit lines corresponding to different first stack structures penetrating a same channel structure are connected with different second conductive structures.

[0336] Different top select gate layers included in different first stack structures are connected with a same third conductive structure.

[0337] In some embodiments, the plurality of first stack structures arranged in a stack constitute a memory surface; the memory device comprises a first memory surface and a second memory surface; the first memory surface and the second memory surface are arranged side by side along a second direction; the memory device further comprises a plurality of word line driving circuits; the plurality of first conductive structures are located between the first memory surface and the second memory surface, and each of the first conductive structures is connected with a gate layer of a different first stack structure in at least one memory surface; the first conductive layers at the same position in the first direction of the first memory surface and the second memory surface are connected with each other and connected with a same word line driving circuit.

[0338] In some embodiments, different bit lines corresponding to different first stack structures penetrating a same channel structure are connected with different second conductive structures; different top select gate layers included in different first stack structures in a same memory surface are connected with a same third conductive structure; different top select gate layers included in first stack structures at the same position in the first direction of different memory surfaces are connected with different third conductive structures.

[0339] In some embodiments, the plurality of first stack structures arranged in a stack constitute a memory module; the memory device comprises a first memory module and a second memory module; the first memory module and the second memory module are arranged in a stack along a first direction; the plurality of first conductive structures are connected with a gate layer of each first stack structure in the first memory module and the second memory module.

[0340] In some embodiments, different bit lines corresponding to different first stack structures penetrating the same channel structure in the same storage module are connected with different second conductive structures; two bit lines corresponding to two first stack structures in different storage modules are connected with each other; different top select gate layers included in different first stack structures in the same storage module are connected with the same third conductive structure; two top select gate layers included in two first stack structures in different storage modules are connected with different third conductive structures.

[0341] In some embodiments, different bit lines corresponding to different first stack structures penetrating the same channel structure in the same storage module are connected with the same second conductive structure; different bit lines corresponding to two first stack structures in different storage modules are connected with different second conductive structures; different top select gate layers included in different first stack structures in the same storage module are connected with different third conductive structures; two top select gate layers included in two first stack structures in different storage modules are connected with the same third conductive structure.

[0342] In some embodiments, the plurality of first stack structures are arranged in the first region, the plurality of first conductive structures are arranged in the second region, the plurality of second conductive structures are arranged in the third region, and the plurality of third conductive structures are arranged in the fourth region; the second region is located in the middle of the first region; or the second region is located on at least one side of the first region in a direction perpendicular to the stacking direction; the third region is located on at least one side of the first region in the third direction; and the fourth region is located between the first region and the second region.

[0343] It should be noted that the relative position relationship between the two regions in the above embodiments of the present application is not limited to the ownership relationship between the two regions. That is, the side of the region in the embodiments of the present application can be understood as being at one end or edge of the region (i.e., belonging to the region), or can be understood as being beside or next to the region (i.e., belonging to another region).

[0344] It should be noted that the above embodiments of the present application can be understood with reference to the descriptions of the corresponding structures in the foregoing embodiments.

[0345] In the embodiments of the present application, the first conductive structure CT1 is connected to any one of the gate layers WL in each deck of the plurality of first stacked structures deck. The first conductive structure CT1 can be located in the first stacked structure or the second stacked structure. The first conductive structure CT1 can partially or completely penetrate the first stacked structure or the second stacked structure. The first conductive structure CT1 can be located in the middle or at the edge of the first stacked structure. The plurality of gate layers of the first stacked structure can form a stepped structure or be flush along a plane perpendicular to the first direction (the direction in which the WL extends). The first conductive structure CT1 can include a conductive column or a hollow conductive layer, and selectively include a first connecting part perpendicular to the first direction. The first conductive structure CT1 connects any one of the gate layers WL in each deck of the plurality of first stacked structures deck to the word line driving circuit SD.

[0346] In the embodiments of the present application, the first conductive structure CT1 is connected to any one of the gate layers WL in each deck of the plurality of first stacked structures deck. Therefore, the total number of the gate layers included in one memory block is equal to the product of the number of decks and the number of the word line driving circuits SD corresponding to the memory block.

[0347] In the embodiments of the present application, for a certain fixed storage capacity, if the number of bit lines corresponding to one memory block in the unfolded architecture (as shown in FIG. 1) is Q (where Q is a positive integer), then the total number corresponding to one memory block in the array Y-axis folding architecture (as shown in FIG. 2) is still Q. Figure 2A In the embodiments of the present application, for a certain fixed storage capacity, if the number of bit lines corresponding to one memory block in the unfolded architecture (as shown in FIG. 1) is Q (where Q is a positive integer), then the total number corresponding to one memory block in the array Y-axis folding architecture (as shown in FIG. 2) is still Q. Figure 2B In the embodiments of the present application, for a certain fixed storage capacity, if the number of bit lines corresponding to one memory block in the unfolded architecture (as shown in FIG. 1) is Q (where Q is a positive integer), then the total number corresponding to one memory block in the array Y-axis folding architecture (as shown in FIG. 2) is still Q. Figure 2C In the embodiments of the present application, for a certain fixed storage capacity, if the number of bit lines corresponding to one memory block in the unfolded architecture (as shown in FIG. 1) is Q (where Q is a positive integer), then the total number corresponding to one memory block in the array Y-axis folding architecture (as shown in FIG. 2) is still Q. Figure 2D In the embodiments of the present application, for a certain fixed storage capacity, if the number of bit lines corresponding to one memory block in the unfolded architecture (as shown in FIG. 1) is Q (where Q is a positive integer), then the total number corresponding to one memory block in the array Y-axis folding architecture (as shown in FIG. 2) is still Q. Figure 2E In the embodiments of the present application, for a certain fixed storage capacity, if the number of bit lines corresponding to one memory block in the unfolded architecture (as shown in FIG. 1) is Q (where Q is a positive integer), then the total number corresponding to one memory block in the array Y-axis folding architecture (as shown in FIG. 2) is still Q.

[0348] In the embodiments of the present application, each deck is interconnected by the source layer ACS and the bit line layer BL, and two decks form a two-stack architecture. Two stacks and two stacks can be mixed to form a multi-stack architecture, or two adjacent decks share the bit line layer BL or share ACS in sequence to form a plurality of multi-stack architectures. In this way, the problem of channel saturation current reduction caused by too many gate layers in the non-folded architecture can be improved, and the corresponding bit line layer BL and ACS can be saved, thereby reducing the manufacturing cost.

[0349] In the embodiments of the present application, the BLs of all decks are connected to the page buffer PB in the peripheral circuit through the second conductive structure CT2. The specific morphology of the second conductive structure CT2 can be a circular, rectangular or channel structure CH-shaped conductive column or directly arranged in the GLS.

[0350] In the embodiments of the present application, the parameters of the memory device under various architectures are shown in Table 1. It should be noted that the various parameters and quantities in Table 1 can be understood with reference to the descriptions of the various parameters and quantities mentioned above. The storage block size and array efficiency can be calculated according to the calculation method described above.

[0351] In Table 1, RS represents the resistance of the entire gate layer (WL). In the X-axis folding, multi-storage surface combination and X+Y-axis folding scheme, the resistance of the entire gate layer is significantly reduced compared to the resistance of the entire gate layer in the non-folding scheme. In this way, the delay can be reduced, thereby improving the speed of read and write operations.

[0352] As can be seen from Table 1, compared with the non-folding scheme, various folding schemes can at least one of reduce the storage block size or improve the array efficiency. The Y folding scheme mainly improves the array efficiency, the X folding scheme mainly reduces the storage block size, and the X+Y-axis folding scheme both reduces the storage block size and improves the array efficiency.

[0353] Table 1

[0354]

[0355] In the embodiments of the present application, the four folding architectures can solve the problem of channel saturation current reduction with the increase of the number of stacked layers. In the array Y-axis folding architecture, the WLs of N decks are shared, so that the SDs can be shared, thereby reducing the total number of SDs, i.e., reducing the area occupied by the SDs, and finally reducing the area of the memory device. In the array X-axis folding architecture, by reducing the BL to 1 / N, the WLs of N decks share the SD area by N times, the CHIP*die size is reduced by 1 / N, the storage block size is reduced by 1 / N, and the WL RC is reduced by 1 / N 2Storage plane combined architecture: further reduces SD area, improves array efficiency, and reduces storage device area; array X-axis + Y-axis folding architecture, which combines the advantages of array Y-axis folding architecture and array X-axis folding architecture.

[0356] In this embodiment, a channel structure runs through all the first stacked structure decks. The portion of the channel structure corresponding to each deck is called a sub-channel structure. During the execution of a read operation or a programming operation (or write operation), each sub-channel structure can be selected and deselected through the semiconductor layer (source layer ACS) and the second conductive layer (bit line layer BL) of the corresponding deck.

[0357] It should be noted that during each read operation, one sub-channel structure within a channel structure is the selected sub-channel group structure. The BL and TSG corresponding to this selected group channel structure are both selected BL (SelBL) and selected TSG (SelTSG). All other sub-channel groups within the same channel structure are unselected sub-channel groups, and their corresponding BL and TSG are both unselected BL (unSelBL) and selected TSG (unSelTSG). In each deck, the selected gate layer is SelWL, and the unselected gate layer is unSelWL.

[0358] In this application embodiment, the architecture of the aforementioned four types of folded storage devices is abstracted into two main categories: the first category: the BL of each deck is interconnected and the TSG is brought out separately; the second category: the TSG of each deck is interconnected and the BL is brought out separately.

[0359] Figure 14A A layout diagram of functional layers coupled to a storage device via a single-channel structure provided in this application embodiment. Figure 1 ; Figure 14B This is a schematic diagram of the voltage applied to each functional layer in the selected subchannel structure during the read operation provided in the embodiments of this application. Figure 1 ; Figure 14C This is a schematic diagram illustrating the application of voltage to each functional layer in the unselected subchannel structure during the read operation provided in this embodiment of the application. Figure 1 ; Figure 14D A schematic diagram of the voltage applied to each functional layer in the selected subchannel structure during the programming operation provided in this application embodiment. Figure 1 ; Figure 14E This is a schematic diagram illustrating the application of voltage to each functional layer in the unselected subchannel structure during the read operation provided in this embodiment of the application. Figure 1 .

[0360] Figure 15AFig. 2 is a layout diagram of a functional layer coupled to a channel structure of a memory device according to an embodiment of the present disclosure; Figure 15B Fig. 6 is a diagram of voltages applied to functional layers in a selected sub-channel structure during a read operation according to an embodiment of the present disclosure; Figure 15C Fig. 7 is a diagram of voltages applied to functional layers in an unselected sub-channel structure during a read operation according to an embodiment of the present disclosure; Figure 15D Fig. 8 is a diagram of voltages applied to functional layers in a selected sub-channel structure during a program operation according to an embodiment of the present disclosure; Figure 15E Fig. 9 is a diagram of voltages applied to functional layers in an unselected sub-channel structure during a program operation according to an embodiment of the present disclosure.

[0361] The following will describe in detail the implementation of the read operation and the write operation of the two categories respectively. Figures 14A-14E Figures 15A-15E The control method of the memory device according to an embodiment of the present disclosure includes: during a read operation, applying a first voltage to a top select gate of an unselected sub-channel structure and / or a bit line coupled thereto, and applying a second voltage to a top select gate of a selected sub-channel structure and a bit line coupled thereto; applying a pass voltage to all unselected gate layers, and applying a read voltage to a selected gate layer.

[0362] In the embodiments of the present disclosure, the first voltage and the second voltage are different when the architecture of the memory device is in different categories based on the difference in the application object. However, the voltages applied to all unselected gate layers and the selected gate layer are unchanged when the architecture of the memory device is in different categories.

[0363] It should be noted that there is no selected gate layer in the unselected sub-channel structure, but considering the sharing of the gate layers between multiple decks, the gate layer connected to the selected gate layer in the selected sub-channel structure in the unselected sub-channel structure is also referred to as the selected gate layer. For the unselected sub-channel structure, since the channel is in the cancellation gating state, even if the gate layer is applied with the read voltage, the read operation will not be performed.

[0364] It should be noted that there is no selected gate layer in the unselected sub-channel structure, but considering the sharing of the gate layers between multiple decks, the gate layer connected to the selected gate layer in the selected sub-channel structure in the unselected sub-channel structure is also referred to as the selected gate layer. For the unselected sub-channel structure, since the channel is in the cancellation gating state, even if the gate layer is applied with the read voltage, the read operation will not be performed.

[0365] ​In some embodiments, the plurality of first conductive layers in the first stack structure further comprises a bottom select gate layer; the bottom select gate layer is located at one end of the corresponding first stack structure close to the semiconductor layer connected with the channel structure in the corresponding first stack structure along the first direction; the control method further comprises: during the reading operation, the second conduction voltage is applied to all the bottom select gate layers.

[0366] In the embodiments of the present application, the memory device comprises N (such as three) first stack structures, and for the first type: the BLs of each deck are interconnected and the TSGs are separately led out, as shown in the following figure, from top to bottom, comprising a first first stack structure deck1, a second first stack structure deck2 and a third first stack structure deck3, deck1 and deck2 share a source layer Source, deck2 and deck3 share a bit line layer BL, each first stack structure comprises a top select gate TSG, a plurality of gate layers and a bottom select gate BSG, and the plurality of gate layers are schematically shown as WL1 and WL2. The WL1s of all the first stack structures are interconnected, the WL2s are interconnected, the BLs are interconnected, the BSGs are interconnected, the Sources are interconnected, and the TSGs are separately led out. Figure 14A

[0367] In some embodiments, the first voltage comprises a cutoff voltage, and the second voltage comprises a first conduction voltage; the first voltage is applied to the top select gate of the unselected sub-channel structure and / or the bit line coupled thereto, and the second voltage is applied to the top select gate of the selected sub-channel structure and the bit line coupled thereto, comprising: applying a cutoff voltage to the top select gate of the unselected sub-channel structure, and applying a first conduction voltage to the top select gate of the selected sub-channel structure.

[0368] In the embodiments of the present application, as shown in the following figure, Figure 14B Figure 14C , a cutoff voltage such as a ground voltage is applied to the top select gate unSel TSG in the unselected sub-channel structure, so that the unselected sub-channel structure is in a cancel conduction state; a first conduction voltage such as a voltage greater than the threshold voltage of the top select transistor is applied to the top select gate Sel TSG in the selected sub-channel structure, so that the selected sub-channel structure is in a conduction state. In addition, the bottom select gate BSG and the unselected gate layer Unsel WL apply a second conduction voltage, the source layer applies a ground voltage, and the selected gate layer Sel WL applies a reading voltage, and then the BL current is read and the storage state of the storage unit Cell is judged. Here, the first conduction voltage can be the same as or different from the second conduction voltage. The reading voltage can comprise a first order or a plurality of orders as shown in Figure 14B Figure 14C

[0369] ​​​​In the embodiments of the present application, the memory device includes N (e.g., three) first stack structures, for the first type: the TSG of each deck is interconnected and the BL is separately led out, as shown in FIG. 1, from top to bottom, including a first first stack structure deck1, a second first stack structure deck2, and a third first stack structure deck3, deck1 and deck2 share a source layer Source, each first stack structure includes a top select gate TSG, a plurality of gate layers, and a bottom select gate BSG, the plurality of gate layers are schematically shown as WL1 and WL2. The WL1 of all first stack structures are interconnected, the WL2 are interconnected, the TSG are interconnected, the BSG are interconnected, the Source are interconnected, and the BL are separately led out. Figure 15A

[0370] In some embodiments, the first voltage includes a program inhibit voltage, and the second voltage includes a program enable voltage; the applying the first voltage to the top select gate of the unselected sub-channel structure and / or the bit line coupled thereto, and the applying the second voltage to the top select gate of the selected sub-channel structure and the bit line coupled thereto, includes: applying the program inhibit voltage to the bit line coupled to the unselected sub-channel structure, and applying the program enable voltage to the bit line coupled to the selected sub-channel structure; and the applying the first conduction voltage to all top select gate layers.

[0371] In the embodiments of the present application, as shown in FIG. 1, Figure 15B Figure 15C , the program inhibit voltage is applied to the bit line unSel BL in the unselected sub-channel structure, so that the unselected sub-channel structure is in the cancel conduction state; the program enable voltage is applied to the bit line Sel BL in the selected sub-channel structure, so that the selected sub-channel structure is in the conduction state. In addition, the second conduction voltage is applied to the bottom select gate BSG and the unselected gate layer Unsel WL, the source layer is applied with a ground voltage, the selected gate layer Sel WL is applied with a read voltage, and then the BL current is read and the storage state of the storage unit Cell is determined. Here, the first conduction voltage can be the same as or different from the second conduction voltage. The read voltage can include a first order or multiple orders as shown in Figure 15B Figure 15C

[0372] ​​​​The embodiment of the present application provides a control method of a memory device, the memory device comprising the memory device provided by the embodiment of the present application, a channel structure is divided into a plurality of sub-channel structures by a plurality of first stack structures; a plurality of first conductive layers in the first stack structure comprises a top selection gate layer and a gate layer; the top selection gate layer is located at one end of the corresponding first stack structure away from the end of the corresponding first stack structure connected to the channel structure of the semiconductor layer along the first direction; the control method of the memory device comprises: in the process of performing a programming operation, a first voltage is applied to the top selection gate of the unselected sub-channel structure in the plurality of sub-channel structures and / or the bit line coupled thereto, and a second voltage is applied to the top selection gate of the selected sub-channel structure in the plurality of sub-channel structures and the bit line coupled thereto; a pass voltage is applied to all unselected gate layers, and a programming voltage is applied to the selected gate layer.

[0373] In the embodiment of the present application, for the architecture of the memory device in different categories, the first voltage and the second voltage will be different based on the difference of the application object. However, for the architecture of the memory device in different categories, the voltages applied to all unselected gate layers and the selected gate layer are unchanged.

[0374] It should be noted that for the unselected sub-channel structure, there is no selected gate layer, but considering the sharing of the gate layer between the decks, the gate layer connected to the selected gate layer in the selected sub-channel structure in the unselected sub-channel structure is also called the selected gate layer. For the unselected sub-channel structure, since the channel is in the cancellation of the gating state, even if the gate layer is applied with the programming voltage, the programming operation will not be performed.

[0375] In some embodiments, the plurality of first conductive layers in the first stack structure further comprises a bottom selection gate layer; the bottom selection gate layer is located at one end of the corresponding first stack structure close to the end of the corresponding first stack structure connected to the channel structure of the semiconductor layer along the first direction; the control method further comprises: in the process of performing a programming operation, a cutoff voltage is applied to all bottom selection gate layers.

[0376] In the embodiment of the present application, the memory device comprises N (such as three) first stack structures, for the first type: the BL of each deck is interconnected and the TSG is separately led out, such as Figure 14AAs shown, from top to bottom, the first, second and third first stack structures deck1, deck2 and deck3 are included in sequence, deck1 and deck2 share the source layer Source, deck2 and deck3 share the bit line layer BL, each first stack structure includes a top select gate TSG, a plurality of gate layers and a bottom select gate BSG, the plurality of gate layers are schematically shown as WL1 and WL2. The WL1 of all first stack structures are interconnected, the WL2 are interconnected, the BL are interconnected, the BSG are interconnected, the Source are interconnected, and the TSG are separately led out respectively.

[0377] In some embodiments, the first voltage includes a cutoff voltage, and the second voltage includes a turn-on voltage; the applying the first voltage on the top select gate of the unselected sub-channel structure and / or the bit line coupled thereto, and the second voltage on the top select gate of the selected sub-channel structure and the bit line coupled thereto, includes: applying the cutoff voltage on the top select gate of the unselected sub-channel structure, and applying the turn-on voltage on the top select gate of the selected sub-channel structure.

[0378] In the embodiments of the present application, as Figure 14D 、 Figure 14E , the cutoff voltage such as ground voltage is applied to the top select gate unSel TSG in the unselected sub-channel structure, so that the unselected sub-channel structure is in the cancel-on state; the first turn-on voltage such as a voltage greater than the threshold voltage of the top select transistor is applied to the top select gate Sel TSG in the selected sub-channel structure, so that the selected sub-channel structure is in the on state. In addition, the bottom select gate BSG applies a cutoff voltage such as a ground voltage, the unselected gate layer Unsel WL applies a second turn-on voltage, the source layer applies a ground voltage, the selected gate layer Sel WL applies a programming voltage, and then the selected sub-channel structure completes the programming operation. Here, the first turn-on voltage can be the same as or different from the second turn-on voltage. The second turn-on voltage applied to the unselected gate layer Unsel WL needs to start before the programming voltage is applied to the selected gate layer Sel WL, and end after the programming voltage applied to the selected gate layer Sel WL ends. And in view of the high programming voltage, the final programming voltage can be obtained by multiple lifting as Figure 14D 、 Figure 14E shown in the above.

[0379] In the embodiments of the present application, the memory device includes N (such as three) first stack structures, for the first type: the TSG of each deck is interconnected and the BL is separately led out, such as Figure 15AAs shown, from top to bottom, the first, second and third first stack structures deck1, deck2 and deck3 are included in sequence, deck1 and deck2 share the source layer Source, each first stack structure includes the top select gate TSG, a plurality of gate layers and the bottom select gate BSG, the plurality of gate layers are schematically shown as WL1 and WL2. The WL1 of all first stack structures are interconnected, the WL2 are interconnected, the TSG are interconnected, the BSG are interconnected, the Source are interconnected, and the BL are separately led out.

[0380] In some embodiments, the first voltage includes a program inhibit voltage, and the second voltage includes a program enable voltage; the applying the first voltage on the top select gate of the unselected sub-channel structure and / or the bit line coupled thereto, and the applying the second voltage on the top select gate of the selected sub-channel structure and the bit line coupled thereto, includes: applying the program inhibit voltage on the bit line coupled to the unselected sub-channel structure, and applying the program enable voltage on the bit line coupled to the selected sub-channel structure; and applying the turn-on voltage on all top select gate layers.

[0381] In the embodiments of the present application, as Figure 15D 、 Figure 15E , the program inhibit voltage is applied to the bit line unSel BL in the unselected sub-channel structure, such as a ground voltage, so that the unselected sub-channel structure is in the cancel-on state; the program enable voltage is applied to the bit line Sel BL in the selected sub-channel structure, so that the selected sub-channel structure is in the on state. In addition, the bottom select gate BSG is applied with a cutoff voltage, such as a ground voltage, the unselected gate layer Unsel WL is applied with a second turn-on voltage, the source layer is applied with a ground voltage, the selected gate layer Sel WL is applied with a program voltage, and then the selected sub-channel structure completes the programming operation. Here, the first turn-on voltage can be the same as or different from the second turn-on voltage. The second turn-on voltage applied to the unselected gate layer Unsel WL needs to start before the program voltage is applied to the selected gate layer Sel WL, and end after the program voltage applied to the selected gate layer Sel WL ends. And in view of the high program voltage, the final program voltage can be obtained by multiple lifting as shown in Figure 15D 、 Figure 15E .

[0382] The embodiments of the present application provide a manufacturing method of a memory device, as Figure 16 The manufacturing method of the memory device includes:

[0383] Step 1601: forming a plurality of first stack structures arranged in layers; the first stack structure includes a plurality of first conductive layers and first dielectric layers arranged alternately along a first direction.

[0384] Step 1602: forming a first conductive structure, the first conductive structure extending along a first direction and connecting with one first conductive layer of at least two first stack structures in the plurality of first stack structures.

[0385] Step 1603: forming a plurality of channel structures; the channel structures penetrating the plurality of first stack structures.

[0386] Step 1604: forming at least one semiconductor layer, one semiconductor layer connecting with the channel structure in at least one first stack structure.

[0387] It should be noted that, Figure 16 The steps shown in the method 1000 are not exclusive and other steps can be performed before, after or between any of the steps shown; Figure 16 The steps shown in the method 1000 can be adjusted in sequence according to actual needs.

[0388] In some embodiments, the forming the plurality of first stack structures arranged in a stack includes: providing a semiconductor structure; the semiconductor structure includes a plurality of semiconductor units, and each semiconductor unit includes at least a stack layer including a plurality of isolation material layers and a plurality of dielectric layers alternately arranged along a first direction; dividing the semiconductor structure along a second direction and / or a third direction to form a plurality of independent semiconductor units; the second direction and the third direction intersect and are both perpendicular to the first direction; stacking the plurality of semiconductor units along the first direction to form a plurality of semiconductor units arranged in a stack; and replacing the isolation material layers in the plurality of semiconductor units arranged in a stack with first conductive layers to form the plurality of first stack structures arranged in a stack.

[0389] In the embodiments of the present application, the semiconductor structure is divided along the X-axis and / or the Y-axis, and the divided semiconductor unit structure is stacked along the Z-axis direction to form the folded memory device.

[0390] In some embodiments, the semiconductor structure is divided by laser cutting to obtain a plurality of semiconductor units.

[0391] In some embodiments, the stacking the plurality of semiconductor units along the first direction includes: using a bonding process to stack the plurality of semiconductor units along the first direction.

[0392] In some embodiments, the material of the isolation material layer includes but is not limited to silicon nitride, the material of the first conductive layer includes but is not limited to tungsten and polysilicon, and the material of the dielectric layer includes but is not limited to silicon oxide. In some embodiments, the isolation material layer in the plurality of semiconductor units arranged in a stack can be replaced with the first conductive layer by using a wet etching process and a deposition process.

[0393] In some embodiments, the semiconductor unit further comprises a semiconductor layer on the first side and a second conductive layer on the second side; the first side and the second side are respectively located on opposite sides of the stacked layer along the first direction; the second conductive layer comprises a plurality of bit lines spaced along the second direction and extending along the third direction; the stacking of the plurality of semiconductor units along the first direction comprises: stacking every two semiconductor units in the plurality of semiconductor units to form a plurality of semiconductor unit groups; the two semiconductor units in each semiconductor unit group are stacked in a direction towards the respective first side; and the plurality of semiconductor unit groups are stacked along the first direction.

[0394] In the embodiments of the present application, the two sides of the semiconductor unit along the Z-axis direction comprise a semiconductor layer and a second conductive layer, and after cutting, the subsequent stacking process can be directly performed, and the two adjacent semiconductor units are stacked in a direction towards the semiconductor layer.

[0395] In some embodiments, the number of independent semiconductor units formed is a first number N; the semiconductor structure is divided along the second direction to form semiconductor units containing a fourth number of bit lines (X-axis direction folding, the number of bit lines is 1 / N of the original); the semiconductor structure is divided along the third direction to form semiconductor units containing a fifth number of bit lines (Y-axis direction folding, the number of bit lines remains unchanged); the fifth number is the product of the first number and the fourth number.

[0396] In some embodiments, the manufacturing method further comprises: before stacking every two semiconductor units in the plurality of semiconductor units, removing the semiconductor layer corresponding to one of the semiconductor units; and the remaining one semiconductor layer forms a semiconductor layer connected to both semiconductor units.

[0397] In the embodiments of the present application, before the two adjacent semiconductor units are stacked in a direction towards the semiconductor layer, one semiconductor layer is removed to form a common semiconductor layer between the two adjacent semiconductor units.

[0398] In other embodiments, the two adjacent semiconductor units are directly stacked in a direction towards the semiconductor layer, so that the structure between the two stacked semiconductor units has two semiconductor layers.

[0399] In some embodiments, the semiconductor unit further comprises a semiconductor layer on the first side and a second conductive layer on the second side; the first side and the second side are respectively located on opposite sides of the stacked layer along the first direction; the second conductive layer comprises a plurality of bit lines spaced along the second direction and extending along the third direction; the stacking of the plurality of semiconductor units along the first direction comprises: stacking every two semiconductor units in the plurality of semiconductor units to form a plurality of semiconductor unit groups; the two semiconductor units in each semiconductor unit group are stacked in a direction towards the respective first side; and the plurality of semiconductor unit groups are stacked along the first direction.

[0400] In the embodiments of the present application, the two sides of the semiconductor unit along the Z-axis direction include the semiconductor layer and the second conductive layer, and after the cutting is performed, the subsequent stacking process can be directly performed. The two adjacent semiconductor units are stacked in the direction of the semiconductor layer and the direction of the second conductive layer.

[0401] In some embodiments, the manufacturing method further includes: forming the semiconductor layer and the second conductive layer on the opposite sides of each semiconductor unit along the first direction, respectively; the second conductive layer includes a plurality of bit lines spaced along the second direction and extending along the third direction; and the plurality of semiconductor units are stacked along the first direction, including: stacking the plurality of semiconductor units formed with the semiconductor layer and the second conductive layer along the first direction.

[0402] In the embodiments of the present application, the two sides of the semiconductor unit along the Z-axis direction can not include the semiconductor layer and the second conductive layer. Based on this, after the cutting is performed, the semiconductor layer and the second conductive layer can be formed on the two sides of the cutting structure along the Z-axis direction, and then the stacking process is performed.

[0403] In some embodiments, the manufacturing method further includes: when the isolation material layer in the plurality of semiconductor units in the layering arrangement is replaced by the first conductive layer, a part of each isolation material layer in the plurality of semiconductor units is replaced by the first conductive layer, and the part of the stacked structure where the isolation material layer is replaced forms a first stacked structure, and the part of the stacked structure where the isolation material layer is not replaced forms a second stacked structure; the medium layer corresponding to the first stacked structure is a first medium layer, and the medium layer corresponding to the second stacked structure is a second medium layer; and the first conductive structure is formed, including: forming the first conductive structure in the second stacked structure.

[0404] In the embodiments of the present application, the large framework of the first stacked structure and the second stacked structure is formed together, and then the part of the stacked structure where the isolation material layer is replaced by the first conductive structure forms the first stacked structure, and the part of the stacked structure where the isolation material layer is not replaced forms the second stacked structure. It can be seen that the first medium layer and the second medium layer are in the same layer and have the same material; the remaining isolation material layer forms an isolation layer, and the isolation layer is in the same layer as the first conductive layer but has different materials.

[0405] In some embodiments, the memory device includes the first stacked structure, the second stacked structure, and the third stacked structure, the second stacked structure and the third stacked structure are arranged along the Y-axis direction and are located in the connection area SS, the third stacked structure includes the third conductive layer and the third medium layer stacked alternately, and the second stacked structure includes the isolation layer and the second medium layer stacked alternately; wherein the first conductive layer, the second conductive layer, and the isolation layer are in the same layer, and the first medium layer, the second medium layer, and the third medium layer are in the same layer.

[0406] In some embodiments, the forming process of the first stack structure, the second stack structure and the third stack structure can include the following steps:

[0407] forming an initial stack structure of the isolation material layer and the dielectric layer stack in the array region GB and the connection region SS; replacing all the isolation layers in the array region with the first conductive layer to form the first stack structure; replacing part of the isolation layers in the connection region on both sides of the gate slit structure with the third conductive layer to form the third stack structure; in the connection region, the un-replaced isolation layers and dielectric layers are retained to form the second stack structure.

[0408] In some embodiments, the manufacturing method further includes: forming a plurality of second conductive structures, the second conductive structures extending in the first direction in the first stack structure and connected to one bit line of the at least one second conductive layer.

[0409] In some embodiments, the second conductive structures can be formed by using a dry etching process and a deposition process.

[0410] In some embodiments, the plurality of first conductive layers in the first stack structure includes a top select gate layer and a gate layer; the manufacturing method further includes: forming a third conductive structure, the third conductive structure extending in the first direction in the first stack structure and connected to one top select gate layer of at least one first stack structure of the plurality of first stack structures; the first conductive structure is connected to one gate layer of at least two first stack structures of the plurality of first stack structures.

[0411] In some embodiments, the third conductive structure is formed by: for each first stack structure, respectively forming a contact portion of the third conductive structure extending in a stacking direction of the plurality of first stack structures and connected to the top select gate layer; and respectively forming a second connection portion of the third conductive structure extending in a direction perpendicular to the stacking direction and connected to the contact structure; forming a third contact hole penetrating through the plurality of first stack structures, forming a second insulating layer on the sidewall of the third contact hole; filling the third contact hole formed with the second insulating layer with a conductive material to form a second lead-out portion of the third conductive structure; the second lead-out portion is connected to one second connection portion corresponding to one or more first stack structures.

[0412] In addition to the aforementioned cutting + stacking method, the folded memory device can also be formed directly by layer-by-layer growth in the embodiments of the present application. In some embodiments, the plurality of first stack structures arranged in a stack are formed by: sequentially forming the plurality of first stack structures arranged in a stack; the first stack structure includes a plurality of first conductive layers and dielectric layers arranged alternately; the manufacturing method further includes: alternately forming a semiconductor layer and a second conductive layer on both sides of the plurality of first stack structures in the first direction and between each adjacent two first stack structures.

[0413] In the embodiments of the present application, a plurality of stack structures can also be stacked along the Z-axis direction; the plurality of stack structures are divided along the Z-axis direction, and the stack structures are split into a plurality of independent stack structures; the bit line layer BL and the source layer ACS are formed on the upper and lower sides of each stack structure, respectively, to form a plurality of independent semiconductor units; and all the semiconductor units form a memory device.

[0414] For the four architectures of the memory device described above, the manufacturing methods of these architectures will be described exemplarily below.

[0415] The embodiments of the present application provide a manufacturing method of a memory device, which is directed to the array Y-axis folding architecture described above, and the manufacturing method of the memory device comprises the following steps: Figure 3A

[0416] Step a1: providing a semiconductor structure, which comprises a stack structure, the stack structure comprising a plurality of semiconductor units arranged along the Y-axis direction, the Y-axis direction being parallel to the extension direction of the bit line BL, and the semiconductor unit comprising the stack structure and the bit line layer BL and the source layer ACS located on the upper and lower sides of the stack structure, respectively.

[0417] Step a2: dividing the stack structure along the Y direction so that all the semiconductor units are separated from each other.

[0418] Step a3: stacking all the semiconductor units along the Z-axis direction to form a memory device.

[0419] In some embodiments, the stacking manner of all the semiconductor units also has various forms, including but not limited to face-to-face stacking of all the semiconductor units, face-to-back stacking of all the semiconductor units, or a combination thereof. Here, after the memory block is divided, each semiconductor unit comprises a top surface and a bottom surface, the face-to-face stacking can comprise the top surface of one semiconductor unit and the top surface of another semiconductor unit being in contact and stacked, or the bottom surface of one semiconductor unit and the bottom surface of another semiconductor unit being in contact and stacked, and the face-to-back stacking can comprise the top surface of one semiconductor unit and the bottom surface of another semiconductor unit being in contact and stacked.

[0420] In some embodiments, the stacking manner between the semiconductor units comprises but is not limited to hybrid bonding.

[0421] In some embodiments, the formed memory device comprises N first stack structures, each first stack structure comprising l gate layers WL, the number of bit lines BL corresponding to the stack structure being Q, the number of bit lines BL corresponding to each semiconductor unit being Q, and the number of bit lines BL of the memory device formed after the semiconductor units are stacked also being Q.

[0422] ​Embodiments of the present application provide a manufacturing method of a memory device, for the array Y-axis folding architecture as described above, Figure 3B The manufacturing method of the memory device comprises:

[0423] Step b1, providing a semiconductor structure, the semiconductor structure comprising a stack structure, the stack structure comprising a plurality of semiconductor units arranged along an X-axis direction, the X-axis direction being perpendicular to the extension direction of the bit line BL;

[0424] Step b2, dividing the stack structure along the X-axis direction so that the plurality of semiconductor units are separated from each other;

[0425] Step b3: stacking all the semiconductor units along the Z-axis direction to form a memory device.

[0426] In some embodiments, the way of stacking all the semiconductor units also has various forms, including but not limited to face-to-face stacking of all the semiconductor units, face-to-back stacking of all the semiconductor units, or a combination thereof.

[0427] In some embodiments, the stacking mode between the semiconductor units includes but is not limited to hybrid bonding.

[0428] In some embodiments, the formed memory device comprises N first stack structures, each first stack structure comprising l gate layers WL, the number of bit lines BL corresponding to the stack structure being Q, the number of bit lines BL corresponding to each semiconductor unit being Q / N, and the number of bit lines BL of the memory device formed after stacking the semiconductor units also being Q / N.

[0429] Embodiments of the present application provide a manufacturing method of a memory device, for the array Y-axis folding architecture as described above, Figure 3C The manufacturing method of the memory device comprises:

[0430] Step c1, providing a semiconductor structure, the semiconductor structure comprising a stack structure, the stack structure comprising a plurality of semiconductor units arranged along an X-axis direction and along a Y-axis direction, the X-axis direction being perpendicular to the extension direction of the bit line BL, and the Y-axis direction being parallel to the extension direction of the bit line BL;

[0431] Step c2, dividing the initial memory device along the X-axis direction so that the plurality of unit structures are separated from each other;

[0432] Step c3: dividing the unit structure along the Y-axis direction so that all the semiconductor units are separated from each other;

[0433] Step c4: stacking all the semiconductor units along the Z-axis direction to form a memory device.

[0434] In some embodiments, the manner of stacking all the semiconductor units can also have various forms, including but not limited to face-to-face stacking of all the semiconductor units, face-to-back stacking of all the semiconductor units, or a combination thereof.

[0435] In some embodiments, the manner of stacking between semiconductor units includes but is not limited to hybrid bonding.

[0436] In other embodiments, the process implementation of the semiconductor structure can also include other various forms, such as first cutting along the Y-axis direction, then cutting along the X-axis direction to form a memory device, or other ways that can implement different semiconductor unit stacking.

[0437] In other embodiments, the arrangement manner of stacking all the semiconductor units can also have various forms, and can be arranged according to Model, can stack the same Finger corresponding to all unit structures together to form a semiconductor unit cell including a plurality of stacked structures, and then stack a plurality of semiconductor unit cells together to form a memory device. All semiconductor units can also be stacked together in sequence so that the same Model corresponding to all unit structures are stacked together, or other ways that can be implemented. For example, the stacking structure arranged from top to bottom can be Model 1 corresponding to semiconductor unit 1 to semiconductor unit N in the first row, and Model 2 corresponding to semiconductor unit 1 to semiconductor unit N in the second row. For example, the stacking structure arranged from left to right can be Model 1 corresponding to semiconductor unit 1 to semiconductor unit N in the first column, and Model 2 corresponding to semiconductor unit 1 to semiconductor unit N in the second column.

[0438] In one embodiment, the formed memory device includes M storage modules, each storage module includes N stacked structures, each stacked structure includes l gate layers WL, the number of bit lines BL corresponding to the stacked structure is Q, the number of bit lines BL corresponding to each semiconductor unit is Q / N, and the number of bit lines BL of the memory device formed by stacking the semiconductor units is also Q / N.

[0439] Embodiments of the present application also provide a storage system, including the memory device in the above embodiments of the present application.

[0440] In some embodiments, the memory device includes a three-dimensional NAND type memory.

[0441] The memory array in the embodiments of the present application can include a plurality of memory cells, which can be configured to store at least one bit of data. For example, the memory cells in the embodiments of the present application can be SLC configured to store one bit of data, MLC configured to store two bits of data, TLC configured to store three bits of data, QLC configured to store four bits of data, or even more bits of data.

[0442] In some embodiments, the storage system further includes a memory controller connected with the memory device and configured to control the memory device.

[0443] In some embodiments, the system in the above embodiments can be a memory system 102 as shown in Figure 17 , which includes a memory controller 106 and a memory device 104 coupled with the memory controller 106. The controller in the above embodiments can be a memory controller 106 as shown in Figure 17 , Figure 18 and Figure 19 . In other embodiments, the system in the above embodiments can be a system 100 as shown in Figure 17 , which includes a host device 108 and a memory system 102 coupled with the host device 108. The controller in the above embodiments can be a control part independent of the memory controller 106, for example, a CPU in the host device. The input data here includes a vector or a matrix.

[0444] According to some embodiments, as shown in Figure 17 , the memory controller 106 is coupled to the memory device 104 and the host device 108, and is configured to control the operation of the memory device 104, such as reading, erasing, programming, and computing operation. The memory controller 106 can manage the data stored in the memory device 104 and communicate with the host device 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital card, a compact flash card, a universal serial bus flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multimedia card used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise memory arrays.

[0445] The memory controller 106 and one or more memory devices 104 can be integrated into various types of memory devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an embedded Multi-Media Card package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. In one example as shown in FIG. 1, the memory controller 106 and a single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a compact flash card, a smart media card, a memory stick, a multimedia card, a secure digital card, a UFS, etc. The memory card 202 can also include a memory card connector 204 that couples the memory card 202 with a host device (e.g., the host device 108 in FIG. 1). In another example as shown in FIG. 1, the memory controller 106 and multiple memory devices 104 can be integrated into an SSD 206. The SSD 206 can also include an SSD connector 208 that couples the SSD 206 with a host device (e.g., the host device 108 in FIG. 1). In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than that of the memory card 202. Figure 18 Figure 17 Figure 19 Figure 17

[0446] It should be noted that the technical solutions disclosed in the embodiments of the present application can be combined arbitrarily without conflict.

[0447] The specific implementation of the present application, but the scope of protection of the present application is not limited to this, any skilled in the art of the technical personnel in the technical range disclosed in the present application, can easily think of changes or replacement, should be covered in the scope of protection of the present application. Therefore, the scope of protection of the present application should be subject to the protection scope of the claims.​​​​

Claims

1. A storage device, characterized in that, include: Multiple first stacked structures are stacked in a layered configuration; The first stacked structure includes a plurality of first conductive layers and first dielectric layers alternately arranged along a first direction; A plurality of first conductive structures, each of which is connected to a first conductive layer of at least two of the plurality of first stacked structures; Multiple channel structures; each of the multiple first stacked structures; At least one semiconductor layer and at least one second conductive layer; A semiconductor layer and a second conductive layer are respectively located on both sides of a first stacked structure along the first direction and are both connected to a channel structure in the first stacked structure; each second conductive layer includes multiple bit lines spaced along the second direction and extending along a third direction; the second direction and the third direction intersect and are both perpendicular to the first direction; Multiple second conductive structures, each of which is connected to a bit line of at least one second conductive layer.

2. The storage device according to claim 1, characterized in that, Different bit lines corresponding to different first stacked structures that are traversed by the same channel structure are all connected to the same second conductive structure.

3. The storage device according to claim 2, characterized in that, At least one of the second conductive layers is located between two adjacent first stacked structures and is connected to the channel structures in both of the adjacent first stacked structures.

4. The storage device according to claim 2, characterized in that, The storage device further includes peripheral circuitry; the peripheral circuitry includes a page cache. The plurality of second conductive structures are connected to the same page buffer.

5. The storage device according to claim 1, characterized in that, Different bit lines corresponding to different first stacked structures through the same channel structure are all connected to different second conductive structures.

6. The storage device according to claim 5, characterized in that, The dimensions of the second conductive layer along the third direction differ for different first stacked structures; Different second bit lines connected to the second conductive layer corresponding to different first stacked structures are arranged sequentially along the third direction.

7. The storage device according to claim 5, characterized in that, The storage device further includes peripheral circuitry; the peripheral circuitry includes multiple page caches. A second conductive structure connected to a bit line of the same second conductive layer is connected to the same page cache among the plurality of page caches; The second conductive structure, connected to the bit lines of different second conductive layers, is connected to different page caches among the plurality of page caches.

8. The storage device according to claim 1, characterized in that, At least one of the semiconductor layers is located between two adjacent first stacked structures and is connected to the channel structures in both of the adjacent first stacked structures.

9. The storage device according to claim 8, characterized in that, Two adjacent first stacking structures in the plurality of first stacking structures form a stacking structure group; The storage device includes multiple semiconductor layers; the multiple semiconductor layers are respectively located between two adjacent first stacked structures in the multiple stacked structure groups; the multiple semiconductor layers are interconnected.

10. The storage device according to claim 1, characterized in that, The cross-sectional shape of the plurality of first stacked structures along the first direction includes a stepped shape; each step in the stepped shape corresponds to an adjacent first conductive layer and a first dielectric layer; The first conductive structure extends along the first direction in the first stacked structure and is connected to at least two steps where a first conductive layer of the at least two first stacked structures is located.

11. The storage device according to claim 1, characterized in that, The storage device further includes a second stacking structure, which includes several layers of alternately arranged isolation layers and a second dielectric layer; The first conductive structure includes a first lead-out portion and a plurality of first connection portions; the first lead-out portion is located along a first line in the second stacked structure and is connected to the plurality of first connection portions; each first connection portion is located in an isolation layer and is connected to a first conductive layer of a corresponding first stacked structure in the at least two first stacked structures.

12. The storage device according to claim 1, characterized in that, The first conductive structure is connected to a first conductive layer in each of the first stacked structures that is equidistant from the semiconductor layer connected to the channel structure of the corresponding first stacked structure.

13. The storage device according to claim 1, characterized in that, The first conductive structure is connected to a first conductive layer in each of the first stacked structures that is at a different distance from the semiconductor layer connected to the channel structure of the corresponding first stacked structure.

14. The storage device according to claim 1, characterized in that, The storage device further includes peripheral circuitry; the peripheral circuitry includes multiple word line driver circuits. A first conductive layer of each of the at least two first stacked structures is interconnected through the first conductive structure and connected to the same word line driving circuit.

15. The storage device according to claim 1, characterized in that, The memory device further includes a plurality of third conductive structures; the first conductive layer in the first stacked structure includes a top selected gate layer and a gate layer; the top selected gate layer is located at one end of the respective first stacked structure along the first direction away from the semiconductor layer connected to the channel structure in the respective first stacked structure. The third conductive structure extends along the first direction in the first stacked structure and is connected to the top selected gate layer included in at least one of the plurality of first stacked structures. The first conductive structure is connected to a gate layer of at least two of the plurality of first stacked structures.

16. The storage device according to claim 15, characterized in that, The memory device further includes a top-select gate isolation structure; the top-select gate isolation structure divides the top-select gate layer into multiple sub-top-select gate layers; Different sub-top selected gate layers included in the same top selected gate layer are connected to different third conductive structures.

17. The storage device according to claim 15, characterized in that, Different top selected gate layers of different first stacked structures are connected to different third conductive structures; Different bit lines corresponding to different first stacked structures that are traversed by the same channel structure are all connected to the same second conductive structure.

18. The storage device according to claim 15, characterized in that, Different bit lines corresponding to different first stacked structures that are traversed by the same channel structure are all connected to different second conductive structures; Different top selected gate layers in different first stacked structures are connected to the same third conductive structure.

19. The storage device according to claim 15, characterized in that, The multiple first stacked structures arranged in a stacked manner constitute a storage surface; the storage device includes a first storage surface and a second storage surface; the first storage surface and the second storage surface are arranged side by side along a second direction; the storage device also includes multiple word line driving circuits; The plurality of first conductive structures are located between the first storage surface and the second storage surface, and the first conductive structure is connected to a gate layer of a different first stacked structure in at least one storage surface. The first conductive layers of the first storage surface and the second storage surface at the same position in the first direction are interconnected and connected to the same word line driving circuit.

20. The storage device according to claim 19, characterized in that, Different bit lines corresponding to different first stacked structures that are traversed by the same channel structure are all connected to different second conductive structures; Different top selected gate layers of different first stacked structures in the same memory plane are connected to the same third conductive structure; The first stacked structures at the same location in the first direction for different storage surfaces include different top selected gate layers connected to different third conductive structures.

21. The storage device according to claim 15, characterized in that, The stacked first stacked structures constitute a storage module; the storage device includes a first storage module and a second storage block; the first storage module and the second storage block are stacked along the first direction. The plurality of first conductive structures are connected to a gate layer of each first stacked structure in the first memory module and the second memory block.

22. The storage device according to claim 21, characterized in that, In the same memory module, different bit lines corresponding to different first stacked structures that are traversed by the same channel structure are all connected to different second conductive structures; The two bit lines corresponding to the two first stacked structures specified in different storage modules are interconnected; Different top selected gate layers in different first stacked structures within the same memory module are connected to the same third conductive structure; In different memory modules, the two first stacked structures include two top selected gate layers connected to different third conductive structures.

23. The storage device according to claim 21, characterized in that, In the same storage module, different bit lines corresponding to different first stacked structures that are traversed by the same channel structure are all connected to the same second conductive structure; In different storage modules, the different bit lines corresponding to the two first stacked structures are all connected to different second conductive structures; Different top selected gate layers of different first stacked structures in the same memory module are connected to different third conductive structures; In the different memory modules, the two first stacked structures include two top selected gate layers connected to the same third conductive structure.

24. The storage device according to claim 15, characterized in that, The plurality of first stacked structures are disposed in a first region, the plurality of first conductive structures are disposed in a second region, the plurality of second conductive structures are disposed in a third region, and the plurality of third conductive structures are disposed in a fourth region. The second region is located in the middle of the first region; or, the second region is located on at least one side of the first region along a direction perpendicular to the stacking direction. The third region is located on at least one side of the first region along the third direction; the fourth region is located between the first region and the second region.

25. A method for controlling a storage device, characterized in that, The memory device includes the memory device according to any one of claims 1 to 24, wherein the channel structure is divided into a plurality of sub-channel structures by the semiconductor layer and the second conductive layer; The first conductive layers in the first stacked structure include a top selected gate layer and a gate layer; the top selected gate layer is located at one end of the corresponding first stacked structure along a first direction away from the end of the semiconductor layer connected to the channel structure in the corresponding first stacked structure. The control method includes: During the read operation, a first voltage is applied to the top select gate and / or the bit line coupled to the unselected sub-channel structure in the plurality of sub-channel structures, and a second voltage is applied to the top select gate and the bit line coupled to the selected sub-channel structure in the plurality of sub-channel structures; a pass voltage is applied to all unselected gate layers, and a read voltage is applied to the selected gate layer.

26. The control method according to claim 25, characterized in that, The first voltage includes a cutoff voltage, and the second voltage includes a first on-voltage. Applying a first voltage to the top select gate and / or its coupled bit lines of the unselected sub-channel structure, and applying a second voltage to the top select gate and its coupled bit lines of the selected sub-channel structure, including: A cutoff voltage is applied to the top selection gate of the unselected sub-channel structure, and a first on voltage is applied to the top selection gate of the selected sub-channel structure.

27. The control method according to claim 25, characterized in that, The first voltage includes a programmable disable voltage, and the second voltage includes a programmable enable voltage; Applying a first voltage to the top select gate and / or its coupled bit lines of the unselected sub-channel structure, and applying a second voltage to the top select gate and its coupled bit lines of the selected sub-channel structure, including: A programmable disable voltage is applied to the bit lines coupled to the unselected sub-channel structures, and a programmable enable voltage is applied to the bit lines coupled to the selected sub-channel structures; a first enable voltage is applied to all top select gate layers.

28. The control method according to claim 25, characterized in that, The first conductive layers in the first stacked structure further include a bottom selected gate layer; the bottom selected gate layer is located at one end of the corresponding first stacked structure along the first direction, near the end of the semiconductor layer connected to the channel structure in the corresponding first stacked structure. The method further includes: During the read operation, a second on-state voltage is applied to all bottom select gate layers.

29. A method for controlling a storage device, characterized in that, include: The storage device includes the storage device according to any one of claims 1 to 24, wherein the channel structure is divided into a plurality of sub-channel structures by the plurality of first stacked structures; The first conductive layers in the first stacked structure include a top selected gate layer and a gate layer; the top selected gate layer is located at one end of the corresponding first stacked structure along the first direction away from the end of the semiconductor layer connected to the channel structure in the corresponding first stacked structure. The control method includes: During the programming operation, a first voltage is applied to the top selection gate and / or the bit lines coupled to the unselected sub-channel structures in the plurality of sub-channel structures, and a second voltage is applied to the top selection gate and the bit lines coupled to the selected sub-channel structures in the plurality of sub-channel structures; a pass voltage is applied to all unselected gate layers, and a programming voltage is applied to the selected gate layers.

30. The control method according to claim 29, characterized in that, The first voltage includes a cutoff voltage, and the second voltage includes a turn-on voltage; Applying a first voltage to the top select gate and / or its coupled bit lines of the unselected sub-channel structure, and applying a second voltage to the top select gate and its coupled bit lines of the selected sub-channel structure, including: A cutoff voltage is applied to the top selection gate of the unselected sub-channel structure, and an on voltage is applied to the top selection gate of the selected sub-channel structure.

31. The control method according to claim 29, characterized in that, The first voltage includes a programmable disable voltage, and the second voltage includes a programmable enable voltage; Applying a first voltage to the top select gate and / or its coupled bit lines of the unselected sub-channel structure, and applying a second voltage to the top select gate and its coupled bit lines of the selected sub-channel structure, including: A programmable disable voltage is applied to the bit lines coupled to the unselected sub-channel structures, and a programmable enable voltage is applied to the bit lines coupled to the selected sub-channel structures. A pass voltage is applied to all top select gate layers.

32. The control method according to claim 29, characterized in that, The first conductive layers in the first stacked structure further include a bottom selected gate layer; the bottom selected gate layer is located at one end of the corresponding first stacked structure along the first direction, near the end of the semiconductor layer connected to the channel structure in the corresponding first stacked structure. The method further includes: During the programming process, a cutoff voltage is applied to all bottom select gate layers.

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