Method for improving negative bias temperature instability of PMOS (P-channel Metal Oxide Semiconductor) device

Abstract

The invention provides a method for improving negative bias temperature instability of a PMOS (P-channel Metal Oxide Semiconductor) device, which is characterized in that a silicon nitride thin film layer with tensile stress is prepared by adopting a furnace tube deposition process, the silicon nitride furnace tube deposition process is characterized in that a reaction gas source is heated and decomposed at high temperature to carry out chemical reaction, and ions in the process belong to thermal motion; therefore, the surface of the substrate does not have large acceleration, bombardment of reaction source ions to the gate dielectric layer of the PMOS device in the chemical reaction process can be effectively reduced or even avoided, the risk of damage to the gate dielectric layer of the PMOS device is reduced, and the effect of improving NBTI of the PMOS device is achieved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to a method for improving the temperature instability of negative bias in PMOS devices. Background Technology

[0002] From the perspective of the inherent development laws of integrated circuits, high performance and high reliability have always been the two commanding heights of their development. On the one hand, the development of integrated circuits is moving towards larger-scale integration, which improves the performance of devices and circuits and reduces the production cost per unit circuit—this is the driving force behind the development of integrated circuit technology. On the other hand, reliability issues have always accompanied the development and application of integrated circuit technology, and as the feature size of integrated circuits further decreases, reliability issues become increasingly prominent. The most significant factor among these is the negative bias temperature instability (NBTI) of PMOS devices.

[0003] First reported in 1966, NBTI refers to the instability of PMOS devices, such as threshold voltage (Vth), transconductance (Gm), and saturation current (Idsat), when operating under negative gate bias and high temperature. In recent years, extensive research has been conducted on NBTI, and the reaction-diffusion model (RD model) is widely accepted to explain the observed phenomena. This model posits that the negative bias applied to the PMOS gate induces a field-dependent reaction at the Si / SiO2 interface, breaking the passivated Si-H bonds and leaving positively charged interface states (Si...). + H is released into the gate dielectric layer, forming H2 and diffusing into the polysilicon gate layer, creating traps in the gate dielectric layer. These interface states and traps lead to changes in semiconductor device parameters. Therefore, current improvements to NBTI mainly focus on adjusting the gate dielectric layer by changing its process conditions. This involves altering the gate oxide layer's growth environment and optimizing its process conditions to significantly improve device performance. However, current improvements to NBTI on device lifetime have not yet met expectations, and further improvements are needed. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a method for improving the negative bias temperature instability of PMOS devices, in order to solve the problem that the existing methods for improving device NBTI do not achieve the expected results in improving device reliability.

[0005] To achieve the above and other related objectives, the present invention provides a method for improving the negative bias temperature instability of a PMOS device, the method comprising:

[0006] A substrate is provided, the substrate including an NMOS region and a PMOS region; the NMOS region and the PMOS region are respectively formed with the gate, source and drain of an NMOS device and a PMOS device;

[0007] A silicon nitride thin film layer with tensile stress is deposited on the surface of the substrate using a furnace tube deposition process;

[0008] An annealing process is performed on the substrate on which the silicon nitride thin film layer is deposited to store the tensile stress of the silicon nitride thin film layer into the channel of the NMOS device.

[0009] Optionally, the furnace tube deposition process includes low-pressure chemical vapor deposition, plasma-enhanced atomic layer deposition, or thermal atomic layer deposition.

[0010] Furthermore, the deposition gas source required for depositing the silicon nitride thin film layer using the furnace tube deposition process includes a silicon-containing gas source and a nitrogen-containing gas source; wherein, the silicon-containing gas source is hexachlorosilane or dichlorosilane, and the nitrogen-containing gas source is ammonia or a mixture of ammonia and nitrogen.

[0011] Furthermore, the furnace tube deposition process is a low-pressure chemical vapor deposition process, the silicon-containing gas source is hexachlorosilane, and the nitrogen-containing gas source is ammonia; the parameters of the low-pressure chemical vapor deposition process are: deposition temperature of 500℃~700℃, chamber pressure of 0.1 torr~1 torr, volumetric flow rate of hexachlorosilane of 0.01 slm~0.1 slm, and volumetric flow rate of ammonia of 0.1 slm~10 slm.

[0012] Furthermore, the deposition temperature is 550℃~650℃, the volumetric flow rate of ammonia is 0.1slm~2slm, and the volumetric flow rate of hexachlorosilane to ammonia is 1:10~1:40.

[0013] Furthermore, the volumetric flow rate of hexachlorosilane to that of ammonia is 1:25 to 1:40.

[0014] Furthermore, the deposition gas source required for the low-pressure chemical vapor deposition process to deposit the silicon nitride thin film layer also includes ethylene gas, and the volumetric flow rate of the ethylene gas is 0 slm to 5 slm, excluding 0 slm.

[0015] Optionally, the furnace tube deposition process is a low-pressure chemical vapor deposition process, the silicon-containing gas source is dichlorosilane, and the nitrogen-containing gas source is ammonia; the parameters of the low-pressure chemical vapor deposition process are: deposition temperature of 500℃~800℃, chamber pressure of 0.05 torr~1 torr, volumetric flow rate of dichlorosilane of 0.05 slm~0.5 slm, and volumetric flow rate of ammonia of 0.1 slm~10 slm.

[0016] Optionally, the furnace tube deposition process is a plasma-enhanced atomic layer deposition process, the silicon-containing gas source is dichlorosilane, and the nitrogen-containing gas source is ammonia; the parameters of the plasma-enhanced atomic layer deposition process are: deposition temperature of 500℃~700℃, chamber pressure of 0.1 torr~5 torr, volumetric flow rate of dichlorosilane of 1 slm~10 slm, and volumetric flow rate of ammonia of 1 slm~10 slm.

[0017] Furthermore, the deposition temperature is 500℃~600℃, the volumetric flow rate of dichlorosilane is 1slm~5slm, the volumetric flow rate of ammonia is 3slm~10slm, and the volumetric flow rate ratio of dichlorosilane to ammonia is 1:1.5~1:5.

[0018] Optionally, the furnace tube deposition process is a thermal atomic layer deposition process, the silicon-containing gas source is dichlorosilane, and the nitrogen-containing gas source is ammonia; the parameters of the thermal atomic layer deposition process are: deposition temperature of 500℃~700℃, chamber pressure of 0.1 torr~5 torr, volumetric flow rate of dichlorosilane of 1slm~10slm, and volumetric flow rate of ammonia of 1slm~10slm.

[0019] Optionally, before performing an annealing process on the substrate with the deposited silicon nitride thin film layer, the process further includes a step of removing the silicon nitride thin film layer deposited on the back side of the substrate, and / or after performing an annealing process on the substrate with the deposited silicon nitride thin film layer, the process further includes a step of removing the silicon nitride thin film layer.

[0020] Optionally, after depositing the silicon nitride thin film layer on the substrate surface, the method further includes a step of UV treatment of the silicon nitride thin film layer.

[0021] Optionally, after depositing the silicon nitride thin film layer on the substrate surface, the method further includes:

[0022] A patterned photoresist layer is formed on the silicon nitride thin film layer, wherein the patterned photoresist layer exposes the silicon nitride thin film layer on the NMOS region;

[0023] The silicon nitride thin film layer on the NMOS region is subjected to plasma treatment based on the patterned photoresist layer.

[0024] As described above, the method for improving the negative bias temperature instability (NBTI) of PMOS devices according to the present invention prepares a silicon nitride thin film layer with tensile stress using a furnace tube deposition process. The silicon nitride furnace tube deposition process involves heating and decomposing a reactive gas source at high temperature to induce a chemical reaction. Since the ions in this process are in thermal motion, they do not have a large acceleration when reaching the substrate surface. Therefore, this effectively reduces or even avoids the bombardment of the PMOS device gate dielectric layer by the reactive source ions during the chemical reaction, reducing the risk of damage to the PMOS device gate dielectric layer and achieving the effect of improving the NBTI of the PMOS device. Simultaneously, further processing of the silicon nitride thin film layer, such as plasma treatment or UV treatment of the silicon nitride thin film layer in the NMOS region, can further increase the stress in the NMOS region or improve the impact on the electrical performance of the PMOS region, thereby improving device performance. Attached Figure Description

[0025] Figure 1 The diagram shows a cross-sectional structure of a substrate having only the PMOS region in the method for improving the negative bias temperature instability of PMOS devices according to the present invention.

[0026] Figure 2 Displayed as Figure 1 A schematic diagram of the cross-sectional structure of the gate in the PMOS region.

[0027] Figure 3 The diagram shows a cross-sectional structure after the deposition of a silicon nitride thin film layer in the method for improving the negative bias temperature instability of PMOS devices according to the present invention.

[0028] Figure 4 The diagram shows a cross-sectional structure after removing the silicon nitride thin film layer on the back side of the substrate in the method for improving the negative bias temperature instability of PMOS devices according to the present invention.

[0029] Figure 5 The diagram shows a cross-sectional view of the annealing process in the method for improving the negative bias temperature instability of PMOS devices according to the present invention.

[0030] Figure 6 The diagram shows a cross-sectional structure after removing the silicon nitride thin film layer in the method for improving the negative bias temperature instability of PMOS devices according to the present invention.

[0031] Figure 7 The chart shows a comparison of the lifetime of PMOS devices obtained by using three sets of experimental examples of the present invention to improve the negative bias temperature instability of PMOS devices with that obtained by using the existing PECVD process to prepare silicon nitride thin films.

[0032] Component designation explanation

[0033] 10 Substrates

[0034] 100 PMOS region

[0035] 101 gate

[0036] 102 Gate dielectric layer

[0037] 103 Polycrystalline silicon gate layer

[0038] 104 gate sidewall

[0039] 105 Silicon Nitride Thin Film Layer

[0040] 106 Backside silicon nitride thin film layer Detailed Implementation

[0041] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0042] Please see Figures 1 to 7 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0043] As described in the background section, existing methods to improve NBTI by changing the process conditions of the gate dielectric layer have not achieved the desired effect. With the rise of technology nodes below 90nm, stress memory technology (SMT) has been introduced to improve the carrier mobility of NMOS devices, thereby increasing device speed. This technology typically involves depositing a high-tensile-stress silicon nitride (SiN) film on the wafer surface after the source and drain electrodes of the MOS device are formed using plasma-enhanced vapor deposition (PECVD) process, and then using an annealing process to memorize the tensile stress of the SiN film into the channel of the NMOS device to improve the speed of the NMOS device. Further research by researchers revealed that the process of forming SiN thin films by PECVD involves ionizing the source gas of the reaction gas through an RF ignition power supply to form plasma, and then guiding the plasma to the wafer surface through an RF bias power supply for chemical deposition. Because the RF bias power supply causes the plasma to accelerate, it produces a certain bombardment effect, which damages the gate dielectric layer of the PMOS device. This results in defects in the gate dielectric layer and at the interface between the gate dielectric layer and the channel layer, which exacerbates the degradation of the NBTI of the PMOS device and ultimately leads to the failure of the PMOS NBTI.

[0044] Based on the above analysis, researchers proposed a method to improve the negative bias temperature instability of PMOS devices, such as... Figures 1 to 6 As shown, the method includes:

[0045] like Figure 1 As shown, a substrate 10 is provided, which includes an NMOS region (not shown) and a PMOS region 100. The NMOS region and the PMOS region 100 respectively form the gate 101, source, and drain of the NMOS and PMOS devices (not shown). It should be noted that semiconductor devices are generally fabricated simultaneously on a whole wafer during the fabrication process, so there may be multiple AA regions on the substrate 10, and each AA region may have several instances. Figure 1 For ease of understanding of the inventive points of this embodiment, only one PMOS region 100 in the substrate 10 is shown. In reality, the area of ​​the substrate 10 will be larger and include more device regions. In addition, the source and drain of the MOS device are fabricated in the substrate 10, and their specific structure, doping concentration and other parameters are designed according to actual needs.

[0046] like Figure 3 As shown, a silicon nitride thin film layer 105 with tensile stress is deposited on the surface of the substrate 10 using a furnace tube deposition process;

[0047] like Figure 5As shown, the substrate on which the silicon nitride thin film layer 105 is deposited is subjected to an annealing process to store the tensile stress of the silicon nitride thin film layer 105 into the channel of the NMOS device.

[0048] The method for improving the negative bias temperature instability of PMOS devices in this embodiment involves preparing a silicon nitride thin film layer with tensile stress using a furnace tube deposition process. The silicon nitride furnace tube deposition process involves heating and decomposing the reactive gas source at high temperature to induce a chemical reaction. The ions in the process are in thermal motion, so they do not have a large acceleration when they reach the substrate surface. Therefore, it can effectively reduce or even avoid the bombardment of the gate dielectric layer of the PMOS device by the reactive source ions during the chemical reaction, reduce the risk of damage to the gate dielectric layer of the PMOS device, and achieve the effect of improving the negative bias temperature instability of PMOS devices.

[0049] As described above, the method for improving the negative bias temperature instability of PMOS devices in this embodiment is a process improvement method suitable for fabricating both PMOS and NMOS devices on substrate 10. Therefore, as long as the devices fabricated on substrate 10 include both PMOS and NMOS devices, the improvement method of this embodiment can be used. This does not excessively limit the fabrication of other active or passive devices, isolation structures, etc. on substrate 10, and the specific selection can be made according to actual needs.

[0050] This embodiment does not excessively limit the fabrication methods and dimensions of the gate, source, and drain of NMOS and PMOS devices; the specific settings are determined according to actual needs. Generally, a gate-first process is used, where the gate is formed first, and then a self-aligned process is used to form the source and drain. The specific process can be implemented using existing conventional processes.

[0051] like Figure 2 As shown, as an example, the gate 101 of NMOS and PMOS devices generally includes a lower gate dielectric layer 102 (the material is generally silicon oxide), an upper polysilicon gate layer 103, and gate sidewalls 104 on the outer walls of both. The gate sidewalls 104 can be a single material layer or a stack of multiple layers of different materials from the inside out, depending on the actual needs.

[0052] like Figure 1 As shown, as an example, the substrate 10 is selected as a silicon substrate.

[0053] In this embodiment, the silicon nitride thin film layer preferably adopts low pressure chemical vapor deposition (LPCVD), thermal atomic layer deposition (TALD), and plasma enhanced atomic layer deposition (PEALD) processes suitable for furnace tube processes.

[0054] LPCVD preparation of silicon nitride uses a high-temperature furnace with a vacuum system. A silicon-containing gas source and a nitrogen-containing gas source undergo a chemical reaction at a preset high temperature to form silicon nitride deposition.

[0055] TALD is a method that alternately introduces a gaseous precursor pulse into a furnace tube, where it undergoes a surface chemisorption reaction on a substrate to form a thin film layer by layer. The chemisorption of the precursor on the substrate surface has the characteristics of self-limitation and self-saturation. Therefore, the thickness of the silicon nitride film can be controlled by the number of reaction cycles. Each cycle mainly includes the following four steps: 1. Introducing a precursor A pulse, which chemisorbs on the substrate surface; 2. Introducing an inert gas for cleaning to remove byproducts and excess precursor A; 3. Introducing a precursor B pulse, which reacts with the adsorbed precursor A to form a thin film; 4. Introducing an inert gas pulse again for cleaning.

[0056] The principle of PEALD is very similar to that of TALD, except that step 3 of the four main steps in each cycle is different. In step 3, PEALD uses a plasma-enhanced precursor B, which is plasma-enhanced before entering the furnace tube.

[0057] As an example, the deposition gas source required for depositing the silicon nitride thin film layer 105 using the furnace tube deposition process includes a silicon-containing gas source and a nitrogen-containing gas source; wherein, the silicon-containing gas source can be selected as hexachlorosilane or dichlorosilane, and the nitrogen-containing gas source can be selected as ammonia or a mixture of ammonia and nitrogen, that is, the nitrogen-containing gas source can be selected as only ammonia, or a mixture of ammonia and nitrogen.

[0058] As a specific example, when the furnace tube deposition process is a low-pressure chemical vapor deposition process, the deposition gas source required for depositing the silicon nitride thin film layer includes not only a silicon-containing gas source and a nitrogen-containing gas source, but also ethylene (C2H4) gas. The carbon element in the ethylene gas can be incorporated into the silicon nitride to effectively reduce the loss of silicon nitride in other processes. The silicon-containing gas source is selected as hexachlorosilane (HCD), and the nitrogen-containing gas source is selected as ammonia (NH3). The parameters of the low-pressure chemical vapor deposition process are: deposition temperature of 500℃~700℃, chamber pressure of 0.1 torr~1 torr, volumetric flow rate of hexachlorosilane of 0.01 slm~0.1 slm, volumetric flow rate of ammonia of 0.1 slm~10 slm, and volumetric flow rate of ethylene gas of 0 slm~5 slm (excluding 0 slm). Preferably, the parameters of the low-pressure chemical vapor deposition process are selected as follows: deposition temperature of 550℃~650℃, chamber pressure of 0.1 torr~1 torr, volumetric flow rate of hexachlorosilane of 0.01 slm~0.1 slm, volumetric flow rate of ammonia of 0.1 slm~2 slm, volumetric flow rate ratio of hexachlorosilane to ammonia of 1:10~1:40, and volumetric flow rate of ethylene gas of 0 slm~5 slm, excluding 0 slm. More preferably, the parameters of the low-pressure chemical vapor deposition process are selected as follows: deposition temperature of 550℃~650℃, chamber pressure of 0.1torr~1torr, volumetric flow rate of hexachlorosilane of 0.01slm~0.1slm, volumetric flow rate of ammonia of 0.1slm~2slm, volumetric flow rate of hexachlorosilane to ammonia of 1:25~1:40, and volumetric flow rate of ethylene gas of 0slm~5slm, excluding 0slm.

[0059] As another specific example, the furnace tube deposition process is a low-pressure chemical vapor deposition process, the silicon-containing gas source is dichlorosilane (DCS), and the nitrogen-containing gas source is ammonia (NH3). The parameters of the low-pressure chemical vapor deposition process are: deposition temperature of 500℃~800℃, chamber pressure of 0.05 torr~1 torr, volumetric flow rate of dichlorosilane of 0.05 slm~0.5 slm, and volumetric flow rate of ammonia of 0.1 slm~10 slm.

[0060] As another specific example, the furnace tube deposition process is a plasma-enhanced atomic layer deposition (PEALD) process, the silicon-containing gas source is dichlorosilane, and the nitrogen-containing gas source is ammonia. The parameters of the PEALD process are: deposition temperature of 500℃~700℃, chamber pressure of 0.1 torr~5 torr, volumetric flow rate of dichlorosilane of 1 slm~10 slm, and volumetric flow rate of ammonia of 1 slm~10 slm. Preferably, the parameters of the PEALD process are: deposition temperature of 500℃~600℃, chamber pressure of 0.1 torr~5 torr, volumetric flow rate of dichlorosilane of 1 slm~5 slm, volumetric flow rate of ammonia of 3 slm~10 slm, and the ratio of dichlorosilane volumetric flow rate to ammonia volumetric flow rate of 1:1.5~1:5.

[0061] As another specific example, the furnace tube deposition process is a thermal atomic layer deposition process, the silicon-containing gas source is dichlorosilane, and the nitrogen-containing gas source is ammonia; the parameters of the thermal atomic layer deposition process are: deposition temperature of 500℃~700℃, chamber pressure of 0.1torr~5torr, volumetric flow rate of dichlorosilane of 1slm~10slm, and volumetric flow rate of ammonia of 1slm~10slm.

[0062] After annealing the substrate 10 on which the silicon nitride thin film layer 105 is deposited, the silicon nitride thin film layer 105 can be removed or not removed as needed. For example... Figure 6 As shown, in many cases, the silicon nitride thin film layer 105 is removed.

[0063] like Figure 3 As shown, the furnace tube deposition process forms the silicon nitride thin film layer 105 on the exposed substrate surface. Therefore, preferably, as... Figure 4 As shown, after the silicon nitride thin film layer 105 is deposited in the furnace tube, the back silicon nitride thin film layer 106 on the back side of the substrate is removed.

[0064] As a preferred example, after depositing the silicon nitride thin film layer 105 on the substrate surface and before performing an annealing process on the silicon nitride thin film layer 105, the silicon nitride thin film layer 105 can be subjected to ultraviolet light irradiation (i.e., UV treatment). UV treatment of the silicon nitride thin film layer 105 can reduce the hydrogen content in the silicon nitride thin film layer 105, thereby mitigating the loss of P-type doped ions (e.g., boron ions) in the source and drain regions of the PMOS device due to the presence of hydrogen, and thus reducing the impact on the performance of the PMOS device.

[0065] As another preferred example, after depositing the silicon nitride thin film layer 105 on the substrate surface and before performing an annealing process on the silicon nitride thin film layer 105, the silicon nitride thin film layer 105 on the NMOS region can be subjected to plasma treatment. Specifically, this method includes: first, coating a photoresist layer onto the surface of the silicon nitride thin film layer 105; then, patterning the photoresist layer to form a patterned photoresist layer, the patterned photoresist layer exposing the silicon nitride thin film layer 105 on the NMOS region; next, performing plasma treatment on the silicon nitride thin film layer 105 on the NMOS region based on the patterned photoresist layer; and finally, removing the patterned photoresist layer. By using a method that shields the silicon nitride thin film layer 105 in the PMOS region and exposes the silicon nitride thin film layer 105 in the NMOS region for plasma treatment, the stress of the silicon nitride thin film layer 105 in the NMOS region can be increased without affecting the NBTI performance of the PMOS region, thereby improving the performance of the NMOS device.

[0066] The method for improving the negative bias temperature instability of PMOS devices in this embodiment is applicable to fabrication methods that require simultaneous fabrication of NMOS and PMOS devices on a substrate, such as in CMOS device fabrication processes.

[0067] To compare the effect of the method for improving the negative bias temperature instability of PMOS devices in this embodiment on improving the lifetime of PMOS devices, the lifetime of PMOS devices prepared using the three sets of furnace tube deposition process parameters of this embodiment to those prepared using the PECVD process were compared. The lifetime comparison results are shown in Table 1 below. Figure 7 .

[0068] Table 1. Parameters of the three groups of furnace tube deposition processes

[0069]

[0070] from Figure 7 As can be seen, the lifetime of the PMOS device obtained by fabricating a silicon nitride thin film using the PECVD process is 1 unit year; the lifetime of the PMOS device obtained by fabricating a silicon nitride thin film using the LPCVD HCD SiN process parameters is 4 unit years; the lifetime of the PMOS device obtained by fabricating a silicon nitride thin film using the LPCVD HCD SiN (nitrogen-rich) process parameters is 5.8 unit years; and the lifetime of the PMOS device obtained by fabricating a silicon nitride thin film using the PEALD DCS SiN process parameters is 9.4 unit years. Compared with the lifetime of the PMOS device obtained by fabricating a silicon nitride thin film using the PECVD process, all three processes in this experimental example effectively extended the lifetime of the PMOS device.

[0071] In summary, this invention proposes a method to improve the negative bias temperature instability (NBTI) of PMOS devices. It employs a furnace tube deposition process to prepare a silicon nitride thin film layer with tensile stress. This process involves heating and decomposing a reactive gas source at high temperatures to induce a chemical reaction. Since the ions in this process are in thermal motion, they do not experience significant acceleration upon reaching the substrate surface. Therefore, this effectively reduces or even eliminates the bombardment of the PMOS device's gate dielectric layer by the reactive ions during the chemical reaction, lowering the risk of damage and thus improving the NBTI of the PMOS device. Furthermore, by further processing the silicon nitride thin film layer, such as plasma treatment of the NMOS region or UV treatment, the stress in the NMOS region can be further increased or the impact on the electrical performance of the PMOS region can be mitigated, thereby improving device performance. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0072] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method of improving negative bias temperature instability of a PMOS device, comprising: The method comprises: providing a substrate comprising an NMOS region and a PMOS region; the NMOS region and the PMOS region are respectively formed with a gate, a source and a drain of an NMOS device and a PMOS device; depositing a tensile stress silicon nitride film layer on the surface of the substrate by a furnace tube deposition process; performing an annealing process on the substrate on which the tensile stress silicon nitride film layer is deposited, so as to memorize the tensile stress of the tensile stress silicon nitride film layer into the channel of the NMOS device.

2. The method of claim 1, wherein the PMOS device is a PMOS transistor. The furnace tube deposition process comprises a low pressure chemical vapor deposition process or a plasma enhanced atomic layer deposition process or a thermal atomic layer deposition process.

3. The method of claim 2, wherein the PMOS device is a PMOS transistor. The deposition gas source required for depositing the tensile stress silicon nitride film layer by the furnace tube deposition process comprises a silicon-containing gas source and a nitrogen-containing gas source; wherein the silicon-containing gas source is hexachlorodisilane or dichlorodisilane, and the nitrogen-containing gas source is ammonia or a mixed gas of ammonia and nitrogen.

4. The method of claim 3, wherein the method further comprises: The furnace tube deposition process is a low pressure chemical vapor deposition process, the silicon-containing gas source is hexachlorodisilane, and the nitrogen-containing gas source is ammonia; the parameters of the low pressure chemical vapor deposition process are as follows: the deposition temperature is 500-700℃, the chamber pressure is 0.1-1torr, the volume flow rate of hexachlorodisilane is 0.01-0.1slm, and the volume flow rate of ammonia is 0.1-10slm.

5. The method of claim 4, wherein the PMOS device is a PMOS transistor. The deposition temperature is 550-650℃, the volume flow rate of ammonia is 0.1-2slm, and the volume flow rate of hexachlorodisilane to the volume flow rate of ammonia is 1:10-1:

40.

6. The method of claim 5, wherein the PMOS device is a PMOS transistor. The volume flow rate of hexachlorodisilane to the volume flow rate of ammonia is 1:25-1:

40.

7. The method of claim 4-6, wherein: The deposition gas source required for depositing the tensile stress silicon nitride film layer by the low pressure chemical vapor deposition process further comprises ethylene gas, and the volume flow rate of ethylene gas is 0-5slm, excluding 0slm.

8. The method of claim 3, wherein the PMOS device is a PMOS transistor. The furnace tube deposition process is a low pressure chemical vapor deposition process, the silicon-containing gas source is dichlorodisilane, and the nitrogen-containing gas source is ammonia; the parameters of the low pressure chemical vapor deposition process are as follows: the deposition temperature is 500-800℃, the chamber pressure is 0.05-1torr, the volume flow rate of dichlorodisilane is 0.05-0.5slm, and the volume flow rate of ammonia is 0.1-10slm.

9. The method of claim 3, wherein the method further comprises: forming a first gate oxide layer on the first gate electrode; and forming a second gate oxide layer on the second gate electrode. The furnace tube deposition process is a plasma enhanced atomic layer deposition process, the silicon-containing gas source is dichlorodisilane, and the nitrogen-containing gas source is ammonia; the parameters of the plasma enhanced atomic layer deposition process are as follows: the deposition temperature is 500-700℃, the chamber pressure is 0.1-5torr, the volume flow rate of dichlorodisilane is 1-10slm, and the volume flow rate of ammonia is 1-10slm.

10. The method of claim 9, wherein the method further comprises: The deposition temperature is 500-600℃, the volume flow rate of dichlorodisilane is 1-5slm, the volume flow rate of ammonia is 3-10slm, and the volume flow rate of dichlorodisilane to the volume flow rate of ammonia is 1:1.5-1:

5.

11. The method of claim 3, wherein the method further comprises: The furnace tube deposition process is a thermal atomic layer deposition process, the silicon-containing gas source is dichlorodihydrogen silicon, and the nitrogen-containing gas source is ammonia; the parameters of the thermal atomic layer deposition process are as follows: a deposition temperature is 500-700 DEG C, a chamber pressure is 0.1-5 torr, a volume flow rate of the dichlorodihydrogen silicon is 1-10 slm, and a volume flow rate of the ammonia is 1-10 slm.

12. The method of claim 1, wherein the PMOS device is a PMOS transistor. The method further comprises the following steps: before the annealing process, removing the silicon nitride film layer deposited on the back surface of the substrate; and / or after the annealing process, removing the silicon nitride film layer.

13. The method of claim 1, wherein the PMOS device is a PMOS transistor. The method further comprises the following step: after the silicon nitride film layer is deposited on the surface of the substrate, performing UV treatment on the silicon nitride film layer.

14. The method of claim 1, wherein the PMOS device is a PMOS transistor. The method further comprises the following steps: After the silicon nitride film layer is deposited on the surface of the substrate, a patterned photoresist layer is formed on the silicon nitride film layer, wherein the patterned photoresist layer exposes the silicon nitride film layer on the NMOS region; The silicon nitride film layer on the NMOS region is subjected to plasma treatment based on the patterned photoresist layer.

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