SOI (Silicon On Insulator) substrate with single polycrystalline silicon interlayer and preparation method of SOI substrate

Abstract

The invention provides an SOI (Silicon On Insulator) substrate with a single polycrystalline silicon interlayer and a preparation method thereof, and the preparation method comprises the following steps: providing a first silicon wafer, and forming a first oxide layer on the surface of the first silicon wafer; providing a second silicon wafer, and forming a second oxide layer on the surface of the second silicon wafer; forming a polycrystalline silicon layer on the surface of the first oxide layer or the second oxide layer, and performing chemical mechanical polishing to obtain a smooth polycrystalline silicon layer; bonding the smooth polycrystalline silicon layer and the oxide layer on which the polycrystalline silicon layer is not formed, and not carrying out plasma activation treatment before bonding; and thinning and polishing the surface of the second silicon wafer to form a single crystal top silicon layer. According to the method, the SOI substrate with the single polycrystalline silicon interlayer can be obtained, the technological process for manufacturing a device by using the substrate can be simplified, and the purpose of easily obtaining a special structure can be achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor materials and preparation, in particular to a SOI substrate with a single polysilicon interlayer and a preparation method thereof. BACKGROUND

[0002] Silicon-On-Insulator (SOI) is a new type of silicon-based semiconductor material with wide application. The SOI substrate is a three-layer structure, the uppermost layer is a single crystal silicon layer for manufacturing devices, the middle layer is an insulating layer, usually a silicon dioxide layer, and the bottom layer is also a single crystal silicon layer. SOI technology realizes full dielectric isolation of devices and substrates through an insulating buried layer, which can effectively eliminate the parasitic latch effect in bulk silicon CMOS circuits, and has the advantages of small parasitic capacitance and high integration density.

[0003] Although SOI substrates have been applied in various types of semiconductor products, traditional SOI substrates also have some limitations. For example, in the field of radio frequency devices, due to the high variability of radio frequency device current and voltage, part of the high-frequency signal will be absorbed by the bottom silicon layer, resulting in electrical loss. Polysilicon has a high trap density, and by adding a layer of polysilicon interlayer, the leakage current and power loss generated by the device layer to the bottom silicon layer can be shielded.

[0004] With the continuous development of semiconductor technology, special SOI substrates need to be used for processing to achieve the purpose of realizing special functions, simplifying processes or easily obtaining special structures, and therefore a SOI substrate with a polysilicon interlayer and a preparation method thereof are needed. SUMMARY

[0005] The purpose of the present application is to provide a SOI substrate with a single polysilicon interlayer and a preparation method thereof to achieve the purpose of realizing special functions, simplifying processes or easily obtaining special structures.

[0006] In order to solve the above problems, a preparation method of a SOI substrate with a single polysilicon interlayer is provided below, comprising the following steps:

[0007] S1, providing a first silicon wafer, and forming a first oxide layer on the surface of the first silicon wafer;

[0008] S2, providing a second silicon wafer, and forming a second oxide layer on the surface of the second silicon wafer;

[0009] S3, forming a polysilicon layer on the surface of the first oxide layer or the second oxide layer and performing chemical mechanical polishing to obtain a smooth polysilicon layer;

[0010] S4. Bond the smooth polycrystalline silicon layer and the oxide layer without a polycrystalline silicon layer, including but not limited to the following two bonding methods: one is to bond the smooth polycrystalline silicon layer formed on the surface of the first oxide layer and the second oxide layer of the second silicon wafer; the other is to bond the smooth polycrystalline silicon layer formed on the surface of the second oxide layer and the first oxide layer of the first silicon wafer; no plasma activation treatment is performed before the bonding.

[0011] S5. Thinning and polishing the surface of the second silicon wafer to form a single-crystal top silicon layer.

[0012] This method effectively reduces bubbles at the bonding interface and improves bonding strength by removing the plasma activation treatment of the silicon wafer.

[0013] The roughness of the smooth polycrystalline silicon layer is ≤1 nm. Low surface roughness is beneficial for bonding between silicon wafers.

[0014] The first and second oxide layers are formed by thermal oxidation, with an oxidation temperature of 800-1100℃ and an oxidation time of 10 min-10 h. This process results in a denser, less defective thermal oxide layer, leading to better bonding. Furthermore, thermal oxidation allows for growth on both the front and back sides, which is beneficial for stress control and results in less warping of the finished product.

[0015] The polycrystalline silicon layer is formed by low-pressure chemical vapor deposition (LPCVD) at a temperature of 550-620°C for 1-4 hours. Polycrystalline silicon layers obtained within this process range exhibit high adhesion and uniform thickness.

[0016] The chemical mechanical polishing process is as follows: polishing pressure 3.5 psi, polishing fluid flow rate 150 mL / min, and polishing time 30 s. These parameters result in good polishing performance, producing a polycrystalline silicon layer with low roughness and uniform thickness.

[0017] The bonding is high-pressure vacuum bonding, with a pressure of 5-20 kN and a vacuum degree of 10. -3 -10 -5 mbar, bonding time 5-20 min. This process produces good bonding results for silicon wafers, effectively reducing bubbles on the bonding surface and improving bonding strength.

[0018] Following step S4, a high-temperature annealing process is performed: the annealing temperature is 1000℃-1150℃, the annealing time is 2h-4h, the atmosphere is nitrogen, and the flow rate is 0.01~20 liters / minute. High-temperature annealing can promote the removal of moisture from the bonding interface, eliminate interface defects, and effectively improve the bonding strength.

[0019] An SOI substrate having a single polycrystalline silicon interlayer is prepared according to the preparation method of an SOI substrate having a single polycrystalline silicon interlayer as described above.

[0020] The SOI substrate with a single polycrystalline silicon interlayer has a six-layer structure, which, from bottom to top, consists of: a back retaining layer, a first single-crystal silicon layer, a first oxide layer, a smooth polycrystalline silicon layer, a second oxide layer, and a single-crystal top silicon layer.

[0021] The thickness of the monocrystalline top silicon layer is ≥5μm; the thickness of the second oxide layer is ≤2μm; the thickness of the smooth polycrystalline silicon layer is ≤1μm; and the thickness of the first oxide layer is ≤2μm.

[0022] Compared with the prior art, the beneficial effects of the present invention mainly include:

[0023] 1. This invention provides an SOI substrate with a single polycrystalline silicon interlayer and a method for preparing the same.

[0024] 2. The SOI substrate in this invention can serve the purpose of achieving special functions, simplifying processes, or easily obtaining special structures. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This invention provides a flowchart of a method for preparing an SOI substrate with a single polycrystalline silicon interlayer.

[0027] Figure 2 This is a schematic diagram of the structure of the first silicon wafer after thermal oxidation treatment according to Embodiment 1 of the present invention.

[0028] Figure 3 This is a schematic diagram of the structure after a polycrystalline silicon layer is deposited on the surface of the first oxide layer, as provided in Embodiment 1 of the present invention.

[0029] Figure 4 This is a schematic diagram of the structure of the polycrystalline silicon layer on the surface of the first oxide layer after CMP treatment, as provided in Embodiment 1 of the present invention.

[0030] Figure 5 This is a schematic diagram of the structure of the second silicon wafer after thermal oxidation treatment, provided in an embodiment of the present invention.

[0031] Figure 6 This is a schematic diagram of the structure of the first silicon wafer and the second silicon wafer after bonding, as provided in Embodiment 1 of the present invention.

[0032] Figure 7 This diagram illustrates the effect of plasma activation technology on bonding performance according to an embodiment of the present invention. Figure A shows the CSAM image of the bonded sheet after plasma activation treatment, and Figure B shows the CSAM image of the bonded sheet after plasma activation removal.

[0033] Figure 8 This is a schematic diagram of the bonding sheet trimming process provided in Embodiment 1 of the present invention.

[0034] Figure 9 This is a schematic diagram of the structure of an SOI substrate with a single polycrystalline silicon interlayer provided in Embodiment 1 of the present invention.

[0035] Figure 10 This is a schematic diagram of the structure after a polycrystalline silicon layer is deposited on the surface of the second oxide layer, as provided in Embodiment 2 of the present invention.

[0036] Figure 11 This is a schematic diagram of the structure of the polycrystalline silicon layer on the surface of the second oxide layer after CMP treatment, as provided in Embodiment 2 of the present invention.

[0037] Figure 12 This is a schematic diagram of the structure of the first silicon wafer and the second silicon wafer after bonding, as provided in Embodiment 2 of the present invention.

[0038] Figure 13 This is a schematic diagram of the bonding sheet trimming process provided in Embodiment 2 of the present invention.

[0039] Figure 14 This is a schematic diagram of the structure of an SOI substrate with a single polycrystalline silicon interlayer provided in Embodiment 2 of the present invention. Detailed Implementation

[0040] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. The directional terms mentioned in the following embodiments, such as up, down, left, right, front, or back, are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative purposes and not for limiting the present invention.

[0041] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0042] The steps in the following embodiments do not correspond one-to-one with the contents of the invention.

[0043] Example 1

[0044] like Figure 1 The diagram shows a fabrication process of an SOI substrate with a single polycrystalline silicon interlayer provided by the present invention.

[0045] refer to Figure 1 This invention provides an SOI substrate with a single polycrystalline silicon interlayer and a method for preparing the same. The preparation method includes the following steps:

[0046] Step 1: Select a suitable first silicon wafer. Its size, crystal orientation, resistivity and other parameters are selected according to the requirements of the finished product.

[0047] In this embodiment, an 8-inch, P-type wafer with a resistivity of 1-100 ohm·cm is selected. <100> A double-sided polished silicon wafer with a crystal orientation and a thickness of 500μm is used as the first silicon wafer.

[0048] In other embodiments, the size of the first silicon wafer can be 4 inches, 6 inches, 8 inches, or 12 inches, the doping type can be N-type or P-type, and the crystal orientation can be [missing information]. <100> , <110> or <111> There are no strict restrictions on silicon wafer conditions; selection can be based on specific needs.

[0049] To meet the requirements of subsequent bonding, thinning and other processes, the first silicon wafer is required to have good flatness, and its TTV (the difference between the maximum and minimum thickness of the silicon wafer) value should be less than 2μm. The smaller the TTV value, the more uniform the overall thickness of the first silicon wafer, which is more conducive to accurate and uniform control of the device layer thickness.

[0050] Step 2: Use a thermal oxidation process to form an oxide layer of a certain thickness on the upper and lower surfaces of the first silicon wafer.

[0051] In this embodiment, the first silicon wafer is cleaned before thermal oxidation. The first silicon wafer is sequentially cleaned with DHF, SC1, and SC2 for 1-2 hours to remove the natural oxide layer and contaminants from its surface. Specifically, DHF is used to remove the natural oxide layer; SC1 is a mixed solution of ammonia, hydrogen peroxide, and ultrapure water to remove surface particles; and SC2 is a mixed solution of hydrochloric acid, hydrogen peroxide, and ultrapure water to clean metal contaminants.

[0052] In this embodiment, the specific thermal oxidation process is as follows: the first silicon wafer is thermally oxidized using a high-temperature furnace at an oxidation temperature of 1100°C for 2 hours. After the thermal oxidation process, the oxide layer thickness on both the upper and lower surfaces of the first silicon wafer is 1 μm.

[0053] The advantages of using thermal oxidation are as follows: First, the thermal oxidation film layer is dense with few defects, resulting in good bonding; second, thermal oxidation grows the entire wafer (both front and back), which is beneficial for stress control and results in less warpage of the finished product. Figure 2As shown, at this point, the structure of the first silicon wafer after thermal oxidation consists of a back oxide layer 103, a first monocrystalline silicon layer 101, and a surface oxide layer (i.e., the first oxide layer 102), which is a silicon dioxide layer. During the thermal oxidation process, an oxide layer (i.e., the back oxide layer 103) is also formed on the back side of the first silicon wafer. The presence of this oxide layer helps maintain the stress balance of the silicon wafer, reduces warpage, and allows subsequent bonding, thinning, and polishing processes to achieve better results. Therefore, the back oxide layer 103 will be retained in subsequent processes. Furthermore, in subsequent processes, the first oxide layer 102 will be connected to the polycrystalline silicon layer. When subjected to high temperatures, the first oxide layer 102 can passivate the polycrystalline silicon and prevent polycrystalline silicon recrystallization. In addition, the first oxide layer 102 can also serve as an etching stop layer.

[0054] In other embodiments, depending on the process requirements, by adjusting the thermal oxidation time and temperature, with the thermal oxidation temperature between 800-1100℃ and the time between 10min-10h, a first oxide layer 102 of different thicknesses (≤2μm) can be obtained.

[0055] In other embodiments, a first oxide layer 102 can also be formed on at least one surface of the first silicon wafer using a chemical vapor deposition process. However, other processes do not have the aforementioned advantages of thermal oxidation and are more difficult to bond. Thermal oxidation is the preferred process for buried oxide layers.

[0056] Step 3: Deposit a polycrystalline silicon layer of a certain thickness on the surface of the first oxide layer using a low-pressure chemical vapor deposition process.

[0057] In this embodiment, before performing low-pressure chemical vapor deposition on the surface of the first oxide layer 102, the first silicon wafer after step 2 is first cleaned. The first silicon wafer is sequentially cleaned with SC1 and SC2 for 1-2 hours to remove contaminants from its surface. Specifically, SC1 is a mixed solution of ammonia, hydrogen peroxide, and ultrapure water, used to remove surface particles; SC2 is a mixed solution of hydrochloric acid, hydrogen peroxide, and ultrapure water, used to clean metal contaminants.

[0058] In this embodiment, the specific low-pressure chemical vapor deposition process is as follows: Polycrystalline silicon is deposited on the upper and lower surfaces of the first silicon wafer after step 2, namely the back oxide layer 103 and the first oxide layer 102, using an LPCVD equipment. The deposition temperature is 600℃, the deposition time is 1.5h, the silicon source gas is SiH4, and the gas flow rate is 325sccm. After deposition, the thickness of the polycrystalline silicon layer on the upper and lower surfaces of the first silicon wafer is 0.5μm.

[0059] like Figure 3As shown, at this time, the first silicon wafer structure after low-pressure chemical vapor deposition is a back polycrystalline silicon layer 105, a back oxide layer 103, a first monocrystalline silicon layer 101, a first oxide layer 102, and a polycrystalline silicon layer 104.

[0060] Table 1 shows the surface roughness results of the polysilicon layer after deposition in this embodiment. At this point, the surface roughness of the polysilicon after deposition is relatively high, approximately 10 nm (in this application, roughness refers to the Rq value). Excessive roughness is detrimental to subsequent bonding, therefore subsequent polishing is necessary. The polysilicon layer can achieve high trap density, high resistivity, and good thermal stability at high temperatures (1100°C), effectively shielding the device layer from leakage current and power loss to the underlying silicon layer. Furthermore, different doping types can be introduced into the polysilicon layer via ion implantation to achieve the desired electrical pathways.

[0061] It should be noted that since the polysilicon layer 104 needs to be planarized using CMP (Chemical Mechanical Polishing) in the subsequent process, the thickness of the polysilicon layer 104 deposited here should be greater than the thickness of the polysilicon layer retained in the final structure; that is, a certain margin must be reserved during deposition. Generally, the CMP removal amount is about 0.3 μm. In this embodiment, the designed polysilicon interlayer thickness is 0.2 μm, therefore the deposition thickness at this point is 0.5 μm.

[0062] In other embodiments, depending on the process requirements, polycrystalline silicon layers 104 of different thicknesses (≤1.2μm) can be obtained by adjusting the vapor deposition time and temperature. When the process temperature is in the range of 550 to 620°C and the growth time is between 1 and 4 hours, polycrystalline silicon deposition layers with a thickness of 0.2 to 1.2μm can be obtained.

[0063] Step 4: Perform chemical mechanical polishing on the surface of the polycrystalline silicon layer 104 deposited in Step 3 to the required thickness.

[0064] Because polysilicon has a high surface roughness of approximately 10 nm after deposition, it cannot be directly bonded. By adding a CMP process, the surface roughness can be reduced to below 1 nm, meeting the bonding conditions and achieving a better bonding effect. In this embodiment, the thickness removed by CMP is approximately 0.3 μm, and the polysilicon layer 104 after CMP treatment is referred to as the smooth polysilicon layer 106.

[0065] CMP (Continuous Polishing) is a process technology that combines the physical abrasion of nanoparticles with the chemical etching of polishing slurry to smooth and flatten the surface of silicon wafers. In this embodiment, Huahai Qingke Universal-200Plus was used for CMP treatment of polysilicon layer 104. The equipment configuration included D2000E polishing slurry, DowIC1010 polishing pad, and 3M165 dressing disc. The specific CMP process conditions were: polishing pressure of 3.5 psi, polishing slurry flow rate of 150 mL / min, and polishing time of 30 s. Table 1 shows the surface roughness results of the polysilicon layer after deposition and after CMP in this embodiment. It can be seen that after CMP treatment using the above process, the required roughness value can be obtained, thereby improving subsequent bonding.

[0066] Table 1: Surface roughness results of the polysilicon layer after deposition and after CMP in this embodiment (8-inch wafer)

[0067]

[0068] The structure after CMP processing is as follows Figure 4 As shown, the first silicon wafer at this time has a five-layer structure, which are as follows from bottom to top: the back polycrystalline silicon layer 105, the back oxide layer 103; the first monocrystalline silicon layer 101; the first oxide layer 102; and the smooth polycrystalline silicon layer 106.

[0069] In this embodiment, the thickness of the polysilicon layer after CMP is 0.2 μm. In other embodiments, smooth polysilicon layers 106 (≤1 μm) of different thicknesses and roughness can be obtained by adjusting the polishing process parameters according to process requirements.

[0070] Step 5: Select a suitable second silicon wafer. Its size, crystal orientation, resistivity and other parameters should be selected according to the requirements of the finished product.

[0071] In this embodiment, an 8-inch, P-type wafer with a resistivity of 1-100 ohm·cm is selected. <100> A single-sided polished silicon wafer with a crystal orientation and a thickness of 700μm is used as the second silicon wafer.

[0072] In other embodiments, the size of the second silicon wafer can be 4 inches, 6 inches, 8 inches, or 12 inches, the doping type can be N-type or P-type, and the crystal orientation can be [missing information]. <100> , <110> or <111> There are no strict restrictions on silicon wafer conditions; selection can be based on specific needs.

[0073] It is understood that, in order to meet the bonding requirements, the first silicon wafer and the second silicon wafer selected in each embodiment are of the same size.

[0074] Step 6: Use a thermal oxidation process to form an oxide layer of a certain thickness on the upper and lower surfaces of the second silicon wafer.

[0075] In this embodiment, the second silicon wafer is cleaned before thermal oxidation. The second silicon wafer is sequentially cleaned with DHF, SC1, and SC2 for 1-2 hours to remove the natural oxide layer and contaminants from its surface. Specifically, DHF is used to remove the natural oxide layer; SC1 is a mixed solution of ammonia, hydrogen peroxide, and ultrapure water to remove surface particles; and SC2 is a mixed solution of hydrochloric acid, hydrogen peroxide, and ultrapure water to clean metal contaminants.

[0076] In this embodiment, the specific thermal oxidation process is as follows: the second silicon wafer is thermally oxidized in a high-temperature furnace at a temperature of 1100°C for 2 hours. After the thermal oxidation process, the oxide layer thickness on both the upper and lower surfaces of the second silicon wafer is 1 μm. The advantages of forming oxide layers on both the upper and lower surfaces of the silicon wafer using the thermal oxidation process are as described above and will not be repeated here. Figure 5 As shown, at this point, the structure of the second silicon wafer after thermal oxidation consists of a second back oxide layer 203, a second monocrystalline silicon layer 201, and a surface oxide layer (i.e., the second oxide layer 202), which is a silicon dioxide layer. In subsequent processes, the second oxide layer 202 will also be connected to the smooth polycrystalline silicon layer 106. When subjected to high-temperature processes, the second oxide layer 202, together with the first oxide layer 102, can passivate the polycrystalline silicon and prevent its recrystallization. Furthermore, the second oxide layer 202 can also serve as an etching stop layer.

[0077] In other embodiments, depending on the process requirements, by adjusting the thermal oxidation time and temperature, with the thermal oxidation temperature between 800-1100℃ and the time between 10min-10h, a second oxide layer 202 of different thicknesses (≤2μm) can be obtained.

[0078] In other embodiments, a second oxide layer 202 can also be formed on at least one surface of the second silicon wafer using a chemical vapor deposition process. However, other processes do not have the aforementioned advantages of thermal oxidation and are more difficult to bond. Thermal oxidation is the preferred process for forming the oxide layer.

[0079] Step 7: Bond the first silicon wafer after CMP treatment obtained in Step 4 and the second silicon wafer obtained after thermal oxidation in Step 6, that is, bond the smooth polycrystalline silicon layer 106 of the first silicon wafer after CMP treatment in Step 4 and the second oxide layer 202 of the second silicon wafer to form a bonded wafer; then, perform high-temperature annealing treatment on the bonded wafer.

[0080] like Figure 6As shown, in this embodiment, the bonding wafer has an eight-layer structure, which, from bottom to top, are: the back polycrystalline silicon layer 105, the back oxide layer 103; the first monocrystalline silicon layer 101; the first oxide layer 102; the smooth polycrystalline silicon layer 106; the second oxide layer 202; the second monocrystalline silicon layer 201; and the second back oxide layer 203.

[0081] In this embodiment, the specific bonding process is as follows:

[0082] 1) Before bonding, the first and second silicon wafers must be cleaned with SPM (a mixed solution of sulfuric acid, hydrogen peroxide and ultrapure water) at 120°C for 10 minutes to remove organic matter from the surface; then the first and second silicon wafers must be cleaned with SC1 at 60°C for 10 minutes to remove surface particles.

[0083] 2) Rinse the first and second silicon wafers with deionized water (DI water) after cleaning and spin dry. The rinsing speed is 200-500 rpm / min and the water washing time is 30s. The spin drying speed is 2500 rpm / min and the spin drying time is 15s to remove surface particles.

[0084] 3) The first and second silicon wafers described above are subjected to high-pressure vacuum bonding, that is, the smooth polycrystalline silicon layer 106 surface of the first silicon wafer and the second oxide layer 202 surface of the second silicon wafer are bonded together in a vacuum environment, and a certain pressure is applied to the silicon wafers to achieve bonding; in this embodiment, the bonding conditions are room temperature, pressure of 10KN, and vacuum degree of 5×10 - 4 mbar, bonding time 20 min. In other embodiments, the bonding pressure is 5-20 kN, and the vacuum degree is 10. -3 -10 -5 mbar, bonding time 5-20 min.

[0085] 4) The bonded silicon wafers are annealed at temperatures above 1000°C to increase bond strength. High temperatures promote atomic interactions at the bonding interface, forming more covalent bonds, resulting in a stronger bond and increased bonding strength. In this embodiment, the annealing temperature is 1100°C, the annealing time is 4 hours, the atmosphere is nitrogen, and the flow rate is 0.01–20 liters / minute. In other embodiments, the annealing temperature is 1000°C–1150°C, the annealing time is 2–4 hours, the atmosphere is nitrogen, and the flow rate is 0.01–20 liters / minute. Compared to low-temperature annealing, high-temperature annealing produces better results, with fewer bubbles and higher strength. In other embodiments, low-temperature annealing can be attempted when the structure does not allow for high-temperature annealing.

[0086] Traditional SOI substrates consist of a single-crystal silicon layer and an oxide layer bonded together. Plasma activation treatment (performed after SPM+SC1 cleaning) can be applied to the silicon wafer before bonding to activate the surface and improve bonding performance to some extent. In this embodiment, the bonding surface is between a polycrystalline silicon layer and an oxide layer. We found that because the structure of polycrystalline silicon is relatively porous, plasma treatment causes significant surface damage, leading to excessive moisture adsorption during subsequent cleaning. This moisture cannot be completely removed during the subsequent high-temperature annealing process, resulting in bubbles remaining in the bonding layer.

[0087] Figure 7 The results shown are obtained by scanning ultrasonic microscopy (CSAM) of the bonded surfaces under two processes: plasma activation treatment and no plasma activation treatment. Figure 7 Figure A shows the CSAM results of the bonded interface after plasma activation treatment, which shows that there are a large number of bubble defects in the bonded interface. Figure 7 Figure B shows the CSAM results of the bonding interface after removing the plasma activation treatment, indicating a significantly tighter bond. This result demonstrates that for bonding polycrystalline silicon and silicon dioxide surfaces, the plasma activation process leads to numerous bubble defects at the bonding interface, resulting in poor bonding performance. Therefore, in this embodiment, the plasma activation process was omitted.

[0088] Step 8: Trim the edges of the bonding wafer after high-temperature annealing in Step 7, that is, trim the edges of the second silicon wafer on top of the bonding wafer.

[0089] like Figure 8 As shown, in this embodiment, the edge of the second silicon wafer is first processed using a thinning machine, grinding off 2-3 mm of the edge, i.e., the width of the trimmed edge is 2-3 mm. Simultaneously, to ensure the complete removal of the second silicon wafer edge, the edge of the first silicon wafer is ground downwards for 20-50 μm, i.e., to a depth of 20-50 μm below the lower surface of the second single-crystal silicon layer 201 of the bonding wafer. This embodiment removes areas with weak edge bonding force by trimming the edge, thereby effectively eliminating edge stress, enhancing the overall bonding force of the bonding wafer, improving the overall bonding quality, and preventing peeling defects during subsequent thinning and polishing processes.

[0090] Step 9: Thin and polish the surface of the bonding sheet after the edge trimming process in Step 8 to the required thickness to obtain an SOI substrate with a single polycrystalline silicon interlayer.

[0091] In this embodiment, the thinning and polishing process consists of two steps: mechanical thinning and chemical mechanical polishing. The first step is the mechanical thinning process, which is divided into coarse grinding and fine grinding. The coarse grinding wheel has a mesh size of 2500, which thins the second monocrystalline silicon layer 201 of the bonding wafer to the required monocrystalline top silicon layer thickness + 20μm (in this embodiment, the designed thickness of the monocrystalline top silicon layer is 5μm, so it should stop at around 25μm thickness, that is, the second back oxide layer 203 and part of the second monocrystalline silicon layer 201 on the surface of the second silicon wafer are removed by mechanical thinning until the remaining thickness of the second monocrystalline silicon layer 201 is around 25μm). Then, fine grinding is performed with a mesh size of 8000. The remaining thickness of about 20μm is ground away to the target thickness using an 8000-mesh fine grinding wheel. It is important to leave a margin for the subsequent polishing process in the fine grinding process, that is, the target thickness (5.8μm) here is the thickness of the monocrystalline top silicon layer plus the thickness removed by polishing. Next, a polishing process is performed using chemical mechanical polishing (CMP) to finely polish the surface, removing approximately 0.8 μm of thickness until the surface roughness is less than 1 nm. At this point, the remaining portion of the second single-crystal silicon layer 201 after thinning and polishing becomes the single-crystal top silicon layer 204. Thus, an SOI substrate with a single polycrystalline silicon interlayer is obtained.

[0092] The structure of the SOI substrate with a single polycrystalline silicon sandwich layer is as follows: Figure 9 As shown, the SOI substrate has a seven-layer structure, which are as follows from bottom to top: the back polycrystalline silicon layer 105, the back oxide layer 103; the first single-crystal silicon layer 101; the first oxide layer 102; the smooth polycrystalline silicon layer 106; the second oxide layer 202; and the single-crystal top silicon layer 204.

[0093] Here, the back polycrystalline silicon layer 105 and the back oxide layer 103 can be regarded as a whole structure, referred to as the back retaining layer. The structure at this time has six layers, from bottom to top: the back retaining layer; the first monocrystalline silicon layer 101; the first oxide layer 102; the smooth polycrystalline silicon layer 106; the second oxide layer 202; and the monocrystalline top silicon layer 204.

[0094] In this embodiment, the thickness of the monocrystalline top silicon layer 204 is 5 μm. In other embodiments, monocrystalline top silicon layers 204 of different thicknesses (≥5 μm) can be obtained by adjusting the thinning and polishing times according to process requirements.

[0095] As described above, the smooth polysilicon layer 106 itself possesses high trap density, high resistivity, and good thermal stability at high temperatures (1100°C). Furthermore, the first oxide layer 102 and the second oxide layer 202 disposed on both sides of the smooth polysilicon layer 106 further passivate the polysilicon and prevent recrystallization, ensuring the stability of the polysilicon in the substrate at high temperatures. This allows the smooth polysilicon layer 106 to better shield the device layer from leakage current and power loss generated by the bottom silicon layer. In addition, during subsequent device fabrication, the first oxide layer 102 and the second oxide layer 202 can also serve as etch stop layers, working in conjunction with the single-crystal top silicon layer 204 to construct specialized structures. SOI substrates with a single polysilicon interlayer can achieve special functions, simplify processes, or easily obtain special structures.

[0096] Example 2

[0097] like Figure 1 The diagram shown is a process flow chart for manufacturing an SOI substrate with a single polycrystalline silicon interlayer provided by the present invention.

[0098] Example 2 shares the same main technical content as Example 1, with the main difference being that the polysilicon layer is formed on the surface of the second oxide layer of the second silicon wafer instead of the surface of the first oxide layer of the first silicon wafer. Steps 1 to 2 are identical in both examples and will not be repeated here. The following description begins with step 3.

[0099] Step 3: Select a suitable second silicon wafer. Its size, crystal orientation, resistivity, and other parameters are selected according to the finished product requirements. The selected second silicon wafer is the same as in Step 5 of Example 1.

[0100] Step 4: Use a thermal oxidation process to form an oxide layer of a certain thickness on the upper and lower surfaces of the second silicon wafer.

[0101] The specific process of this step is the same as step 6 in Example 1. The structure of the second silicon wafer after thermal oxidation is as follows: Figure 5 As shown, from bottom to top, the layers are the second back oxide layer 203, the second single-crystal silicon layer 201, and the second oxide layer 202.

[0102] Step 5: Deposit a polycrystalline silicon layer of a certain thickness on the surface of the second oxide layer using a low-pressure chemical vapor deposition process.

[0103] In this embodiment, before performing low-pressure chemical vapor deposition on the surface of the second oxide layer 202, the second silicon wafer after step 4 is first cleaned. The process is the same as step 3 in Embodiment 1.

[0104] In this embodiment, polysilicon is deposited on the upper and lower surfaces of the second silicon wafer, namely the surfaces of the second back oxide layer 203 and the second oxide layer 202, and the specific process is as described in step 3 of embodiment one.

[0105] like Figure 10 As shown, at this time, the second silicon wafer structure after low-pressure chemical vapor deposition is a back polycrystalline silicon layer 206, a second back oxide layer 203, a second monocrystalline silicon layer 201, a second oxide layer 202, and a polycrystalline silicon layer 205.

[0106] Step 6: Perform chemical mechanical polishing on the surface of the polycrystalline silicon layer 205 deposited in Step 5 to the required thickness.

[0107] In this embodiment, the specific process of this step is the same as step 4 in embodiment 1, and after polysilicon layer 205CMP, there is a smooth polysilicon layer 207.

[0108] The structure after CMP processing is as follows Figure 11 As shown, the second silicon wafer at this time has a five-layer structure, which are as follows from bottom to top: the back polycrystalline silicon layer 206, the second back oxide layer 203; the second monocrystalline silicon layer 201; the second oxide layer 202; and the smooth polycrystalline silicon layer 207.

[0109] Step 7: Bond the second silicon wafer after CMP treatment obtained in Step 6 and the first silicon wafer obtained after thermal oxidation in Step 2, that is, bond the smooth polycrystalline silicon layer 207 of the second silicon wafer after CMP treatment in Step 6 to the first oxide layer 102 of the first silicon wafer to form a bonded wafer; then, perform high-temperature annealing treatment on the bonded wafer.

[0110] In this embodiment, the specific process of this step is the same as step 7 in Embodiment 1.

[0111] like Figure 12 As shown, in this embodiment, the bonding wafer has an eight-layer structure, which are as follows from bottom to top: the back oxide layer 103; the first monocrystalline silicon layer 101; the first oxide layer 102; the smooth polycrystalline silicon layer 207; the second oxide layer 202; the second monocrystalline silicon layer 201; the second back oxide layer 203; and the back polycrystalline silicon layer 206.

[0112] Step 8: Trim the edges of the bonding wafer after high-temperature annealing in Step 7, that is, trim the edges of the second silicon wafer on top of the bonding wafer.

[0113] In this embodiment, the specific process of this step is the same as step 8 in Embodiment 1. The structure after trimming is as follows: Figure 13 As shown.

[0114] Step 9: Thin and polish the surface of the bonding sheet after the edge trimming process in Step 8 to the required thickness to obtain an SOI substrate with a single polycrystalline silicon interlayer.

[0115] In this embodiment, the specific process of this step is the same as that in step 9 of embodiment one.

[0116] The structure of the SOI substrate with a single polycrystalline silicon sandwich layer is as follows: Figure 14 As shown, the SOI substrate at this time has a six-layer structure, which are as follows from bottom to top: the back retaining layer (i.e., the back oxide layer 103); the first single crystal silicon layer 101; the first oxide layer 102; the smooth polycrystalline silicon layer 207; the second oxide layer 202; and the single crystal top silicon layer 208.

[0117] The schemes of Embodiment 1 and Embodiment 2 are slightly different, but the final structure of the SOI substrate with a single polycrystalline silicon interlayer is basically the same. In this Embodiment 2, the smooth polycrystalline silicon layer 207 corresponds to the smooth polycrystalline silicon layer 106 in Embodiment 1, and the single-crystal top silicon layer 208 corresponds to the single-crystal top silicon layer 204 in Embodiment 1.

[0118] The common English terms or letters used in this invention for clarity of description are for illustrative purposes only and are not limiting interpretations or specific uses. They should not be used to limit the scope of protection of this invention based on their possible Chinese translations or specific letters.

[0119] It should also be noted that in this article, relational terms such as “first” and “second” are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

Claims

1. A method for fabricating an SOI substrate with a single polycrystalline silicon interlayer, characterized in that, Includes the following steps: S1. A first silicon wafer is provided, and a first oxide layer is formed on the surface of the first silicon wafer; S2. Provide a second silicon wafer, and form a second oxide layer on the surface of the second silicon wafer; S3. A polycrystalline silicon layer is formed on the surface of the first oxide layer or the second oxide layer and chemically mechanically polished to obtain a smooth polycrystalline silicon layer. S4. Bond the smooth polycrystalline silicon layer and the oxide layer without polycrystalline silicon layer, without performing plasma activation treatment before bonding; S5. Thinning and polishing the surface of the second silicon wafer to form a single-crystal top silicon layer.

2. The method for preparing an SOI substrate with a single polycrystalline silicon interlayer according to claim 1, characterized in that, The roughness of the smooth polycrystalline silicon layer is ≤1nm.

3. The method for preparing an SOI substrate with a single polycrystalline silicon interlayer according to claim 1, characterized in that, The first oxide layer and the second oxide layer are formed by thermal oxidation treatment. The oxidation temperature of the first oxide layer and the second oxide layer is 800-1100℃, and the oxidation time is 10min-10h.

4. The method for preparing an SOI substrate with a single polycrystalline silicon interlayer according to claim 1, characterized in that, The polycrystalline silicon layer is formed by low-pressure chemical vapor deposition at a temperature of 550-620°C for 1-4 hours.

5. The method for preparing an SOI substrate with a single polycrystalline silicon interlayer according to claim 1, characterized in that, The chemical mechanical polishing process is as follows: polishing pressure 3.5 psi, polishing fluid flow rate 150 mL / min, polishing time 30 s.

6. The method for preparing an SOI substrate with a single polycrystalline silicon interlayer according to claim 1, characterized in that, The bonding is high-pressure vacuum bonding, with a pressure of 5-20 kN and a vacuum degree of 10. -3 -10 -5 mbar, bonding time 5-20 min.

7. The method for preparing an SOI substrate with a single polycrystalline silicon interlayer according to claim 1, characterized in that, After step S4, a high-temperature annealing process is also included: the annealing temperature is 1000℃-1150℃, the annealing time is 2h-4h, the atmosphere is nitrogen, and the flow rate is 0.01~20 liters / minute.

8. An SOI substrate having a single polycrystalline silicon interlayer, characterized in that, The SOI substrate with a single polycrystalline silicon interlayer is prepared according to any one of claims 1-7.

9. An SOI substrate with a single polycrystalline silicon interlayer according to claim 8, characterized in that, The SOI substrate with a single polycrystalline silicon interlayer has a six-layer structure, which, from bottom to top, consists of: a back-side retention layer, a first single-crystal silicon layer, a first oxide layer, a smooth polycrystalline silicon layer, a second oxide layer, and a single-crystal top silicon layer.

10. An SOI substrate with a single polycrystalline silicon interlayer according to claim 9, characterized in that, The thickness of the monocrystalline top silicon layer is ≥5μm; the thickness of the second oxide layer is ≤2μm; the thickness of the smooth polycrystalline silicon layer is ≤1μm; and the thickness of the first oxide layer is ≤2μm.

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