A compact electrostatic and surge protection device

Abstract

The application provides a compact electrostatic and surge protection device, comprising a wafer and a plurality of device modules arranged in parallel in the wafer, two ends of the device module being electrically connected with an upper surface of the wafer and a lower surface of the wafer respectively, the upper surface of the wafer and the lower surface of the wafer each being provided with an electrode, the device module being composed of M stacked device modules in series, M being a positive integer, M being greater than or equal to 1 and the number of device modules M of at least one device module being greater than or equal to 2, the stacking direction of the device module being perpendicular to the upper surface of the wafer and the lower surface of the wafer, there being at least one device module with voltage resistance capacity in at least one device module, and an electrostatic and surge discharge channel being formed in the device module. The application has the beneficial effect that the voltage resistance capacity can be significantly improved while maintaining the wafer area and the surge protection capacity.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge (ESD) protection devices, and more specifically to a compact ESD and surge protection device. Background Technology

[0002] Electromagnetic interference (EMI) refers to the coupling of signals from one electrical network to another by an interference source (typically electronic equipment) through a conductive medium (such as cables) or spatial radiation. Filters are a good EMI solution; they allow specific frequency components of a signal to pass through while significantly attenuating or suppressing other frequency components. For certain applications, filters can remove noise or harmonics that interfere with normal signals within the system. For example, low-pass filters can be used in signal processing circuits such as digital signals, communications, audio, image, video compression, and sensor outputs to effectively filter out high-frequency noise while retaining low-frequency signal components, thereby improving signal quality.

[0003] Electrostatic discharge (ESD) is a phenomenon in which the charge stored in a human body or substance is discharged to surrounding objects through a conductive channel. Transient voltage suppressors (TVS) can provide efficient electrostatic protection for electronic circuits.

[0004] In the research and development and application of modern electronic products, electrostatic discharge (ESD) and surge protection have become crucial for ensuring stable equipment operation and extending its lifespan. With the rapid development of electronic technology and the continuous increase in the integration of electronic products, the sensitivity of internal circuits and components to ESD and surges is also constantly increasing. In everyday environments, static electricity discharge from the human body, surges generated during the start-up and shutdown of industrial equipment, or electrical transients caused by lightning strikes can all exceed the tolerance threshold of electronic equipment, damaging core components such as chips and circuit boards, causing data loss, equipment malfunctions, and even safety accidents.

[0005] TVS (Transient Voltage Suppressor) products have become the mainstream choice in the field of electrostatic discharge (ESD) and surge protection due to their advantages such as fast response speed, strong surge absorption capability, and good clamping characteristics. Among them, Zener diodes utilize reverse breakdown characteristics to quickly clamp voltage, making them suitable for low-voltage, low-power protection scenarios; NPN and PNP TVS, with their transistor structure, precisely regulate current and voltage in signal line protection, ensuring that signal transmission is not interfered with; and SCRs, with their high surge withstand capability, excel in harsh scenarios such as high-power equipment and lightning protection, building a multi-level, all-round ESD and surge protection network for modern electronic products, supporting the stable and reliable operation of electronic equipment in complex electromagnetic environments.

[0006] However, for some typical high-voltage applications, such as USB fast charging ports, RF antenna ports, and automotive 24V / 48V applications, TVS products are usually limited by the "power law." This means that as the operating voltage of the product increases, its surge protection level typically decreases. To maintain robustness in this case, a larger chip area is required, undoubtedly increasing manufacturing costs. On the other hand, for vertically structured TVS products, using multiple chips in series in the package can improve the product's high-voltage withstand capability without compromising robustness. However, this usually significantly increases packaging costs and can easily lead to reliability issues.

[0007] Figure 1 This diagram illustrates two classic TVS device structures. The left side shows a unidirectional Zener diode, whose anode is typically connected to a power or signal port, and its cathode is usually grounded. The right side shows a bidirectional PNP device, providing bidirectional voltage blocking capability and bidirectional ESD and surge protection. However, for some typical high-voltage applications, it is necessary to increase the breakdown voltage of these TVS devices, which inevitably degrades their robustness. In this case, to maintain the same surge and ESD protection capabilities, the chip area needs to be increased, which increases manufacturing costs and makes miniaturization packaging difficult. Summary of the Invention

[0008] To address the problems in the prior art, this invention provides a compact electrostatic discharge (ESD) and surge protection device. By incorporating mutually cooperating wafers and device modules within the compact ESD and surge protection device, multiple semiconductor device modules are vertically stacked in a direction perpendicular to the wafer surface to form a device module. The device module contains ESD and surge discharge channels, which significantly improves withstand voltage while maintaining the wafer area and surge protection capability. This solves the problem that classic TVS devices in the prior art struggle to balance high breakdown voltage and robustness in some typical high-voltage applications.

[0009] This invention provides a compact electrostatic discharge (ESD) and surge protection device, comprising a wafer and multiple device modules arranged in parallel within the wafer. The two ends of each device module are electrically connected to the upper and lower surfaces of the wafer, respectively. Each of the upper and lower surfaces of the wafer is provided with an electrode. The upper surface of the wafer can be electrically connected to port one, and the lower surface of the wafer can be electrically connected to port two. Each device module consists of M stacked device modules connected in series, where M is a positive integer, M≥1, and at least one device module has a number of device modules M not less than 2. The stacking direction of the device modules is perpendicular to the upper and lower surfaces of the wafer. At least one device module contains at least two device modules with withstand voltage capability. When only one device module has exactly two stacked device modules, the device modules in that device module are not allowed to be single forward-biased PN diodes without withstand voltage capability. An ESD and surge discharge channel is formed within the device module.

[0010] The present invention is further improved in that the device module is a PN diode, Zener diode, NPN transistor, PNP transistor, silicon controlled rectifier, or field-effect transistor.

[0011] The present invention is further improved in that the wafer is single-crystal silicon, gallium arsenide, gallium nitride, or silicon carbide.

[0012] In a further improvement to the present invention, among the multiple device modules connected in parallel, an isolation structure is provided between two adjacent device modules, wherein the isolation structure is an isolation deep trench or an isolation deep PN junction.

[0013] The present invention is further improved in that the structure of the device module is either a homogeneous stacking of device modules of the same type stacked vertically, or a heterogeneous stacking of device modules of different types stacked vertically.

[0014] The present invention is further improved in that the device module is a simplified device module, which includes, from top to bottom, a first P-type active region, a first N-type epitaxial layer, a first P-type epitaxial layer, a second N-type epitaxial layer, and a first P-type doped substrate. The first P-type active region, the first N-type epitaxial layer, and the first P-type epitaxial layer constitute a bidirectional first PNP transistor. The bidirectional first PNP transistor is located near the upper surface of the wafer. The first P-type epitaxial layer, the second N-type epitaxial layer, and the first P-type doped substrate constitute a bidirectional second PNP transistor. The bidirectional second PNP transistor is located near the lower surface of the wafer. The bidirectional first PNP transistor and the bidirectional second PNP transistor are stacked vertically to form the simplified device module. A bidirectional electrostatic discharge and surge discharge channel is formed within the simplified device module.

[0015] The present invention is further improved in that the doping concentration of the first P-type active region is C1, and the value of C1 ranges from 1e19cm. -3 ≤C1≤5e21cm -3 The doping concentration of the first P-type doped substrate is C2, and the value of C2 ranges from 1e19cm. -3 ≤C2≤5e21cm -3 The doping concentration of the first P-type epitaxial layer is C3, and the value of C3 ranges from 5e18cm. -3 ≤C3≤1e21cm -3 The doping concentration of the first N-type epitaxial layer is C4, and the value of C4 ranges from 1e13cm. -3 ≤C4≤1e18cm -3 The doping concentration of the second N-type epitaxial layer is C5, and the value of C5 ranges from 1e13cm. -3 ≤C5≤1e18cm -3 .

[0016] The present invention is further improved in that the plurality of device modules include one forward discharge channel device module and one reverse discharge channel device module. The forward discharge channel device module and the reverse discharge channel device module constitute a dual discharge channel device module unit. The dual discharge channel device module unit includes, from top to bottom, a dual discharge channel P-type active region, a dual discharge channel first layer N-type epitaxial layer, a dual discharge channel P-type buried layer, a dual discharge channel N-type buried layer, and a dual discharge channel first layer P-type epitaxial layer. An epitaxial layer and a dual-channel N-type doped substrate are provided. The dual-channel P-type active region, the first N-type epitaxial layer, and the dual-channel P-type buried layer constitute a dual-channel first PNP transistor. The dual-channel first PNP transistor is located near the upper surface of the wafer. The dual-channel P-type buried layer and the dual-channel N-type buried layer constitute a dual-channel first PN diode. The dual-channel N-type buried layer and the first P-type epitaxial layer... The first NPN transistor of the dual-discharge channel is formed by the N-type doped substrate of the dual-discharge channel. The first NPN transistor of the dual-discharge channel is close to the lower surface of the wafer. The first PNP transistor of the dual-discharge channel, the first PN diode of the dual-discharge channel, and the first NPN transistor of the dual-discharge channel are stacked vertically to form the forward discharge channel device module. A reverse N-type active region of the dual-discharge channel is also provided near the upper surface of the wafer in the first N-type epitaxial layer of the dual-discharge channel, which cooperates with the P-type active region of the dual-discharge channel. The N-type doped substrate of the dual-discharge channel, the first P-type epitaxial layer of the dual-discharge channel, the first N-type epitaxial layer of the dual-discharge channel, and the reverse N-type active region of the dual-discharge channel constitute the reverse discharge channel device. A forward surge discharge channel is formed in the forward discharge channel device module, and a reverse surge discharge channel is formed in the reverse discharge channel device module. The forward surge discharge channel and the reverse surge discharge channel are connected in parallel.

[0017] The present invention is further improved in that the doping concentration of the dual-discharge channel P-type buried layer is C6, and the value of C6 ranges from 1e19cm. -3 ≤C6≤5e21cm -3 The doping concentration of the dual-discharge channel N-type buried layer is C7, and the value of C7 ranges from 1e19cm. -3 ≤C7≤5e21cm -3 .

[0018] The present invention is further improved in that the plurality of device modules include one forward high-voltage device module and one reverse high-voltage device module. The forward high-voltage device module and the reverse high-voltage device module constitute a high-voltage device module unit. The high-voltage device module unit includes, from top to bottom, a high-voltage P-type active region, a high-voltage first N-type epitaxial layer, a high-voltage P-type buried layer, a high-voltage N-type buried layer, a high-voltage second N-type epitaxial layer, a high-voltage P-type doped substrate, and a high-voltage N-type active region. The P-type active region, the high-voltage first N-type epitaxial layer, and the high-voltage P-type buried layer constitute a high-voltage first PNP transistor. The high-voltage first PNP transistor is located near the upper surface of the wafer. The high-voltage P-type buried layer, the high-voltage second N-type epitaxial layer, the high-voltage P-type doped substrate, and the high-voltage N-type active region constitute a high-voltage first silicon-controlled rectifier. The high-voltage first silicon-controlled rectifier is located near the lower surface of the wafer. The high-voltage first PNP transistor and the high-voltage first... The silicon controlled rectifiers are vertically stacked to form the forward high-voltage device module. A high-voltage reverse N-type active region, cooperating with the high-voltage P-type active region, is also provided near the upper surface of the wafer within the first high-voltage N-type epitaxial layer. A high-voltage reverse P-type active region, cooperating with the high-voltage N-type active region, is also provided near the lower surface of the wafer within the high-voltage P-type doped substrate. The high-voltage P-type active region, the first high-voltage N-type epitaxial layer, the high-voltage P-type buried layer, and the second high-voltage N-type epitaxial layer... A forward surge discharge channel is formed within the epitaxial layer, the high-voltage P-type doped substrate, and the high-voltage N-type active region. The high-voltage reverse P-type active region, the high-voltage P-type doped substrate, the high-voltage second N-type epitaxial layer, the high-voltage first N-type epitaxial layer, and the high-voltage reverse N-type active region constitute the reverse high-voltage device module, within which a reverse surge discharge channel is formed. The doping concentration of the high-voltage P-type doped substrate is C8, and the value of C8 ranges from 1e14cm. -3 ≤C8≤1e18cm -3 .

[0019] The present invention is further improved in that the number of device modules is N, where N is a positive integer and N≥2. The bottom of each device module is provided with a common P-type doped substrate or N-type doped substrate and a back port is led out. Each device module has a port connected to its top. Single or multiple device modules can form a vertical current channel with the back port, and multiple device modules can form a horizontal current channel with each other.

[0020] Compared with the prior art, the beneficial effects of the present invention are: it provides a compact electrostatic discharge (ESD) and surge protection device, which sets up mutually cooperating wafers and device modules within the compact ESD and surge protection device. Multiple device modules are arranged in parallel within the wafer, and multiple semiconductor device modules are vertically stacked in a direction perpendicular to the wafer surface to form a device module. The device module forms an ESD and surge discharge channel, thus constituting an ESD and surge protection device. It can significantly improve the withstand voltage capability while maintaining the wafer area and surge protection capability unchanged, and flexibly adjust the electrical IV characteristic curve. It solves the problem that the classic TVS device in the prior art is difficult to balance high breakdown voltage and robustness in some typical high voltage application scenarios. Attached Figure Description

[0021] To more clearly illustrate the solutions in this invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0022] Figure 1 Schematic diagrams of two existing classic TVS device structures;

[0023] Figure 2 This is a schematic diagram of the first embodiment of the compact electrostatic and surge protection device of the present invention;

[0024] Figure 3(a) is a schematic diagram of the second embodiment of the compact electrostatic and surge protection device of the present invention;

[0025] Figure 3(b) shows the IV characteristic curve of the second embodiment of the compact electrostatic and surge protection device of the present invention;

[0026] Figure 4(a) is a schematic diagram of the third embodiment of the compact electrostatic and surge protection device of the present invention;

[0027] Figure 4(b) shows the IV characteristic curve of the third embodiment of the compact electrostatic and surge protection device of the present invention;

[0028] Figure 5(a) is a schematic diagram of the fourth embodiment of the compact electrostatic and surge protection device of the present invention;

[0029] Figure 5(b) shows the IV characteristic curve of the fourth embodiment of the compact electrostatic and surge protection device of the present invention;

[0030] Figure 6 This is a schematic diagram of the fifth embodiment of the compact electrostatic and surge protection device of the present invention. Detailed Implementation

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs; the terminology used herein and in the specification of the application is for the purpose of describing particular embodiments only and is not intended to limit the invention; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings are used to distinguish different objects and not to describe a particular order.

[0032] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0033] To enable those skilled in the art to better understand the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0034] like Figure 2 As shown in Figure 5(b), the present invention provides a compact electrostatic discharge (ESD) and surge protection device, comprising a wafer and multiple device modules 250 arranged in parallel within the wafer. The two ends of each device module 250 are electrically connected to the upper and lower surfaces of the wafer, respectively. Each of the upper and lower surfaces of the wafer is provided with an electrode. The upper surface of the wafer can be electrically connected to port one, and the lower surface of the wafer can be electrically connected to port two. Each device module 250 is composed of M stacked device modules 240 connected in series, where M is a positive integer, M≥1, and at least one device module 250 is connected in series. The number M of device modules 240 is not less than 2. The stacking direction of device modules 240 is perpendicular to the upper and lower surfaces of the wafer. At least one device module 250 contains not less than 2 device modules 240 with voltage withstand capability (excluding a single forward-biased PN diode). That is, when only one set of device modules 250 has exactly 2 stacked device modules, the device modules 240 in that device module are not allowed to be a single forward-biased PN diode without voltage withstand capability. Static electricity and surge discharge channels are formed within the device module 250. Among them, the device module 240 is a PN diode, Zener diode, NPN transistor, PNP transistor, silicon controlled rectifier, or field-effect transistor. The wafer is single-crystal silicon, gallium arsenide, gallium nitride, or silicon carbide. In multiple device modules 250 connected in parallel, an isolation structure is provided between two adjacent device modules. The isolation structure is an isolation deep trench or an isolation deep PN junction.

[0035] In this first embodiment of the invention, the device module can be homogeneously stacked, meaning that the same type of device modules are stacked vertically; or it can be heterogeneously stacked, meaning that different types of device modules are stacked vertically. The vertically stacked semiconductor devices can be PN diodes, Zener diodes, NPN transistors, PNP transistors, silicon controlled rectifiers (SCRs), or field-effect transistors. The overall structure can be unidirectional or bidirectional, possessing unidirectional and bidirectional voltage blocking capabilities, respectively. Furthermore, the wafer referred to in this invention typically refers to single-crystal silicon, but can also be a wafer made of other materials such as gallium arsenide (GaAs), gallium nitride (GaN), or silicon carbide (SiC).

[0036] As shown in Figures 3(a)-3(b), in the second embodiment of the present invention, the device module is a simplified device module. The simplified device module includes, from top to bottom, a first P-type active region 310, a first N-type epitaxial layer 371, a first P-type epitaxial layer 330, a second N-type epitaxial layer 321, and a first P-type doped substrate 340. The first P-type active region 310, the first N-type epitaxial layer 371, and the first P-type epitaxial layer 330 constitute a bidirectional first PNP transistor 350. The bidirectional first PNP transistor 350... Near the upper surface of the wafer, a first P-type epitaxial layer 330, a second N-type epitaxial layer 321, and a first P-type doped substrate 340 constitute a bidirectional second PNP transistor 351. Near the lower surface of the wafer, the bidirectional first PNP transistor 350 and the bidirectional second PNP transistor 351 are vertically stacked to form a simplified device module. A bidirectional electrostatic discharge and surge discharge channel is formed within the simplified device module. The doping concentration of the first P-type active region 310 is C1, and the value of C1 ranges from 1e19cm. -3 ≤C1≤5e21cm -3 The first p-type doped substrate 340 has a doping concentration of C2, and the value of C2 ranges from 1e19cm. -3 ≤C2≤5e21cm -3 The first p-type epitaxial layer 330 has a doping concentration of C3, and the value of C3 ranges from 5e18cm. -3 ≤C3≤1e21cm -3 The first N-type epitaxial layer 371 has a doping concentration of C4, and the value of C4 ranges from 1e13cm. -3 ≤C4≤1e18cm -3 The doping concentration of the second N-type epitaxial layer 321 is C5, and the value of C5 ranges from 1e13cm. -3 ≤C5≤1e18cm -3In this embodiment, both the bidirectional first PNP transistor and the bidirectional second PNP transistor have bidirectional voltage blocking capability and electrostatic discharge (ESD) and surge protection capability. By vertically connecting them in series, the withstand voltage capability can be effectively improved while maintaining the layout area and robustness. At this time, the forward and reverse ESD and surge discharge channels are reused, as shown in Figure 3(a), where 370 is the bidirectional ESD and surge discharge channel. The isolation structure 300 is used to protect each PN junction and prevent edge leakage. In this embodiment, it is an isolation deep trench. Figure 3(b) shows the quasi-static IV characteristic curve of this embodiment under transmission line pulse test (TLP) to characterize its ESD protection characteristics. It can be seen that this embodiment can successfully realize the stacking of two bidirectional PNP transistors, thereby achieving bidirectional high-voltage blocking capability while maintaining the ESD and surge protection capability and layout area, so as to meet various high-voltage application scenarios.

[0037] As shown in Figures 4(a) and 4(b), in the third embodiment of the present invention, the multiple device modules include one forward discharge channel device module and one reverse discharge channel device module. The forward discharge channel device module and the reverse discharge channel device module constitute a dual discharge channel device module unit. The dual discharge channel device module unit includes, from top to bottom, a dual discharge channel P-type active region 410, a dual discharge channel first layer N-type epitaxial layer 420, a dual discharge channel P-type buried layer 460, a dual discharge channel N-type buried layer 461, and a dual discharge channel first layer P-type... Epitaxial layer 430, dual-channel N-type doped substrate 440, dual-channel P-type active region 410, dual-channel first N-type epitaxial layer 420, and dual-channel P-type buried layer 460 constitute a dual-channel first PNP transistor 450. The dual-channel first PNP transistor 450 is located near the upper surface of the wafer. Dual-channel P-type buried layer 460 and dual-channel N-type buried layer 461 constitute a dual-channel first PN diode 451. Dual-channel N-type buried layer 461, dual-channel first P-type epitaxial layer 430, and dual-channel... The N-type doped substrate 440 forms the first NPN transistor 452 of the dual-discharge channel. The first NPN transistor 452 of the dual-discharge channel is located near the lower surface of the wafer. The first PNP transistor 450 of the dual-discharge channel, the first PN diode 451 of the dual-discharge channel, and the first NPN transistor 452 of the dual-discharge channel are stacked vertically to form a forward discharge channel device module. The first N-type epitaxial layer 420 of the dual-discharge channel also has a reverse N-type active region 400 of the dual-discharge channel near the upper surface of the wafer, which cooperates with the P-type active region 410 of the dual-discharge channel. The dual-channel N-type doped substrate 440, the dual-channel first-layer P-type epitaxial layer 430, the dual-channel first-layer N-type epitaxial layer 420, and the dual-channel reverse N-type active region 400 constitute a reverse discharge channel device module 453. A forward surge discharge channel is formed within the forward discharge channel device module, and a reverse surge discharge channel is formed within the reverse discharge channel device module. The forward surge discharge channel and the reverse surge discharge channel are connected in parallel. The doping concentration of the dual-channel P-type buried layer 460 is C6, and the value of C6 ranges from 1e19cm. -3 ≤C6≤5e21cm -3 The doping concentration of the dual-channel N-type buried layer 461 is C7, and the value of C7 ranges from 1e19cm. -3 ≤C7≤5e21cm -3In this embodiment, the device module includes a forward surge discharge channel 470 and a reverse surge discharge channel 471. These two channels are connected in parallel to form the structure of this embodiment. ① The forward channel is formed by vertically stacking three device modules: a first PNP transistor 450, a first PN diode 451, and a first NPN transistor 452. The forward withstand voltage is mainly provided by the first PNP transistor 450 and the first NPN transistor 452. ② The reverse channel is composed of a reverse surge discharge channel device module 453, which can provide a certain withstand voltage. As shown in Figure 4(b), this embodiment is a heterogeneous stack, which allows for the fusion of the I-V characteristics of various devices, thereby enabling flexible control of the overall I-V characteristics. Under forward bias (port 1 → port 2), the first PNP transistor 450 with no hysteresis (snapback) and the first NPN transistor 452 with shallow hysteresis are connected in series to obtain high-voltage I-V characteristics with a certain degree of shallow hysteresis, while simultaneously satisfying high withstand voltage and low clamping voltage. Under reverse bias, the withstand voltage and hysteresis depth of the reverse discharge channel device module 453 can be adjusted independently. The overall embodiment structure has asymmetrical bidirectional I-V characteristics. In the forward direction, it withstands high voltage through the stacking of multiple device modules, and in the reverse direction, it can withstand specific low or medium voltage. This embodiment can be used to protect ports with asymmetrical operating voltages.

[0038] As shown in Figures 5(a)-5(b), in the fourth embodiment of the present invention, the plurality of device modules include one forward high-voltage device module and one reverse high-voltage device module. The forward high-voltage device module and the reverse high-voltage device module constitute a high-voltage device module unit. The high-voltage device module unit includes, from top to bottom, a high-voltage P-type active region 510, a high-voltage first N-type epitaxial layer 520, a high-voltage P-type buried layer 550, a high-voltage second N-type epitaxial layer 530, a high-voltage P-type doped substrate 540, and a high-voltage N-type buried layer 550. Source region 501, high-voltage P-type active region 510, high-voltage first N-type epitaxial layer 520, and high-voltage P-type buried layer 550 constitute a high-voltage first PNP transistor 560. The high-voltage first PNP transistor 560 is close to the upper surface of the wafer. High-voltage P-type buried layer 550, high-voltage second N-type epitaxial layer 530, high-voltage P-type doped substrate 540, and high-voltage N-type active region 501 constitute a high-voltage first thyristor rectifier. The high-voltage first thyristor rectifier is close to the lower surface of the wafer. High-voltage first PNP transistor 560, high-voltage P-type buried layer 550, high-voltage second N-type epitaxial layer 530, high-voltage P-type doped substrate 540, and high-voltage N-type active region 501 constitute a high-voltage first thyristor rectifier. The first high-voltage thyristor rectifier is vertically stacked to form a forward high-voltage device module. A high-voltage reverse N-type active region 500, cooperating with a high-voltage P-type active region 510, is also provided near the upper surface of the high-voltage first N-type epitaxial layer 520 within the high-voltage first layer N-type epitaxial layer 520. A high-voltage reverse P-type active region 511, cooperating with a high-voltage N-type active region 501, is also provided near the lower surface of the high-voltage P-type doped substrate 540 within the high-voltage first layer N-type epitaxial layer 520. The module consists of a high-voltage P-type active region 510, a high-voltage first N-type epitaxial layer 520, a high-voltage P-type buried layer 550, and a high-voltage second N-type... A forward surge discharge channel is formed within the epitaxial layer 530, the high-voltage P-type doped substrate 540, and the high-voltage N-type active region 501. A reverse high-voltage device module is formed within the high-voltage reverse P-type active region 511, the high-voltage P-type doped substrate 540, the high-voltage second N-type epitaxial layer 530, the high-voltage first N-type epitaxial layer 520, and the high-voltage reverse N-type active region 500. A reverse surge discharge channel is formed within the reverse high-voltage device module. The doping concentration of the high-voltage P-type doped substrate 540 is C8, and the value of C8 ranges from 1e14cm. -3 ≤C8≤1e18cm -3In this embodiment, the forward current channel 570 is heterogeneously stacked from a high-voltage first PNP transistor 560 and a high-voltage first thyristor rectifier, which allows for more flexible control of the quasi-static TLP IV characteristics while significantly improving the withstand voltage. The reverse current channel 571 is composed of a high-voltage reverse P-type active region 511, a high-voltage P-type doped substrate 540, a high-voltage second N-type epitaxial layer 530, a high-voltage first N-type epitaxial layer 520, and a high-voltage reverse N-type active region 500. It is a forward-biased diode that can provide extremely low on-state voltage, surge voltage, and electrostatic clamping voltage. In this embodiment, photolithography is required on the back of the wafer to simultaneously form the high-voltage N-type active region 501 and the high-voltage reverse P-type active region 511. The spacing between these two active regions is not required and can be as small as zero. These two active regions are finally shorted to port 2 through back gold. As shown in Figure 5(b), in this embodiment, under forward bias, high voltage is achieved by stacking a high-voltage first PNP transistor 560 with no hysteresis characteristics and a high-voltage first thyristor rectifier with deep hysteresis characteristics. At the same time, the introduction of the high-voltage first PNP transistor can also improve the holding voltage of the high-voltage first thyristor rectifier and suppress potential latch-up risks.

[0039] like Figure 6 As shown in the fifth embodiment of the present invention, the number of device modules is N, where N is a positive integer and N≥2. A common P-type doped substrate or N-type doped substrate is provided at the bottom of each device module, and a back port is led out. Each device module has a port connected to its top. Single or multiple device modules can form a vertical current channel with the back port, and multiple device modules can form horizontal current channels with each other. This embodiment is based on Embodiment 1 in Figure 2, extended to a multi-port scenario. In this case, there are multiple ports (port 1 to port X) on the upper surface of the wafer, and one port (port Y) on the lower surface of the wafer. Multiple device modules exist between each of ports 1 to X and the bottom port Y. Each device module consists of M vertically stacked device modules, and the number of stacked device modules in each device module can be different. Furthermore, each device module can provide unidirectional or bidirectional breakdown voltage capability. All current channels pass through the same substrate 600, which is a P-type doped substrate or an N-type doped substrate. Isolation modules are provided between the devices with multiple ports, which can be isolation trenches or isolation deep PN junctions. In practical applications, this embodiment presents two scenarios: ① Multiple top-surface ports form "vertical current channels" with the back-side port Y, thus constituting a "vertical multi-path architecture product." ② Multiple top-surface ports mutually form multiple "horizontal current channels," which can be unidirectional or bidirectional. In this case, all effective ports are located on the top surface of the wafer, and the back-side port Y can be omitted. ③ When using "double-sided lithography technology," the back side of the wafer can also be expanded to include multiple ports.

[0040] As can be seen from the above, the present invention provides a compact electrostatic discharge (ESD) and surge protection device. By setting mutually cooperating wafers and device modules within the compact ESD and surge protection device, multiple device modules are arranged in parallel within the wafer. Multiple semiconductor device modules are vertically stacked in a direction perpendicular to the wafer surface to form a device module. ESD and surge discharge channels are formed within the device module, thus constituting an ESD and surge protection device. This device can significantly improve the withstand voltage capability while maintaining the wafer area and surge protection capability unchanged, and flexibly adjust the electrical IV characteristic curve. It solves the problem that classic TVS devices in the prior art cannot simultaneously achieve high breakdown voltage and robustness in some typical high-voltage application scenarios.

[0041] The specific embodiments described above are preferred embodiments of the present invention and are not intended to limit the specific scope of the present invention. The scope of the present invention includes, but is not limited to, these specific embodiments. All equivalent changes made in accordance with the present invention are within the protection scope of the present invention.

Claims

1. A compact electrostatic discharge and surge protection device, characterized in that: The device includes a wafer and multiple device modules arranged in parallel within the wafer. Each device module has two ends electrically connected to the upper and lower surfaces of the wafer, respectively. Each surface of the wafer has an electrode. The upper surface of the wafer can be electrically connected to port one, and the lower surface can be electrically connected to port two. Each device module consists of M stacked device modules connected in series, where M is a positive integer, M≥1, and at least one device module has a number of device modules M not less than 2. The stacking direction of the device modules is perpendicular to the upper and lower surfaces of the wafer. At least one device module... The module contains at least two device modules with withstand voltage capability. When only one set of device modules has exactly two stacked device modules, the device modules in that device module are not allowed to be single forward-biased PN diodes without withstand voltage capability. The device module has electrostatic discharge and surge discharge channels. The device modules are PN diodes, Zener diodes, NPN transistors, PNP transistors, silicon controlled rectifiers, or field-effect transistors. The structure of the device module is either a homogeneous stack of device modules of the same type stacked vertically, or a heterogeneous stack of device modules of different types stacked vertically.

2. The compact electrostatic and surge protection device according to claim 1, characterized in that: The wafer is made of single-crystal silicon, gallium arsenide, gallium nitride, or silicon carbide.

3. The compact electrostatic and surge protection device according to claim 2, characterized in that: Among the multiple device modules connected in parallel, an isolation structure is provided between two adjacent device modules, and the isolation structure is an isolation deep trench or an isolation deep PN junction.

4. The compact electrostatic and surge protection device according to claim 1, characterized in that: The device module is a simplified device module, which includes, from top to bottom, a first P-type active region, a first N-type epitaxial layer, a first P-type epitaxial layer, a second N-type epitaxial layer, and a first P-type doped substrate. The first P-type active region, the first N-type epitaxial layer, and the first P-type epitaxial layer constitute a bidirectional first PNP transistor. The bidirectional first PNP transistor is located near the upper surface of the wafer. The first P-type epitaxial layer, the second N-type epitaxial layer, and the first P-type doped substrate constitute a bidirectional second PNP transistor. The bidirectional second PNP transistor is located near the lower surface of the wafer. The bidirectional first PNP transistor and the bidirectional second PNP transistor are stacked vertically to form the simplified device module. A bidirectional electrostatic discharge and surge discharge channel is formed within the simplified device module.

5. The compact electrostatic and surge protection device according to claim 4, characterized in that: The doping concentration of the first P-type active region is C1, and the value of C1 ranges from 1e19cm. -3 ≤C1≤5e21cm -3 The doping concentration of the first P-type doped substrate is C2, and the value of C2 ranges from 1e19cm. -3 ≤C2≤5e21cm -3 The doping concentration of the first P-type epitaxial layer is C3, and the value of C3 ranges from 5e18cm. -3 ≤C3≤1e21cm -3 The doping concentration of the first N-type epitaxial layer is C4, and the value of C4 ranges from 1e13cm. -3 ≤C4≤1e18cm -3 The doping concentration of the second N-type epitaxial layer is C5, and the value of C5 ranges from 1e13cm. -3 ≤C5≤1e18cm -3 .

6. The compact electrostatic and surge protection device according to claim 1, characterized in that: The plurality of device modules include one forward discharge channel device module and one reverse discharge channel device module. The forward discharge channel device module and the reverse discharge channel device module constitute a dual discharge channel device module unit. The dual discharge channel device module unit includes, from top to bottom, a dual discharge channel P-type active region, a dual discharge channel first layer N-type epitaxial layer, a dual discharge channel P-type buried layer, a dual discharge channel N-type buried layer, a dual discharge channel first layer P-type epitaxial layer, and a dual discharge channel N-type doped substrate. The dual-discharge channel P-type active region, the dual-discharge channel first N-type epitaxial layer, and the dual-discharge channel P-type buried layer constitute a dual-discharge channel first PNP transistor. The dual-discharge channel first PNP transistor is located near the upper surface of the wafer. The dual-discharge channel P-type buried layer and the dual-discharge channel N-type buried layer constitute a dual-discharge channel first PN diode. The dual-discharge channel N-type buried layer, the dual-discharge channel first P-type epitaxial layer, and the dual-discharge channel N-type doped substrate constitute a dual-discharge channel first NPN transistor. The dual-discharge channel first NPN transistor is located near the lower surface of the wafer. The dual-discharge channel first PNP transistor, the dual-discharge channel first PN diode, and the dual-discharge channel first NPN transistor are vertically stacked to form the forward discharge channel device module. A dual-discharge channel reverse N-type active region, cooperating with the dual-discharge channel P-type active region, is also provided near the upper surface of the wafer within the dual-discharge channel first N-type epitaxial layer. The dual-discharge channel N-type doped substrate, the... The dual-discharge channel first-layer P-type epitaxial layer, the dual-discharge channel first-layer N-type epitaxial layer, and the dual-discharge channel reverse N-type active region constitute the reverse discharge channel device. A forward surge discharge channel is formed within the forward discharge channel device module, and a reverse surge discharge channel is formed within the reverse discharge channel device module. The forward surge discharge channel and the reverse surge discharge channel are connected in parallel. The doping concentration of the dual-discharge channel P-type buried layer is C6, and the value of C6 ranges from 1e19cm. -3 ≤C6≤5e21cm -3 The doping concentration of the dual-discharge channel N-type buried layer is C7, and the value of C7 ranges from 1e19cm. -3 ≤C7≤5e21cm -3 .

7. The compact electrostatic discharge and surge protection device according to claim 1, characterized in that: The plurality of device modules include one forward high-voltage device module and one reverse high-voltage device module. The forward high-voltage device module and the reverse high-voltage device module constitute a high-voltage device module unit. The high-voltage device module unit includes, from top to bottom, a high-voltage P-type active region, a high-voltage first N-type epitaxial layer, a high-voltage P-type buried layer, a high-voltage N-type buried layer, a high-voltage second N-type epitaxial layer, a high-voltage P-type doped substrate, and a high-voltage N-type active region. A high-voltage first N-type epitaxial layer and a high-voltage P-type buried layer constitute a high-voltage first PNP transistor. The high-voltage first PNP transistor is located near the upper surface of the wafer. The high-voltage P-type buried layer, a high-voltage second N-type epitaxial layer, a high-voltage P-type doped substrate, and a high-voltage N-type active region constitute a high-voltage first thyristor rectifier. The high-voltage first thyristor rectifier is located near the lower surface of the wafer. The high-voltage first PNP transistor and the high-voltage first thyristor rectifier... The high-voltage device module is formed by vertical stacking. A high-voltage reverse N-type active region, cooperating with the high-voltage P-type active region, is also provided near the upper surface of the wafer within the first high-voltage N-type epitaxial layer. A high-voltage reverse P-type active region, cooperating with the high-voltage N-type active region, is also provided near the lower surface of the wafer within the high-voltage P-type doped substrate. The high-voltage P-type active region, the first high-voltage N-type epitaxial layer, the high-voltage P-type buried layer, and the second high-voltage N-type epitaxial layer are also included. The high-voltage P-type doped substrate and the high-voltage N-type active region have a forward surge discharge channel formed within them. The high-voltage reverse P-type active region, the high-voltage P-type doped substrate, the high-voltage second N-type epitaxial layer, the high-voltage first N-type epitaxial layer, and the high-voltage reverse N-type active region constitute the reverse high-voltage device module, and a reverse surge discharge channel is formed within the reverse high-voltage device module. The doping concentration of the high-voltage P-type doped substrate is C8, and the value of C8 ranges from 1e14cm. -3 ≤C8≤1e18cm -3 .

8. The compact electrostatic and surge protection device according to claim 3, characterized in that: The number of device modules is N, where N is a positive integer and N≥2. Each device module has a common P-type doped substrate or N-type doped substrate at its bottom and a back port is led out. Each device module has a port at its top. One or more device modules can form a vertical current channel with the back port, and multiple device modules can form a horizontal current channel with each other.

Images