Solar cell and preparation method thereof
By setting isolation zones and patterning at the edges of the silicon substrate in solar cells, the problems of edge recombination and short-circuit leakage caused by metal film deposition at the edges of silicon wafers are solved, thereby improving cell efficiency and module reliability.
Patent Information
- Application Number
- CN202510450030.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-10
- Publication Date
- 2025-12-19
AI Technical Summary
In existing solar cells, metal films are deposited at the edges of silicon wafers during the preparation of the seed layer, which leads to problems such as edge recombination, decreased parallel resistance, and short-circuit leakage between adjacent cells.
A first isolation region is set at the edge of the silicon substrate, and a patterned mask layer and a coating layer are prepared after depositing a metal seed layer on the doped layer. After depositing the gate line, the excess metal seed layer is removed to ensure that there is isolation between the metal seed layer and the edge of the silicon substrate.
It effectively avoids edge recombination of solar cells, improves cell efficiency and module reliability, prevents short circuits and leakage between adjacent cells, and enhances the performance of photovoltaic modules.
Smart Images
Figure CN121174643A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of photovoltaic technology, in particular to a solar cell and a preparation method thereof. BACKGROUND
[0002] Currently, the mainstream electrode preparation of solar cells is to form silver grid lines by using a screen printing process. However, the silver paste is relatively expensive, resulting in high production cost of the solar cells. The use of an electroplating process to prepare the grid lines can use a metal such as copper at a lower price as the electrode material, and therefore the electroplating process becomes an important direction to reduce the production cost.
[0003] By using the electroplating process, a seed layer needs to be prepared on the surface of the solar cell first, and then electroplating is performed to thicken the seed layer to form a metal electrode with a certain height and width. The seed layer is usually prepared by using a physical vapor deposition (PVD) process, and the edge of the silicon wafer will also be deposited when the seed layer is prepared, and even the edge of the silicon wafer will be plated around. At the same time, the edge position will also be superimposed with a tip effect, and a metal film with a thickness much higher than that of the grid line will be deposited at the edge. The existence of the metal film will cause many problems, for example: 1. The edge of the solar cell will have serious edge recombination, resulting in a serious decrease in parallel resistance; 2. When the edges of adjacent solar cells are in contact after the assembly is welded, short circuit and leakage will occur. SUMMARY
[0004] Therefore, it is necessary to provide a solar cell and a preparation method thereof to solve the problem of the deposition of the metal film on the edge of the silicon wafer when the seed layer is prepared.
[0005] A preparation method of a solar cell, comprising the following steps:
[0006] preparing a doped layer on a first side of a silicon substrate, the doped layer having a first isolation area between the edge of the silicon substrate and the doped layer;
[0007] depositing a metal seed layer on the first side on which the doped layer is formed;
[0008] preparing a patterned mask layer on the metal seed layer located on the doped layer;
[0009] applying an encapsulating layer on the edge of the silicon substrate, the encapsulating layer covering the first isolation area and the metal seed layer on the side edge of the silicon substrate;
[0010] depositing a grid line on the metal seed layer through the mask layer;
[0011] removing the mask layer and the encapsulating layer;
[0012] removing the metal seed layer outside the grid line area.
[0013] In one of the embodiments, the doped layers include a P-type doped layer and an N-type doped layer, and the P-type doped layer and the N-type doped layer have a second isolation region therebetween.
[0014] In one of the embodiments, the P-type doped layer includes a plurality of first fine gate connection portions, and the N-type doped layer includes a plurality of second fine gate connection portions, and the plurality of first fine gate connection portions and the plurality of second fine gate connection portions are alternately distributed along a first direction.
[0015] The first fine gate connection portion and the second fine gate connection portion closest to the edge of the silicon substrate are edge fine gate connection portions, and the other first fine gate connection portions and the other second fine gate connection portions are non-edge fine gate connection portions, the width of the edge fine gate connection portion is D1, the width of the non-edge fine gate connection portion is D2, and for the same doping type, D1 is greater than D2.
[0016] In one of the embodiments, D1 is less than or equal to 2D2.
[0017] In one of the embodiments, D2 is 10μm-1000μm.
[0018] In one of the embodiments, the width of the second isolation region between adjacent non-edge fine gate connection portions is d1, and the width of the first isolation region at the edge fine gate connection portion is d2, and d2 is greater than d1, and d2 is greater than D2.
[0019] In one of the embodiments, d2 is less than or equal to 2d1.
[0020] In one of the embodiments, d2 is less than or equal to 2D2.
[0021] In one of the embodiments, d1 is 10μm-200μm.
[0022] In one of the embodiments, the P-type doped layer further includes a plurality of first main gate connection portions, and the N-type doped layer further includes a plurality of second fine gate connection portions, and the plurality of first main gate connection portions and the plurality of second fine main gate connection portions are alternately distributed along a second direction.
[0023] The first main gate connection portion and the second main gate connection portion closest to the edge of the silicon substrate are edge main gate connection portions, and the other first main gate connection portions and the other second main gate connection portions are non-edge main gate connection portions.
[0024] In one of the embodiments, the width of the non-edge main gate connection portion is D3, and the width of the edge main gate connection portion is D4, and for the same doping type, D4 is greater than D3.
[0025] In one of the embodiments, the width of the first isolation region at the edge main grid connection is d3, and the width of the second isolation region between adjacent non-main edge grid connections is d4, wherein d3 is greater than d4.
[0026] In one of the embodiments, the edge grid connections at the edge of the one side of the silicon substrate are continuous without intervals.
[0027] In one of the embodiments, the edge grid connections at the edge of the one side of the silicon substrate are continuous without intervals.
[0028] In one of the embodiments, the edge of the silicon substrate further has a chamfered edge, and the ratio of the width of the first isolation region at the chamfered edge to the width of the first isolation region at the edge of the chamfered edge is greater than 1 and less than or equal to 2.
[0029] In one of the embodiments, the first isolation region is formed by patterning the doped layer.
[0030] In one of the embodiments, the encapsulation layer covers the edge of the mask layer.
[0031] A solar cell prepared by the preparation method of any one of the above embodiments.
[0032] Compared with the conventional technology, the preparation method of the solar cell has the following beneficial effects:
[0033] The preparation method of the solar cell sets the first isolation region between the doped layer and the edge of the silicon substrate, deposits the metal seed layer, and then prepares the patterned mask layer on the metal seed layer located on the doped layer, and coats the encapsulation layer on the edge of the silicon substrate, and then removes the metal seed layer outside the grid line area after depositing the grid line. In this way, the edge of the metal seed layer and the edge of the silicon substrate have the first isolation region, which avoids the edge recombination of the solar cell, improves the performance of the cell efficiency, and also avoids the short circuit and the leakage of the metal seed layer between the adjacent solar cells during the manufacturing of the photovoltaic module, thereby improving the reliability of the module. BRIEF DESCRIPTION OF DRAWINGS
[0034] Figure 1 A flowchart of the preparation method of the solar cell of one embodiment;
[0035] Figure 2 A schematic diagram of preparing the doped layer on the first side of the silicon substrate;
[0036] Figure 3 Schematic diagram for depositing a metal seed layer on the first side with the doped layer formed;
[0037] Figure 4 Schematic diagram for preparing a patterned mask layer and an encapsulation layer;
[0038] Figure 5 Schematic diagram for depositing a gate line on the metal seed layer;
[0039] Figure 6 Schematic diagram for distribution of the gate line;
[0040] Figure 7 Schematic diagram for Figure 6 partial enlargement of the structure;
[0041] Figure 8 Microscope diagram of the edge structure of a solar cell;
[0042] Figure 9 Schematic diagram of the structure of the edge cross section of a cell piece with a passivation layer deposited along the first direction;
[0043] Figure 10 Schematic diagram for distribution of the mask layer and the encapsulation layer;
[0044] Figure 11 Schematic diagram of the structure of the edge cross section of a solar cell along the first direction.
[0045] Explanation of reference signs:
[0046] 100, silicon substrate; 110, first edge; 120, second edge; 130, third edge; 140, fourth edge; 150, chamfered edge; 200, doped layer; 210, P-type doped layer; 211, first fine grid connection; 212, first main grid connection; 220, N-type doped layer; 221, second fine grid connection; 222, second main grid connection; 101, first isolation region; 102, second isolation region; 300, metal seed layer; 400, gate line; 410, fine grid; 420, main grid; 401, conductive bulk layer; 402, conductive protective layer; 440, first polarity gate line; 450, second polarity gate line; 500, passivation layer; 510, first opening; 20, mask layer; 21, second opening; 30, encapsulation layer. DETAILED DESCRIPTION
[0047] In order to make the above objectives, characteristics and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application are described in detail below with reference to the drawings. In the following description, a large number of specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be implemented in many other different ways than those described herein, and those skilled in the art can make similar improvements without departing from the spirit of the present application, and therefore the present application is not limited to the specific embodiments disclosed below.
[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.
[0049] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.
[0050] In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "a plurality of" is at least two, such as two, three, etc., unless otherwise specifically limited.
[0051] In the present application, unless otherwise specifically defined and limited, the terms "mounting", "connection", "connection", "fixing" and the like should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise specifically defined. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0052] The present application provides a preparation method of a solar cell.
[0053] As shown in FIG. 1, a method for manufacturing a solar cell includes the following steps: Figure 1
[0054] Step S1, as shown in FIG. 2, a doped layer 200 is prepared on a first side of a silicon substrate 100, and a first isolation region 101 is formed between the doped layer 200 and the edge of the silicon substrate 100. Figure 2
[0055] Step S2, as shown in FIG. 3, a metal seed layer 300 is deposited on the first side where the doped layer 200 is formed. Figure 3
[0056] Step S3, as shown in FIG. 4, a patterned mask layer 20 is prepared on the metal seed layer 300 located on the doped layer 200. Figure 4
[0057] Step S4, an encapsulation layer 30 is coated on the edge of the silicon substrate 100, and the encapsulation layer 30 covers the first isolation region 101 and the metal seed layer 300 on the side of the silicon substrate 100.
[0058] Step S5, as shown in FIG. 6 and FIG. 7, a grid line 400 is deposited on the metal seed layer 300 through the mask layer 20. Figure 5 Figure 6
[0059] Step S6, the mask layer 20 and the encapsulation layer 30 are removed.
[0060] Step S7, the metal seed layer 300 outside the area of the grid line 400 is removed.
[0061] When the metal seed layer 300 is deposited, the metal seed layer 300 is difficult to avoid also on the edge of the silicon substrate 100. The above method for manufacturing a solar cell sets a first isolation region 101 between the doped layer 200 and the edge of the silicon substrate 100, and after the metal seed layer 300 is deposited, a patterned mask layer 20 is prepared on the metal seed layer 300 located on the doped layer 200, and an encapsulation layer 30 is coated on the edge of the silicon substrate 100, and after the grid line 400 is deposited, the metal seed layer 300 outside the area of the grid line 400 is removed. In this way, the edge of the metal seed layer 300 and the edge of the silicon substrate 100 have the first isolation region 101, which avoids the edge recombination of the solar cell, improves the performance of the cell efficiency, and also avoids the edge of the metal seed layer 300 of adjacent solar cells from contacting each other to cause short circuit and leakage during the manufacturing of the photovoltaic module, thereby improving the reliability of the module.
[0062] The material of the silicon substrate 100 is, for example, monocrystalline silicon. The silicon substrate 100 can be P-type doped, for example, boron doped, or N-type doped, for example, phosphorus doped.
[0063] In some examples, before step S1, the method for preparing a solar cell comprises the following steps:
[0064] A tunneling oxide layer is prepared on the first side of the silicon substrate 100 (not shown in the figure).
[0065] In the above examples, in step S1, the doped layer 200 is formed on the tunneling oxide layer.
[0066] In other examples, the tunneling oxide layer can also not be prepared.
[0067] In some examples, the doped layer 200 comprises a P-type doped layer 210 and an N-type doped layer 220. The P-type doped layer 210 and the N-type doped layer 220 have a second isolation region 102 therebetween. The material of the P-type doped layer 210 is, for example, P-type doped polysilicon. The material of the N-type doped layer 220 is, for example, N-type doped polysilicon.
[0068] In the above examples, the P-type doped layer 210 and the N-type doped layer 220 are located on the same side of the silicon substrate 100, and the prepared solar cell is a back contact solar cell.
[0069] In some examples, the N-type doped layer 220 and the P-type doped layer 210 are in a finger shape.
[0070] The first isolation region 101 can be formed by patterning the doped layer 200, for example, by using a laser etching process.
[0071] In some examples, step S1 comprises:
[0072] Step S11, depositing a first doped type of polysilicon on the silicon substrate 100. The first doped type can be P-type doping or N-type doping.
[0073] Step S12, performing a first patterning process to remove the first doped type of polysilicon at a position reserved for preparing a second doped type of polysilicon and at an edge of the silicon substrate 100, to form a first doped layer. The second doped type is opposite to the first doped type.
[0074] Step S13, depositing a second doped type of polysilicon on the silicon substrate 100.
[0075] Step S14, performing a second patterning process to remove the second doped type of polysilicon on the first doped layer, adjacent to the first doped layer 200, and at an edge of the silicon substrate 100, to form a second doped layer.
[0076] The first patterning process and the second patterning process described above can be performed, for example, by using a laser etching process.
[0077] In some examples, prior to step S2, the method for fabricating a solar cell includes the following steps:
[0078] A passivation layer 500 is prepared on the doped layer 200.
[0079] Furthermore, in some examples, prior to step S2, the method for fabricating the solar cell includes the following steps:
[0080] The passivation layer 500 is subjected to a third patterning process to remove the passivation layer 500 in the reserved area of the gate line 400 on the doped layer 200, forming a first opening 510 that exposes the doped layer 200.
[0081] The reserved area for gate line 400 is the area where gate line 400 is to be formed. When the metal seed layer 300 is subsequently deposited (step S2), the metal seed layer 300 contacts the reserved area for gate line 400 of the exposed doped layer 200.
[0082] The aforementioned third patterning process can, for example, employ laser etching. In some examples, after the third patterning process, the resulting solar cell is sequentially subjected to sintering and light injection. This can repair damage to the laser-etched openings.
[0083] like Figure 2 and Figure 6 As shown, in some examples, the P-type doped layer 210 includes a plurality of first fine gate connections 211. The N-type doped layer 220 includes a plurality of second fine gate connections 221. The fine gate connections are used to connect the fine gate 410. The plurality of first fine gate connections 211 and the plurality of second fine gate connections 221 are alternately distributed along a first direction.
[0084] More specifically, the silicon substrate 100 has a first edge 110 and a second edge 120, which are disposed opposite to each other in a first direction. A plurality of first fine gate connections 211 are, for example, strip structures parallel to the first edge 110 and the second edge 120. A plurality of second fine gate connections 221 are, for example, strip structures parallel to the first edge 110 and the second edge 120. The first fine gate connections 211 and the second fine gate connections 221 are alternately distributed from the first edge 110 to the second edge 120, and a second isolation region 102 is provided between the first fine gate connections 211 and the second fine gate connections 221.
[0085] It is understood that the fine gate connection portions adjacent to the edges (first edge 110 and second edge 120) of the silicon substrate 100 can all be the first fine gate connection portion 211, or they can all be the second fine gate connection portion 221, or one side can be the first fine gate connection portion 211 and the other side can be the second fine gate connection portion 221.
[0086] The fine gate connection (the first fine gate connection 211 and the second fine gate connection 221) adjacent to the edge of the silicon substrate 100 is referred to as an edge fine gate connection, and other fine gate connections are referred to as non-edge fine gate connections.
[0087] To better collect the carriers at the first isolation region 101 at the first edge 110 and the second edge 120, the edge fine gate connection preferably has a larger width.
[0088] As shown in Figure 7 and Figure 9 , the width of the edge fine gate connection is denoted as D1, and the width of the non-edge fine gate connection is denoted as D2. For fine gate connections of the same doping type, D1 is preferably greater than D2 to improve the collection ability of carriers at the edge. Further, D1 is preferably less than or equal to 2D2. In some specific examples, the ratio of D1 to D2 is, for example, 1.1:1, 1.2:1, 1.3:1, 1.4:1, 1.5:1, 1.6:1, 1.7:1, 1.8:1, 1.9:1, 2:1, etc.
[0089] In some examples, the width (D2) of the non-edge fine gate connection is 10 μm to 1000 μm, and is specifically, for example, 10 μm, 30 μm, 50 μm, 80 μm, 100 μm, 300 μm, 500 μm, 800 μm, 1000 μm, etc.
[0090] For non-edge fine gate connections of different doping types, the width is preferably kept substantially the same, such as the ratio of the width of the P-type doped layer 210 to the width of the N-type doped layer 220 being (0.8-1.2):1.
[0091] As shown in Figure 7 , Figure 8 and Figure 9 , the width of the second isolation region between adjacent non-edge fine gate connections is denoted as d1. The width of the first isolation region 101 at the edge fine gate connection is denoted as d2. The part of the gate line 400 formed on the P-type doped layer 210 is a first polarity gate line 440, and the part of the gate line 400 formed on the N-type doped layer 220 is a second polarity gate line 450.
[0092] d2 is preferably greater than d1. Further, d2 is preferably less than or equal to 2D1. In some specific examples, the ratio of d2 to d1 is, for example, 1.1:1, 1.2:1, 1.3:1, 1.4:1, 1.5:1, 1.6:1, 1.7:1, 1.8:1, 1.9:1, 2:1, etc.
[0093] In some examples, the width (d1) of the second isolation region between adjacent non-edge fine grid connection portions is 10-200 μm, for example 10 μm, 30 μm, 50 μm, 80 μm, 100 μm, 130 μm, 150 μm, 180 μm, 200 μm, etc.
[0094] d2 is preferably greater than D2 to effectively prevent edge leakage. Further, d2 is preferably less than or equal to 2D2. In some specific examples, the ratio of d2 to D2 is, for example, 1.1:1, 1.2:1, 1.3:1, 1.4:1, 1.5:1, 1.6:1, 1.7:1, 1.8:1, 1.9:1, 2:1, etc.
[0095] In some examples, the P-type doped layer 210 further includes a plurality of first main grid connection portions 212. The N-type doped layer 220 further includes a plurality of second main grid connection portions 222. The plurality of first main grid connection portions 212 and the plurality of second main grid connection portions 222 are alternately distributed along a second direction. The second direction is different from the first direction. For example, the first direction is perpendicular to the second direction. The main grid connection portions are used to connect the main grid 420.
[0096] More specifically, the silicon substrate 100 has a third edge 130 and a fourth edge 140, which are oppositely arranged in the second direction. The plurality of first main grid connection portions 212 are, for example, strip-shaped structures parallel to the third edge 130 and the fourth edge 140. The plurality of second main grid connection portions 222 are, for example, strip-shaped structures parallel to the third edge 130 and the fourth edge 140. From the third edge 130 to the fourth edge 140, the first main grid connection portions 212 and the second main grid connection portions 222 are alternately distributed, and the first main grid connection portions 212 and the second main grid connection portions 222 have the second isolation region 102 therebetween.
[0097] It can be understood that the main grid connection portions adjacent to the edges (the third edge 130 and the fourth edge 140) of the silicon substrate 100 can all be the first main grid connection portions 212, can all be the second main grid connection portions 222, or can be the first main grid connection portions 212 on one side and the second main grid connection portions 222 on the other side.
[0098] Hereinafter, the main grid connection portions (the first main grid connection portions 212 and the second main grid connection portions 222) adjacent to the edges of the silicon substrate 100 are referred to as edge main grid connection portions, and the other main grid connection portions are referred to as non-edge main grid connection portions. In order to better collect the carriers at the first isolation region 101 at the third edge 130 and the fourth edge 140, the edge main grid connection portions preferably have a larger width.
[0099] As shown in FIG. 1, the first main grid connection portions 212 and the second main grid connection portions 222 are alternately distributed along the second direction. The first main grid connection portions 212 and the second main grid connection portions 222 are arranged in a staggered manner along the second direction. Figure 7 , Figure 8 and Figure 9As shown, the width of the non-edge main gate connection is denoted as D3, and the width of the edge main gate connection is denoted as D4. For main gate connections with the same doping type, D4 is preferably greater than D3 to improve the carrier collection capability at the edge. Further, D4 is preferably less than or equal to 2D3. In some specific examples, the ratio of D4 to D3 is, for example, 1.1∶1, 1.2∶1, 1.3∶1, 1.4∶1, 1.5∶1, 1.6∶1, 1.7∶1, 1.8∶1, 1.9∶1, 2∶1, etc.
[0100] In some examples, the width of the non-edge main gate connection is greater than the width of the non-edge fine gate connection, i.e., D3 is greater than D2.
[0101] In some examples, the width (D3) of the non-edge main gate connection is 30μm to 2000μm, specifically 30μm, 50μm, 80μm, 100μm, 300μm, 500μm, 800μm, 1000μm, 1100μm, 1300μm, 1500μm, 1800μm, 2000μm, etc.
[0102] like Figure 7 As shown, the width of the first isolation region 101 at the edge main gate connection is d3. The width of the second isolation region between adjacent non-main edge fine gate connections is d4.
[0103] d3 is preferably greater than d4. Further, d3 is preferably less than or equal to 2D4. In some specific examples, the ratio of d3 to d4 is, for example, 1.1∶1, 1.2∶1, 1.3∶1, 1.4∶1, 1.5∶1, 1.6∶1, 1.7∶1, 1.8∶1, 1.9∶1, 2∶1, etc.
[0104] In some examples, the width (d3) of the first isolation region 101 at the edge main gate connection is 10μm~200μm, specifically for example 10μm, 30μm, 50μm, 80μm, 100μm, 130μm, 150μm, 180μm, 200μm, etc.
[0105] Optionally, the edge gate connection on one side edge (such as the first edge or the second edge) of the silicon substrate 100 can be continuous or discontinuous.
[0106] In some examples, the edge fine gate connections on one side of the silicon substrate 100 are discontinuous (multiple connections are spaced apart), and the distance between adjacent edge fine gate connections is greater than the width (d4) of the second isolation region 102 between the non-edge fine gate connections and the main gate connection, but less than the width (D3) of the non-edge main gate connection.
[0107] In some examples, the edge gate connections on one side of the silicon substrate 100 are discontinuous, and the ratio of the distance between adjacent edge gate connections to the width of the second isolation region 102 between adjacent non-edge gate connections is greater than 1 and less than 10.
[0108] If it is a gateless structure, when the edge fine gate connection on one side of the silicon substrate 100 is discontinuous, the ratio of the distance between adjacent edge fine gate connections to the width of the second isolation region 102 between adjacent non-edge fine gate connections is greater than 1 and less than 10.
[0109] In some examples, the silicon substrate 100 is rectangular. The first edge 110 and the second edge 120 are parallel and perpendicular to the third edge 130 and the fourth edge 140.
[0110] like Figure 2 As shown, in some examples, the edge of the silicon substrate 100 also has a chamfered edge 150. The chamfered edge 150 can be a straight edge or a curved edge. The number of chamfered edges 150 is not limited to only one; there can be multiple chamfered edges, such as two, three, four, etc.
[0111] It is understood that the chamfer edge 150 has two adjacent edges. These two adjacent edges are, for example, perpendicular to each other. In some examples, the ratio of the width of the first isolation zone at the chamfer edge 150 to the width of the first isolation zone at the adjacent edge of the chamfer edge 150 is greater than 1 and less than or equal to 2. For example, the ratio of the width of the first isolation zone at the chamfer edge 150 to the width of the first isolation zone at the adjacent edge of the chamfer edge 150 is 1.1∶1, 1.2∶1, 1.3∶1, 1.4∶1, 1.5∶1, 1.6∶1, 1.7∶1, 1.8∶1, 1.9∶1, 2∶1, etc.
[0112] It is understandable that in other examples, the edges of the silicon substrate 100 may not have a chamfered edge 150.
[0113] In some examples, in step S2, the metal seed layer 300 is prepared using a physical vapor deposition (PVD) process, such as magnetron sputtering or evaporation. When the metal seed layer 300 is deposited using a PVD process, it is unavoidable that a metal seed layer 300 will also be deposited at the edge of the silicon substrate 100.
[0114] In step S2, the material of the metal seed layer 300 can be, but is not limited to, copper.
[0115] In some examples, in step S3, the mask layer 20 fabrication process includes coating, exposure, and development to form a second opening 21 that exposes the doped layer 200.
[0116] like Figure 4 As shown, in some examples, in step S4, the adhesive layer 30 covers the edge of the mask layer 20.
[0117] Figure 10 Distribution diagram of the mask layer 20 and the encapsulation layer 30 is shown. Figure 10 The mask area of the mask layer 20 is in the dashed box except the electrode reserved area. The mask layer 20 shields all the non-grid line area. Figure 10 The distribution area of the encapsulation layer 30 is outside the dashed box.
[0118] In some examples, the process of depositing the grid line 400 on the metal seed layer 300 in step S5 is an electroplating process.
[0119] As shown in the figure, in some examples, the grid line 400 includes a conductive body layer 401 disposed on the metal seed layer 300 in step S5. The material of the conductive body layer 401 can be but is not limited to copper. Figure 11 In some examples, the grid line 400 further includes a conductive protection layer 402 disposed on the side of the conductive body layer 401 away from the metal seed layer 300. The material of the conductive protection layer 402 can be but is not limited to tin.
[0120] In some examples, the method of removing the metal seed layer 300 outside the area of the grid line 400 in step S7 is acid pickling.
[0121] The above-mentioned preparation method of the solar cell sets the first isolation area 101 between the doped layer 200 and the edge of the silicon substrate 100, deposits the metal seed layer 300, prepares the patterned mask layer 20 on the metal seed layer 300 located on the doped layer 200, and coats the encapsulation layer 30 on the edge of the silicon substrate 100, deposits the grid line 400, and then removes the metal seed layer 300 outside the area of the grid line 400. In this way, the edge of the metal seed layer 300 and the edge of the silicon substrate 100 have the first isolation area 101, which avoids the edge recombination of the solar cell, improves the performance of the cell efficiency, and also avoids the short circuit and leakage caused by the edge of the metal seed layer 300 of the adjacent solar cells contacting each other during the manufacturing of the photovoltaic module, thereby improving the reliability of the module.
[0122] Further, the present application also provides a solar cell prepared by the preparation method of any of the above-mentioned examples.
[0123] The above-mentioned solar cell includes a silicon substrate 100, a doped layer 200, a metal seed layer 300, and a grid line 400. The doped layer 200 is disposed on the silicon substrate 100, and the doped layer 200 and the edge of the silicon substrate 100 have a first isolation area 101. The metal seed layer 300 is disposed on the doped layer 200. The grid line 400 is disposed on the metal seed layer 300.
[0124] The above-mentioned solar cell includes a silicon substrate 100, a doped layer 200, a metal seed layer 300, and a grid line 400. The doped layer 200 is disposed on the silicon substrate 100, and the doped layer 200 and the edge of the silicon substrate 100 have a first isolation area 101. The metal seed layer 300 is disposed on the doped layer 200. The grid line 400 is disposed on the metal seed layer 300.
[0125] The following specific examples are provided to further illustrate the present application. The present application provides the following specific examples for better further understanding of the present application, and is not limited to the specific embodiments, and does not constitute a limitation on the scope of protection of the present application.
[0126] Example 1
[0127] The present embodiment provides a preparation method of a solar cell, comprising the following steps:
[0128] Step 1, provide a phosphorus-doped monocrystalline silicon wafer, and perform cleaning and rough polishing treatment to remove impurities and grooves on the surface of the monocrystalline silicon wafer, so that the surface of the monocrystalline silicon wafer is flat, serving as a silicon substrate 100. The silicon substrate 100 has opposite back and front surfaces.
[0129] Step 2, form a first tunneling oxide layer on the back surface by an oxidation process, and deposit boron-doped polysilicon on the first tunneling oxide layer by an LPCVD process. Then perform first patterning treatment by laser to remove the first tunneling oxide layer and the boron-doped polysilicon at the position reserved for preparing N-type doped polysilicon and at the edge of the silicon substrate 100, forming a P-type doped layer 210.
[0130] Step 3, perform alkali polishing cleaning treatment on the cell wafer obtained in step 4.
[0131] Step 4, form a second tunneling oxide layer on the back surface by an oxidation process, and deposit phosphorus-doped polysilicon on the second tunneling oxide layer by an LPCVD process. Then perform second patterning treatment by laser to remove the second tunneling oxide layer and the phosphorus-doped polysilicon on the P-type doped layer 210, adjacent to the P-type doped layer 210, and at the edge of the silicon substrate 100, forming an N-type doped layer 220. A first isolation region 101 is formed at the edge of the silicon substrate 100. A second isolation region 102 is formed between the P-type doped layer 210 and the N-type doped layer 220.
[0132] Step 5, perform alkali cleaning and texturing treatment on the cell wafer obtained in step 4, so that the exposed area of the silicon substrate 100 (including the first and second isolation regions 101 and 102 on the back surface and the front surface) is all made into a pyramid textured surface.
[0133] Step 6, sequentially deposit an aluminum oxide layer and a silicon nitride layer on the back surface and the front surface by a PECVD process, forming a passivation layer 500.
[0134] Step 7, perform third patterning treatment on the cell wafer obtained in step 6 to remove the passivation layer 500 in the reserved area of the grid line 400 on the P-type doped layer 210 and the N-type doped layer 220, exposing the P-type doped layer 210 and the N-type doped layer 220. Then sequentially perform sintering treatment and photo injection treatment to repair the damage of the laser opening.
[0135] Step 8, a metal seed layer 300 is deposited on the back surface by a magnetron sputtering process. The metal seed layer 300 is also deposited on the edge of the silicon substrate 100.
[0136] Step 9, a patterned mask layer 20 is prepared on the metal seed layer 300 on the P-type doped layer 210 and the N-type doped layer 220. The mask layer 20 covers all the areas except the gate lines 400.
[0137] Step 10, a potting layer 30 is coated on the edge of the silicon substrate 100, covering the first isolation area 101 and the metal seed layer 300 on the side edge of the silicon substrate 100. The potting layer 30 also covers the edge of the mask layer 20.
[0138] Step 11, a conductive body layer 401 is formed by depositing copper on the metal seed layer 300 through the mask layer 20 by an electroplating process.
[0139] Step 12, a conductive protection layer 402 is formed by depositing tin on the conductive body layer 401 through the mask layer 20 by an electroplating process.
[0140] Step 13, the solar cell obtained in step 12 is subjected to acid washing to remove the mask layer 20 and the potting layer 30.
[0141] Step 14, the solar cell obtained in step 14 is subjected to etching back to remove the metal seed layer 300 except the area of the gate lines 400.
[0142] Comparative Example 1
[0143] The difference between the present comparative example and Example 1 is that the first isolation area 101 is not formed on the edge of the silicon substrate 100.
[0144] The solar cells prepared in the above examples and comparative examples are subjected to performance testing, and the test results are shown in Table 1.
[0145] Table 1 Performance test results of the solar cells prepared in Example 1 and Comparative Example 1
[0146]
[0147] As can be seen from the results in Table 1, compared with Comparative Example 1, the solar cell prepared in Example 1 has a more obvious improvement in efficiency and a more obvious decrease in parallel resistance. In addition, the open circuit voltage, short circuit current, fill factor and other parameters are also improved to a certain extent.
[0148] The technical features of the above examples can be combined in any manner. In order to make the description simple, not all possible combinations of the technical features in the above examples are described, however, as long as the combinations of the technical features do not exist contradictory, they should be considered as the scope of the present disclosure.
[0149] The above embodiments only express several implementation manners of the present application, which are described in a more specific and detailed manner, but cannot be understood as a limitation on the patent scope of the present application. It should be noted that, for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, which all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims, and the description can be used to explain the content of the claims.
Claims
1. A method for fabricating a solar cell, characterized in that, Includes the following steps: A doped layer is formed on a first side of a silicon substrate, wherein the doped layer has a first isolation region between itself and the edge of the silicon substrate; A metal seed layer is deposited on the first side where the doped layer is formed; A patterned mask layer is prepared on the metal seed layer located on the doped layer; An encapsulation layer is coated at the edge of the silicon substrate, the encapsulation layer covering the first isolation region and the metal seed layer on the side of the silicon substrate; Gate lines are deposited on the metal seed layer through the mask layer; Remove the mask layer and the adhesive layer; Remove the metal seed layer outside the gate line region.
2. The preparation method according to claim 1, characterized in that, The doped layer includes a P-type doped layer and an N-type doped layer, and a second isolation region is provided between the P-type doped layer and the N-type doped layer.
3. The preparation method according to claim 2, characterized in that, The P-type doped layer includes a plurality of first fine gate connections, and the N-type doped layer includes a plurality of second fine gate connections, wherein the plurality of first fine gate connections and the plurality of second fine gate connections are alternately distributed along a first direction; The first and second fine gate connections adjacent to the edge of the silicon substrate are edge fine gate connections, and the other first and second fine gate connections are non-edge fine gate connections. The width of the edge fine gate connection is D1, and the width of the non-edge fine gate connection is D2. For fine gate connections of the same doping type, D1 is greater than D2.
4. The preparation method according to claim 3, characterized in that, D1 is less than or equal to 2D2; and / or D2 ranges from 10 μm to 1000 μm.
5. The preparation method according to claim 3, characterized in that, The width of the second isolation zone between adjacent non-edge fine gate connecting portions is d1, and the width of the first isolation zone at the edge fine gate connecting portion is d2. Then d2 is greater than d1, and d2 is greater than D2.
6. The preparation method according to claim 5, characterized in that, d2 is less than or equal to 2d1; and / or d2 is less than or equal to 2D2; and / or d1 ranges from 10 μm to 200 μm.
7. The preparation method according to claim 3, characterized in that, The P-type doped layer further includes a plurality of first main gate connection portions, and the N-type doped layer further includes a plurality of second fine gate connection portions, wherein the plurality of first main gate connection portions and the plurality of second fine main gate connection portions are alternately distributed along the second direction; The first main gate connection portion and the second main gate connection portion adjacent to the edge of the silicon substrate are edge main gate connection portions, and the other first main gate connection portions and the second main gate connection portions are non-edge main gate connection portions; The width of the non-edge main gate connection is D3, and the width of the edge main gate connection is D4. For main gate connections with the same doping type, D4 is greater than D3; and / or The width of the first isolation zone at the edge main gate connection is d3, and the width of the second isolation zone between adjacent non-main edge fine gate connections is d4, then d3 is greater than d4.
8. The preparation method according to claim 7, characterized in that, The edge gate connection on one side of the silicon substrate is continuous and uninterrupted; or There are multiple edge fine gate connections spaced apart on one side of the silicon substrate. The distance between adjacent edge fine gate connections is greater than the width of the second isolation region between the non-edge fine gate connection and the main gate connection, but less than the width of the non-edge main gate connection; and / or, the ratio of the distance between adjacent edge fine gate connections to the width of the second isolation region between adjacent non-edge fine gate connections is greater than 1 and less than 10.
9. The preparation method according to any one of claims 1 to 8, characterized in that, The edge of the silicon substrate also has a chamfered edge, and the ratio of the width of the first isolation region at the chamfered edge to the width of the first isolation region at the adjacent edge of the chamfered edge is greater than 1 and less than or equal to 2.
10. The preparation method according to any one of claims 1 to 8, characterized in that, The first isolation region is formed by patterning the doped layer; and / or The overlay layer covers the edge of the mask layer.
11. A solar cell, characterized in that, It is prepared by the preparation method according to any one of claims 1 to 10.