Stacked battery and method of manufacturing the same and photovoltaic module

Abstract

The embodiment of the present application relates to the field of photovoltaics, and provides a kind of laminated cell and its preparation method and photovoltaic module, the laminated cell includes sequentially stacked first electrode, electron transport layer, passivation layer, perovskite absorption layer, hole transport layer, silicon bottom layer and second electrode;Wherein, the material of passivation layer is CsPbCl3, the size of CsPbCl3 is quantum dot level, perovskite absorption layer includes at least two layers of different band gap perovskite absorption sublayer stacked, and the band gap of perovskite absorption sublayer closer to hole transport layer is lower.The present application sets up perovskite absorption layer includes at least two layers of different band gap perovskite absorption sublayer stacked, and the band gap of perovskite absorption sublayer closer to hole transport layer is lower, it is helpful to optimize the absorption of solar spectrum, especially can better utilize red light band, to improve the overall photoelectric conversion efficiency of cell.

Description

Technical Field

[0001] This application relates to the photovoltaic field, and in particular to a tandem cell, its preparation method, and a photovoltaic module. Background Technology

[0002] Currently, crystalline silicon solar cells remain the mainstream photovoltaic technology, accounting for approximately 90% of the entire photovoltaic market. Their highest efficiency has reached 27.3%, which is very close to the theoretical efficiency of 29.4% for monocrystalline silicon cells, indicating limited room for further efficiency improvements. To further enhance the conversion efficiency of silicon-based solar cells, researchers have proposed constructing tandem cells based on crystalline silicon. This involves layering a wide bandgap material on top of a crystalline silicon cell to broaden the spectral response and increase the cell's efficiency, with theoretical efficiencies exceeding 40%. Perovskite, with its excellent photoelectric properties and tunable bandgap, has become one of the preferred materials for tandem cells. Summary of the Invention

[0003] This application provides a tandem battery, its preparation method, and a photovoltaic module, which at least helps to improve the photoelectric conversion efficiency of the tandem battery.

[0004] To achieve the above objectives, according to one aspect of the present invention, a stacked battery is provided, comprising a first electrode, an electron transport layer, a passivation layer, a perovskite absorber layer, a hole transport layer, a silicon substrate, and a second electrode stacked sequentially; wherein the passivation layer is made of CsPbCl3, the size of the CsPbCl3 is at the quantum dot level, the perovskite absorber layer comprises at least two stacked perovskite absorber layers with different band gaps, and the perovskite absorber layer closer to the hole transport layer has a lower band gap.

[0005] Furthermore, the passivation layer has a thickness of 5-10 nm; the CsPbCl3 has a particle size of 7.5-8.5 nm.

[0006] Furthermore, the band gap of each perovskite absorption layer is independently 1.55~1.75eV; the thickness of the perovskite absorption layer is 400~1100nm.

[0007] Furthermore, the perovskite absorber layer comprises a first perovskite absorber layer, a second perovskite absorber layer, a third perovskite absorber layer, and a fourth perovskite absorber layer stacked sequentially.

[0008] Furthermore, the band gap of the first perovskite absorption layer is 0.04~0.07 eV higher than that of the second perovskite absorption layer; the band gap of the second perovskite absorption layer is 0.04~0.07 eV higher than that of the third perovskite absorption layer; and the band gap of the third perovskite absorption layer is 0.04~0.07 eV higher than that of the fourth perovskite absorption layer.

[0009] Furthermore, the band gap of the first perovskite absorption layer is 1.70~1.75 eV; the band gap of the second perovskite absorption layer is 1.65~1.70 eV; the band gap of the third perovskite absorption layer is 1.60~1.65 eV; and the band gap of the fourth perovskite absorption layer is 1.55~1.60 eV.

[0010] Furthermore, the thickness of the first perovskite absorption layer is 70~100nm; the thickness of the second perovskite absorption layer is 80~300nm; the thickness of the third perovskite absorption layer is 100~300nm; and the thickness of the fourth perovskite absorption layer is 150~400nm.

[0011] Furthermore, the stacked battery also includes a first conductive layer and a second conductive layer stacked together, the first conductive layer and the second conductive layer being located between the first electrode and the electron transport layer, with the first conductive layer being close to the first electrode.

[0012] Furthermore, the thickness of the first conductive layer is 10~60 nm; and / or, the thickness of the second conductive layer is 10~20 nm.

[0013] Furthermore, the tandem solar cell also includes an n-type polycrystalline silicon layer and a SiO layer. x Layer, Al2O3 layer and SiN x Layer, n-type polycrystalline silicon layer and SiO x The layer is located between the hole transport layer and the silicon substrate, consisting of the Al2O3 layer and the SiN layer. x The layer is located between the second electrode and the silicon substrate.

[0014] According to another aspect of the present invention, a method for fabricating the aforementioned tandem solar cell is provided, the method comprising: step S1, depositing a second electrode material on one side of a silicon wafer to form a second electrode, and depositing a hole transport material on the other side of the silicon wafer to form a hole transport layer; step S2, depositing at least two perovskite materials with different band gaps on the side of the hole transport layer away from the silicon wafer to form a perovskite absorption layer comprising at least two perovskite absorption layers with different band gaps, wherein the perovskite absorption layer closer to the hole transport layer has a lower band gap; step S3, depositing CsPbCl3 with a size at the quantum dot level on the side of the perovskite absorption layer away from the hole transport layer to form a passivation layer; step S4, depositing an electron transport material on the side of the passivation layer away from the perovskite absorption layer to form an electron transport layer; and step S5, depositing a first electrode material on the side of the electron transport layer away from the passivation layer to form a first electrode, thereby obtaining a tandem solar cell.

[0015] Furthermore, the preparation of the passivation layer includes: coating CsPbCl3 with a size at the quantum dot level on the side of the perovskite absorber layer away from the hole transport layer, and then performing a first annealing treatment to form the passivation layer; the temperature of the first annealing treatment is 100~150℃; and the time of the first annealing treatment is 5~10min.

[0016] Furthermore, after each deposition of a perovskite material with a gap, a second annealing treatment is performed at a temperature of 150~200℃ and a time of 5~10min.

[0017] Further, step S5 includes: step S51, depositing a second conductive layer material on the side of the electron transport layer away from the passivation layer to form a second conductive layer; step S52, depositing a first conductive layer material on the side of the second conductive layer away from the electron transport layer to form a first conductive layer; step S53, depositing a first electrode material on the side of the first conductive layer away from the second conductive layer to form a first electrode, thereby obtaining a stacked battery.

[0018] According to another aspect of the present invention, a photovoltaic module is provided, comprising a battery string, an encapsulating film and a cover plate, wherein the battery string is formed by connecting a plurality of the aforementioned stacked cells or stacked cells prepared by the aforementioned method of preparing stacked cells.

[0019] The technical solution provided in this application has at least the following advantages:

[0020] This application establishes a perovskite absorption layer comprising at least two stacked perovskite absorption layers with different band gaps. The perovskite absorption layer closer to the hole transport layer has a lower band gap, which helps optimize the absorption of the solar spectrum, especially better utilizing the red light band, thereby improving the overall photoelectric conversion efficiency of the battery. Quantum dot-level CsPbCl3 serves as a passivation layer, effectively passivating the interface between the perovskite layer and the electron transport layer, reducing non-radiative recombination, increasing carrier lifetime and diffusion length, and thus improving the open-circuit voltage. The synergistic effect between the hole transport layer and the silicon substrate enhances hole transport efficiency and mobility. The positional relationship between the layers in this application further improves the photoelectric performance of the battery and reduces interface defects and charge recombination problems. Attached Figure Description

[0021] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the drawings in the accompanying drawings do not constitute a limitation on scale. In order to more clearly illustrate the technical solutions in the embodiments of this application or in the conventional art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 A schematic diagram of the structure of a first type of stacked battery according to an embodiment of this application is shown;

[0023] Figure 2 A schematic diagram of the structure of a second type of stacked battery according to an embodiment of this application is shown;

[0024] Figure 3 A schematic diagram of a third type of stacked battery provided according to an embodiment of this application is shown;

[0025] Figure 4 A schematic diagram of the structure of a fourth type of stacked battery according to an embodiment of this application is shown;

[0026] Figure 5 A schematic diagram of the structure of a fifth type of stacked battery according to an embodiment of this application is shown;

[0027] The above figures include the following reference numerals:

[0028] 10. First electrode; 20. First conductive layer; 30. Second conductive layer; 40. Electron transport layer; 50. Passivation layer; 60. Perovskite absorption layer; 61. First perovskite absorption layer; 62. Second perovskite absorption layer; 63. Third perovskite absorption layer; 64. Fourth perovskite absorption layer; 70. Hole transport layer; 81. n-type polycrystalline silicon layer; 82. SiO x Layer; 90, Silicon bottom layer; 101, Al2O3 layer; 102, SiN x Layer; 110, second electrode. Detailed Implementation

[0029] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. The present invention will now be described in detail with reference to the embodiments.

[0030] Terminology explanation: FA is short for CH(NH2)2, and MA is short for CH3NH3.

[0031] As analyzed in the background section of this application, the existing technology of tandem solar cells has the problem of low photoelectric conversion efficiency. In order to solve this problem, this application provides a tandem solar cell, a method for its fabrication, and a photovoltaic module.

[0032] In a typical embodiment of this application, a stacked battery is provided, such as Figure 1 As shown, the stacked battery includes a first electrode 10, an electron transport layer 40, a passivation layer 50, a perovskite absorber layer 60, a hole transport layer 70, a silicon substrate 90, and a second electrode 110 stacked sequentially. The passivation layer 50 is made of CsPbCl3, and the size of the CsPbCl3 is at the quantum dot level. The perovskite absorber layer 60 includes at least two stacked perovskite absorber layers with different band gaps, and the perovskite absorber layer closer to the hole transport layer 70 has a lower band gap.

[0033] This application establishes a perovskite absorption layer comprising at least two stacked perovskite absorption layers with different band gaps. The perovskite absorption layer closer to the hole transport layer has a lower band gap, which helps optimize the absorption of the solar spectrum, especially better utilizing the red light band, thereby improving the overall photoelectric conversion efficiency of the battery. Quantum dot-level CsPbCl3 serves as a passivation layer, effectively passivating the interface between the perovskite layer and the electron transport layer, reducing non-radiative recombination, increasing carrier lifetime and diffusion length, and thus improving the open-circuit voltage. The synergistic effect between the hole transport layer and the silicon substrate enhances hole transport efficiency and mobility. The positional relationship between the layers in this application further improves the photoelectric performance of the battery and reduces interface defects and charge recombination problems.

[0034] In some embodiments of this application, the stacked battery further includes an emitter layer located on the back side of the silicon substrate 90.

[0035] In some embodiments of this application, the stacked battery comprises, from top to bottom, a first electrode 10, an electron transport layer 40, a passivation layer 50, a perovskite absorber layer 60, a hole transport layer 70, a silicon substrate 90, and a second electrode 110, which are stacked sequentially. The passivation layer 50 is made of CsPbCl3, and the size of the CsPbCl3 is at the quantum dot level. The perovskite absorber layer 60 includes at least two stacked perovskite absorber layers with different band gaps, and the perovskite absorber layer closer to the hole transport layer 70 has a lower band gap.

[0036] In some embodiments of this application, the number of perovskite absorption layers with different band gaps in the perovskite absorption layer is 2 to 4.

[0037] Controlling the number of layers in the perovskite absorption layer within the above range helps to improve the response to infrared light while controlling production costs.

[0038] In some embodiments of this application, the thickness of the passivation layer 50 is 5~10 nm; the particle size of CsPbCl3 is 7.5~8.5 nm.

[0039] Controlling the thickness of the passivation layer within the aforementioned range helps to effectively passivate surface defects, reduce non-radiative recombination, and does not affect the rapid transport of charge carriers. Controlling the particle size of CsPbCl3 within the aforementioned range helps to form a uniform and dense passivation layer, enhances the stability of the battery structure, and reduces device aging and performance degradation.

[0040] In some embodiments of this application, the band gap of each perovskite absorption layer is independently 1.55~1.75eV; the thickness of the perovskite absorption layer 60 is 400~1100nm.

[0041] Controlling the band gaps of each perovskite absorption layer to be independently within the aforementioned range helps to expand the spectral response range of the battery, thereby improving photon capture efficiency and short-circuit current. Controlling the thickness of the perovskite absorption layer within the aforementioned range helps to improve light absorption and efficient carrier transport, while reducing recombination losses during carrier transport, thus contributing to improved photoelectric conversion efficiency.

[0042] In order to further improve the photoelectric conversion efficiency of the tandem solar cell, in some embodiments of this application, the perovskite absorption layer 60 includes a first perovskite absorption layer 61, a second perovskite absorption layer 62, a third perovskite absorption layer 63 and a fourth perovskite absorption layer 64 stacked in sequence.

[0043] In some embodiments of this application, the perovskite absorption layer 60 comprises, from top to bottom, a first perovskite absorption layer 61, a second perovskite absorption layer 62, a third perovskite absorption layer 63, and a fourth perovskite absorption layer 64 stacked sequentially.

[0044] In some embodiments of this application, the band gap of the first perovskite absorption layer 61 is 0.04~0.07 eV higher than that of the second perovskite absorption layer 62; the band gap of the second perovskite absorption layer 62 is 0.04~0.07 eV higher than that of the third perovskite absorption layer 63; and the band gap of the third perovskite absorption layer 63 is 0.04~0.07 eV higher than that of the fourth perovskite absorption layer 64.

[0045] Controlling the bandgap difference between two adjacent perovskite absorption layers within the aforementioned range helps to further optimize photon capture efficiency and carrier transport path, thereby contributing to further improvement in the photoelectric conversion efficiency of tandem solar cells.

[0046] In some embodiments of this application, the band gap of the first perovskite absorption layer 61 is 1.70~1.75 eV; the band gap of the second perovskite absorption layer 62 is 1.65~1.70 eV; the band gap of the third perovskite absorption layer 63 is 1.60~1.65 eV; and the band gap of the fourth perovskite absorption layer 64 is 1.55~1.60 eV.

[0047] Controlling the band gap of each perovskite absorption layer within the above-mentioned range helps the battery to efficiently absorb light in the spectral range from short wavelengths to long wavelengths, thereby helping to increase the generation of photogenerated carriers and thus improve the photoelectric conversion efficiency.

[0048] In some embodiments of this application, the thickness of the first perovskite absorption layer 61 is 70-100 nm; the thickness of the second perovskite absorption layer 62 is 80-300 nm; the thickness of the third perovskite absorption layer 63 is 100-300 nm; and the thickness of the fourth perovskite absorption layer 64 is 150-400 nm.

[0049] Controlling the thickness of each perovskite absorption layer within the above range helps to further improve carrier separation and transport efficiency, thereby helping to further improve photoelectric conversion efficiency.

[0050] To further improve carrier separation and transport efficiency, in some embodiments of this application, the ratio of the thickness of the first perovskite absorption layer, the thickness of the second perovskite absorption layer, the thickness of the third perovskite absorption layer, and the thickness of the fourth perovskite absorption layer is 70:(80~150):(100~150):(150~200).

[0051] In some embodiments of this application, the chemical formula of the perovskite in the perovskite absorber layer is ABX3, wherein A is selected from any one or more of Cs, CH(NH2)2 and CH3NH3, B is Pb, and X is selected from any one or more of Cl, Br and I.

[0052] Because Cs, CH(NH2)2 and CH3NH3 at the A site and Cl, Br and I at the X site can combine to form different perovskite structures, this diversity allows perovskite materials to have an adjustable band gap.

[0053] In some embodiments of this application, such as Figure 2 As shown, the above-mentioned stacked battery also includes a first conductive layer 20 and a second conductive layer 30 stacked together. The first conductive layer 20 and the second conductive layer 30 are located between the first electrode 10 and the electron transport layer 40, and the first conductive layer 20 is close to the first electrode 10.

[0054] The first and second conductive layers serve as additional layers, and their presence helps to enhance the lateral and longitudinal transport capabilities of electrons and holes.

[0055] In some embodiments of this application, the thickness of the first conductive layer 20 is 10-60 nm; and / or, the thickness of the second conductive layer 30 is 10-20 nm.

[0056] Controlling the thickness and material type of the first conductive layer within the aforementioned range helps to improve the efficiency of photogenerated electron collection while also increasing light transmittance.

[0057] In some embodiments of this application, such as Figure 3 As shown, the above-mentioned tandem solar cell also includes an n-type polycrystalline silicon layer 81 and SiO2. x Layer 82, Al2O3 layer 101 and SiN x Layer 102, n-type polycrystalline silicon layer 81 and SiO x Layer 82 is located between hole transport layer 70 and silicon substrate 90, Al2O3 layer 101 and SiN x Layer 102 is located between the second electrode 110 and the silicon substrate 90.

[0058] n-type polycrystalline silicon layer 81, SiO x Layer 82, Al2O3 layer 101 and SiN x The introduction of layer 102 helps reduce interfacial recombination and improve carrier lifetime.

[0059] In some embodiments of this application, the n-type polycrystalline silicon layer 81 and SiO x Layer 82 stacked, SiO x Layer 82 is located between n-type polycrystalline silicon layer 81 and silicon substrate 90; Al2O3 layer 101 and SiN x Layers 102 are stacked, and Al2O3 layer 101 is located on SiN. x Between layer 102 and silicon bottom layer 90.

[0060] To further optimize the rapid electron transport and reduce contact resistance, in some embodiments of this application, the material of the first conductive layer is selected from any one or more of indium tin oxide, zinc-doped indium oxide, tungsten-doped indium oxide, aluminum-doped zinc oxide, fluorine-doped tin oxide, and boron-doped zinc oxide; and / or, the material of the second conductive layer is SnO; to further reduce electron-hole recombination losses, the n-type polycrystalline silicon layer 81, SiO x The total thickness of layer 82 is 80~110 nm; and / or, Al2O3 layer 101 and SiN x The total thickness of layer 102 is 100~150nm.

[0061] In some embodiments of this application, the thickness of the first electrode is 100 nm to 1 μm; and / or, the material of the first electrode may be silver, gold, copper, aluminum, platinum, etc.; and / or, the thickness of the electron transport layer is 5 to 30 nm; and / or, the material of the electron transport layer is C60; and / or, the thickness of the hole transport layer is 15 to 30 nm; and / or, the material of the hole transport layer is selected from NiO and / or graphene quantum dots; and / or, the thickness of the silicon substrate is 160 to 200 μm; and / or, the material of the silicon substrate is n-type CzSi; and / or, the thickness of the second electrode is 20 to 1000 μm; and / or, the material of the second electrode may be silver paste, silver-aluminum paste, copper paste, etc.

[0062] Controlling the thickness and material type of the first electrode within the aforementioned range helps improve its conductivity and current collection capability. Controlling the thickness and material type of the second electrode within the aforementioned range helps improve the stability of the current output and reduce the risk of electrode breakage. Controlling the thickness and material type of the electron transport layer within the aforementioned range helps improve electron transport efficiency. Controlling the thickness and material type of the hole transport layer within the aforementioned range helps improve charge separation efficiency. Controlling the thickness and material type of the silicon substrate within the aforementioned range helps reduce resistive losses within the silicon mass while improving photoelectric conversion efficiency.

[0063] In some embodiments of this application, the material of the hole transport layer is a combination of NiO and graphene quantum dots, and the mass ratio of NiO to graphene quantum dots is (15~25):0.5.

[0064] In another typical embodiment of this application, a method for fabricating the aforementioned tandem solar cell is provided. The method includes: step S1, depositing a second electrode material on one side of a silicon wafer to form a second electrode, and depositing a hole transport material on the other side of the silicon wafer to form a hole transport layer; step S2, depositing at least two perovskite materials with different band gaps on the side of the hole transport layer away from the silicon wafer to form a perovskite absorption layer including at least two perovskite absorption layers with different band gaps, wherein the perovskite absorption layer closer to the hole transport layer has a lower band gap; step S3, depositing CsPbCl3 with a size at the quantum dot level on the side of the perovskite absorption layer away from the hole transport layer to form a passivation layer; step S4, depositing an electron transport material on the side of the passivation layer away from the perovskite absorption layer to form an electron transport layer; and step S5, depositing a first electrode material on the side of the electron transport layer away from the passivation layer to form a first electrode, thereby obtaining a tandem solar cell.

[0065] In step S1, the formation of the second electrode helps improve the stability of the current output and mechanical strength, while the formation of the hole transport layer helps improve charge separation efficiency. In step S2, by controlling the deposition sequence of the perovskite material, at least two perovskite absorption layers with different band gaps are formed, and the perovskite absorption layers closer to the hole transport layer have lower band gaps, which helps optimize spectral absorption and promote the separation and transport of photogenerated carriers. In step S3, the formation of the passivation layer helps suppress interfacial recombination and improve the overall performance and stability of the battery. In step S4, the formation of the electron transport layer helps optimize electron extraction and transport, reducing energy loss. In step S5, the formation of the first electrode helps improve the current collection efficiency.

[0066] In some embodiments of this application, the preparation of the passivation layer includes: coating CsPbCl3 with a size at the quantum dot level on the side of the perovskite absorber layer away from the hole transport layer, and then performing a first annealing treatment to form the passivation layer; the temperature of the first annealing treatment is 100~150℃; and the time of the first annealing treatment is 5~10min.

[0067] Controlling the temperature and time of the first annealing treatment within the above range helps to improve the uniformity of the distribution of CsPbCl3 with quantum dot-sized dimensions on the perovskite surface, thereby helping to improve the density of the passivation layer.

[0068] In order to reduce the defect density in the perovskite layer and improve the stability of the material itself, in some embodiments of this application, a second annealing treatment is performed after each deposition of a perovskite material with a gap. The temperature of the second annealing treatment is 150~200℃ and the time of the second annealing treatment is 5~10min.

[0069] In some embodiments of this application, step S1 above further includes pre-processing the silicon wafer, which includes: sequentially performing double-sided polishing and single-sided texturing on the silicon wafer.

[0070] Polishing removes surface roughness, while texturing introduces a pyramid structure on the front side, which helps to enhance the scattering and absorption of light on the silicon surface, while reducing light reflection on the front side, thereby helping to improve the light utilization rate of the tandem solar cell.

[0071] In some embodiments of this application, step S5 includes: step S51, depositing a second conductive layer material on the side of the electron transport layer away from the passivation layer to form a second conductive layer; step S52, depositing a first conductive layer material on the side of the second conductive layer away from the electron transport layer to form a first conductive layer; and step S53, depositing a first electrode material on the side of the first conductive layer away from the second conductive layer to form a first electrode, thereby obtaining a stacked battery.

[0072] The formation of the second conductive layer helps accelerate hole transport. The formation of the first conductive layer helps optimize electron collection and transport paths, reducing contact resistance.

[0073] In another typical embodiment of this application, a photovoltaic module is provided, including a battery string, an encapsulating film and a cover plate, wherein the battery string is formed by connecting multiple of the aforementioned stacked cells or stacked cells prepared by the aforementioned method of preparing stacked cells.

[0074] Since the cell strings in the above-mentioned photovoltaic module are connected by the stacked cells of this application or the stacked cells prepared by the method of this application, the photovoltaic module has a high photoelectric conversion efficiency.

[0075] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0076] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0077] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A exists, A and B exist simultaneously, and B exists. In addition, the character " / " in this document generally indicates that the related objects before and after it have an "or" relationship.

[0078] The embodiments of this application will now be described in detail with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been provided in the embodiments of this application to facilitate a better understanding of the application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0079] Example 1

[0080] Both sides of a silicon wafer (n-type CzSi, resistivity 0.5 Ω·cm, thickness 160 μm) were polished, followed by RCA (a cleaning method proposed by American Wireless) cleaning to remove metallic impurities. Then, single-sided texturing was performed using a potassium hydroxide aqueous solution with 10% isopropanol as an additive. The texturing temperature was 80°C, resulting in a pyramidal textured surface with a thickness of 1.5 μm. This silicon wafer was used as the silicon underlayer. The wafer was then placed in a 950°C dry oxygen environment to form a 1.5 nm thick SiO2 layer on the texturized surface. A 100 nm amorphous silicon layer was deposited on the SiO2 layer using low-pressure chemical vapor deposition at 620°C and 300 mTorr. The amorphous silicon layer was then doped at 850°C in a POCl3 atmosphere to form n-type CzSi. + - A Si layer (sheet resistance of 150Ω / □) was formed, and finally annealed in nitrogen at 900℃ for 30 min to form an n-type polycrystalline silicon layer 81. The SiO2 layer was then converted to SiO2. x Layer 82, n-type polycrystalline silicon layer 81 and SiO x The total thickness of layer 82 is 101.5 nm. An Al2O3 layer 101 with a thickness of 10 nm was deposited on the untextured surface using atomic layer deposition (precursor: trimethylaluminum, temperature: 150℃, thickness per cycle: 0.12 nm). A SiN layer with a thickness of 90 nm was then formed on the surface of the Al2O3 layer using plasma-enhanced chemical vapor deposition (SiH4 to NH3 volume ratio: 1:3, RF power: 300 W). x Layer 102 (x is 1.5~1.8), refractive index 2.05%, Al2O3 layer 101 and SiN x The total thickness of layer 102 is 100 nm. (This is in the context of SiN.) x The surface of layer 102 was screen-printed with silver paste (15 μm linewidth, 20 μm thickness) and sintered in a chain furnace under N2 atmosphere at a peak temperature of 800 °C to form the second electrode 110. NiO nanoparticles (average particle size 3 nm) were dissolved in water to form a solution with a concentration of 20 mg / mL. 17.5 μL of a lithium bis(trifluoromethanesulfonyl)imide aqueous solution (concentration 0.1 mg / L), 28 μL of 4-tert-butylpyridine, and graphene quantum dots (average particle size 3 nm) were added to the solution to form a mixed solution with a graphene quantum dot concentration of 0.5 mg / mL. The mixed solution was spin-coated (3000 rpm × 30 s) onto the surface of the n-type polycrystalline silicon layer 81, and then oxidized for 12 h in an environment with humidity <30% to form a hole transport layer 70 with a thickness of 15 nm. FA 0.9 MA 0.1PbI3 solution (solvents: N,N-dimethylformamide and dimethyl sulfoxide, volume ratio 4:1) was spin-coated onto the surface of the hole transport layer and annealed in N2 at 150°C for 7 min to form a fourth perovskite absorption layer with a thickness of 150 nm and a band gap of 1.55 eV. The PbI3 solution was then annealed to (FA) via vacuum evaporation. 0.8 Cs 0.2 )Pb(I 0.8 Br 0.2 )3 was deposited on the surface of the fourth perovskite absorption layer and annealed in N2 at 150°C for 7 min to form a third perovskite absorption layer 63 with a thickness of 100 nm and a band gap of 1.62 eV. (FA) was then applied by a blade coating method (substrate temperature 80°C). 0.9 Cs 0.1 )Pb(I 0.75 Br 0.25 )3 was deposited on the surface of the third perovskite absorption layer and annealed in N2 at 150°C for 7 min to form a second perovskite absorption layer 62 with a thickness of 80 nm and a band gap of 1.68 eV. FA was then removed by vacuum evaporation. 0.8 Cs 0.2 Pb(I 0.7 Br 0.3 )3. The first perovskite absorption layer 61 with a thickness of 70 nm and a band gap of 1.72 eV was deposited on the surface of the second perovskite absorption layer and annealed in N2 at 150 °C for 7 min. Cs2CO3 solution (oleic acid as solvent) and PbCl2 solution (oleylamine as solvent) were injected into a reactor at 180 °C and reacted for 5 min to obtain CsPbCl3 with a particle size of 7.5~8.5 nm. CsPbCl3 was spin-coated (4000 rpm × 20 s) onto the first perovskite layer. The surface of the absorption layer is annealed at 100°C for 5 min to form a passivation layer 50 with a thickness of 5 nm. C60 is then deposited on the passivation layer to form an electron transport layer 40 with a thickness of 20 nm. SnO is then deposited on the electron transport layer to form a second conductive layer 30 with a thickness of 20 nm. Zinc-doped indium oxide is then deposited on the second conductive layer to form a first conductive layer 20 with a thickness of 30 nm. Finally, silver is deposited on the first conductive layer to form a first electrode 10 with a thickness of 100 nm, resulting in a tandem battery with the structure shown below. Figure 4 As shown.

[0081] Example 2

[0082] The difference from Example 1 is that CsPbCl3 is spin-coated onto the surface of the first perovskite absorption layer and annealed at 100°C for 10 min to form a passivation layer with a thickness of 10 nm, ultimately obtaining a tandem solar cell.

[0083] Example 3

[0084] The difference from Example 1 is that CsPbCl3 is spin-coated onto the surface of the first perovskite absorber layer and annealed at 100°C for 10 min to form a passivation layer with a thickness of 15 nm, ultimately obtaining a tandem solar cell.

[0085] Example 4

[0086] The difference from Example 1 is that the material of the fourth perovskite absorber layer is CsPbI3 with a band gap of 1.5 eV, which finally yields a tandem solar cell.

[0087] Example 5

[0088] The difference from Example 1 is that the second perovskite absorption layer is eliminated, resulting in a tandem solar cell with the structure as shown in Example 1. Figure 5 As shown.

[0089] Example 6

[0090] The difference from Example 1 is that the thickness of the fourth perovskite absorption layer is 200 nm, the thickness of the third perovskite absorption layer is 150 nm, the thickness of the second perovskite absorption layer is 150 nm, and the thickness of the first perovskite absorption layer is 70 nm, thus obtaining a stacked solar cell.

[0091] Example 7

[0092] The difference from Example 1 is that the thickness of the fourth perovskite absorption layer is 400 nm, the thickness of the third perovskite absorption layer is 100 nm, the thickness of the second perovskite absorption layer is 300 nm, and the thickness of the first perovskite absorption layer is 70 nm, thus obtaining a stacked solar cell.

[0093] Example 8

[0094] The difference from Example 1 is that the thickness of the fourth perovskite absorption layer is 150 nm, the thickness of the third perovskite absorption layer is 300 nm, the thickness of the second perovskite absorption layer is 80 nm, and the thickness of the first perovskite absorption layer is 100 nm, thus obtaining a stacked solar cell.

[0095] Example 9

[0096] The difference from Example 1 is that the thickness of the fourth perovskite absorption layer is 100 nm, the thickness of the third perovskite absorption layer is 350 nm, the thickness of the second perovskite absorption layer is 70 nm, and the thickness of the first perovskite absorption layer is 150 nm, thus obtaining a stacked solar cell.

[0097] Example 10

[0098] The difference from Example 1 is that the thickness of the second conductive layer is 10 nm and the thickness of the second conductive layer is 60 nm, resulting in a stacked battery.

[0099] Example 11

[0100] The difference from Example 1 is that the thickness of the second conductive layer is 5nm and the thickness of the second conductive layer is 65nm, resulting in a stacked battery.

[0101] Example 12

[0102] The difference from Example 1 is that the n-type polycrystalline silicon layer 81 and SiO are... x The thickness ratio between layers 82 remains unchanged, and the n-type polycrystalline silicon layer 81 and SiO2 remain unchanged. x The total thickness of layer 82 is 80 nm, and the Al2O3 layer 101 and SiN are also present. x The thickness ratio between layers 102 remains unchanged, while the Al2O3 layer 101 and SiN... x The total thickness of layer 102 is 150nm, resulting in a stacked solar cell.

[0103] Example 13

[0104] The difference from Example 1 is that the n-type polycrystalline silicon layer 81 and SiO are... x The thickness ratio between layers 82 remains unchanged, and the n-type polycrystalline silicon layer 81 and SiO2 remain unchanged. x The total thickness of layer 82 is 120 nm, and the Al2O3 layer 101 and SiN are also present. x The thickness ratio between layers 102 remains unchanged, while the Al2O3 layer 101 and SiN... x The total thickness of layer 102 is 80nm, resulting in a stacked solar cell.

[0105] Example 14

[0106] The difference from Example 1 is that both sides of the silicon wafer (n-type CzSi, resistivity 0.5 Ω·cm, thickness 200 μm) were polished, followed by RCA (a cleaning method proposed by American Wireless) cleaning to remove metallic impurities. Then, single-sided texturing was performed using a potassium hydroxide aqueous solution with 10% isopropanol as an additive. The texturing temperature was 80°C, resulting in a pyramidal textured surface with a thickness of 1.5 μm. The silicon wafer was placed in a 950°C dry oxygen environment to form a 1.5 nm thick SiO2 layer on the texturized surface. A 100 nm amorphous silicon layer was deposited on the SiO2 layer using low-pressure chemical vapor deposition at 620°C and 300 mTorr. The amorphous silicon layer was then doped at 850°C in a POCl3 atmosphere to form n-type CzSi. + - A Si layer (sheet resistance of 150Ω / □) was formed, and finally annealed in nitrogen at 900℃ for 30 min to form an n-type polycrystalline silicon layer 81. The SiO2 layer was then converted to SiO2. x Layer 82, n-type polycrystalline silicon layer 81 and SiOx The total thickness of layer 82 is 101.5 nm. An Al2O3 layer 101 with a thickness of 10 nm was deposited on the untextured surface using atomic layer deposition (precursor: trimethylaluminum, temperature: 150℃, thickness per cycle: 0.12 nm). A SiN layer with a thickness of 90 nm was then formed on the surface of the Al2O3 layer using plasma-enhanced chemical vapor deposition (SiH4 to NH3 volume ratio: 1:3, RF power: 300 W). x Layer 102 (x is 1.5~1.8), refractive index 2.05%, Al2O3 layer 101 and SiN x The total thickness of layer 102 is 100 nm. (This is in the context of SiN.) x The surface of layer 102 was screen-printed with silver paste (15 μm linewidth, 100 μm thickness) and sintered in a chain furnace under N2 atmosphere at a peak temperature of 800 °C to form the second electrode. NiO nanoparticles (average particle size 3 nm) were dissolved in water to form a solution with a concentration of 20 mg / mL. 17.5 μL of lithium bis(trifluoromethanesulfonyl)imide aqueous solution (concentration 0.1 mg / L), 28 μL of 4-tert-butylpyridine, and graphene quantum dots (average particle size 3 nm) were added to the solution to form a mixed solution with a graphene quantum dot concentration of 0.5 mg / mL. The mixed solution was spin-coated (3000 rpm × 30 s) onto the surface of n-type polycrystalline silicon layer 81, and then oxidized for 12 h in an environment with humidity <30% to form a hole transport layer with a thickness of 30 nm. FA 0.9 MA 0.1 PbI3 solution (solvents: N,N-dimethylformamide and dimethyl sulfoxide, volume ratio 4:1) was spin-coated onto the surface of the hole transport layer and annealed in N2 at 150°C for 7 min to form a fourth perovskite absorption layer with a thickness of 150 nm and a band gap of 1.55 eV. The PbI3 solution was then removed by vacuum evaporation. 0.8 Cs 0.2 )Pb(I 0.8 Br 0.2 )3 was deposited on the surface of the fourth perovskite absorption layer and annealed in N2 at 150°C for 7 min to form a third perovskite absorption layer with a thickness of 100 nm and a band gap of 1.62 eV. (FA) was then applied by a blade coating method (substrate temperature 80°C). 0.9 Cs 0.1 )Pb(I 0.75 Br 0.25 )3 was deposited on the surface of the third perovskite absorption layer and annealed in N2 at 150°C for 7 min to form a second perovskite absorption layer with a thickness of 80 nm and a band gap of 1.68 eV. FA was then removed by vacuum evaporation. 0.8 Cs 0.2 Pb(I 0.7 Br0.3 )3. The first perovskite absorption layer is deposited on the surface of the second perovskite absorption layer and annealed in N2 at 150°C for 7 min to form a first perovskite absorption layer with a thickness of 70 nm and a band gap of 1.72 eV. Cs2CO3 solution (oleic acid as solvent) and PbCl2 solution (oleylamine as solvent) are injected into a reactor at 180°C and reacted for 5 min to obtain CsPbCl3 with a particle size of 7.5~8.5 nm. CsPbCl3 is spin-coated (4000 rpm × 20 s) on the surface of the first perovskite absorption layer and annealed at 100°C for 5 min to form a passivation layer with a thickness of 5 nm. C60 is evaporated on the passivation layer to form an electron transport layer with a thickness of 30 nm. SnO is evaporated on the electron transport layer to form a second conductive layer with a thickness of 20 nm. Zinc-doped indium oxide is evaporated on the second conductive layer to form a first conductive layer with a thickness of 30 nm. Silver is evaporated on the first conductive layer to form a first electrode with a thickness of 500 nm, thus obtaining a tandem battery.

[0107] Comparative Example 1

[0108] The difference from Example 1 is that the passivation layer formed by CsPbCl3 is removed, resulting in a stacked battery.

[0109] Comparative Example 2

[0110] The difference from Example 1 is that the particle size of CsPbCl3 is 100nm, and a stacked battery is finally obtained.

[0111] Comparative Example 3

[0112] The difference from Example 1 is that the fourth, third, and second perovskite absorption layers are all replaced with the first perovskite absorption layer, resulting in a stacked solar cell.

[0113] Performance testing

[0114] Test method for photoelectric conversion efficiency of tandem solar cells: 25℃, one atmosphere, under standard simulated sunlight (AM1.5G, 100 milliwatts per square centimeter (mW / cm²)). 2 Under irradiation, the battery performance was tested to obtain the IV curve (volt-ampere characteristic curve). Based on the IV curve and the data fed back by the testing equipment (four-channel digital source meter, Keithley 2450), the short-circuit current density Jsc (unit: milliampere / cm²) can be obtained. 2 )), Open circuit voltage Voc (unit: volts (V)).

[0115] The fill factor FF of the battery can be calculated using the formula FF = Jsc × Voc / (Jmpp × Vmpp), in percentage. The photoelectric conversion efficiency PCE of the battery can be calculated using the formula PCE = Jsc × Voc × FF / Pw, in percentage; Pw represents the input power, in milliwatts (mW).

[0116] The tandem solar cells prepared in the above embodiments and comparative examples were tested for photoelectric conversion efficiency, open-circuit voltage, short-circuit current density and fill factor, respectively. The test results are shown in Table 1.

[0117] Table 1

[0118]

[0119] As can be seen from the above description, the embodiments of the present invention achieve the following technical effects:

[0120] This application establishes a perovskite absorption layer comprising at least two stacked perovskite absorption layers with different band gaps. The perovskite absorption layer closer to the hole transport layer has a lower band gap, which helps optimize the absorption of the solar spectrum, especially better utilizing the red light band, thereby improving the overall photoelectric conversion efficiency of the battery. Quantum dot-level CsPbCl3 serves as a passivation layer, effectively passivating the interface between the perovskite layer and the electron transport layer, reducing non-radiative recombination, increasing carrier lifetime and diffusion length, and thus improving the open-circuit voltage. The synergistic effect between the hole transport layer and the silicon substrate enhances hole transport efficiency and mobility. The positional relationship between the layers in this application further improves the photoelectric performance of the battery and reduces interface defects and charge recombination problems.

[0121] Those skilled in the art will understand that the above embodiments are specific examples of implementing this application, and in practical applications, various changes in form and detail can be made without departing from the spirit and scope of this application. Any person skilled in the art can make various alterations and modifications without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A stacked battery, characterized by comprising: The tandem battery comprises a first electrode (10), an electron transport layer (40), a passivation layer (50), a perovskite absorber layer (60), a hole transport layer (70), a silicon substrate (90), and a second electrode (110) stacked sequentially. The passivation layer (50) is made of CsPbCl3, and the size of the CsPbCl3 is at the quantum dot level. The perovskite absorber layer (60) includes at least two stacked perovskite absorber layers with different band gaps, and the perovskite absorber layer closer to the hole transport layer (70) has a lower band gap. The band gap of each perovskite absorber layer is independently 1.55~1.75 eV.

2. The stacked battery of claim 1, wherein, The passivation layer (50) has a thickness of 5~10 nm; the CsPbCl3 has a particle size of 7.5~8.5 nm.

3. The stacked battery of claim 1, wherein, The thickness of the perovskite absorber layer (60) is 400~1100 nm.

4. The stacked battery according to any one of claims 1 to 3, characterized by, The perovskite absorption layer (60) includes a first perovskite absorption layer (61), a second perovskite absorption layer (62), a third perovskite absorption layer (63), and a fourth perovskite absorption layer (64) stacked sequentially.

5. The stacked battery according to claim 4, characterized in that, The band gap of the first perovskite absorption layer (61) is 0.04~0.07 eV higher than that of the second perovskite absorption layer (62); The band gap of the second perovskite absorption layer (62) is 0.04~0.07 eV higher than that of the third perovskite absorption layer (63); The band gap of the third perovskite absorption layer (63) is 0.04~0.07 eV higher than that of the fourth perovskite absorption layer (64).

6. The stacked battery of claim 4, wherein, The band gap of the first perovskite absorption layer (61) is 1.70~1.75 eV; the band gap of the second perovskite absorption layer (62) is 1.65~1.70 eV; the band gap of the third perovskite absorption layer (63) is 1.60~1.65 eV; and the band gap of the fourth perovskite absorption layer (64) is 1.55~1.60 eV.

7. The stacked battery of claim 4, wherein, The thickness of the first perovskite absorption layer (61) is 70~100nm; the thickness of the second perovskite absorption layer (62) is 80~300nm; the thickness of the third perovskite absorption layer (63) is 100~300nm; and the thickness of the fourth perovskite absorption layer (64) is 150~400nm.

8. The stacked battery according to any one of claims 1 to 3, characterized by, The stacked battery further includes a first conductive layer (20) and a second conductive layer (30) stacked together. The first conductive layer (20) and the second conductive layer (30) are located between the first electrode (10) and the electron transport layer (40), and the first conductive layer (20) is close to the first electrode (10).

9. The stacked battery of claim 8, wherein, The thickness of the first conductive layer (20) is 10~60nm; and / or the thickness of the second conductive layer (30) is 10~20nm.

10. The stacked battery according to any one of claims 1 to 3, characterized in that, The stacked battery also includes an n-type polycrystalline silicon layer (81) and SiO2. x Layer (82), Al2O3 layer (101) and SiN x Layer (102), the n-type polycrystalline silicon layer (81) and the SiO x Layer (82) is located between the hole transport layer (70) and the silicon substrate (90), the Al2O3 layer (101) and the SiN x The layer (102) is located between the second electrode (110) and the silicon substrate (90).

11. A method of producing the stacked cell according to any one of claims 1 to 10, characterized by, The preparation method includes: Step S1: Deposit the second electrode material on one side of the silicon wafer to form the second electrode, and deposit the hole transport material on the other side of the silicon wafer to form the hole transport layer. Step S2: Deposit at least two perovskite materials with different band gaps on one side of the hole transport layer away from the silicon wafer to form a perovskite absorption layer including at least two perovskite absorption layers with different band gaps, and the perovskite absorption layer with a lower band gap is closer to the hole transport layer. Step S3: Deposit CsPbCl3 with a size of quantum dot on the side of the perovskite absorber layer away from the hole transport layer to form a passivation layer; Step S4: Electron transport material is deposited on the side of the passivation layer away from the perovskite absorption layer to form an electron transport layer; Step S5: Deposit the first electrode material on the side of the electron transport layer away from the passivation layer to form the first electrode, thereby obtaining the stacked battery.

12. The method of claim 11, wherein the step of forming the stack of cells is performed by a method comprising: The preparation of the passivation layer includes: coating the CsPbCl3 with a size at the quantum dot level on one side of the perovskite absorber layer away from the hole transport layer, and then performing a first annealing treatment to form the passivation layer; the temperature of the first annealing treatment is 100~150℃; and the time of the first annealing treatment is 5~10min.

13. The method of claim 11, wherein the step of forming the stack of cells is performed by a method comprising: After each deposition of a perovskite material with a gap, a second annealing treatment is performed. The temperature of the second annealing treatment is 150~200℃, and the time of the second annealing treatment is 5~10min.

14. The method of claim 11 to 13, wherein Step S5 includes: Step S51: Deposit the second conductive layer material on the side of the electron transport layer away from the passivation layer to form the second conductive layer; Step S52: Deposit the first conductive layer material on the side of the second conductive layer away from the electron transport layer to form the first conductive layer; Step S53: Deposit the first electrode material on the side of the first conductive layer away from the second conductive layer to form the first electrode layer, thereby obtaining the stacked battery.

15. A photovoltaic module comprising a string of cells, an encapsulant film and a cover sheet, characterized in that, The battery string is formed by connecting multiple stacked batteries prepared by the method of any one of claims 1 to 10 or any one of claims 11 to 14.

Images