Crystalline silicon perovskite laminated cell and preparation method thereof

Abstract

According to the crystalline silicon perovskite laminated cell and the preparation method thereof disclosed by the invention, a metal seed thin layer with a grid line pattern is introduced between a transparent conductive film and a grid line electrode of the laminated cell, so that on one hand, the contact resistance between the grid line electrode and the transparent conductive film can be greatly reduced; the contact resistance is reduced to 5% of the original contact resistance compared with that of a cell without a metal seed thin layer; and on the other hand, the binding force between the grid line and the transparent conductive film is improved, so that the ultralow-temperature curing slurry and the transparent conductive film can be fully bonded. In conclusion, the metal seed thin layer with the grid line pattern is introduced to achieve the purpose of improving the conversion efficiency and the stability of the crystalline silicon / perovskite laminated cell at the same time.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of perovskite batteries, and particularly relates to a crystalline silicon perovskite stacked battery and a preparation method thereof. BACKGROUND

[0002] The perovskite crystalline silicon stacked battery is a new type of solar cell structure, which stacks a perovskite solar cell and a crystalline silicon solar cell together. The design of this stacked structure aims to improve the solar energy conversion efficiency and achieve wider light absorption in the spectral range. The working principle of the perovskite crystalline silicon stacked battery is that, in the stacked structure, the perovskite solar cell is located at the top layer for absorbing high-energy light, and the crystalline silicon solar cell is located at the bottom layer for absorbing low-energy light.

[0003] However, the problem of thermal decomposition of the material limits the selection of electrode materials and electrode preparation methods for perovskite batteries. The current mainstream method is to use screen printing of ultra-low temperature paste (solidification temperature not greater than 120℃) to prepare the electrodes of the crystalline silicon / perovskite stacked battery. However, all the ultra-low temperature pastes on the market cannot achieve similar performance to traditional low-temperature pastes (solidification temperature about 200℃). Since the ultra-low temperature solidification paste cannot fully bond with the transparent conductive film, it results in excessive ohmic contact resistance, making it difficult to improve the photoelectric conversion efficiency of the stacked battery. Therefore, it is necessary to develop a new type of grid line electrode structure. SUMMARY

[0004] In order to overcome the problems existing in the prior art, one of the purposes of the present application is to provide a crystalline silicon perovskite stacked battery. The second purpose of the present application is to provide a preparation method of the above-mentioned crystalline silicon perovskite stacked battery.

[0005] The present application innovatively introduces a layer of metal seed thin layer with a grid line pattern between the transparent conductive film and the grid line electrode of the stacked battery, which not only greatly reduces the contact resistance between the grid line electrode and the transparent conductive film, solves the problem that it is difficult to improve the photoelectric conversion efficiency of the stacked battery, but also improves the bonding force between the grid line and the transparent conductive film, achieving the purpose of simultaneously improving the conversion efficiency and stability of the crystalline silicon / perovskite stacked battery.

[0006] In order to achieve the above-mentioned purposes, the technical solutions adopted by the present application are as follows: The first aspect of the present application provides a crystalline silicon perovskite stacked battery, which comprises a perovskite battery, a crystalline silicon battery and a composite layer; the composite layer is used to connect the top battery and the bottom battery in series; The perovskite battery comprises a front metal grid line electrode, a front metal seed thin layer and a front transparent conductive film layer arranged in sequence; the crystalline silicon battery comprises a back metal grid line electrode, a back metal seed thin layer and a back transparent conductive film layer arranged in sequence; The front and back metal seed thin layers are seed grid line structures; the front and back metal grid line electrodes are electrode grid line structures; the grid line patterns of the seed grid line structures and the electrode grid line structures are the same.

[0007] In the present application, the grid line pattern comprises a plurality of main grids and a plurality of vertical auxiliary grids, the main grids are parallel to each other, and the auxiliary grids are also parallel to each other.

[0008] Preferably, the grid line width of the electrode grid line structure is greater than or equal to the grid line width of the seed grid line structure.

[0009] The metal seed thin layer is beneficial to enhancing the conductivity between the silver grid line electrode and the transparent conductive thin film, but if the grid line width of the seed thin layer is too wide (greater than the grid line width of the grid line electrode), the light absorption efficiency of the battery piece will be affected, and the present application controls the grid line width of the electrode grid line structure to be greater than or equal to the grid line width of the seed grid line structure, so as to effectively balance the light absorption efficiency and electrical performance of the battery piece prepared subsequently.

[0010] More preferably, when the grid line width of the electrode grid line structure is greater than the grid line width of the seed grid line structure, the front / back metal grid line electrode covers the front / back metal seed thin layer to form a combined state, and the front / back metal grid line electrode is in contact with the front / back transparent conductive film layer.

[0011] More preferably, when the grid line width of the electrode grid line structure is equal to the grid line width of the seed grid line structure, the front / back metal grid line electrode covers the top surface of the front / back metal seed thin layer.

[0012] Preferably, the thickness of the seed grid line structure is 70-150 nm; the width of the seed grid line structure is 20-50 μm; and the distance between adjacent grid lines of the seed grid line structure is 1-2 mm.

[0013] More preferably, the thickness of the seed grid line structure is 80-100 nm.

[0014] More preferably, the front and back metal seed thin layers are seed grid line structure 1 and seed grid line structure 2 respectively; the width of the seed grid line structure 1 is 20-30 μm; and the width of the seed grid line structure 2 is 30-50 μm.

[0015] Preferably, the thickness of the electrode grid line structure is 5-20 μm; the width of the electrode grid line structure is 20-50 μm; and the distance between adjacent grid lines of the electrode grid line structure is 1-2 mm.

[0016] More preferably, the front metal grid line electrode and the back metal grid line electrode are electrode grid line structure 1 and electrode grid line structure 2, respectively; the width of electrode grid line structure 1 is 20-30 μm; and the width of electrode grid line structure 2 is 30-50 μm.

[0017] Preferably, the front and back metal seed layers are made of copper or a copper-nickel alloy.

[0018] Preferably, the raw materials for preparing the front metal grid electrode and the back metal grid electrode include one or more of Ag and Cu.

[0019] Preferably, the front transparent conductive film layer and the back transparent conductive film layer are selected from one or two of ITO, IZO, IWO, and AZO.

[0020] Preferably, the thicknesses of the front transparent conductive film layer and the back transparent conductive film layer are 40-60nm and 80-120nm, respectively.

[0021] Preferably, the composite layer can be one or two of ITO, IZO, IWO, and AZO stacked together.

[0022] Preferably, the thickness of the composite layer is 10-30 nm.

[0023] Preferably, the crystalline silicon perovskite tandem solar cell includes, sequentially arranged, a front metal grid electrode, a front metal seed layer, a front transparent conductive film layer, an intermediate protective layer, an electron transport layer, a perovskite absorption layer, a hole transport layer, a composite layer, intrinsic amorphous silicon and phosphorus-doped amorphous silicon thin layers, a silicon substrate, intrinsic amorphous silicon and boron-doped amorphous silicon thin layers, a back transparent conductive film layer, a back metal seed layer, and a back metal grid electrode.

[0024] More preferably, the intermediate protective layer is a SnO2 layer.

[0025] More preferably, the thickness of the intermediate protective layer is 5-25 nm.

[0026] More preferably, the material of the electron transport layer includes at least one of fullerene (C60) and its derivatives, PCBM, SnO2, TiO2, and ZnO.

[0027] More preferably, the thickness of the electron transport layer is 10-30 nm.

[0028] More preferably, the perovskite light-absorbing layer comprises a perovskite material with an ABX3 structure, wherein A is selected from methylamino, formamidinyl, and Cs + , phenylethylamine, Ru + K +At least one of them, B is selected from Pb 2+ Sn 2+ Cu 2+ At least one of them, X is selected from I - ,Br - Cl - F - At least one of them.

[0029] More preferably, the thickness of the perovskite light-absorbing layer is 500-800 nm.

[0030] More preferably, the material of the hole transport layer includes at least one of spiro-OMeTAD, PTAA, NiOx, and PEDOT:PSS.

[0031] More preferably, the thickness of the hole transport layer is 5-15 nm.

[0032] More preferably, the thickness of the intrinsic amorphous silicon and phosphorus-doped amorphous silicon thin layer is 7-20 nm.

[0033] More preferably, the thickness of the silicon substrate is 50-150 μm.

[0034] More preferably, the silicon substrate has a textured surface on both sides.

[0035] More preferably, the thickness of the intrinsic amorphous silicon and boron-doped amorphous silicon thin layer is 10-30 nm.

[0036] A second aspect of the present invention provides a method for preparing the crystalline silicon perovskite tandem solar cell described in the first aspect, comprising the following steps: A patterned mask is fixed on the front transparent conductive film layer, a front metal seed thin layer with a seed grid structure is deposited, and then a front metal grid electrode is formed on the front metal seed thin layer. A patterned mask is fixed on a transparent conductive film layer on the back side, a thin layer of back metal seed with a seed grid structure is deposited, and then a back metal grid electrode is formed on the thin layer of back metal seed.

[0037] Preferably, metal grid electrodes are formed on a thin layer of metal seeds using screen printing.

[0038] More preferably, in the screen printing method, the metal paste is cured at a temperature not exceeding 120°C to form metal grid electrodes.

[0039] Preferably, the deposition method of the front metal seed thin layer / back metal seed thin layer is magnetron sputtering, thermal evaporation or atomic layer deposition.

[0040] More preferably, the process parameters of the magnetron sputtering include: sputtering vacuum degree of 0.2-0.6 Pa, argon flow rate of 200-350 sccm, sputtering power density of 2-3 kW / M, and silicon substrate temperature controlled within 60-80°C.

[0041] The sputtering power density of this invention is controlled at 2-3 kW / M to prevent excessive power from causing sputtering damage to the substrate. The temperature of the silicon wafer substrate is controlled within 60-80°C. A certain temperature can increase the adhesion between the metal seed layer and the transparent conductive film, but it is necessary to prevent excessive temperature from causing thermal damage to the perovskite material.

[0042] More preferably, the magnetron sputtering process specifically includes: placing the battery cell on a carrier disk with a grid line mask pattern, and feeding the battery cell into the magnetron sputtering equipment by means of carrier disk transfer to deposit a thin metal seed layer with a grid line pattern.

[0043] The beneficial effects of this invention are: This invention provides a crystalline silicon perovskite tandem solar cell. The invention introduces a metal seed layer with a grid pattern between the transparent conductive film and the grid electrodes of the tandem solar cell. This significantly reduces the contact resistance between the grid electrodes and the transparent conductive film, lowering it to 5% compared to a cell without the metal seed layer. Furthermore, it enhances the adhesion between the grid lines and the transparent conductive film, allowing for thorough bonding of the ultra-low temperature curing slurry to the transparent conductive film. In summary, this invention, by introducing a metal seed layer with a grid pattern, achieves the goal of simultaneously improving the conversion efficiency and stability of the crystalline silicon / perovskite tandem solar cell. Attached Figure Description

[0044] Figure 1 This is a structural diagram of the crystalline silicon perovskite tandem solar cell of Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the grid pattern mask used to prepare a thin layer of metal seeds; Figure 3 This is a schematic diagram showing the positions of the mask, carrier disk, and solar cell used in the preparation of the metal seed thin layer; Figure 4 This is a structural diagram of the crystalline silicon perovskite tandem solar cell of Embodiment 2 of the present invention. Detailed Implementation

[0045] The present invention will be further described in detail below through specific embodiments. Unless otherwise specified, the raw materials used in the following embodiments can be obtained from conventional commercial channels or prepared and isolated through simple synthesis; unless otherwise specified, the processes employed are conventional processes in the art.

[0046] Example 1 This embodiment provides a crystalline silicon perovskite tandem solar cell, the structure of which comprises, in sequence, a front metal grid electrode, a front metal seed layer, a front transparent conductive film, an intermediate protective layer, an electron transport layer, a perovskite absorber layer, a hole transport layer, a composite layer, intrinsic amorphous silicon and phosphorus-doped amorphous silicon thin layers, a silicon substrate, intrinsic amorphous silicon and boron-doped amorphous silicon thin layers, a back transparent conductive film, a back metal seed layer, and a back metal grid electrode. Specifically, as shown below... Figure 1 As shown.

[0047] The fabrication methods for each layer of the crystalline silicon perovskite tandem solar cell are as follows: 1. The front metal grid line electrode is generally formed by screen printing pure silver paste or silver-coated copper paste and curing it at a temperature not exceeding 120℃. The grid line width is 20-30μm and the aspect ratio is above 0.3.

[0048] 2. The material of the front metal seed layer is pure copper (purity 99.99%) or copper-nickel alloy (copper wt%: nickel wt% = 99:1). Correspondingly, magnetron sputtering, thermal evaporation or ALD can be used to deposit the metal seed layer at room temperature through a mask to form a metal seed layer with a gate line pattern and a thickness of 10-100nm. The width of this layer is called the bottom layer width. The bottom layer width is smaller than the width of the metal gate line electrode, and the contact resistance between it and the front transparent conductive film is 0.35Ω.

[0049] The specific fabrication process of magnetron sputtering is as follows: Figure 2 This is a schematic diagram of the grid pattern mask used to prepare a thin layer of metal seeds; Figure 3 This is a schematic diagram showing the positions of the mask, carrier disk, and solar cell used for preparing the metal seed thin layer. The solar cell is placed on a carrier disk with a grid pattern mask. The shape of the grid pattern mask is the same as the solar cell's grid pattern. The mask opening width is 40 μm, the spacing between adjacent openings is 1.5 mm, and the height of the mask relative to the solar cell is 0.5 mm. The solar cell is fed into a magnetron sputtering apparatus via the carrier disk for deposition of the metal seed thin layer with the grid pattern. The preferred sputtering parameters are: sputtering vacuum degree 0.3 Pa, silicon wafer temperature controlled at 60-80℃, and sputtering power density 2 kW / M. Ionized argon ions bombard a copper target or a copper-nickel alloy target to deposit a copper or copper-nickel alloy seed thin layer with a grid pattern of approximately 100 nm thickness on the solar cell.

[0050] 3. The front transparent conductive film layer can be IZO with a thickness of 40-60nm. It is prepared by deposition at room temperature through magnetron sputtering, thermal evaporation or ALD. Generally, the sheet resistance is <150 Ω and the light transmittance is >90%.

[0051] 4. The intermediate protective layer can be SnO2, with a thickness of 5-25nm, and is prepared by thermal evaporation, PRD or ALD at low temperature.

[0052] 5. The electron transport layer can be C60 with a thickness of 10-30nm, and can be prepared by magnetron sputtering, thermal evaporation, inkjet printing or doctor blade coating.

[0053] 6. The perovskite absorber layer has a material structure of ABX3, selected from the following components: Cs 0.05 (FA 0.85 MA 0.15 ) 0.95 Pb(I 0.85 Br 0.15 3. The film thickness is 500-800nm, and it is prepared by methods such as screen printing, slot coating, inkjet printing, doctor blade coating or chemical vapor deposition.

[0054] 7. The hole transport layer can be NiO. X With a thickness of 5-15 nm, it is prepared by methods such as magnetron sputtering, thermal evaporation, inkjet printing or doctor blade coating.

[0055] 8. The composite layer can be ITO with a thickness of 10-30nm, which is prepared by magnetron sputtering or RPD at a temperature of about 200℃. Generally, the sheet resistance is <150Ω and the transmittance is >90%.

[0056] 9. Intrinsic amorphous silicon and phosphorus-doped amorphous silicon thin films, with a thickness of 7-20 nm, are currently mainly prepared by PECVD or hot-wire CVD deposition.

[0057] 10. The silicon substrate has a thickness of 50-150μm, a minority carrier lifetime of ≥800μs, and a resistivity of 0.3-2.1Ω·cm. Both sides of the substrate need to be textured, with the textured surface size of the silicon surface adjacent to the front side being 0.5-0.8μm and the textured surface size of the silicon surface adjacent to the back side being 1-3μm.

[0058] 11. Intrinsic amorphous silicon and boron-doped amorphous silicon thin films, with a thickness of 10-30 nm, are currently mainly prepared by PECVD or hot-wire CVD deposition.

[0059] 12. The transparent conductive film layer on the back can be one or two of ITO, IZO, IWO, and AZO stacked together, with a thickness of 80-120nm. It is prepared by magnetron sputtering or RPD at a temperature of about 200℃, and generally has a sheet resistance of <40Ω and a light transmittance of >88%.

[0060] 13. The material of the back metal seed layer is pure copper (purity 99.99%) or copper-nickel alloy (copper wt%: nickel wt% = 99:1). Correspondingly, magnetron sputtering, thermal evaporation or ALD can be used to deposit the metal seed layer with a gate pattern at room temperature through a mask method to form a metal seed layer with a thickness of 10-100nm. The preparation method is the same as step 2 above. The width of this thin layer is called the bottom layer width. The bottom layer width is smaller than the width of the metal gate electrode. The contact resistance between the bottom layer and the back transparent conductive film is 0.35Ω.

[0061] 14. The back metal grid line electrodes are generally formed by screen printing pure silver paste or silver-coated copper paste and curing at a temperature not exceeding 120°C. The grid line width is 30-50um and the aspect ratio is above 0.3.

[0062] Example 2 This embodiment provides a crystalline silicon perovskite tandem solar cell, the structure of which comprises, in sequence, a front metal grid electrode, a front metal seed layer, a front transparent conductive film, an intermediate protective layer, an electron transport layer, a perovskite absorber layer, a hole transport layer, a composite layer, intrinsic amorphous silicon and phosphorus-doped amorphous silicon thin layers, a silicon substrate, intrinsic amorphous silicon and boron-doped amorphous silicon thin layers, a back transparent conductive film, a back metal seed layer, and a back metal grid electrode. Specifically, as shown below... Figure 4 As shown.

[0063] The fabrication methods for each layer of the crystalline silicon perovskite tandem solar cell are basically the same as in Example 1, except that: 2. The material of the front metal seed layer is pure copper (purity 99.99%) or copper-nickel alloy (copper wt%: nickel wt% = 99:1). Correspondingly, magnetron sputtering, thermal evaporation or ALD can be used to deposit the metal seed layer at room temperature through a mask to form a metal seed layer with a gate pattern and a thickness of 10-100nm. The width of this layer is called the bottom layer width, which is equal to the width of the metal gate electrode. The contact resistance between the bottom layer and the front transparent conductive film is 0.15Ω. 13. The bottom layer width of the metal seed layer on the back is equal to the width of the metal grid electrode, and the contact resistance between it and the transparent conductive film on the back is 0.15Ω.

[0064] Comparative Example 1 This comparative example provides a crystalline silicon perovskite tandem solar cell, the structure of which consists of, sequentially arranged, a front metal grid electrode, a front transparent conductive film layer, an intermediate protective layer, an electron transport layer, a perovskite absorption layer, a hole transport layer, a composite layer, an intrinsic amorphous silicon and phosphorus-doped amorphous silicon thin layer, a silicon substrate, an intrinsic amorphous silicon and boron-doped amorphous silicon thin layer, a back transparent conductive film layer, and a back metal grid electrode.

[0065] This comparative example does not include a thin layer of metal seeds.

[0066] Application testing The crystalline silicon perovskite tandem solar cells prepared in Examples 1-2 and Comparative Example 1 were subjected to relevant performance tests. The specific results are shown in Table 1. Among them, the short-circuit current density (Jsc), open-circuit voltage (Voc), conversion efficiency (Eff), fill factor (FF), and contact resistance were all measured under standard test conditions (AM1.5, 25℃, 1000W / m). 2 The result was measured below.

[0067] Table 1

[0068] As shown in Table 1, the Jsc, Voc, Eff and FF of the crystalline silicon perovskite tandem solar cells in Examples 1-2 are all better than those in Comparative Example 1. From the perspective of contact resistance, introducing a thin layer of metal seed with grid line pattern can significantly reduce the contact resistance between the grid line electrode and the transparent conductive film.

[0069] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A crystalline silicon perovskite tandem solar cell, characterized in that, It includes perovskite solar cells, crystalline silicon solar cells, and a composite layer; the composite layer is used to connect the top cell and the bottom cell in series. The perovskite solar cell includes a front metal grid electrode, a front metal seed layer, and a front transparent conductive film layer arranged sequentially; the crystalline silicon solar cell includes a back metal grid electrode, a back metal seed layer, and a back transparent conductive film layer arranged sequentially. The front and back metal seed layers are seed grid structures; the front and back metal grid electrodes are electrode grid structures; the grid patterns of the seed grid structure and the electrode grid structure are the same.

2. The crystalline silicon perovskite tandem solar cell according to claim 1, characterized in that, The grid line width of the electrode grid line structure is greater than or equal to the grid line width of the seed grid line structure; And / or, the thickness of the seed grid structure is 70-150 nm; the width of the seed grid structure is 20-50 μm; and the spacing between adjacent grid lines of the seed grid structure is 1-2 mm. And / or, the thickness of the electrode grid structure is 5-20 μm; the width of the electrode grid structure is 20-50 μm; and the spacing between adjacent grid lines of the electrode grid structure is 1-2 mm.

3. The crystalline silicon perovskite tandem solar cell according to claim 1, characterized in that, The front and back metal seed layers are made of copper or a copper-nickel alloy.

4. The crystalline silicon perovskite tandem solar cell according to claim 1, characterized in that, The raw materials for preparing the front metal grid electrode and the back metal grid electrode include one or more combinations of Ag and Cu.

5. The crystalline silicon perovskite tandem solar cell according to claim 1, characterized in that, The front transparent conductive film layer and the back transparent conductive film layer are selected from one or two of ITO, IZO, IWO, and AZO.

6. The crystalline silicon perovskite tandem solar cell according to claim 1, characterized in that, The composite layer is selected from one or two of ITO, IZO, IWO, and AZO.

7. The crystalline silicon perovskite tandem solar cell according to claim 1, characterized in that, The crystalline silicon perovskite tandem solar cell includes, in sequence, a front metal grid electrode, a front metal seed layer, a front transparent conductive film, an intermediate protective layer, an electron transport layer, a perovskite absorption layer, a hole transport layer, a composite layer, intrinsic amorphous silicon and phosphorus-doped amorphous silicon thin layers, a silicon substrate, intrinsic amorphous silicon and boron-doped amorphous silicon thin layers, a back transparent conductive film, a back metal seed layer, and a back metal grid electrode.

8. The method for preparing a crystalline silicon perovskite tandem solar cell according to any one of claims 1-7, characterized in that, Includes the following steps: A patterned mask is fixed on the front transparent conductive film layer, a front metal seed thin layer with a seed grid structure is deposited, and then a front metal grid electrode is formed on the front metal seed thin layer. A patterned mask is fixed on a transparent conductive film layer on the back side, a thin layer of back metal seed with a seed grid structure is deposited, and then a back metal grid electrode is formed on the thin layer of back metal seed.

9. The method for preparing a crystalline silicon perovskite tandem solar cell according to claim 8, characterized in that, Metal grid electrodes are formed on a thin layer of metal seeds using screen printing.

10. The method for preparing a crystalline silicon perovskite tandem solar cell according to claim 8, characterized in that, The deposition method for the front / back metal seed thin layer is magnetron sputtering, thermal evaporation or atomic layer deposition. Preferably, the process parameters of the magnetron sputtering include: sputtering vacuum degree of 0.2-0.6 Pa, argon flow rate of 200-350 sccm, sputtering power density of 2-3 kW / M, to prevent excessive power from causing sputtering damage to the substrate, and the temperature of the silicon wafer substrate is controlled below 100°C.

Images