Data transmission methods, request systems, response systems, electronic devices, and media

Abstract

This disclosure provides a data transmission method, a request system, a response system, an electronic device, and a medium. The method is applied to a requesting device, which includes a first computing core, a first memory, and a first physical network port. The data transmission method includes: in response to receiving a data transmission instruction from a requesting host, the first computing core reads target data from the first memory and sends the target data to a data transmission link via the first physical network port, wherein the data transmission link is used for data transmission between the requesting device and the responding device. This method avoids the additional control path latency and bandwidth waste caused by the complex logic of traditional operating models, achieving not only end-to-end lossless transmission but also significantly reducing transmission latency, increasing effective bandwidth, and simplifying hardware design.

Description

Technical Field

[0001] Embodiments of this disclosure relate to the field of computer technology, and more specifically to a data transmission method, a request system, a response system, an electronic device, and a medium. Background Technology

[0002] Distributed computing is a computing paradigm that breaks down large-scale computational tasks into multiple subtasks and distributes them collaboratively among multiple computing nodes. Through parallel execution and resource sharing, distributed computing can significantly improve the overall computing power of a system and is widely used in high-performance computing scenarios such as artificial intelligence training and big data analysis. A typical computing node usually consists of one or more hosts and multiple devices, with each node collaborating through a high-speed interconnect network.

[0003] In distributed computing scenarios, efficient communication mechanisms are crucial for system performance. On one hand, the host needs to issue instructions to devices, thus communication between the host and devices requires low latency and high reliability. On the other hand, as model size and computational complexity continue to increase, multiple devices often need to frequently exchange intermediate results during parallel execution. This means that there is also a demand for large-scale, high-frequency, and high-bandwidth data exchange between devices. Therefore, how to achieve efficient data transmission between devices has become a key technical challenge. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a data transmission method applied to a requesting device, wherein the requesting device includes a first computing core, a first memory, and a first physical network port. The data transmission method includes: in response to receiving a data transmission instruction from a requesting host, the first computing core reads target data from the first memory and sends the target data to a data transmission link via the first physical network port, wherein the data transmission link is used for data transmission between the requesting device and the responding device.

[0005] In the data transmission method provided in at least one embodiment of this disclosure, the first physical network port includes an Ethernet port.

[0006] In at least one embodiment of the data transmission method provided in this disclosure, the step of reading target data from the first memory and sending the target data to the data transmission link via the first physical network port in response to receiving a data transmission instruction from the requesting host includes: in response to receiving the data transmission instruction from the requesting host, the first computing core executes the data transmission instruction and reads the target data from the first memory; the first computing core generates a target request carrying the target data and sends the target request to the first physical network port; the first physical network port generates a message conforming to a preset format based on the target request and sends the message to the data transmission link.

[0007] In at least one embodiment of the data transmission method provided in this disclosure, the first computing core, the first memory, and the first physical network port are connected via a first on-chip network. The first computing core executes the data transmission instruction to read the target data from the first memory, including: the first computing core executes the data transmission instruction to read the target data from the first memory via the first on-chip network. The first computing core generates a target request carrying the target data and sends the target request to the first physical network port, including: the first computing core generates the target request and sends the target request to the first physical network port via the first on-chip network.

[0008] In at least one embodiment of the data transmission method provided in this disclosure, the first physical network port generates a message conforming to a preset format based on the target request and sends the message to the data transmission link, including: the first physical network port parses and encapsulates the target request into a message conforming to a preset format, and sends the message to the data transmission link to transmit it to the second physical network port of the responding terminal device.

[0009] In at least one embodiment of the data transmission method provided in this disclosure, a backup of the message is temporarily stored in the first physical network port. The data transmission method further includes: triggering retransmission of the message in response to receiving a negative acknowledgment signal, wherein the negative acknowledgment signal indicates that the responding end device has received erroneous data; and triggering retransmission of the message in response to not receiving an acknowledgment signal within a preset time, wherein the acknowledgment signal indicates that the responding end device has received correct data.

[0010] In the data transmission method provided in at least one embodiment of this disclosure, the message transmitted through the first physical network port conforms to a preset format. The preset format specifies that the message header includes at least one of the following fields: a format field, a type field, a requester identifier field, a responseer identifier field, a message length field, a tag field, or a variable field. The format field is used to indicate the operation type, the type field is used to indicate the subtype under the operation type, the requester identifier field is used to indicate the number of the requesting device, the responseer identifier field is used to indicate the number of the response device, the message length field is used to indicate the length of the message, the tag field is used to indicate the current timestamp, and the function of the variable field is determined based on the format field.

[0011] In the data transmission method provided in at least one embodiment of this disclosure, the operation type includes: memory write operation, atomic operation, memory read operation, completion operation, or acknowledgment operation.

[0012] In the data transmission method provided in at least one embodiment of this disclosure, when the format field indicates that the operation type is the memory write operation or the atomic operation, the variable field is used to indicate the byte enable setting of the target data.

[0013] In the data transmission method provided in at least one embodiment of this disclosure, when the format field indicates that the operation type is the completed operation, the variable field is used to indicate the completion status of the responding terminal device.

[0014] In the data transmission method provided in at least one embodiment of this disclosure, the preset format further specifies that the message header includes at least one of the following fields: packet sequence number field, acknowledgment request field, and padding field, wherein the packet sequence number field is used to indicate the sequence number of the data packet corresponding to the message, the acknowledgment request field is used to indicate whether the responding end needs to reply with an acknowledgment signal, and the padding field is used to achieve byte alignment in the message header.

[0015] At least one embodiment of this disclosure provides a data transmission method applied to a response end device, wherein the response end device includes a second computing core and a second physical network port, the data transmission method includes: in response to receiving a message from a data transmission link and the message passing verification, the second physical network port obtains a target request carrying target data based on the message, and provides it to the second computing core for processing, wherein the data transmission link is used for data transmission between the request end device and the response end device.

[0016] In at least one embodiment of the data transmission method provided in this disclosure, the step of receiving a message from a data transmission link and the message passing verification, and the second physical network port obtaining a target request carrying target data based on the message and providing it to the second computing core for processing, includes: in response to receiving a message from the data transmission link and the message passing verification, the second physical network port parses the message and converts it into the target request; the second physical network port sends the target request to the second computing core.

[0017] In at least one embodiment of the data transmission method provided in this disclosure, the responding terminal device further includes a second memory, and the data transmission method further includes: the second computing core writing the target data carried by the target request into the second memory.

[0018] In at least one embodiment of the data transmission method provided in this disclosure, the second computing core, the second memory, and the second physical network port are connected via a second on-chip network. The second physical network port sending the target request to the second computing core includes: the second physical network port sending the target request to the second computing core via the second on-chip network. The second computing core writing the target data carried by the target request into the second memory includes: the second computing core writing the target data carried by the target request into the second memory via the second on-chip network.

[0019] In at least one embodiment of the data transmission method provided in this disclosure, the method further includes: verifying the message based on at least one of the sequence number of the data packet corresponding to the message, the number of the responding end device, and the length of the message; returning an acknowledgment signal to the requesting end device in response to the message passing the verification; and returning a negative acknowledgment signal to the requesting end device in response to the message failing the verification.

[0020] At least one embodiment of this disclosure provides a request system, including a requesting device and a requesting host. The requesting device includes a first computing core, a first memory, and a first physical network port. The first computing core is configured to: in response to receiving a data transmission instruction from the requesting host, read target data from the first memory and send the target data to a data transmission link via the first physical network port. The data transmission link is used for data transmission between the requesting device and the responding device.

[0021] At least one embodiment of this disclosure provides a response system including a response end device. The response end device includes a second computing core and a second physical network port. The second physical network port is configured to: in response to receiving a message from a data transmission link and the message passing verification, obtain a target request carrying target data based on the message and provide it to the second computing core for processing. The data transmission link is used for data transmission between the request end device and the response end device.

[0022] At least one embodiment of this disclosure provides an electronic device, including: at least one processor; at least one memory including one or more computer program modules; wherein the one or more computer program modules are stored in the at least one memory and configured to be executed by the at least one processor, and the one or more computer program modules are used to implement the data transmission method provided in the at least one embodiment above.

[0023] At least one embodiment of this disclosure provides a non-transitory computer-readable storage medium storing computer-readable instructions thereon, wherein the computer-readable instructions, when executed by at least one processor, perform the data transmission method provided in the at least one embodiment described above.

[0024] This disclosure provides a data transmission method, request system, response system, electronic device, and non-transitory computer-readable storage medium in at least one embodiment, proposing an end-to-end reliable transmission mechanism. First, this method offloads the data transmission control path from the host (e.g., CPU) to the device (e.g., GPU), enabling direct communication between the computing core and the physical network port. Compared to the multi-step interaction dominated by the CPU in the traditional send-receive operation model, it eliminates the latency traversing the kernel, driver software, and PCIe link, reducing transmission control latency from microseconds to hundreds of nanoseconds. Second, this method reduces multiple interactions between the host and device, freeing up internal chip bus bandwidth, allowing the high throughput capacity of the physical network port to be fully utilized, improving effective bandwidth utilization, and thus significantly improving transmission efficiency and avoiding link congestion. Finally, this method simplifies hardware design, eliminating the complex hardware logic for WQE and CQE queue management, eliminating the need to allocate large amounts of on-chip cache, and reducing hardware implementation complexity, chip area, and power consumption. By avoiding the additional control path delays and bandwidth waste caused by the complex logic of traditional operating models, this method not only achieves end-to-end lossless transmission, but also significantly reduces transmission latency, increases effective bandwidth, and simplifies hardware design.

[0025] Furthermore, by adopting the "send+ACK" interaction process and implementing an end-to-end retransmission mechanism with memory semantics through physical network ports, this method can not only reduce transmission latency, increase effective bandwidth, and simplify hardware design, but also improve the reliability of data transmission.

[0026] Furthermore, by designing a simplified message header format, this method reduces protocol overhead by more than 50% compared to the 28-byte header (BTH+RETH) of RDMA Write messages, thereby further improving effective bandwidth utilization. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0028] Figure 1A This is a schematic block diagram illustrating the interconnection of multiple devices based on Ethernet.

[0029] Figure 1B This is a schematic diagram of an RDMA communication process.

[0030] Figure 1C This is a schematic diagram of a send-receive operation based on the IB protocol.

[0031] Figure 2 This is a flowchart illustrating a data transmission method provided in at least one embodiment of the present disclosure.

[0032] Figure 3 A flowchart illustrating another data transmission method provided in at least one embodiment of this disclosure.

[0033] Figure 4A This is a schematic diagram of another data transmission method provided in at least one embodiment of the present disclosure.

[0034] Figure 4B This is a schematic diagram of a data retransmission method provided in at least one embodiment of the present disclosure.

[0035] Figure 4C This is a schematic diagram of another data retransmission method provided in at least one embodiment of the present disclosure.

[0036] Figure 5A This is a schematic block diagram of a request system provided for at least one embodiment of the present disclosure.

[0037] Figure 5B This is a schematic block diagram of a response system provided for at least one embodiment of the present disclosure.

[0038] Figure 6A This is a schematic block diagram of an apparatus provided for at least one embodiment of the present disclosure.

[0039] Figure 6B This is a schematic block diagram of an Ethernet port provided for at least one embodiment of the present disclosure.

[0040] Figure 7 This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0041] Figure 8 This is a schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure.

[0042] Figure 9 This is a schematic block diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0044] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0045] The present disclosure will now be described through several specific embodiments. To keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of known functions and known components may be omitted. When any component of an embodiment of the present disclosure appears in more than one drawing, the component is represented by the same or similar reference numerals in each drawing.

[0046] In distributed computing scenarios, computing nodes are the basic building blocks of the system, enabling efficient parallel processing of large-scale tasks through collaboration and communication between nodes. Each computing node may include one or more hosts, and each host connects to one or more devices. The hosts and devices collaborate to complete computing tasks. Within a computing node, data transmission between hosts and devices can be achieved in various ways. Devices (also known as "slave devices") can directly connect to the host via hardware interfaces (e.g., through a PCI Express, PCIe bus) for low-latency data transmission; or they can collaborate with the host via a network in a software-defined manner (such as virtualization technology).

[0047] For example, the host described above may include a central processing unit (CPU), and the device may include a graphics processing unit (GPU), a general-purpose graphics processing unit (GPGPU), a tensor processing unit (TPU), a deep learning processing unit (DPU), an accelerated processing unit (APU), a neural network processing unit (NPU), an application-specific integrated circuit (ASIC), or a field-programmable gate array (FPGA), etc.

[0048] It is worth noting that in distributed computing scenarios, not only is efficient communication required between hosts and devices, but there is also a need for frequent data exchange between devices. Therefore, efficient collaboration between devices relies on high-performance data transmission mechanisms, and cross-device data interaction can be achieved through various technical paths.

[0049] Ethernet is a widely used data transmission technology in local area network (LAN) environments and is one of the most common and widely deployed LAN technologies. It supports efficient communication between multiple devices within a local area and primarily follows the IEEE 802.3 standard. With the continuous growth in computing power demands for large-scale model training, data centers need to achieve interconnection of larger-scale devices (GPUs as an example below). Ethernet offers advantages such as strong scalability, high bandwidth, and ease of management and maintenance. First, the Ethernet protocol supports large-scale network deployment; the number of nodes is not limited by the protocol, and the physical distance between nodes is large, making it easy to build computing centers. Second, the effective data rate of a single Ethernet channel has reached 100Gbps. By integrating multiple 112G SerDes channels based on the IEEE 802.3ck standard on GPUs, higher communication bandwidth can be achieved through aggregation, fully meeting the high-throughput interconnection requirements between multiple GPUs. Finally, based on standard Ethernet technology, existing network management tools can be used for monitoring and maintenance of the interconnected network. This makes the configuration and fault diagnosis of computing centers simpler and more efficient.

[0050] Figure 1A This is a schematic block diagram illustrating the interconnection of multiple devices based on Ethernet.

[0051] like Figure 1A As shown, a multi-device interconnection (multi-GPU interconnection) system can be built based on Ethernet technology: each GPU is equipped with a network port, which is connected to an Ethernet switch via an Ethernet link. Taking GPU_0 of compute node 0 accessing other GPUs as an example, it first sends the encapsulated Ethernet packet to the Ethernet switch via Link0; the Ethernet switch determines the destination port among ports P1 to P7 based on the destination address field in the packet header.

[0052] However, in high-concurrency communication scenarios, Ethernet switches may face congestion problems. For example... Figure 1A As shown, when multiple source GPUs simultaneously send data packets to the same target GPU, if the unidirectional bandwidth of each port (P0~P7) of the Ethernet switch is 400 Gbps, the "many-to-one" transmission mode is highly susceptible to congestion within the Ethernet switch. This congestion not only significantly reduces data transmission efficiency but can also lead to packet loss within the Ethernet switch, thus affecting the stability of distributed computing. For example, when the GPU needs to communicate with up to 1024 GPUs via an Ethernet switch, the interconnection topology becomes extremely complex, significantly increasing the probability of congestion and packet loss within the Ethernet switch.

[0053] Some data transmission schemes are based on Ethernet technology. The following section will use Transmission Control Protocol / Internet Protocol (TCP / IP) and Remote Direct Memory Access (RDMA) as examples.

[0054] TCP / IP is a widely used network protocol for transmitting data over computer networks. TCP is a connection-oriented, reliable, byte-stream-based transport layer communication protocol. Before data transmission, TCP establishes an end-to-end connection through a "three-way handshake" process, and supports a one-to-one message transmission mode after the connection is established. After data transmission is completed, the connection is securely disconnected through a "four-way handshake" process, ensuring the orderly establishment and release of the communication link.

[0055] However, the TCP / IP protocol stack is implemented in the operating system kernel. During data transmission, it needs to traverse the kernel protocol stack multiple times, resulting in high latency. The actual throughput performance is usually no more than 10 Gbps, which is difficult to meet the needs of high bandwidth and low latency scenarios (such as large-scale GPU interconnects).

[0056] In contrast, RDMA is a highly efficient network communication technology that allows data to be transferred directly between the memory of two computers without the intervention of the operating system, thus achieving low-latency and high-throughput communication. With RDMA, applications can initiate data transfer directly in user space, avoiding the multiple data copies between user space and kernel space required in traditional methods; simultaneously, the protocol processing at the transport and network layers is handled by hardware such as smart NICs, reducing CPU overhead.

[0057] Compared to TCP / IP-based communication mechanisms, RDMA reduces the number of data copies between user space and kernel space, lowers latency, and improves network communication efficiency.

[0058] Figure 1B This is a schematic diagram of an RDMA communication process.

[0059] For example, such as Figure 1BAs shown, a local application running on the local CPU submits a remote memory operation request by calling the RDMA operation interface (i.e., VerbsAPI, such as ibv_post_send). After receiving the request, the RDMA network card (NIC) reads data directly from local memory without going through the operating system kernel, encapsulates it into an RDMA packet, and then transmits the RDMA packet to the remote node via the high-speed network. Upon receiving the packet, the remote RDMA NIC, based on the target memory address and remote key (R_Key) carried within, directly writes or reads data from the remote memory. After completing the operation, the remote RDMA NIC returns a completion response to the local RDMA NIC, indicating that the data has been successfully written / read. The local RDMA NIC then feeds back this operation status to the local application, signifying the completion of the RDMA operation.

[0060] Although RDMA has advantages over traditional TCP / IP communication such as zero copy, kernel bypass, and network card offloading, it still has performance bottlenecks in data transmission between devices: each data transfer still requires multiple interactions between the host (e.g., CPU) and the device (e.g., GPU), resulting in frequent communication between the host and the device, which not only increases latency but also limits overall throughput efficiency.

[0061] This issue is particularly prominent in the send-receive operation model defined in the InfiniBand (IB) protocol. InfiniBand is a high-speed interconnect technology designed for high-performance computing (HPC) and data centers, providing low-latency and high-bandwidth data transmission capabilities and natively supporting RDMA. The aforementioned send-receive operation model is a two-sided communication mechanism that not only requires the CPU to frequently intervene in the data transmission control path, but also requires the CPUs of both the sending and receiving ends to actively participate in the communication process.

[0062] Figure 1C This is a schematic diagram of a send-receive operation based on the IB protocol.

[0063] For example, such as Figure 1CAs shown, the sending host CPU0 and sending device GPU0 are located on the sending compute node, while the receiving host CPU1 and receiving device GPU1 are located on the receiving compute node. Both GPU0 and GPU1 include an RDMA module, queue pairs (QPs), memory, and a completion queue (CQ). QPs and CQs can be located in the device's memory or cache, for example. The RDMA module is integrated within the GPU, for example, as an RDMA Intellectual Property Core (IPCore), a hardware logic unit specifically designed to execute the RDMA protocol stack and implement RDMA communication functions. Each queue pair consists of a pair of work queues: a send queue (SQ) and a receive queue (RQ). The send queue stores work queue elements (WQEs) in the sending direction, such as SEND, RDMA WRITE, and RDMA READ operation requests; the receive queue stores WQEs in the receiving direction, such as RECV type operation requests, used for pre-registering the receive buffer. WQE is an operation descriptor submitted by an application on the CPU via the Verbs API, including the operation type (e.g., SEND / RECV / RDMA WRITE), data buffer address, and length. Memory can be, for example, High Bandwidth Memory (HBM) or other local storage media, used to store data to be sent or received. The completion queue is used to collect information about completed work requests. When an operation is completed, the corresponding Completion Queue Element (CQE) is placed in the completion queue. The application (CPU) can retrieve this information from the completion queue through polling or event-driven methods to confirm the status of the operation.

[0064] Figure 1C The complete process of data transfer between GPU0 and GPU1 via the Send & Receive operation model is shown, including steps S1 to S13.

[0065] Before data transmission begins, the sending and receiving ends complete connection initialization through software interaction (CPU-driven). Figure 1C (Not shown in the image), including operations such as QP creation, memory region registration, and address swapping, establishes the communication context between the sender and receiver, and completes the interconnection topology construction.

[0066] S1: CPU1 sends the RECV task description to the receive queue (RQ) of GPU1. For example, the RECV task description is written to the RQ in the form of WQE.

[0067] S2: CPU0 sends a SEND task description to the send queue (SQ) of GPU0. For example, the SEND task description is written to the SQ in the form of WQE.

[0068] S3: CPU0 triggers GPU0's RDMA module to read the SEND task description.

[0069] S4: GPU0's RDMA module reads the SEND task description from GPU0's SQ and parses the task parameters.

[0070] S5: According to the SEND task description, the RDMA module of GPU0 reads the data to be sent from the memory of GPU0 and encapsulates the data packet.

[0071] S6: The RDMA module of GPU0 transmits the encapsulated data packets to the RDMA module of GPU1 via the data transmission link. Here, the data transmission link refers to the physical link.

[0072] S7: After verifying the received data (e.g., integrity check), the RDMA module of GPU1 returns an acknowledgment (ACK) signal to the RDMA module of GPU0.

[0073] S8: GPU1's RDMA module reads the RECV task description from RQ and parses the task parameters.

[0074] S9: According to the RECV task description, the RDMA module of GPU1 writes data to the memory of GPU1.

[0075] S10: The RDMA module of GPU1 generates task completion information and stores it in the completion queue (CQ) of GPU1. For example, the task completion information is stored in the CQ in the form of CQE.

[0076] S11: CPU1 obtains task completion information from GPU1's CQ through polling or event-driven methods to confirm that the receiving operation has been completed.

[0077] S12: After receiving the ACK signal, the RDMA module of GPU0 generates task completion information and stores it in the CQ of GPU0.

[0078] S13: CPU0 obtains task completion information from GPU0's CQ through polling or event-driven methods to confirm that the sending operation has been completed.

[0079] As can be seen from the above process, although data plane transmission is autonomously handled by the RDMA hardware, there are still multiple explicit interactions between the host (CPU) and the device (GPU) throughout the process. These include the CPU actively sending task descriptions, the CPU triggering the RDMA module to read the task descriptions, and the CPU polling the CQ (Content Queuing). Furthermore, although not explicitly shown in the flowchart, the CPU typically needs to coordinate with the GPU computing cores to write the computation results to a designated memory area accessible by the RDMA module. Crucially, these multiple CPU-GPU interactions must be executed at both the sending and receiving ends, creating bilateral control overhead. Such frequent interactions not only introduce additional latency but also consume CPU resources, limiting the potential for high-throughput, low-latency data transmission between devices.

[0080] At least one embodiment of this disclosure provides a data transmission method applied to a requesting device, wherein the requesting device includes a first computing core, a first memory, and a first physical network port. The data transmission method includes: in response to receiving a data transmission instruction from a requesting host, the first computing core reads target data from the first memory and sends the target data to a data transmission link via the first physical network port, wherein the data transmission link is used for data transmission between the requesting device and the responding device.

[0081] At least one embodiment of this disclosure provides a data transmission method applied to a response end device, wherein the response end device includes a second computing core and a second physical network port. The data transmission method includes: in response to receiving a message from a data transmission link and the message passing verification, the second physical network port obtains a target request carrying target data based on the message, and provides it to the second computing core for processing, wherein the data transmission link is used for data transmission between the requesting end device and the response end device.

[0082] The data transmission method provided in at least one embodiment of this disclosure proposes an end-to-end reliable transmission mechanism. First, this method offloads the data transmission control path from the host (e.g., CPU) to the device (e.g., GPU), enabling direct communication between the computing core and the physical network port. Compared to the multi-step interaction dominated by the CPU in the traditional send-receive operation model, this eliminates the latency traversing the kernel, driver software, and PCIe link, reducing transmission control latency from microseconds to hundreds of nanoseconds. Second, this method reduces multiple interactions between the host and device, freeing up internal chip bus bandwidth and fully utilizing the high throughput capacity of the physical network port, improving effective bandwidth utilization and thus significantly improving transmission efficiency and avoiding link congestion. Finally, this method simplifies hardware design, eliminating the complex hardware logic for WQE and CQE queue management, eliminating the need to allocate large amounts of on-chip cache, and reducing hardware implementation complexity, chip area, and power consumption. By avoiding the additional control path latency and bandwidth waste caused by the complex logic of the traditional operation model, this method not only achieves end-to-end lossless transmission but also significantly reduces transmission latency, increases effective bandwidth, and simplifies hardware design.

[0083] Furthermore, by adopting the "send+ACK" interaction process and implementing an end-to-end retransmission mechanism with memory semantics through physical network ports, this method can not only reduce transmission latency, increase effective bandwidth, and simplify hardware design, but also improve the reliability of data transmission.

[0084] Furthermore, by designing a simplified message header format, this method reduces protocol overhead by more than 50% compared to the 28-byte header (BTH+RETH) of RDMA Write messages, thereby further improving effective bandwidth utilization.

[0085] In some examples, the requesting party refers to the party that actively initiates the data transmission request, while the responding party refers to the party that receives the data transmission request and responds accordingly. Their roles are dynamically determined based on the specific communication direction.

[0086] In some examples, the requesting or responding host may include a central processing unit. For example, the requesting or responding device may include a graphics processor, a general-purpose graphics processor, a tensor processor, a deep learning processor, an accelerator processor, a neural network processor, an application-specific integrated circuit, or a field-programmable gate array, etc., and this disclosure does not limit this.

[0087] Figure 2 The flowchart illustrates a data transmission method provided in at least one embodiment of this disclosure, applied to a requesting device, which includes a first computing core, a first memory, and a first physical network port.

[0088] For example, a computing core is a hardware execution unit within a device used to perform specific computational tasks; it is also called a computing kernel or core. The computing core supports parallel computing and can perform floating-point operations, integer operations, logical operations, etc., and is a component that enables the device's high-throughput computing capabilities. A computing core may include, for example, an Arithmetic Logic Unit (ALU) and a floating-point unit. Memory may include different storage levels within the device, such as shared memory, cache, or global memory. Global memory can be implemented as High Bandwidth Memory (HBM). A physical network port is a hardware interface for external communication of the device; for example, it is a high-speed interconnect port that can convert internal bus protocols (such as the Advanced Dextensible Interface (AXI) protocol) into network transmission formats. A physical network port may include, for example, an Ethernet port. Within the same device, the computing core, memory, and physical network ports can be interconnected through a Network-on-Chip (NoC) to achieve high-bandwidth, low-latency data exchange and collaborative operation.

[0089] In at least one embodiment of this disclosure, the first computing core, the first memory, and the first physical network port mentioned above, as well as the second computing core, the second memory, and the second physical network port mentioned below, are all applicable to the above definitions of computing core, memory, and physical network port.

[0090] For example, such as Figure 2 As shown, at least one embodiment of the present disclosure provides a data transmission method including step S201.

[0091] Step S201: In response to receiving a data transmission instruction from the requesting host, the first computing core reads the target data from the first memory and sends the target data to the data transmission link via the first physical network port, wherein the data transmission link is used for data transmission between the requesting device and the responding device.

[0092] In some examples, a data transmission link may include a Media Access Control (MAC) module, a serializer / deserializer (Serdes) circuit, and a switch. The MAC module is used for frame encapsulation and decapsulation, as well as link-layer control; the Serdes circuit is used for transmitting and receiving high-speed serial signals; and the switch has routing or switching functions to forward data packets in a multi-node topology. The MAC module and Serdes circuit can be integrated within the requesting and responding devices. The above is only one example of a data transmission link; in other examples, the data transmission link may employ different component combinations or topologies depending on the actual system architecture and performance requirements.

[0093] In some examples, the data transmission instructions sent by the requesting host may indicate information such as the operation type, source memory address, and destination memory address. The operation type may include, for example, a memory read operation, a memory write operation, an atomic operation, a send-receive operation, etc., and the embodiments of this disclosure are not limited to the examples described above. For instance, when the operation type is a memory write operation, the source memory address is the memory address on the requesting device's local memory where the data to be sent is stored, and the destination memory address is the memory address on the responding device used to receive the data; when the operation type is a memory read operation, the source memory address is the memory address on the responding device where the data to be read is stored, and the destination memory address is the memory address on the requesting device's local memory where the read-back data is stored.

[0094] In step S201, taking a memory write operation as an example, based on the received data transmission instruction, the first computing core can determine the address of the target data to be read in the first memory, and also determine the write address of the target data in the second memory of the responding device. Therefore, the requesting host directly sends a data transmission instruction to the first computing core, and the first computing core can directly send the target data read from the first memory to the network through the first physical network port, without requiring the requesting host to interact with the requesting device multiple times.

[0095] Specifically, taking the requesting host as the CPU and the requesting device as the GPU as an example, compared with the RDMA scheme introduced above, this scheme does not require the following CPU-GPU interaction operations: the CPU sends a task description to the GPU's send queue (e.g., WQE), the CPU triggers the RDMA module to read the task description, and the CPU obtains task completion information from the completion queue (e.g., CQE).

[0096] This solution offloads the data transmission control path from the host (e.g., CPU) to the device (e.g., GPU), enabling direct communication between the computing core and the physical network port. Compared to the CPU-driven multi-step interaction in RDMA solutions, it eliminates the latency traversing the kernel, driver software, and PCIe link, reducing transmission control latency from microseconds to hundreds of nanoseconds. Furthermore, this solution reduces multiple host-device interactions, freeing up internal chip bus bandwidth and fully utilizing the high throughput capacity of the physical network port, improving effective bandwidth utilization and significantly enhancing transmission efficiency while avoiding link congestion.

[0097] Furthermore, this solution avoids the use of redundant elements such as WQE and CQE while ensuring reliable transmission, thereby reducing latency and improving the overall system efficiency. At the same time, it eliminates the complex hardware logic for managing WQE and CQE queues, eliminating the need to allocate a large amount of on-chip cache, thus reducing hardware implementation complexity, chip area, and power consumption.

[0098] In the data transmission method provided in at least one embodiment of this disclosure, step S201 may include steps S211 to S213.

[0099] Step S211: In response to receiving a data transmission instruction from the requesting host, the first computing core executes the data transmission instruction and reads the target data from the first memory.

[0100] Step S212: The first computing core generates a target request carrying the target data and sends the target request to the first physical network port.

[0101] Step S213: The first physical network port generates a message conforming to a preset format based on the target request and sends the message to the data transmission link.

[0102] In step S211, since the data transfer instruction indicates the source address (e.g., carries a source address field), when the data transfer instruction is executed, the first computing core can read the target data from the first memory according to the source address.

[0103] In step S212, the first computing core can generate a target request, which may include target data and necessary control fields (such as operation type, destination memory address, etc.). In some examples, the AXI protocol can be used, and the corresponding target request is an AXI request.

[0104] One example of step S213 is that the first physical network port parses and encapsulates the target request into a message conforming to a preset format, and sends the message to the data transmission link for transmission to the second physical network port of the responding device. For example, the first physical network interface can encapsulate the target data and destination memory address in the message, and map other control information to the corresponding fields in the message header according to the preset format.

[0105] In the data transmission method provided in at least one embodiment of this disclosure, the first computing core, the first memory, and the first physical network port are connected within the requesting device via a first on-chip network.

[0106] Correspondingly, one example of step S211 may be: the first computing core executes a data transfer instruction to read target data from the first memory via the first on-chip network.

[0107] Correspondingly, one example of step S212 may be: the first computing core generates a target request and sends the target request to the first physical network port via the first on-chip network.

[0108] By introducing on-chip networking as the internal interconnection architecture of the device, and utilizing its packet switching, parallel transmission and distributed routing mechanisms, the performance bottleneck of traditional buses or cross switches under high loads can be effectively avoided, thereby further reducing transmission latency and alleviating congestion.

[0109] In at least one embodiment of the data transmission method provided in this disclosure, the first physical network port includes a buffer. The buffer can temporarily store backups of sent messages to support a retransmission mechanism, prevent permanent data loss, and ensure data transmission reliability. When an acknowledgment signal is received from the responding end device, the first physical network port can safely delete the backup from the buffer to release storage resources.

[0110] The data transmission method provided in at least one embodiment of this disclosure may further include step S202.

[0111] Step S202: In response to receiving a negative acknowledgment signal, trigger a retransmission of the message, wherein the negative acknowledgment signal indicates that the responding device has received erroneous data.

[0112] For example, after receiving a message, the responding device will verify the message. If the verification fails, it will return a negative acknowledgment signal (such as a NAK message) to the requesting device. When the first physical network interface receives the negative acknowledgment signal, it will retrieve a backup of the message from the buffer and resend the message.

[0113] The data transmission method provided in at least one embodiment of this disclosure may further include step S203.

[0114] Step S203: In response to the failure to receive an acknowledgment signal within a preset time, a retransmission of the message is triggered, wherein the acknowledgment signal indicates that the responding device has received the correct data.

[0115] For example, after receiving a message, the responding device verifies the message. If the verification passes, it returns an acknowledgment signal (e.g., an ACK message) to the requesting device. If the first physical network interface does not receive an acknowledgment signal for an extended period, it retrieves a backup of the message from the buffer and retransmits it. For example, the preset time can be 10 milliseconds, and the specific value can be configured according to network link latency, device processing capacity, and reliability requirements. This embodiment does not limit this.

[0116] The aforementioned dual end-to-end retransmission mechanism triggers retransmission promptly when no response is received for an extended period or when a verification error is detected. This ensures reliable data transmission under various abnormal network conditions (such as packet loss, out-of-order delivery, and duplicate packets), improves system stability and fault tolerance, and balances performance and resource utilization while guaranteeing data integrity.

[0117] In the data transmission method provided in at least one embodiment of this disclosure, the message transmitted through the first physical network port conforms to a preset format. The message may include a message header and a message payload. The message header typically carries control information to guide the transmission, parsing, and processing of the message; the message payload is typically used to carry the actual data to be transmitted.

[0118] The default format specifies that the message header may include at least one of the following fields: format field, type field, requester identifier field, responseer identifier field, message length field, tag field, or variable field.

[0119] For example, the format field is used to indicate the operation type. Operation types include: memory write operation, atomic operation (uninterruptible, indivisible memory access operation), memory read operation, completion operation, or acknowledgment operation. For example, the format field can use 3-bit encoding to support up to 8 different operation types. For example, 'b000' represents a memory write operation with data, 'b001' represents an atomic operation with data, 'b010' represents a memory read operation without data, 'b011' represents a completion operation without data, 'b100' represents a completion operation with data, and 'b101' represents an acknowledgment operation. It should be noted that the above correspondence between encoding and operation type is only illustrative. In practical applications, the encoding mapping of the format field can be customized according to requirements, including but not limited to: adjusting the encoding values ​​of each operation type, adding new operation types (such as memory read operations with data), or reducing unused operation types to adapt to different application scenarios and hardware designs.

[0120] For example, the type field is used to indicate the subtype under the operation type. For instance, the type field can use 5-bit encoding to support up to 32 different subtypes under each operation type. Subtypes can be customized according to actual needs. For example, when the operation type is a memory write operation, a corresponding subtype could be conditional write, where a comparison operation (such as comparing the current value in the target memory with the expected value) is performed before writing, and the write is only performed if the comparison result meets a specific condition. It should be noted that the above is only an example; different subtypes can be customized according to actual needs, and this disclosure does not impose any limitations on this.

[0121] By setting the above format and type fields, data streams can be distinguished when converting requests into messages, and different data streams correspond to different formats.

[0122] For example, the requester identifier field is used to indicate the number of the requesting device. For instance, the requester identifier field can be 16-bit encoded. In a multi-device interconnect topology, each device is assigned a globally unique device identifier (ID). When a responding device receives a request, it can identify the source of the request based on this requester identifier field and accurately return the response to the corresponding requesting device when necessary.

[0123] For example, the responder identifier field is used to indicate the number of the responder device. For instance, the responder identifier field can be 16-bit encoded. In a multi-device interconnect topology, each device is assigned a globally unique device identifier. When the responder device receives a message, it can compare the value of this field with its locally configured device ID. If they do not match, the message is discarded, thereby improving the robustness and security of communication. In some examples, communication between the requesting and responding devices can also be implemented based on a queue pair (QP) mechanism. In this case, the responder identifier field can also be used to indicate the destination queue pair (Destination QP) so that the message is correctly routed to the correct receiving queue.

[0124] For example, the message length field is used to indicate the length of the message. For example, the message length field can be encoded in 13 bits. For example, the requesting end uses this field to identify the message length, and the responding end uses this field to check the message length, thereby improving the robustness of data transmission.

[0125] For example, the tag field is used to indicate the current timestamp. The tag field can be encoded in 8 bits. The timestamp can be used to support the measurement of Round-Trip Time (RTT), thus providing input for RTT-based congestion control algorithms. By sensing changes in transmission delay along the network path in real time, the sender can dynamically adjust its transmission rate to avoid link overload, thereby improving network throughput and enhancing transmission stability.

[0126] For example, the functionality of a variable field is determined based on a format field. For example, a variable field can use 8-bit encoding.

[0127] When the format field indicates that the operation type is a memory write operation or an atomic operation, the variable field is used to indicate the byte enable settings of the target data. For example, the 8-bit variable field includes a 4-bit Last DWORD Byte Enables (Last DW BE) field and a 4-bit First DWORD Byte Enables (First DW BE) field. The First DWORD Byte Enables field indicates the validity of each byte in the 4 bytes of data corresponding to the start offset of the target data, and the Last DWORD Byte Enables field indicates the validity of each byte in the 4 bytes of data corresponding to the end offset of the target data. In the AXI protocol, the write data channel includes the write data wdata and the write byte enable wstrb signal. wstrb indicates whether each byte in wdata is valid, and each bit of wstrb corresponds to one byte of wdata. When the first physical network port encapsulates the AXI request into a message, it can map the wstrb field to this variable field to reduce additional message overhead. It should be noted that the above example only applies to scenarios where the valid bits in wstrb are consecutive, that is, all valid bits (e.g., 1) must appear consecutively without interruption. It is allowed to have several 0s at the beginning and end of wstrb, but it does not apply to non-consecutive valid bits such as 01011011 where 1s are interspersed with 0s.

[0128] Encapsulating the complete WSTRB information (e.g., 64 bits) directly into the Ethernet packet would significantly increase packet overhead and impact network transmission efficiency. The method described above uses only 8 bits to represent the critical information regarding byte validity, thus reducing the additional overhead of the packet header.

[0129] When the format field indicates that the operation type is a completion operation (complete operation with data or complete operation without data), the variable field is used to indicate the completion status of the responding device. For example, a 2-bit completion status field can be used to indicate the completion status of the responding device. Here, 00 indicates successful completion, 01 indicates the request was not supported, 10 indicates the requesting device should retry the request, and 11 indicates the responding device has terminated the transaction. The requesting device can associate this status code with the corresponding original request and notify upper-layer software (such as device drivers or applications) to execute appropriate error recovery, retry, or exception handling logic.

[0130] When the format field indicates that the operation type is other than other types, the variable field is filled with 0.

[0131] In the data transmission method provided in at least one embodiment of this disclosure, the preset format further specifies that the message header includes at least one of the following fields: packet sequence number field, acknowledgment response request field, and padding field.

[0132] For example, the packet sequence number field is used to indicate the sequence number of the data packet corresponding to the message. For example, the packet sequence number field can be encoded using 24 bits. The packet sequence number field is used at the receiving end to detect packet loss, out-of-order packets, or duplicate packets, thereby ensuring reliable transmission.

[0133] For example, the Acknowledgment Request field is used to indicate whether the responding end needs to send an acknowledgment signal (ACK). For example, the Acknowledgment Request field can be encoded using 1 bit. For example, a value of 1 indicates a request for ACK, and a value of 0 indicates no ACK is needed, suitable for communication scenarios with different reliability requirements.

[0134] For example, padding fields are used to achieve byte alignment in the message header to meet the data structure alignment requirements of hardware processing or protocol parsing. For example, the length of the padding field can be adjusted according to the configuration of the actual fields in the message header so that the total length of the message header is an integer multiple of a specified number of bytes (such as 4 bytes or 8 bytes).

[0135] It should be noted that in practical applications, the above fields can be selected and different field sizes can be set according to requirements, including but not limited to: adjusting the field size of each field, adding new fields, or reducing unused fields, in order to adapt to different application scenarios and hardware designs.

[0136] At least one embodiment of this disclosure provides a preset format for a message, specifying that the message consists of a 12-byte header and a payload. Compared to the RDMA Write message format, this preset format does not require an additional 16-byte Reliable Extended Transport Header (RETH), and compared to the 12-byte Base Transport Header (BTH) of the RDMA Write message format, the message header has no redundant fields; all bytes are defined as functional fields carrying valid control information. This scheme, through a simplified message header format, reduces protocol overhead by more than 50% compared to the 28-byte header (BTH+RETH) of the RDMAWrite message, not only improving effective bandwidth utilization but also still supporting end-to-end reliable transmission based on acknowledgment and retransmission mechanisms. Furthermore, since the switch does not parse or depend on the content of the aforementioned 12-byte message header, the design of this message header does not affect the normal forwarding behavior of the switch, nor does it require modification to the existing network infrastructure.

[0137] Table 1 below shows a message header format provided in at least one embodiment of this disclosure.

[0138] Table 1 Message Header Format

[0139]

[0140] Figure 3 This flowchart illustrates another data transmission method provided in at least one embodiment of the present disclosure, applied to a responding device, which includes a second computing core and a second physical network port. The second computing core and the second physical network port have already been described above in the description of the requesting device, and will not be repeated here.

[0141] For example, such as Figure 3 As shown, at least one embodiment of the present disclosure provides a data transmission method including step S301.

[0142] Step S301: In response to receiving a message from the data transmission link and the message passing the verification, the second physical network port obtains the target request carrying the target data based on the message and provides it to the second computing core for processing. The data transmission link is used for data transmission between the requesting end device and the responding end device.

[0143] For example, verification may include format verification (e.g., checking whether the received message conforms to the preset format mentioned above), sequence number verification, length consistency verification, identifier verification, etc. Different verification dimensions can be selected according to the actual application scenario, and this disclosure embodiment does not limit this.

[0144] In step S301, if the second physical network port receives a message sent by the requesting device through the data transmission link and the message passes verification, the message can be converted into a target request. When using the AXI protocol, the message is converted into an AXI request. The second computing core can process the target request and perform corresponding operations based on it.

[0145] In a data transmission method provided in at least one embodiment of this disclosure, an example of step S301 may include the following steps S311 to S312.

[0146] Step S311: In response to receiving a message from the data transmission link and the message passing the verification, the second physical network port parses the message and converts it into a target request.

[0147] Step S312: The second physical network port sends the target request to the second computing core.

[0148] In a data transmission method provided in at least one embodiment of this disclosure, the responding end device further includes a second memory, and the data transmission method may further include step S302.

[0149] Step S302: The second computing core writes the target data carried by the target request into the second memory.

[0150] In step S302, taking a memory write operation as an example, the second computing core can obtain the target data and the destination memory address from the target request, and write the target data into the second memory according to the destination memory address. In some examples, an address translation module can also be set in the responding device. The address translation module is used to convert the original virtual address in the target request into the physical address corresponding to the responding device.

[0151] In a data transmission method provided in at least one embodiment of this disclosure, a second computing core, a second memory, and a second physical network port are connected within the responding device via a second on-chip network.

[0152] Correspondingly, one example of step S302 can be: the second computing core writes the target data carried by the target request into the second memory via the second on-chip network.

[0153] Correspondingly, one example of step S312 may be: the second physical network port sends the target request to the second computing core via the second on-chip network.

[0154] By introducing on-chip networking as the internal interconnection architecture of the device, and utilizing its packet switching, parallel transmission and distributed routing mechanisms, the performance bottleneck of traditional buses or cross switches under high loads can be effectively avoided, thereby further reducing transmission latency and alleviating congestion.

[0155] The data transmission method provided in at least one embodiment of this disclosure may further include step S303.

[0156] Step S303: Verify the message based on at least one of the following: the sequence number of the data packet corresponding to the message, the number of the responding terminal device, and the length of the message.

[0157] For example, when a message is received at the second physical network port, the message header is first parsed to extract the packet sequence number field, the response end identifier field, and the message length field.

[0158] When verifying the sequence number of a data packet, the packet sequence number field can be compared with the expected sequence number. If they match, it means that the message has arrived in order, and the expected sequence number is incremented. If they do not match, it indicates that there is an out-of-order, lost, or duplicate packet situation. In this case, the message should be discarded and a negative acknowledgment signal should be returned.

[0159] When verifying the number of the responding device, the responding device identifier field can be compared with the pre-assigned unique device number of the responding device. If the two match, the message is determined to be a valid recipient of the responding device; if the two do not match, the message is considered to be data sent to other nodes, and the message should be discarded and a negative acknowledgment signal should be returned.

[0160] When verifying the length of a message, the message length field can be compared with the actual byte length of the message. If they match, it means that the message has not been truncated or padded during transmission, the message structure is complete, and the message header information is reliable. If they do not match, it means that the message may have been damaged during transmission. In this case, the message should be discarded and a negative acknowledgment signal should be returned.

[0161] It should be noted that the message fields to be verified can be flexibly selected based on the actual application scenario and reliability requirements. For example, in scenarios with high verification strength requirements, the message can be verified based on the sequence number of the corresponding data packet, the number of the responding device, and the length of the message. This multi-dimensional and multi-layered verification mechanism improves the robustness and security of the system. Conversely, in resource-constrained or real-time-critical scenarios, only some fields can be verified to achieve a balance between reliability and time overhead.

[0162] The data transmission method provided in at least one embodiment of this disclosure may further include step S304.

[0163] Step S304: In response to the message passing the verification, return an acknowledgment signal to the requesting device.

[0164] In step S304, after confirming that the message passes the verification, the second physical network interface returns an acknowledgment signal to the requesting device. For example, the second physical network interface sends an acknowledgment signal to the first physical network interface through the data transmission link.

[0165] The data transmission method provided in at least one embodiment of this disclosure may further include step S305.

[0166] Step S305: In response to the message failing verification, a negative acknowledgment signal is returned to the requesting device.

[0167] In step S305, after determining that the message has failed verification, the second physical network interface returns a negative acknowledgment signal to the requesting device. For example, the second physical network interface sends a negative acknowledgment signal to the first physical network interface through the data transmission link.

[0168] Figure 4A This is a schematic diagram illustrating another data transmission method provided in at least one embodiment of the present disclosure. The following description uses a configuration with the CPU as the host and the GPU as the device as an example.

[0169] For example, in Figure 4AIn this diagram, CPUA, GPUA, and GPUB represent the requesting host, requesting device, and responding device, respectively. GPUA includes a first physical network port, a first computing core, and first memory, all of which can be connected via a first on-chip network. GPUB includes a second physical network port, a second computing core, and second memory, all of which can be connected via a second on-chip network. GPUA and GPUB communicate with each other via a switch with routing capabilities. An example of the first and second physical network ports could be Ethernet ports, and the corresponding switch could be an Ethernet switch.

[0170] Figure 4A An example of data transfer between GPUA and GPUB according to at least one embodiment of the present disclosure is shown, including steps S41 to S47.

[0171] Before the data transmission begins, CPUA communicates with the responding host (which can be represented as CPUB). Figure 4A (Not shown in the image) The connection initialization is completed through software interaction (such as Socket-based communication), including the exchange of device identifiers (such as GPU ID), address exchange, etc., to establish the communication context between the requesting and responding ends and complete the construction of the interconnection topology.

[0172] S41: CPUA sends a data transfer instruction to the first computing core of GPUA.

[0173] S42: The first computing core executes a data transfer instruction to read target data from the first memory. For example, the first computing core reads the target data from the first memory via a first on-chip network.

[0174] S43: The first computing core generates a target request carrying the target data and sends the target request to the first physical network port. For example, the first computing core sends the target request to the first physical network port via the first on-chip network.

[0175] S44: The first physical network port parses the target request and encapsulates it into a message conforming to a preset format, and sends the message to the data transmission link. After being routed by the switch, it is transmitted to the second physical network port.

[0176] S45: The second physical network port receives and verifies the message, and returns an acknowledgment signal (e.g., ACK) to the first physical network port after passing the verification.

[0177] For example, if the verification fails, the second physical network interface can return a negative acknowledgment signal (e.g., NAK) to the first physical network port and discard the received message.

[0178] S46: If the message passes the verification, the second physical network port parses the message and converts it into a target request, and then sends the target request to the second computing core.

[0179] S47: The second computing core writes the target data carried by the target request into the second memory.

[0180] To address the data unreliability issue caused by the random packet loss strategy employed by switches during link congestion, the data transmission method provided in at least one embodiment of this disclosure proposes an end-to-end reliable transmission mechanism. Specifically, this method offloads the data transmission control path from the host (e.g., CPU) to the device (e.g., GPU), enabling direct communication between the computing core and the physical network port. This method employs a "send + ACK" interaction process, eliminating the latency traversing the kernel, driver software, and PCIe link compared to the multi-step interaction dominated by the CPU in the traditional send-receive operation model, reducing transmission control latency from microseconds to hundreds of nanoseconds. By reducing multiple interactions between the host and device, the internal bus bandwidth of the chip is freed up, allowing the high throughput capacity of the physical network port to be fully utilized, improving effective bandwidth utilization, and thus significantly improving transmission efficiency and avoiding link congestion. Furthermore, by designing a simplified message header format, compared to the 28-byte header (BTH+RETH) of RDMA Write messages, this method reduces protocol overhead by more than 50%, further improving effective bandwidth utilization. Meanwhile, this method implements an end-to-end retransmission mechanism with memory semantics through physical network ports, simplifying hardware design and eliminating the complex hardware logic for WQE and CQE queue management. It also eliminates the need to allocate large amounts of on-chip cache, reducing hardware implementation complexity, chip area, and power consumption. By avoiding the additional control path latency and bandwidth waste caused by the complex logic of traditional operating models, this method not only achieves end-to-end lossless transmission but also significantly reduces transmission latency, increases effective bandwidth, and simplifies hardware design.

[0181] Figure 4B This is a schematic diagram of a data retransmission method provided in at least one embodiment of the present disclosure. Figure 4B This is an example of steps S202 and S305 above.

[0182] For example, such as Figure 4B As shown, GPUA continuously sends two packets with sequence numbers PSN1 and PSN2 to GPUB. During transmission via the switch, the packet corresponding to PSN1 is lost. Since GPUB did not receive the expected packet corresponding to PSN1, it returns a negative acknowledgment signal (NAK1) to GPUA. Upon receiving this negative acknowledgment signal, GPUA immediately retransmits the packet corresponding to PSN1.

[0183] Figure 4C This is a schematic diagram of another data retransmission method provided in at least one embodiment of the present disclosure. Figure 4C This is an example of steps S203 and S304 above.

[0184] For example, such as Figure 4C As shown, GPUA continuously sends two packets with sequence numbers PSN1 and PSN2 to GPUB. During transmission via the switch, the packet corresponding to PSN2 is lost. Since GPUA does not receive the expected acknowledgment signal within a preset time, it determines that the packet corresponding to PSN2 has been lost and actively retransmits the packet corresponding to PSN2.

[0185] It should also be noted that the execution order of the various steps of the data transmission method in the various embodiments of this disclosure is not limited. Although the execution process of each step has been described in a specific order above, this does not constitute a limitation on the embodiments of this disclosure. The various steps in the data transmission method can be executed serially or in parallel, which can be determined according to actual needs.

[0186] For example, compared to the above description, the data transmission method provided in at least one embodiment of this disclosure may include more or fewer steps, and the embodiments of this disclosure do not limit this.

[0187] Figure 5A This is a schematic block diagram of a request system provided for at least one embodiment of the present disclosure.

[0188] For example, such as Figure 5A As shown, at least one embodiment of the present disclosure provides a request system 500 including a requesting device 520 and a requesting host 510. The requesting device 520 includes a first computing core 521, a first memory 522, and a first physical network port 523. The first computing core 521 is configured to: in response to receiving a data transmission instruction from the requesting host 510, read target data from the first memory 522 and send the target data to the data transmission link via the first physical network port 523. The data transmission link is used for data transmission between the requesting device 520 and the responding device.

[0189] For a description of the requesting host, requesting device, first computing core, first memory, first physical network port, and data transmission link, please refer to the description in the method embodiment, which will not be repeated here.

[0190] In some examples, the first physical network port 523 includes an Ethernet port.

[0191] In some examples, the first computing core 521 is further configured to, in response to receiving a data transfer instruction from the requesting host 510, execute the data transfer instruction, read the target data from the first memory 522, generate a target request carrying the target data, and send the target request to the first physical network port 523.

[0192] In some examples, the first physical network port 523 is configured to generate a message conforming to a preset format based on the target request and send the message to the data transmission link.

[0193] In some examples, the first computing core 521, the first memory 522, and the first physical network port 523 are connected via a first on-chip network. The first computing core 521 is further configured to: execute data transfer instructions to read target data from the first memory 522 via the first on-chip network; generate a target request and send the target request to the first physical network port 523 via the first on-chip network.

[0194] In some examples, the first physical network port 523 is further configured to parse and encapsulate the target request into a message conforming to a preset format, and send the message to the data transmission link for transmission to the second physical network port of the responding device.

[0195] In some examples, the requesting device is further configured to: trigger a retransmission of a message in response to receiving a negative acknowledgment signal, wherein the negative acknowledgment signal indicates that the responding device received erroneous data; and trigger a retransmission of a message in response to not receiving an acknowledgment signal within a preset time, wherein the acknowledgment signal indicates that the responding device received correct data.

[0196] In some examples, messages transmitted through the first physical network port 523 conform to a preset format, which specifies that the message header includes at least one of the following fields: a format field, a type field, a requester identifier field, a responseer identifier field, a message length field, a tag field, or a variable field. The format field indicates the operation type; the type field indicates the subtype under the operation type; the requester identifier field indicates the number of the requesting device; the responseer identifier field indicates the number of the responding device; the message length field indicates the message length; the tag field indicates the current timestamp; and the function of the variable field is determined based on the format field.

[0197] In some examples, the operation types include: memory write operation, atomic operation, memory read operation, completion operation, or acknowledgment operation.

[0198] In some examples, when the format field indicates that the operation type is a memory write operation or an atomic operation, the variable field is used to indicate the byte enable setting of the target data.

[0199] In some examples, when the format field indicates that the operation type is a completion operation, the variable field is used to indicate the completion status of the responding device.

[0200] In some examples, the default format also specifies that the message header includes at least one of the following fields: packet sequence number field, acknowledgment request field, and padding field. The packet sequence number field is used to indicate the sequence number of the data packet corresponding to the message, the acknowledgment request field is used to indicate whether the responding end needs to reply with an acknowledgment signal, and the padding field is used to implement byte alignment in the message header.

[0201] Figure 5B This is a schematic block diagram of a response system provided for at least one embodiment of the present disclosure.

[0202] For example, such as Figure 5B As shown, at least one embodiment of the response system 600 provided in this disclosure includes a response end device 610, wherein the response end device 610 includes a second computing core 611 and a second physical network port 612. The second physical network port 612 is configured to: in response to receiving a message from a data transmission link and the message passing verification, obtain a target request carrying target data based on the message, and provide it to the second computing core 611 for processing, wherein the data transmission link is used for data transmission between the request end device and the response end device 610.

[0203] Although Figure 5B As not shown in the diagram, the response system 600 may further include a response host. Descriptions of the response host, response device, second computing core, and second physical network port can be found in the method embodiments and will not be repeated here.

[0204] In some examples, the second physical network port 612 includes an Ethernet port.

[0205] In some examples, the second physical network port 612 is further configured to: in response to receiving a message from the data transmission link and the message passing the verification, parse the message and convert it into a target request; and send the target request to the second computing core 611.

[0206] In some examples, the responding device also includes a second memory, and the second computing core 611 is further configured to write the target data carried by the target request into the second memory.

[0207] In some examples, the second computing core 611, the second memory, and the second physical network port 612 are connected via a second on-chip network. The second physical network port 612 is further configured to send a target request to the second computing core 611 via the second on-chip network. The second computing core 611 is further configured to write the target data carried by the target request into the second memory via the second on-chip network.

[0208] In some examples, the responding device is further configured to: verify the message based on at least one of the sequence number of the data packet corresponding to the message, the number of the responding device, and the length of the message; return an acknowledgment signal to the requesting device in response to the message passing the verification; and return a negative acknowledgment signal to the requesting device in response to the message failing the verification.

[0209] It should be understood that the request system and response system provided in at least one embodiment of this disclosure can be used to implement the aforementioned data transmission method and can also achieve similar technical effects as the aforementioned data transmission method, which will not be elaborated here.

[0210] It should be noted that, in the embodiments of this disclosure, the request system and response system may include more or fewer modules or units, and the connection relationship between the various modules or units is not limited and can be determined according to actual needs. The specific configuration of each module or unit is not limited; it can be constructed from analog devices according to circuit principles, or from digital chips, or in other suitable ways.

[0211] Figure 6A This is a schematic block diagram of an apparatus provided for at least one embodiment of the present disclosure. Figure 6A An example of a requesting or responding device provided in at least one embodiment of this disclosure.

[0212] For example, such as Figure 6A As shown, the device includes a computing core, memory, and physical network ports interconnected via an on-chip network. The device also includes a MAC module and a serializer-deserializer circuit connected sequentially to the physical network ports. The device is connected to a switch via the serializer-deserializer circuit, enabling interconnection of multiple devices. The MAC module, serializer-deserializer circuit, and switch constitute part of the data transmission link. An example of a physical network port can be an Ethernet port, and an example of a corresponding switch can be an Ethernet switch.

[0213] The requesting or responding device involved in at least one embodiment of this disclosure can be referred to. Figure 6A This is an exemplary architecture, but is not limited to this specific implementation.

[0214] Figure 6BThis is a schematic block diagram of an Ethernet port provided for at least one embodiment of the present disclosure. The Ethernet port in this example is based on the AXI protocol, but different protocols may be used depending on actual needs, and the embodiments of the present disclosure do not limit this.

[0215] For example, such as Figure 6B As shown, an Ethernet port includes a receive module (also known as Ethernet RX), a transmit module (also known as Ethernet TX), a decapsulation module, a recapsulation module, an AXI bridge, a master module, and a slave module. The receive and transmit modules of the Ethernet port can be connected to a data transmission link, such as connecting to... Figure 6A The MAC module is shown. Both the decapsulation and encapsulation modules include buffers for temporarily storing received and sent messages, respectively. The encapsulation module encapsulates AXI requests into messages, and the decapsulation module decapsulates messages into AXI requests. The AXI bridge has multiple built-in first-in-first-out (FIFO) queues for transmitting different types of requests or responses between the decapsulation / encapsulation modules and the master / slave modules, such as write requests (wr req), atomic operation requests (at req), read requests (rd req), and read responses (rd resp).

[0216] Both the master and slave modules are connected to the on-chip network via five channels: write address channel (Aw), write data channel (W), read address channel (AR), write response channel (B), and read data and response channel (R). For the master module, the write address channel (Aw), write data channel (W), and read address channel (AR) run from the master module to the on-chip network; the write response channel (B) and read data and response channel (R) run from the on-chip network to the master module. For the slave module, the write address channel (Aw), write data channel (W), and read address channel (AR) run from the on-chip network to the slave module; the write response channel (B) and read data and response channel (R) run from the slave module to the on-chip network. Therefore, the master module is used to return responses and receive requests, while the slave module is used to send requests and receive responses.

[0217] The aforementioned Ethernet ports adopt a split-channel architecture, where the sending and receiving paths are independent in terms of physical layer, data buffer, and control logic, thereby avoiding mutual blocking of read and write operations and supporting low-latency, high-bandwidth memory semantic communication.

[0218] Figure 7 This is a schematic block diagram of an electronic device provided for at least one embodiment of the present disclosure.

[0219] For example, such as Figure 7As shown, the electronic device 700 includes at least one processor 701 and at least one memory 702. The at least one memory 702 includes one or more computer program modules. These computer program modules are stored in the memory 702 and configured to be executed by the at least one processor 701. The one or more computer program modules include instructions for performing the data transmission method described above. When executed by the at least one processor 701, they can perform one or more steps of the data transmission method provided in at least one embodiment of this disclosure. The memory 702 and the processor 701 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0220] For example, processor 701 can be a central processing unit (CPU), digital signal processor (DSP), graphics processing unit (GPU), general-purpose graphics processing unit (GPGPU), artificial intelligence (AI) accelerator, or other form of processing unit with data processing and / or program execution capabilities, such as a field-programmable gate array (FPGA); for example, the central processing unit (CPU) can be an x86, ARM, or RISC-V architecture. Processor 701 can be a general-purpose processor or a special-purpose processor, capable of controlling other components in electronic device 700 to perform desired functions.

[0221] For example, memory 702 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc.

[0222] Figure 8 This is a schematic block diagram of another electronic device provided for at least one embodiment of the present disclosure.

[0223] The electronic devices in at least one embodiment of this disclosure may include, but are not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, personal digital assistants (PDAs), tablet computers (PADs), portable multimedia players (PMPs), in-vehicle terminals (e.g., in-vehicle navigation terminals), wearable electronic devices, and fixed terminals such as digital TVs and desktop computers. Figure 8 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0224] The electronic device includes at least one processor and a memory. The processor may be referred to as processing device 801 as described below, and the memory may include at least one of ROM 802, RAM 803, and storage device 808 as described below. The memory is used to store programs for performing the methods described in the various method embodiments above; the processor is configured to execute the programs stored in the memory. The processor may include a central processing unit (CPU) or other forms of processing unit having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0225] like Figure 8 As shown, the electronic device 800 may include a processing unit 801 (e.g., a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to a program stored in ROM 802 or a program loaded from storage device 808 into RAM 803. RAM 803 also stores various programs and data required for the operation of the electronic device 800. The processing unit 801, ROM 802, and RAM 803 are interconnected via bus 804. Input / output (I / O) interfaces are also connected to bus 804.

[0226] Typically, the following devices can be connected to I / O interface 805: input devices 806 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 807 including, for example, displays, speakers, vibrators, etc.; storage devices 808 including, for example, magnetic tapes, hard disks, etc.; and communication devices 809. Communication device 809 allows electronic device 800 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 8 An electronic device 800 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively.

[0227] In particular, according to at least one embodiment of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, at least one embodiment of this disclosure includes a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such an embodiment, the computer program can be downloaded and installed from a network via a communication device 809, or installed from a storage device 808, or installed from a ROM 802. When the computer program is executed by a processing device 801, it performs the functions defined in the methods of at least one embodiment of this disclosure.

[0228] It should be noted that the computer-readable medium described above in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In at least one embodiment of this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In at least one embodiment of this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, radio frequency (RF), etc., or any suitable combination thereof.

[0229] The aforementioned computer-readable medium may be included in the aforementioned electronic device 800; or it may exist independently and not assembled into the electronic device 800.

[0230] Figure 9 This is a schematic block diagram of a non-transitory computer-readable storage medium provided for at least one embodiment of the present disclosure.

[0231] For example, such as Figure 9 As shown, a non-transitory computer-readable storage medium 900 stores computer-readable instructions 901, which, when executed by at least one processor, perform one or more steps of the data transmission method described above.

[0232] For example, the storage medium may include a memory card for a smartphone, a storage component for a tablet computer, a hard drive for a personal computer, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), flash memory, or any combination of the above storage media, or other suitable storage media. For example, the readable storage medium may also be... Figure 7 The memory 702 in the memory is described in the foregoing content and will not be repeated here.

[0233] Although the present disclosure has been described in detail above with general descriptions and specific embodiments, modifications or improvements can be made to the embodiments of the present disclosure, which will be obvious to those skilled in the art. Therefore, all such modifications or improvements made without departing from the spirit of the present disclosure are within the scope of protection claimed by the present disclosure.

[0234] The following points should be noted regarding this disclosure:

[0235] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0236] (2) For clarity, the thickness of layers or regions in the drawings used to describe embodiments of the present disclosure is enlarged or reduced, i.e., these drawings are not drawn to actual scale.

[0237] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0238] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A data transmission method, characterized by, The data transmission method is applied to a request-side device in a request-side computing node, the request-side computing node comprising a request-side host and the request-side device, the request-side device comprising a first computing core, a first memory and a first physical network port, and the data transmission method comprising: in response to receiving a data transmission instruction from the request-side host, the first computing core reading target data from the first memory and sending the target data to a data transmission link via the first physical network port, wherein the data transmission link is used for data transmission between the request-side device and a response-side device, wherein the request-side device is a graphics processor or a general-purpose graphics processor, and the first computing core is a hardware execution unit in the request-side device that executes a parallel computing task.

2. The data transmission method of claim 1, wherein, The first physical network port comprises an Ethernet port.

3. The data transmission method of claim 1, wherein, The first computing core reading target data from the first memory and sending the target data to a data transmission link via the first physical network port in response to receiving a data transmission instruction from the request-side host comprises: in response to receiving a data transmission instruction from the request-side host, the first computing core executing the data transmission instruction and reading the target data from the first memory; the first computing core generating a target request carrying the target data and sending the target request to the first physical network port; the first physical network port generating a message conforming to a preset format based on the target request and sending the message to the data transmission link.

4. The data transmission method of claim 3, wherein, The first computing core, the first memory and the first physical network port are connected through a first network-on-chip, wherein the first computing core executing the data transmission instruction and reading the target data from the first memory comprises the first computing core executing the data transmission instruction and reading the target data from the first memory via the first network-on-chip, wherein the first computing core generating a target request carrying the target data and sending the target request to the first physical network port comprises the first computing core generating the target request and sending the target request to the first physical network port via the first network-on-chip.

5. The data transmission method of claim 3, wherein, The first physical network port generating a message conforming to a preset format based on the target request and sending the message to the data transmission link comprises: the first physical network port parsing and encapsulating the target request into a message conforming to a preset format and sending the message to the data transmission link for transmission to a second physical network port of the response-side device.

6. The data transmission method of claim 3, wherein, The first physical network port temporarily stores a backup of the message, and the data transmission method further comprises: in response to receiving a negative acknowledgement signal, triggering retransmission of the message, wherein the negative acknowledgement signal indicates that the response-side device receives incorrect data; In response to not receiving the acknowledgement signal within a preset time, triggering retransmission of the message, wherein the acknowledgement signal indicates that the response end device receives correct data.

7. The data transmission method of claim 1, wherein, The message transmitted through the first physical network port conforms to a preset format, and the preset format stipulates that the message header includes at least one of the following fields: a format field, a type field, a request end identifier field, a response end identifier field, a message length field, a tag field, or a variable field, The format field is used to indicate an operation type, the type field is used to indicate a sub-type under the operation type, the request end identifier field is used to indicate a number of the request end device, the response end identifier field is used to indicate a number of the response end device, the message length field is used to indicate a length of the message, the tag field is used to indicate a current timestamp, and a function of the variable field is determined based on the format field.

8. The data transmission method of claim 7, wherein, The operation type includes a memory write operation, an atomic operation, a memory read operation, a completion operation, or an acknowledgement reply operation.

9. The data transmission method of claim 8, wherein, When the format field indicates that the operation type is the memory write operation or the atomic operation, the variable field is used to indicate a byte enable setting of the target data.

10. The data transmission method of claim 8, wherein, When the format field indicates that the operation type is the completion operation, the variable field is used to indicate a completion status of the response end device.

11. The data transmission method of claim 7, wherein, The preset format further stipulates that: The message header further includes at least one of the following fields: a packet sequence number field, an acknowledgement reply request field, and a padding field, The packet sequence number field is used to indicate a sequence number of a data packet corresponding to the message, the acknowledgement reply request field is used to indicate whether the response end needs to reply an acknowledgement signal, and the padding field is used to realize byte alignment in the message header.

12. A data transmission method, characterized by, The data transmission method is applied to a response end device in a response end computing node, the response end computing node includes a response end host and the response end device, the response end device includes a second computing core, a second memory, and a second physical network port, and the data transmission method includes: In response to receiving a message from a data transmission link and the message passing verification, the second physical network port obtains a target request carrying target data based on the message to provide to the second computing core for processing; The second computing core writes the target data carried by the target request into the second memory, The data transmission link is used for data transmission between a request end device and the response end device, The response end device is a graphics processor or a general-purpose graphics processor, and the second computing core is a hardware execution unit that performs a parallel computing task in the response end device.

13. The data transmission method of claim 12, wherein, In response to receiving a message from a data transmission link and the message passing verification, the second physical network port obtains a target request carrying target data based on the message to provide to the second computing core for processing, including: In response to receiving a message from the data transmission link and the message passing verification, the second physical network port parses and converts the message into the target request; The second physical network port sends the target request to the second computing core.

14. The data transmission method of claim 13, wherein, The second computing core, the second memory, and the second physical network port are connected by a second network-on-chip, The second physical network port sends the target request to the second computing core includes that the second physical network port sends the target request to the second computing core via the second network-on-chip. The second computing core writes the target data carried by the target request into the second memory includes that the second computing core writes the target data carried by the target request into the second memory via the second network-on-chip.

15. The data transmission method of claim 12, wherein, The data transmission method further includes: verifying the message based on at least one of a sequence number of a data packet corresponding to the message, a number of the response-end device, and a length of the message; in response to the message passing verification, returning an acknowledgement signal to the request-end device; in response to the message failing verification, returning a negative acknowledgement signal to the request-end device.

16. A request system, characterized by The request system includes a request-end device and a request-end host, and the request-end device includes a first computing core, a first memory, and a first physical network port, The first computing core is configured to: in response to receiving a data transmission instruction from the request-end host, read target data from the first memory and send the target data to a data transmission link via the first physical network port, The data transmission link is used for data transmission between the request-end device and a response-end device, The request-end device is a graphics processing unit or a general-purpose graphics processing unit, and the first computing core is a hardware execution unit that performs a parallel computing task in the request-end device.

17. A response system characterized by, The response system includes a response-end device and a response-end host, and the response-end device includes a second computing core, a second memory, and a second physical network port, The second physical network port is configured to, in response to receiving a message from the data transmission link and the message passing verification, obtain a target request carrying target data based on the message to provide to the second computing core for processing, The second computing core is configured to write the target data carried by the target request into the second memory, The data transmission link is used for data transmission between the request-end device and the response-end device, The response-end device is a graphics processing unit or a general-purpose graphics processing unit, and the second computing core is a hardware execution unit that performs a parallel computing task in the response-end device.

18. An electronic device, comprising: The electronic device includes: at least one processor; at least one memory including one or more computer program modules; The one or more computer program modules are stored in the at least one memory and configured to be executed by the at least one processor, and the one or more computer program modules are used to implement the data transmission method in any one of claims 1-15.

19. A non-transitory computer-readable storage medium, comprising: The non-transitory computer readable storage medium has stored thereon computer readable instructions, wherein the computer readable instructions, when executed by at least one processor, perform the data transmission method of any one of claims 1-15.

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