Processor, memory access control method and device

Abstract

Embodiments of the present application provide a processor, a memory access control method and equipment. The processor comprises a request unit. The request unit is configured to send a first request corresponding to each write instruction to a bus in any order to obtain a write permission. The request unit is further configured to update a global sequence number after determining that each preceding write instruction has obtained the write permission in response to any one write instruction obtaining the write permission. The request unit is further configured to send a second request corresponding to any one write instruction to the bus in any order to write to-be-written data to a corresponding write address. Through the above technical solution, the execution efficiency of the write operation can be improved on the basis of meeting the requirements of the TSO model on the execution order of the write instruction.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a processor, memory access control method and device. Background Technology

[0002] Total Store Order (TSO) is a common memory consistency model that requires all memory write operations within a single processor to be executed in the order of the program code. Furthermore, it requires that all processors see the same order of all memory write operations, resulting in a globally unique sequence of operations. Under the TSO model, when performing write operations, under normal circumstances, the cache lines corresponding to each write operation are pre-loaded into the processor's private cache. Multiple write operations access the cache lines in the private cache sequentially, completing the data write in turn.

[0003] When write streaming mode is triggered, cache lines are no longer loaded into the processor's private cache, but are stored in the lower-level shared cache or main memory. As a result, each write operation needs to access the lower-level shared cache or main memory through the bus to complete the data writing.

[0004] However, during bus transmission, write operations may occur out of order, making it impossible to guarantee the execution sequence of each write operation. Therefore, the next write operation can only be sent to the bus after the preceding write operation is completed, which limits the execution efficiency of write operations. Summary of the Invention

[0005] In view of this, embodiments of this application provide a processor, a memory access control method, and an apparatus to at least partially solve the above-mentioned problems.

[0006] According to a first aspect of the embodiments of this application, a processor is provided, including: a request unit;

[0007] The request unit is used to send a first request corresponding to each write instruction to the bus, the first request being used to obtain write permission; the transmission order of the first requests corresponding to each write instruction on the bus is arbitrary.

[0008] The request unit is further configured to, in response to any write instruction obtaining write permission, update the global sequence number after determining that all preceding write instructions of any write instruction have obtained write permission, wherein the global sequence number is used to identify the currently executing write instruction.

[0009] The request unit is further configured to send a second request corresponding to any one of the write instructions to the bus, the second request being used to write the data to be written to the corresponding write address; the transmission order of the second request corresponding to any one of the write instructions on the bus is arbitrary.

[0010] According to a second aspect of the embodiments of this application, a memory access control method is provided, applied to the processor as described in the first aspect, the method comprising: sending a first request corresponding to each write instruction to a bus by a request unit, the first request being used to obtain write permission; the transmission order of the first requests corresponding to each write instruction on the bus is arbitrary.

[0011] The request unit obtains write permission in response to any write instruction. After determining that all preceding write instructions of any write instruction have obtained write permission, the global sequence number is updated. The global sequence number is used to identify the currently executing write instruction.

[0012] The request unit sends a second request corresponding to any one of the write instructions to the bus. The second request is used to write the data to be written to the corresponding write address. The transmission order of the second request corresponding to any one of the write instructions on the bus is arbitrary.

[0013] According to a third aspect of the embodiments of this application, an electronic device is provided, the electronic device including a processor as described in the first aspect, the processor being configured to perform the method as described in the second aspect.

[0014] According to a fourth aspect of the embodiments of this application, a computer storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the method described in the second aspect.

[0015] In the technical solution of this application embodiment, the processor can send write permission requests corresponding to each write instruction to the bus in any order to obtain write permissions. Then, it can control each write instruction to enter the globally visible state sequentially according to the program order. After entering the globally visible state, it can send second requests corresponding to each write instruction to the bus in any order to complete the actual data write operation. Through the above technical solution, before executing the actual write operation, the processor first controls each write instruction to enter the globally visible state in sequence, thereby satisfying the TSO model's requirement for the execution order of write instructions. In this way, when executing the actual write operation, the processor can send the second requests corresponding to each write instruction to the bus in any order, thereby improving the parallelism of each write operation and increasing the execution efficiency of the write operation. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0017] Figure 1 A schematic diagram of the structure of a processor provided in an embodiment of this application;

[0018] Figure 2 Another schematic diagram of the processor provided in an embodiment of this application;

[0019] Figure 3 This is a schematic diagram illustrating the functional implementation of a processor provided in an embodiment of this application;

[0020] Figure 4 A schematic diagram illustrating another functional implementation of the processor provided in an embodiment of this application;

[0021] Figure 5 A flowchart of a memory access control method provided in an embodiment of this application;

[0022] Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0023] To enable those skilled in the art to better understand the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art should fall within the protection scope of the embodiments of this application.

[0024] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0025] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0026] It should also be noted that the terms "first, second, and third" used in the embodiments of this application are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first, second, and third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0027] Furthermore, in the embodiments of this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0028] To facilitate understanding of the technical solutions of the embodiments of this application, the relevant technologies of the embodiments of this application are described below. The following relevant technologies are optional solutions and can be combined with the technical solutions of the embodiments of this application in any way, and they all fall within the protection scope of the embodiments of this application.

[0029] Multi-core processors employ a multi-level cache architecture comprising three main tiers: Level 1 Cache, Level 2 Cache, and Level 3 Cache. Level 1 cache resides within each core of the multi-core processor; it is a private cache, fast, and small in size. Level 2 cache resides within each core or is shared among multiple cores; it is slower than Level 1 cache but has a larger capacity. Level 3 cache is shared by all cores; it is slower than Level 2 cache but has a larger capacity.

[0030] In a store instruction execution scenario, target data needs to be written to the target address. Before writing the target data, the entire cache line (usually 64 bytes) containing the target address needs to be loaded from memory into a private cache. In this way, when the processor core executes the store instruction, it can directly read the corresponding cache line from its own private cache to complete the data writing, resulting in faster memory access speed.

[0031] Total Store Order (TSO) requires that all memory write operations within a single processor be executed in the order of the program code. Furthermore, it requires that the order in which all processors see all memory write operations must be identical, resulting in a globally unique sequence of operations. When performing a write operation under the TSO model, the processor core sends the received write instructions sequentially to the internal store buffer. The store buffer is typically a first-in, first-out (FIFO) queue, where each write instruction is executed sequentially, accessing the private cache in turn to complete the data write.

[0032] However, when write streaming mode is triggered, the program needs to access large contiguous memory addresses. If all cache lines are loaded into the processor's private cache, the limited capacity of the private cache might crowd out other, more important data, leading to cache pollution. Therefore, upon detecting write streaming mode, cache lines are no longer pre-loaded into the private cache but are instead sent to the lower-level shared cache or main memory via the bus. Consequently, when executing a write instruction, the data to be written needs to be sent to the lower-level shared cache or main memory via the bus to complete the write operation. However, the data to be written for each write instruction may become out of order during bus transmission, making it impossible to guarantee the execution order of each write operation, violating the requirements of the TSO model. Therefore, the data for the next write instruction must wait for the previous write instruction to complete before sending the data for the next write instruction to the bus, resulting in low execution efficiency for each write instruction in write streaming mode.

[0033] This application is submitted to address the aforementioned issues.

[0034] In this embodiment, a processor is provided, which can be any processor in a multi-core processor system. The processor provided in this embodiment may include a request unit, which can be used to send write permission requests corresponding to each write instruction to the bus in any order to obtain write permission for each write instruction. Furthermore, after any write instruction obtains write permission, the request unit can update the current global sequence number after determining that all preceding write instructions of that any write instruction have obtained write permission, so that the global sequence number points to the next write instruction, used to identify the next write instruction as the currently executing write instruction. Here, each preceding write instruction refers to the write instructions that are executed first. Furthermore, the request unit can send the write data of that any write instruction to the bus in any order to complete the data writing.

[0035] In the above implementation, the request unit can, for example, determine the preceding write instruction based on the sequence number carried by each write instruction. The sequence number of each write instruction can be generated by the request unit or other functional units in the processor according to the receiving order of the write instructions. Furthermore, each write instruction may also carry write permission status identification information. For any write instruction, after obtaining write permission, the request unit can, for example, set the corresponding write permission status identification information to "has write permission". Then, the request unit can determine whether each preceding write instruction has obtained write permission by checking the write permission status identification information of each preceding write instruction. Alternatively, the request unit can also determine whether each preceding write instruction has obtained write permission through other methods. Details will be explained in subsequent embodiments.

[0036] In the above technical solution, write permissions for each write instruction can be obtained through the bus in any order. Then, each write instruction can be marked as globally visible in sequence, and write operations for each instruction can be initiated to the bus in any order. This satisfies the requirements of the TSO model while improving the parallelism of write operations and enhancing the execution efficiency of write operations in streaming write mode.

[0037] The processor and its functional implementation provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0038] Figure 1 This is a schematic diagram of a processor provided in this application. Figure 1 As shown, the processor provided in this embodiment may include a memory access unit 11, a pre-order unit 12, and a request unit 13. The pre-order unit 12 may be connected to both the memory access unit 11 and the request unit 13. The pre-order unit 12 and the request unit 13 may, for example, be located within the processor's memory. The request unit 13 may, for example, be implemented as a request buffer.

[0039] Based on such Figure 1 In the processor with the illustrated architecture, the memory access unit can determine the current memory access mode based on the access addresses of each memory access instruction. Upon detecting a triggered streaming write mode, the memory access unit can sequentially send the received write instructions to the order-keeping unit in the order they are received. Each write instruction refers to a write instruction within the streaming write mode.

[0040] Furthermore, the sequence-preserving unit can be used to add sequence number identifiers to each write instruction according to the receiving order. Then, the sequence-preserving unit can send each write instruction with the added sequence number identifier to the requesting unit to await execution. The sending order of each write instruction to the requesting unit can be arbitrary.

[0041] In a multi-core processor system, copies of the same data may exist simultaneously in the private caches of multiple processor cores. Therefore, to ensure the consistency of the same data held by each core, any core (hereinafter referred to as the target core) needs to send a listen request to other cores via the bus before modifying the data. The listen request can be used to notify the target data that it will be modified by the target core. At the same time, the listen request can be used to drive other cores to perform cache line state transitions, thereby enabling the target core to obtain write permissions.

[0042] In the MESI cache coherence protocol, cache line states include Modified (M), Exclusive (E), Shared (S), and Invalid (I). The M state indicates that only this core has the latest copy, and the version stored in memory is the older version. The E state indicates that only this core has the latest copy, and it is consistent with the version in memory. The S state indicates that multiple cores have the latest copy, and all of them are consistent with the version in memory. The I state indicates that the copy has expired and cannot be used.

[0043] Taking the MESI protocol as an example, in this embodiment, the request unit can be used to send a first request corresponding to each write instruction to the bus. The first request can be used to obtain write permission. Specifically, the first request can be, for example, a write permission request. The first request can be used to trigger the bus to send a listen request to other processors. The listen request can be used to notify other processor cores to return cache line status information to the current processor core, and if they hold the latest copy, return the latest copy to the current processor core, and invalidate the copy they hold. The transmission order of the first requests corresponding to each write instruction on the bus can be arbitrary.

[0044] In this embodiment, the request unit may maintain a global sequence number, which can be shared by all processor cores. The global sequence number can be used to identify the currently executing write instruction. Based on the global sequence number, each processor core can determine the write instructions that have been completed and the write instructions that are currently being executed. For example, if the global sequence number is 5, each processor core can determine that the currently executing write instruction is write instruction 5, and can determine that write instructions 0-4 have been completed.

[0045] In this embodiment, the global sequence number can be updated after the currently pointed-to write instruction obtains write permission to point to the next write instruction. Therefore, for any write instruction (hereinafter referred to as the target write instruction), after obtaining write permission, the requesting unit can determine whether all preceding write instructions of the target write instruction have obtained write permission based on the sequence number identifier of the target write instruction. Specifically, the requesting unit can compare the sequence number identifier of the target write instruction with the global sequence number.

[0046] If the comparison is consistent, it can be determined that all preceding write instructions have acquired write permissions, and the target write instruction is precisely the currently executing write instruction. Since the target write instruction has acquired write permissions, the original data copies held by other processor cores are invalidated. Therefore, any subsequent processor core that needs to read the latest data must request it from the current processor core, which will then provide the latest data. In other words, although the target write instruction has not yet completed its data write operation, the current processor core already holds the latest data copy corresponding to the target write instruction and can share this copy with other processor cores. Therefore, after confirming that all preceding write instructions have acquired write permissions, the requesting unit can directly update the global sequence number, pointing the currently executing write instruction to the next write instruction. This makes the target write instruction globally visible. Global visibility of the target write instruction means that all processor cores can determine that the target write instruction has been executed based on the global sequence number and can obtain the latest data copy from the current processor core.

[0047] If the comparison is inconsistent, it means that not all preceding write commands have obtained write permissions. In this case, you can wait for all preceding write commands to obtain write permissions before updating the global serial number.

[0048] By implementing the above method, each write instruction can be made to enter the globally visible state in sequence before a formal write operation is initiated to the bus, thereby satisfying the TSO model's requirement for the execution order of write instructions.

[0049] Furthermore, after the target write instruction enters the globally visible state, the requesting unit can send a second request corresponding to the target write instruction to the bus. The second request can be a write request, and the second request can carry the data to be written. The second request is used to write the data to be written to the corresponding write address in the lower-level shared cache or memory.

[0050] In this embodiment, since the target write instructions have entered the globally visible state in sequence, the transmission order of the second request corresponding to the target write instruction on the bus can be arbitrary. That is, after entering the globally visible state in sequence, the actual write operations of each write instruction can be executed in any order. In this way, the subsequent write instruction does not need to wait for the previous write instruction to complete its write operation before sending the second request to the bus, thereby improving the parallelism of the write operation and increasing the execution efficiency of the write operation in streaming write mode.

[0051] In the above technical solution, the processor can send write permission requests corresponding to each write instruction to the bus in any order to obtain write permissions. Then, it can control each write instruction to enter the globally visible state sequentially according to the program order. After entering the globally visible state, it can send the second requests corresponding to each write instruction to the bus in any order to complete the actual data write operation. Through this technical solution, before executing the actual write operation, the processor first controls each write instruction to enter the globally visible state in sequence, thereby satisfying the TSO model's requirement for the execution order of write instructions. In this way, when executing the actual write operation, the processor can send the second requests corresponding to each write instruction to the bus in any order, thereby improving the parallelism of each write operation and increasing the execution efficiency of the write operation.

[0052] Figure 2 Another schematic diagram of the processor provided in this application. (See diagram below.) Figure 2 As shown, the processor provided in this embodiment may include a memory access unit 11, a preserving order unit 12, a query unit 14, a private cache 15, and a request unit 13. The preserving order unit 12, the query unit 14, the private cache 15, and the request unit 13 may be located within the processor's memory unit. The query unit 14 may be connected to the private cache 15, the preserving order unit 12, and the request unit 13, respectively. The query unit 14 may be implemented as a main flow, for example, and the request unit 13 may be implemented as a request buffer, for example.

[0053] Figure 3 A flowchart illustrating the functional implementation of the processor provided in an embodiment of this application is given. (Reference) Figure 3 In this embodiment of the application, firstly, the memory access unit can be used to send the received write instructions to the order-keeping unit in accordance with the receiving order after detecting the current triggered streaming write mode.

[0054] Furthermore, the sequence-preserving unit can be used to add a sequence number identifier to each write instruction according to the order in which they are received, and then send each write instruction with the added sequence number identifier to the query unit. The order in which the sequence-preserving unit sends each write instruction to the query unit can be arbitrary.

[0055] After the memory access unit detects the streaming write mode, the cache lines corresponding to some write instructions in the streaming write mode may have already been loaded into the processor's private cache. Therefore, in this embodiment, the query unit can query the hit status of the cache lines corresponding to each write instruction in the private cache, and generate request information for each write instruction based on the hit status. The request information may include data cache status, write permission status, write data, write address, etc.

[0056] Specifically, for any write instruction, if the query unit finds that the cache line corresponding to the write instruction is in a first-hit state in the private cache, the data cache status in the generated request information will be in a hit state, and the write permission status will be "write permission granted." Here, "first-hit state" means that the corresponding cache line exists in the private cache, and the cache line status is either exclusive or modified. In this case, the corresponding write instruction will not need to send a first request to the bus to obtain write permission; it only needs to wait for all preceding write instructions to obtain write permission before updating to a globally visible state in sequence. Therefore, the corresponding data can be directly modified in the private cache without sending a second request to the bus.

[0057] If the cache line corresponding to the write instruction is found to be in a second-hit state in the private cache, the data cache status in the generated request information will be in a hit state, and the write permission status will be "no write permission". Here, a second-hit state means that the corresponding cache line exists in the private cache, and the cache line status is shared. In this case, the corresponding write instruction needs to send a first request to the bus to obtain write permission, and after waiting for all preceding write instructions to obtain write permission, it will be updated to a globally visible state in sequence. Therefore, the corresponding data can be directly modified in the private cache without sending a second request to the bus.

[0058] If the cache line corresponding to a write instruction is found to be in a miss state in the private cache, the data cache status in the generated request information will also be a miss state, and the write permission status will be "no write permission". In this case, the corresponding write instruction needs to send a first request to the bus to obtain write permission, and after waiting for all preceding write instructions to obtain write permission, it will be updated to a globally visible state in sequence. Then, a second request needs to be sent to the bus to execute the data write.

[0059] Furthermore, the query unit can send the request information corresponding to each write instruction to the request unit. The order in which the request information for each write instruction is sent can be arbitrary.

[0060] Then, the requesting unit can determine the write permission status of each write instruction based on the request information. For any write instruction, if the write permission status is determined to be "no write permission," the requesting unit can send a first request corresponding to the write instruction to the bus to obtain write permission. When sending the first requests corresponding to each write instruction to the bus, the requesting unit does not need to pay attention to the sequence number of each write instruction and can send them in any order. For example, the first request corresponding to write instruction 3 can be sent first, followed by the first request corresponding to write instruction 2. Alternatively, after sending the first request corresponding to write instruction 4, the first request corresponding to write instruction 5 can be sent before receiving the corresponding response. In this way, the efficiency of obtaining write permission for each write instruction can be improved.

[0061] Furthermore, for any write instruction, after obtaining the corresponding write permission, the requesting unit can query the ordering unit to determine whether all preceding write instructions have obtained write permission.

[0062] Specifically, in this embodiment, the sequence-preserving unit may maintain a global sequence number. The requesting unit may send the sequence number identifier corresponding to the write instruction to the sequence-preserving unit, and then the sequence-preserving unit may compare the sequence number identifier corresponding to the write instruction with the sequence number identifier of the global sequence number.

[0063] If the comparison matches, it indicates that the write instruction is the currently executing write instruction. This means that all preceding write instructions have entered a globally visible state, and therefore, it can be determined that all preceding write instructions have acquired write permissions. The sequence-preserving unit can then send a first query result to the requesting unit. This first query result can be used by the requesting unit to confirm that all preceding write instructions have acquired write permissions. Furthermore, the sequence-preserving unit can update the current global sequence number, making it point to the next write instruction, thereby enabling the current write instruction to enter a globally visible state.

[0064] If the comparison is inconsistent, it indicates that the write instruction is not the currently executing write instruction. In other words, not all preceding write instructions have yet entered the globally visible state. Therefore, it can be determined that some preceding write instructions have not yet obtained write permissions. The sequence-preserving unit can then send a second query result to the requesting unit. This second query result can be used by the requesting unit to determine that not all preceding write instructions have obtained write permissions. Furthermore, the sequence-preserving unit can maintain the global sequence number unchanged.

[0065] It's important to note that if the current write instruction obtains write permission, it means that this processor core holds the latest version of the data. Therefore, when other processor cores need to read the latest version of the data, they must send a data request to this processor. In other words, although no actual data write operation has been performed yet, this processor core can already provide the latest version of the data to other processor cores when they need it. In other words, the latest version of the data is now globally visible. Therefore, if the write instruction obtains write permission and it is confirmed that all preceding write instructions have obtained write permission, the global sequence number can be updated directly. This allows the current write instruction to complete execution from a global perspective and enter a globally visible state.

[0066] In this embodiment, the request information of each write instruction in the request unit may also include a global status identifier. For any write instruction, after receiving the first query result, if the request unit determines that all preceding write instructions have obtained write permissions, then the global status identifier corresponding to the write instruction can be changed from globally invisible to globally visible. Furthermore, the request unit can determine the data cache status based on the request information of the write instruction. If the data cache status is determined to be a miss, the request unit can send a second request corresponding to the write instruction to the bus. The second request may carry the data to be written, which is used by the bus to send the data to be written to the corresponding lower-level shared cache or memory to complete the data writing. It should be noted that since the write instructions have entered the globally visible state in sequence, the transmission order of the second requests of each write instruction on the bus can be arbitrary. For example, if both write command 2 and write command 3 have entered a globally visible state, a second request for write command 3 can be sent to the bus first, followed by a second request for write command 2; alternatively, the second request for write command 3 can be sent immediately after the second request for write command 2 is issued, without waiting for the bus to return a completion response for write command 2; or the second requests for write command 2 and write command 3 can be sent in parallel. If the data cache status is determined to be a hit state, the requesting unit does not need to send a second request to the bus and can directly access the private cache to complete the data write.

[0067] For any write command, after receiving the second query result, if the requesting unit determines that not all preceding write commands have obtained write permissions, then the requesting unit may wait until all preceding write commands have obtained write permissions before executing the subsequent processing flow for the write command.

[0068] In the above technical solution, the processor can control the acquisition of write permissions for each write instruction from the bus in any order. Furthermore, based on the identifier number carried by each write instruction and the global sequence number in the order-keeping unit, it can control each write instruction to enter the globally visible state in sequence, thereby satisfying the instruction execution order requirements of the TSO model. Furthermore, it can control the initiation of write operations corresponding to each instruction on the bus in any order, thereby improving the execution efficiency of write operations. Through the above technical solution, the execution efficiency of write operations can be improved while satisfying the instruction execution order requirements of the TSO model.

[0069] In multi-core processor systems, introducing an order-preserving mechanism between requests that have no address dependencies can easily lead to system deadlock. Here, "no address dependencies" means that two memory write operations access different memory addresses; for example, core A writes to address X, and core B writes to address Y. The following concrete example illustrates the mechanism by which system deadlock occurs in this situation.

[0070] Suppose a dual-core system includes core A and core B. Core A issues write request A, which needs to read address X, while core B issues write request B, which needs to read address Y. The ordering mechanism requires that request A must be executed before request B. During the execution of request A, core A sends a listen request for address Y to core B. If the response to the listen request for address Y depends on the completion of request B, and request B in turn depends on the completion of request A, then the bus response of request A on the bus side depends on the completion of the listen request. This will result in a deadlock.

[0071] To prevent the aforementioned deadlock phenomenon, in the embodiments of this application, such as Figure 4 As shown, the request unit is further configured to, in response to a first request for an off-core write instruction sent by the bus, determine whether an associated write instruction exists in the request unit. The write address of the associated write instruction is the same as the write address of the off-core write instruction, which is a write instruction to be executed by another processor.

[0072] If no associated write instruction exists in the request unit, the request unit can process the listen request in the normal manner. Please refer to the relevant technical documentation for details.

[0073] If an associated write instruction exists in the requesting unit, the requesting unit can determine whether the global status identifier of the associated write instruction is globally visible. If the global status identifier is globally visible, a first response message for the first request to the off-core write instruction can be generated. The first response message can be used to return the latest write data at the write address corresponding to the off-core write instruction. If the global status identifier is globally invisible, the requesting unit can invalidate the write permission of the associated write instruction and generate a second response message for the first request to the off-core write instruction. The second response message can be used to indicate that the requesting unit does not hold the latest write data at the write address corresponding to the off-core write instruction.

[0074] Since the TSO model requires that subsequent write requests cannot be globally visible while preceding write requests are incomplete, the above technical solution can directly invalidate the write permissions of subsequent write requests after receiving the listening request of the preceding write request, instead of blocking the execution of the listening request of the preceding write request. This satisfies the requirements of the TSO model and prevents system deadlock.

[0075] Based on the above example, according to the deadlock prevention scheme provided in the embodiments of this application, after core B receives the listening request for address Y sent by core A, if it determines that write request B has not yet entered the globally visible state, then the listening request for address Y can be allowed to be completed without relying on write request B for address Y, and the write permission of write request B can be directly invalidated, thereby preventing deadlock.

[0076] Figure 5 A flowchart illustrating a memory access control method provided in an embodiment of this application. Figure 5 As shown, the memory access control method provided in this application embodiment may include:

[0077] Step 102: The requesting unit sends the first request corresponding to each write instruction to the bus in any transmission order.

[0078] Step 104: The requesting unit obtains write permission in response to any write instruction. After confirming that all preceding write instructions of any write instruction have obtained write permission, the global sequence number is updated.

[0079] Step 106: The requesting unit sends a second request corresponding to any write command to the bus in any transmission order.

[0080] Since the details of the memory access control method have been described in detail in the processor embodiment section above with reference to the structural diagram, the specific process can be found in the description of the aforementioned processor embodiment, and will not be repeated here.

[0081] The memory access control method provided in this application can improve the execution efficiency of write operations while meeting the instruction execution order requirements of the TSO model.

[0082] Figure 6 The diagram illustrates the structure of an electronic device according to an embodiment of this application. The electronic device may be configured with a processor provided in the embodiment of this application. The processor can be used to execute the memory access control method provided in the embodiment of this application. The specific embodiments of this application do not limit the specific implementation of the electronic device.

[0083] like Figure 6 As shown, the electronic device may include: a processor 502, a communications interface 504, a memory 506, and a communications bus 508.

[0084] The processor 502, communication interface 504, and memory 506 communicate with each other via communication bus 508. Communication interface 504 is used to communicate with other electronic devices or servers. The processor 502 executes program 510, specifically performing the relevant steps in the above-described memory access control method embodiment.

[0085] Specifically, program 510 may include program code that includes computer operation instructions.

[0086] Processor 502 may be a CPU, an Application Specific Integrated Circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application. The smart device includes one or more processors, which may be processors of the same type, such as one or more CPUs; or processors of different types, such as one or more CPUs and one or more ASICs.

[0087] Memory 506 is used to store program 510. Memory 506 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0088] Program 510 can specifically be used to cause processor 502 to execute the corresponding steps in the above-described processor embodiments and memory access control method embodiments, which will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working process of the devices and modules described above can be referred to the corresponding process descriptions in the foregoing method embodiments, which will not be repeated here.

[0089] This application also provides a computer program product, including computer instructions that instruct a computing device to perform an operation corresponding to any of the memory access control methods in the above-described plurality of method embodiments. It should be noted that, depending on implementation needs, the various components / steps described in the embodiments of this application can be broken down into more components / steps, or two or more components / steps or parts of the operations of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of this application.

[0090] This application also provides a computer-readable storage medium in which the methods described in this application can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code downloaded over a network that is originally stored in a remote recording medium or a non-transitory machine-readable medium and will be stored in a local recording medium. Thus, the methods described herein can be stored on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as ASIC or FPGA) for such software processing. It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components (e.g., RAM, ROM, flash memory, etc.) capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the memory access control methods described herein are implemented. Furthermore, when a general-purpose computer accesses the code used to implement the memory access control methods shown herein, the execution of the code transforms the general-purpose computer into a dedicated computer for executing the memory access control methods shown herein.

[0091] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the embodiments of this application.

[0092] It should be noted that, in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0093] Furthermore, it should be noted that the user-related information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to sample data used for training the model, data used for analysis, stored data, displayed data, etc.) involved in the embodiments of this application are all information and data authorized by the user or fully authorized by all parties. Moreover, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0094] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0095] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0096] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0097] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0098] The above embodiments are only used to illustrate the embodiments of this application, and are not intended to limit the embodiments of this application. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of this application. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of this application, and the patent protection scope of the embodiments of this application should be defined by the claims.

Claims

1. A processor, characterized in that, include: Request unit; The request unit is used to send a first request corresponding to each write instruction to the bus, and the first request is used to obtain write permission. The transmission order of the first requests corresponding to each write instruction on the bus is arbitrary; The request unit is further configured to, in response to any write instruction obtaining write permission, update the global sequence number after determining that all preceding write instructions of any write instruction have obtained write permission, wherein the global sequence number is used to identify the currently executing write instruction; the preceding write instruction refers to the write instruction executed first. The request unit is further configured to send a second request corresponding to any one of the write instructions to the bus, the second request being used to write the data to be written to the corresponding write address; the transmission order of the second request corresponding to any one of the write instructions on the bus is arbitrary.

2. The processor according to claim 1, characterized in that, The processor further includes a sequence preservation unit, which is connected to the request unit; The sequence-preserving unit is used to add a sequence number identifier to each write instruction according to the order in which the write instructions are received.

3. The processor according to claim 2, characterized in that, The request unit is specifically used for: Based on the sequence number of any one of the write instructions, it is determined that all preceding write instructions of any one of the write instructions have obtained write permission.

4. The processor according to claim 3, characterized in that, The global sequence number is stored in the sequence-preserving unit; The request unit is specifically used to: in response to obtaining write permission from any write instruction, send the sequence number identifier corresponding to the any write instruction to the sequence preservation unit; The sequence preservation unit is used to compare the sequence number identifier corresponding to any one of the write instructions with the global sequence number. If the comparison is consistent, the unit sends a first query result to the request unit. The first query result is used by the request unit to determine that all preceding requests of any one of the write instructions have obtained write permission. Update the global serial number.

5. The processor according to claim 2, characterized in that, The processor further includes a memory access unit; the memory access unit is connected to the order-preserving unit; the memory access unit is used for: After detecting the current triggered streaming write mode, the received write commands are sent to the order-keeping unit in the order of reception.

6. The processor according to claim 2, characterized in that, The processor further includes a query unit and a private cache; the query unit is connected to the private cache, the order preservation unit, and the request unit, respectively. After adding a sequence number identifier to each of the write instructions, the sequence preservation unit is further configured to: send each of the write instructions to the query unit; The query unit is used to query the hit status of the cache line corresponding to each write instruction in the private cache; generate request information for each write instruction based on the hit status; the request information includes data cache status and write permission status; and send the request information of each write instruction to the request unit; the order in which the request information of each write instruction is sent is arbitrary.

7. The processor according to claim 6, characterized in that, Before sending the first request corresponding to each of the write instructions to the bus, the request unit is further configured to: Based on the request information, the write permission status of the write instruction is determined to be no write permission. Before sending the second request corresponding to any one of the write instructions to the bus, the request unit is further configured to: Based on the request information, the data cache status in the request information of any one of the write instructions is determined to be a miss status.

8. The processor according to claim 1, characterized in that, After determining that all preceding write instructions of any one write instruction have obtained write permission, the request unit is further configured to update the global status identifier corresponding to any one write instruction from globally invisible to globally visible.

9. The processor according to claim 8, characterized in that, The request unit is also used for, In response to a first request for an off-core write instruction, it is determined whether there is an associated write instruction in the requesting unit, wherein the write address of the associated write instruction is the same as the write address of the off-core write instruction; the off-core write instruction is a write instruction to be executed by another processor. If the associated write instruction exists in the request unit, determine whether the global status identifier of the associated write instruction is globally visible; When the global status identifier is globally visible, a first response message is generated for the first request of the off-core write instruction; the first response message is used to return the latest write data of the write address corresponding to the off-core write instruction; When the global state identifier is globally invisible, the write permission of the associated write instruction in the request unit is invalidated, and a second response message is generated for the first request of the off-core write instruction. The second response message is used to indicate that the requesting unit does not hold the latest write data for the write address corresponding to the off-core write instruction.

10. A memory access control method, characterized in that, Applied to the processor as described in any one of claims 1 to 9; the method comprises: The request unit sends a first request corresponding to each write instruction to the bus, and the first request is used to obtain write permission; the transmission order of the first requests corresponding to each write instruction on the bus is arbitrary. The request unit obtains write permission in response to any write instruction. After determining that all preceding write instructions of any write instruction have obtained write permission, the global sequence number is updated. The global sequence number is used to identify the currently executing write instruction. The request unit sends a second request corresponding to any one of the write instructions to the bus. The second request is used to write the data to be written to the corresponding write address. The transmission order of the second request corresponding to any one of the write instructions on the bus is arbitrary.

11. An electronic device, characterized in that, Includes a processor as described in any one of claims 1 to 9, the processor being configured to perform the method as described in claim 10.

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