High-speed data processing and switching method and system based on zynq ultra scale+mpsoCs

Abstract

The application discloses a high-speed data processing and exchanging method and system based on Zynq UltraScale+MPSoCs, and belongs to the technical field of data processing, and comprises the following steps: generating a nanosecond-level synchronization pulse by using the PL end of Zynq, collecting initial multi-modal data, analyzing transmission rate and integrity by using a double SERDES controller of the PL end, and constructing a dynamic data processing matrix; simulating and optimizing the data stream distribution of the PL end and the PS end by using a preset multi-data granularity scale, and generating an exchanging instruction set; combining an on-chip bus topology, forming a first data exchanging path through DMA-OCM interaction and a hardware accelerator adaptation, obtaining a second data exchanging path through adjustment of sub-channel distribution and bus priority; and writing the running state parameters of the second data exchanging path back to the corresponding data frame state attribute column of the dynamic data processing matrix in real time, so that multi-modal data efficient processing and dynamic optimization are realized, and the system stability and transmission efficiency are improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of data processing, and in particular relates to a high-speed data processing and exchange method and system based on Zynq UltraScale+MPSoCs. BACKGROUND

[0002] Multi-modal data fuses multiple different types of information, such as original image detail information contained in a RAW image and rich spectral feature information contained in a hyperspectral cube, and can provide a system with a more comprehensive and accurate cognitive basis, thereby supporting more complex and intelligent decision-making and applications. However, existing multi-modal data processing and exchange technologies have exposed many deficiencies in the face of growing data volume and complex application requirements. In terms of data transmission rate, traditional acquisition and transmission methods are difficult to meet the rapid transmission requirements of large amounts of RAW image and hyperspectral cube data, resulting in poor real-time performance of data acquisition and failing to provide data support for subsequent processing in a timely manner. In terms of data integrity protection, due to interference, protocol defects and other problems in the transmission process, data is prone to loss, damage and other situations, affecting the accuracy of subsequent analysis results. Moreover, the processing requirements of different modal data differ greatly, and the existing data processing framework lacks effective dynamic allocation capabilities, making it difficult to flexibly optimize different data types and application scenarios, resulting in low processing efficiency and failing to fully utilize the advantages of multi-modal data. Zynq UltraScale+MPSoCs technology, as a multi-core heterogeneous system-on-a-chip technology that combines ARM processors and programmable logic, provides a new way and possibility to solve the above problems. SUMMARY

[0003] In view of the deficiencies of the prior art, the application provides a high-speed data processing and exchange method and system based on Zynq UltraScale+MPSoCs. A nanosecond-level synchronization pulse is generated by the PL end of Zynq to collect initial multi-modal data. The transmission rate and integrity are analyzed by the PL end double SERDES controller to construct a dynamic data processing matrix. The data stream allocation of the PL and PS ends is simulated and optimized according to a preset multi-data granularity scale to generate a set of exchange instructions. A first data exchange path is formed by DMA-OCM interaction and hardware accelerator adaptation in combination with the on-chip bus topology. A second data exchange path is obtained by adjusting the sub-channel allocation and bus priority. The running state parameters of the second data exchange path are written back to the corresponding data frame state attribute column of the dynamic data processing matrix in real time to realize efficient multi-modal data processing and dynamic optimization, thereby improving the system stability and transmission efficiency.

[0004] To achieve the above object, the application provides the following technical scheme:

[0005] The high-speed data processing and exchange method based on Zynq UltraScale+MPSoCs comprises:

[0006] The nanosecond-level synchronization pulse generated by the PL end of the Zynq triggers the multi-modal acquisition module to acquire initial multi-modal data, and the double SERDES controller of the PL end receives the initial multi-modal data and analyzes the transmission rate and integrity thereof, and constructs a dynamic data processing matrix; the initial multi-modal data comprises RAW images and hyperspectral cubes;

[0007] Based on the dynamic data processing matrix, the data flow allocation of the PL and PS ends is simulated and optimized through a preset multi-data granularity scale to generate a set of exchange instructions;

[0008] According to the set of exchange instructions, the data exchange path is reconstructed in combination with the on-chip bus topology of the Zynq UltraScale+MPSoCs, and through DMA-OCM interaction and hardware accelerator adaptation, a first data exchange path is formed;

[0009] The first data exchange path is quantitatively analyzed by using a bus load model integrating temperature feedback and cyclic redundancy check, and the sub-channel allocation and bus priority in the first data exchange path are adjusted according to the quantitative analysis result to obtain a second data exchange path;

[0010] The running state parameters of the second data exchange path are written back to the data frame state attribute column corresponding to the dynamic data processing matrix in real time; the running state parameters comprise actual throughput, delay and latest load coefficient.

[0011] Specifically, the double SERDES controller of the PL end receives the initial multi-modal data and analyzes the transmission rate and integrity of each initial multi-modal data to construct a dynamic data processing matrix, comprising:

[0012] In the PL end, the double SERDES controller receives the RAW image data stream and the hyperspectral cube data stream in the initial multi-modal data through respective independent physical links;

[0013] The state machine inside the double SERDES controller analyzes the header structure of the input data packet in real time and calculates the check sequence to obtain the key parameters of each frame of data, and generates a data validity flag for each frame of data based on the key parameters and a preset threshold; the key parameters comprise transmission rate parameters and integrity parameters;

[0014] The frame data from the dual SERDES controller is mapped and filled into a two-dimensional dynamic data processing matrix according to its data type, data validity flag, transmission rate and time stamp information at the time of collection as input attributes; the rows of the dynamic data processing matrix represent different data sources and data types, the columns represent data frame instances arranged in time sequence, and each cell stores a set of state attributes of the corresponding data frame.

[0015] Specifically, the generation process of the exchange instruction set includes:

[0016] Reading the constructed dynamic data processing matrix, based on the dynamic data processing matrix, predefining three data granularity scales of fine granularity, medium granularity and coarse granularity;

[0017] Taking the dynamic data processing matrix as input, running a lightweight simulator on the PS side, the lightweight simulator simulates different allocation strategies of data between the PL side and the PS side based on the three data granularity scales and outputs simulation results, including delay and throughput performance data evaluated;

[0018] The lightweight simulator allocates processing units for each data preprocessing task to be executed in the dynamic data processing matrix according to the simulation results, and specifies the corresponding data granularity scale for each data preprocessing task, and finally generates a structured exchange instruction set.

[0019] Specifically, the exchange instruction set includes preprocessing task instructions, computing power scheduling instructions and data transmission instructions; the preprocessing task instructions specify bad point repair of RAW graph and dark current correction operation of hyperspectral cube; the computing power scheduling instructions specify the number of accelerators on the PL side and CPUs on the PS side to be enabled.

[0020] Specifically, the formation process of the first data exchange path includes:

[0021] The system configuration manager reads the exchange instruction set, parses the key information from it, and at the same time calls the on-chip bus topology data of Zynq UltraScale+MPSoCs to determine the connection relationship of each node of the bus and the type of hardware accelerator;

[0022] Based on the key information and the on-chip bus topology, the system configuration manager plans a basic path framework for data transmission, determines that the initial interaction channel between the specified DMA controller and the OCM is established from the data output interface on the PL side, and obtains the DMA-OCM interaction channel.

[0023] According to the requirements of the preprocessing task in the exchange instruction set, the system configuration manager identifies the enabled hardware accelerator, queries the connection port of the hardware accelerator in the on-chip bus topology and accesses it into the established DMA-OCM interaction channel, completes the adaptation of the hardware accelerator and the channel by configuring the input and output interface parameters, data processing format and handshake protocol with the bus, and forms an integrated channel;

[0024] The integrated channel is subjected to integrity verification, the configurations of the nodes are checked for consistency with the exchange instruction set, and after the data is output from the PL end, it is confirmed whether the full path of the data from the scheduling of the DMA controller, the processing of the hardware accelerator and the completion of the data temporary storage or forwarding through the OCM is smooth, forming a first data exchange path.

[0025] Specifically, the on-chip bus topology of the Zynq UltraScale+MPSoCs includes AXI4-Stream high-speed bus and AXI4-Lite control bus, and when reconstructing the data exchange path, the data routing between different buses is completed by configuring the bus interconnection matrix.

[0026] Specifically, the quantitative analysis using the bus load model fused with temperature feedback and cyclic redundancy check includes:

[0027] During the operation of the first data exchange path, the temperature sensor data of the on-chip bus exchange node and the data error rate calculated through cyclic redundancy check are collected in real time;

[0028] The system calls the bus load model fused with temperature feedback and cyclic redundancy check, and uses the collected temperature sensor data and the calculated data error rate as input parameters of the bus load model together, and substitutes them into the built-in bus load evaluation function of the bus load model;

[0029] The bus load evaluation function is used to operate the input temperature sensor data and data error rate, and the load coefficient and stability score of the current first data exchange path are calculated respectively, and they are used as the quantitative analysis result of the first data exchange path together.

[0030] Specifically, the adjustment of the sub-channel allocation and bus priority in the first data exchange path according to the quantitative analysis result to obtain the second data exchange path includes:

[0031] The path scheduler obtains the quantitative analysis result of the first data exchange path, and compares the load coefficient in the quantitative analysis result with the preset load threshold;

[0032] If the load coefficient exceeds the preset load threshold, the path scheduler adjusts the subchannel allocation in the first data exchange path to obtain an adjusted subchannel allocation scheme; the adjustment includes: splitting the wide subchannel originally allocated to the hyperspectral cube data into multiple narrow subchannels, and separately allocating an independent subchannel to the RAW graph data;

[0033] The path scheduler adjusts the bus priority of the data flow on the basis of the adjusted subchannel according to the real-time requirement of the data flow, to obtain a bus priority setting; the real-time requirement is that the real-time transmission requirement of the RAW graph data is higher than that of the hyperspectral cube data.

[0034] The path scheduler generates corresponding path configuration parameters according to the adjusted subchannel allocation scheme and the bus priority setting, and reconstructs the first data exchange path by using the path configuration parameters to obtain a second data exchange path.

[0035] The high-speed data processing and exchange system based on Zynq UltraScale+MPSoCs includes a data acquisition module, a matrix construction module, an instruction generation module, an exchange path construction module, a path optimization module and a state feedback module.

[0036] The data acquisition module is configured to trigger and acquire initial multi-modal data.

[0037] The matrix construction module is configured to receive the initial multi-modal data, analyze data transmission quality, and construct a structured dynamic data processing matrix.

[0038] The instruction generation module is configured to optimize the algorithmic power allocation of the PL end and the PS end based on the information of the dynamic data processing matrix, and generate a structured exchange instruction set.

[0039] The exchange path construction module is configured to construct a first data exchange path according to the exchange instruction set and in combination with an on-chip bus topology.

[0040] The path optimization module is configured to adjust the subchannel allocation and the bus priority by quantitatively analyzing the running state of the first data exchange path, and generate a second data exchange path.

[0041] The state feedback module is configured to collect the running state parameters of the second data exchange path and write them back to the dynamic data processing matrix in real time.

[0042] Compared with the prior art, the present application has the following advantages:

[0043] 1. The application proposes a high-speed data processing and switching system based on Zynq UltraScale+MPSoCs, and optimizes and improves the architecture, operation steps and processes, the system has the advantages of simple process, low investment and operation cost, and low production cost.

[0044] 2. The application proposes a high-speed data processing and switching method based on Zynq UltraScale+MPSoCs, generates nanosecond-level synchronization pulses on the PL side of Zynq, can accurately trigger multi-modal acquisition modules to synchronously acquire RAW images and hyperspectral cube data, analyzes the data transmission rate and integrity with the help of double SERDES controllers, and constructs a dynamic data processing matrix to realize clear control of data state; at the same time, through multi-data granularity scale simulation optimization of PL and PS end data flow distribution, combined with on-chip bus topology and DMA-OCM interaction, hardware accelerator adaptation to build the first data exchange path, improve the accuracy and efficiency of multi-modal data acquisition and preliminary transmission, meet the basic needs of high-speed processing.

[0045] 3. The application proposes a high-speed data processing and switching method based on Zynq UltraScale+MPSoCs, quantitatively analyzes the first data exchange path by fusing temperature feedback and cyclic redundancy check bus load model, adjusts sub-channel allocation and bus priority according to the quantitative analysis result to obtain the second data exchange path, which can dynamically optimize data transmission performance and avoid transmission problems caused by high load or priority confusion; and the running state parameters of the second data exchange path are written back to the dynamic data processing matrix in real time, forming a closed-loop optimization mechanism, which can continuously provide accurate reference for data processing and switching, guarantee the long-term stable and efficient operation of the whole system, and is suitable for scenes with high requirements for multi-modal data processing timeliness and stability. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figure 1 The application is a high-speed data processing and switching method based on Zynq UltraScale+MPSoCs;

[0047] Figure 2 The application is a high-speed data processing and switching method based on Zynq UltraScale+MPSoCs;

[0048] Figure 3 The application is a high-speed data processing and switching system based on Zynq UltraScale+MPSoCs. DETAILED DESCRIPTION

[0049] Example 1:

[0050] Please refer to Figure 1 andFigure 2 In one embodiment, the application provides a high-speed data processing and switching method based on Zynq UltraScale+MPSoCs, which comprises steps S1-S5.

[0051] S1: A nanosecond-level synchronization pulse is generated at the PL end of Zynq to trigger the acquisition of initial multi-modal data by the multi-modal acquisition module. The dual SERDES controller at the PL end receives the initial multi-modal data and analyzes its transmission rate and integrity, and constructs a dynamic data processing matrix. The initial multi-modal data includes RAW images and hyperspectral cubes.

[0052] Further, when the PL end generates a nanosecond-level synchronization pulse, a phase-locked loop is used for frequency division and frequency multiplication processing of the reference clock to generate a synchronization pulse with a jitter of less than 50 picoseconds. The pulse width of the synchronization pulse is 10-100 nanoseconds, which is used to trigger the multi-modal acquisition module to start the acquisition of RAW images and hyperspectral cubes synchronously. 1 picosecond is equal to 10 to the power of -12 seconds, and 1 nanosecond is equal to 10 to the power of -9 seconds.

[0053] Further, the RAW images reflect morphological details, and the hyperspectral cubes reflect internal component distribution.

[0054] S2: Based on the dynamic data processing matrix, the data flow allocation of the PL and PS ends is simulated and optimized through a pre-set multi-data granularity scale to generate a switching instruction set.

[0055] The switching instruction set includes pre-processing task instructions, computing power scheduling instructions, and data transmission instructions. The pre-processing task instructions specify bad pixel repair of RAW images and dark current correction operations of hyperspectral cubes. The computing power scheduling instructions specify the number of accelerators at the PL end and CPUs at the PS end to be enabled.

[0056] S3: According to the switching instruction set, the data switching path is reconstructed in combination with the on-chip bus topology of Zynq UltraScale+MPSoCs, and the first data switching path is formed through DMA-OCM interaction and hardware accelerator adaptation.

[0057] The on-chip bus topology of Zynq UltraScale+MPSoCs includes AXI4-Stream high-speed bus and AXI4-Lite control bus. When the data switching path is reconstructed, the data routing between different buses is completed through the configuration of the bus interconnection matrix.

[0058] Further, SERDES is a serializer / deserializer, OCM is on-chip memory, and DMA is direct memory access.

[0059] S4: quantitatively analyze the first data exchange path by using a bus load model fusing temperature feedback and cyclic redundancy check, and adjust the sub-channel allocation and bus priority in the first data exchange path according to the quantitative analysis result to obtain a second data exchange path;

[0060] S5: write the running state parameters of the second data exchange path back to the data frame state attribute column of the corresponding dynamic data processing matrix in real time; the running state parameters include actual throughput, delay and latest load coefficient.

[0061] Further, the specific steps of S5 include:

[0062] (1) The system deploys a state monitoring module at the key nodes of the second data exchange path; the key nodes include the PL end data output interface, the transmission cache of the DMA controller, the processing port of the hardware accelerator and the read-write interface of the OCM; the monitoring module directly accesses the hardware register to real-time capture the original running state data of the path at runtime, wherein the actual achieved throughput is calculated by counting the number of bytes successfully transmitted by each node per unit time, the delay is determined by recording the time difference between when the data frame enters the path from the PL end and when the OCM completes storage, and the latest load coefficient is calculated in real time by calling the bus load model;

[0063] (2) The state monitoring module performs format standardization processing on the captured original running state data, converts the throughput, delay and load coefficient into a unified data format according to the field definition of the data frame state attribute column in the dynamic data processing matrix, for example, converts the throughput into an integer form of megabytes per second, converts the delay into an integer form of nanoseconds, ensures that the written data can be correctly recognized by the matrix, and adds a timestamp to each state parameter, which maintains the same reference as the timestamp when the data frame is collected, for accurate correspondence to specific data frame instances;

[0064] (3) The system establishes a communication link between the state monitoring module and the storage area of the dynamic data processing matrix through a dedicated control channel of the on-chip bus, and adopts an interrupt triggering mechanism in the communication process; when the state parameters are updated, the state monitoring module sends an interrupt request to the matrix controller, and the matrix controller starts data transmission after responding; in the transmission process, the physical storage address of the state attribute column of the corresponding data frame in the dynamic data processing matrix is directly located through hardware-level address mapping, avoiding the delay caused by software layer addressing;

[0065] (4) The matrix controller first performs integrity check on the target storage address before writing data, and confirms that the storage area has not been damaged by comparing the current stored check value with the preset value, and after the check is passed, the matrix controller writes the standardized running state parameters in the corresponding data frame state attribute column in field order, covering the original old data, and after the writing is completed, the matrix controller reads the parameter value written and compares it with the original value of the sending end to ensure that there is no error in the data transmission process, and if inconsistency is found, the retransmission mechanism is triggered immediately until the writing is correct;

[0066] (5) After completing parameter writing, the matrix controller updates the global state flag of the dynamic data processing matrix, marks the state of the corresponding data frame as updated, and records the operation log of this writing, including writing time, operation result and hardware module number involved, at the same time, the log information is transmitted to the non-volatile storage area of the PS end through DMA, ensuring that the system can still be traced after power failure.

[0067] Further, the Zynq UltraScale+MPSoCs is a multi-core heterogeneous system-on-chip integrating a high-performance processing system (PS) and a flexible programmable logic (PL). The PS part usually includes a quad-core 64-bit Arm Cortex-A53 application processing unit and a dual-core Arm Cortex-R5 real-time processing subsystem, and the PL part is based on the UltraScale architecture of Xilinx, and has logic resources including logic cells, configurable logic blocks and high-speed serial transceivers. In the Zynq UltraScale+MPSoCs, the PS and the PL are closely cooperated through a high-speed internal bus and a memory interface. The PS serves as the control center of the system, and can configure and manage the hardware logic in the PL, and call the hardware acceleration function in the PL according to different application scenarios and task requirements. For example, in a video processing application, the PS can transmit video data to the customized video codec hardware accelerator in the PL for fast processing, and then the PS performs analysis and application layer operation after the processing is completed. This mode of cooperative work of software and hardware not only fully utilizes the high-performance computing and system management capabilities of the PS, but also utilizes the hardware customization acceleration advantages of the PL, so that the system can realize efficient data processing and exchange when facing high-load and complex application scenarios such as multi-modal data processing, and can reduce system power consumption and improve overall performance while ensuring processing speed.

[0068] Further, the overall logic can be summarized as follows: generate nanosecond-level synchronization pulses using the high-speed timing control capability of the Zynq PL end to ensure that multi-modal acquisition modules such as cameras and spectrometers are strictly synchronized in time, avoid data time deviation, and configure the dual SERDES controller into multi-channel mode to receive RAW images and hyperspectral cubes respectively, and through the built-in check logic to count the transmission error rate, and finally write the analysis results to the dynamic data processing matrix; the PS end analyzes the dynamic data processing matrix through software algorithms, divides the PL / PS task boundary according to the data granularity, such as assigning the FFT processing of the hyperspectral cube to the PL end DSP slice and assigning the data alignment logic to the PS end Cortex-A53, and the instruction set is stored in the bus protocol format; the PL end logic configures the DMA channel according to the instructions, writes the initial multi-modal data received by the SERDES to the OCM through the AXI bus, and at the same time activates the interface logic of the hardware accelerator to directly read the data from the OCM for preprocessing, the bus connection relationship in the path is dynamically reconstructed through the configuration register to form the first data exchange path; the PL end temperature sensor sends the temperature sensor data to the PS end in real time through the AXI-Lite bus, the PS end combines the CRC check result to run the load model algorithm to calculate the path optimization parameters, adjusts the priority through the PL end bus arbiter, and resets the DMA channel mapping to realize sub-channel allocation, finally writes the optimized path state parameters back to the storage unit of the dynamic data processing matrix, and completes the closed loop.

[0069] For example, taking the multi-modal data collected for the growth state of edible fungi as an example, the high-speed data processing and exchange process based on Zynq UltraScale UltraScale+MPSoCs is as follows:

[0070] The PL end generates nanosecond-level synchronization pulses to trigger the multi-modal acquisition module to synchronously shoot the RAW image and hyperspectral cube of the edible fungus. The double SERDES controller of the PL end receives the two types of data through independent physical links: one receives the RAW image data stream, and the other receives the hyperspectral cube data stream. The internal state machine of the controller analyzes the data packet header in real time, calculates the check sequence, obtains the transmission rate of each frame of data, such as 30 frames per second of the RAW image and 10 frames per second of the hyperspectral cube, and the integrity parameters such as the packet loss rate, and compares them with the preset threshold to generate a data validity flag, such as no loss of data. Subsequently, the system maps the data type, validity flag, transmission rate and acquisition timestamp to a dynamic data processing matrix: the rows of the matrix distinguish between the two types of data sources, the columns arrange the frame instances in time sequence, and each cell stores the state attributes of the corresponding frame, such as RAW image-valid-30 frames / second-10:00:00. The system reads the dynamic data processing matrix, and based on the characteristics of the RAW image and the hyperspectral cube recorded therein, it predefines the data granularity: fine granularity corresponds to local area cropping of the RAW image, medium granularity corresponds to waveband filtering of the hyperspectral cube, and coarse granularity corresponds to overall data compression. The PS end lightweight simulator takes the matrix as input and simulates the PL / PS distribution strategy based on the three granularities: for example, fine-grained tasks such as RAW image bad pixel repair are assigned to the PL end accelerator, and coarse-grained tasks such as hyperspectral cube dark current correction are processed by the PS end CPU in cooperation. The simulation output delay and throughput are used to allocate units for preprocessing tasks, such as enabling 2 PL accelerators to process RAW images and specifying the granularity, to generate an exchange instruction set containing preprocessing instructions, computing power scheduling instructions and data transmission instructions. The preprocessing instructions are, for example, bad pixel repair and dark current correction, the computing power scheduling instructions are, for example, enabling 2 PL accelerators and 1 PS CPU, and the data transmission instructions are, for example, RAW image DMA to OCM. The system configuration manager analyzes the exchange instructions, calls the on-chip bus topology, and explicitly enables the bad pixel repair accelerator on the PL end and the dark current correction accelerator on the PS end. First, the basic path is planned: from the PL end data output interface to the OCM through the DMA controller to establish an interactive channel, the DMA is configured in burst transmission mode, then the bad pixel repair accelerator is connected to the channel, the input interface is configured in RAW image format, and the output is handshake with the AXI4-Stream bus, the adaptation is completed to form an integrated channel, and finally the channel is checked: after confirming that the RAW image is output from the PL, it is scheduled by the DMA, repaired by the accelerator, and then stored in the OCM, the whole path is smooth, forming the first data exchange path.The first data exchange path runs, and the temperature and cyclic redundancy check data error rate of the bus exchange node are collected in real time. The bus load model is called, the temperature and error rate are substituted into the evaluation function, the load coefficient and stability score are calculated, and the path scheduler adjusts accordingly: the wide sub-channel originally occupied by the hyperspectral cube is split into three narrow sub-channels, and the RAW graph is allocated an independent sub-channel. This is because the RAW graph needs to provide real-time feedback on morphological changes, and its bus priority needs to be improved. Configuration parameters are generated to reconstruct the path, and the second data exchange path is obtained. During the operation of the second data exchange path, the state monitoring module captures the actual throughput, delay, and load coefficient through the hardware register, standardizes them, adds a timestamp, and writes them to the attribute column of the corresponding frame of the dynamic data processing matrix through the dedicated control channel interrupt trigger. After the dynamic data processing matrix is updated, it provides a basis for the granularity division and instruction generation of the next round of data collection, forming a closed loop. Through the above process, high-speed synchronous processing and dynamic optimization of edible mushroom multi-modal data are realized, meeting the real-time monitoring requirements.

[0071] The double SERDES controller at the PL end receives the initial multi-modal data and analyzes the transmission rate and integrity of each initial multi-modal data, and constructs a dynamic data processing matrix, including:

[0072] S1.1: At the PL end, the double SERDES controller receives the RAW graph data stream and hyperspectral cube data stream in the initial multi-modal data through independent physical links respectively;

[0073] Further, the specific steps of S1.1 include:

[0074] (1) According to the transmission characteristics of the RAW graph data stream and the hyperspectral cube data stream, independent physical channels are allocated to the double SERDES controller, including dedicated transceiver pins, transmission media and isolation circuits, to ensure that the two links have no signal interference at the physical layer. At the same time, according to the data format and transmission rate requirements of the RAW graph and the hyperspectral cube, the two SERDES controllers are initialized and configured: the data encoding method uses 8B / 10B encoding to ensure the reliability of transmission, and the clock frequency is configured to match the output frequency of the corresponding data source, avoiding data sampling errors caused by clock deviation;

[0075] (2) After completing the physical layer and initialization configuration, the two SERDES controllers start link training respectively: by sending and receiving training sequences to detect the signal quality of their respective links, and automatically adjusting the equalizer parameters to compensate for signal attenuation and distortion in the transmission process, until the link reaches a stable transmission state;

[0076] (3) After the completion of link training, configure the receiving buffer parameters: the SERDES controller corresponding to the RAW image data stream sets the internal receiving buffer to a cache depth matching the RAW image frame size, ensuring that a complete RAW image frame can be temporarily stored without overflow; the SERDES controller corresponding to the hyperspectral cube data stream configures a larger cache space for the receiving buffer and uses a segmented storage mechanism to store the hyperspectral cube by band or spatial region;

[0077] (4) When the data source starts sending data, the RAW image data stream is transmitted to the corresponding SERDES controller through a dedicated physical link. The controller receives the input serial signal, performs deserialization processing, converts the high-speed serial data into parallel data, and identifies the start and end markers of the data frame through an internal synchronization detection circuit. The effective data of each RAW image frame is extracted, and the controller checks the data in real time during the extraction process. The integrity of the data block is determined by checking the check code at the frame header and frame tail. If an error is found, the data block is marked and the retransmission mechanism is triggered.

[0078] (5) The hyperspectral cube data stream is transmitted to the corresponding SERDES controller through a dedicated physical link. The controller receives the input serial signal and performs deserialization processing to convert the high-speed serial data into parallel data. After parallel processing, the hyperspectral data enters the controller, and the dimension analysis unit parses the serially transmitted data stream into a three-dimensional structure according to the preset hyperspectral cube data format, including the number of bands, spatial resolution, etc. The data block of each band is independently checked and marked, and the parsed hyperspectral data is stored in the corresponding partition of the receiving buffer according to the band order.

[0079] (6) During data reception, the two SERDES controllers monitor the transmission status of their respective links in real time through the internal state monitoring module, including the current data transmission rate, error rate, buffer occupancy rate, etc. These state information is fed back to the upper layer control logic in real time.

[0080] (7) The upper layer control logic dynamically adjusts according to the feedback state information: if the transmission rate of any link decreases or the error rate exceeds the standard, the SERDES controller parameters of that link are adjusted in time, such as increasing the compensation strength of the equalizer or adjusting the clock phase, to restore the normal transmission performance of the link. At the same time, because the controllers use independent control signals and interrupt mechanisms, when one of the links completes the reception of a frame of data, it will trigger the corresponding interrupt signal separately, ensuring that the reception process of the RAW image data stream and the hyperspectral cube data stream is independent and efficient.

[0081] S1.2: The state machine inside the dual SERDES controller analyzes the packet header structure of the input data packet in real time and calculates the check sequence, obtains the key parameters of each frame of data, and generates a data validity flag for each frame of data based on the key parameters and the preset threshold; the key parameters include the transmission rate parameter and the integrity parameter;

[0082] Further, the specific steps of S1.2 include:

[0083] (1) The state machine inside the dual SERDES controller is initially in an initialization state, at which time the preset packet header structure analysis rule and check sequence calculation algorithm, such as CRC32, are loaded, and the transmission rate threshold range and integrity parameter threshold configured by the system are read, after the initialization is completed, the state machine switches to an idle state, and waits for data packet input; the transmission rate threshold and the integrity parameter threshold are respectively set according to the RAW graph and the hyperspectral cube to adapt to the different requirements of the two types of data streams, wherein CRC32 is a prior art content in the field and is not the inventive scheme of the present application, and is not described here;

[0084] (2) When the data packet starts to be input, the state machine in the idle state switches to a packet header detection state, and identifies the preset packet header start flag sequence by continuously monitoring the bit stream of the input data;

[0085] (3) Once the packet header start flag is detected, the state machine enters a packet header analysis state, and according to the field order defined by the packet header structure, the data type identifier, frame number, expected data length, timestamp and other information in the packet header are extracted in turn, and the system clock count at which the analysis starts is recorded;

[0086] (4) During the packet header analysis process, the state machine synchronously starts a check sequence calculation process, and according to the preset check algorithm, the data in the packet header is operated byte by byte to generate a packet header check value, which is compared with the check field carried in the packet header, if the comparison is consistent, it is confirmed that the packet header analysis is valid, and the state machine enters a data frame receiving state; if the comparison is inconsistent, it is marked as a packet header error, and a packet header re-analysis mechanism is triggered to return to the packet header detection state to re-detect and analyze the packet header of the data packet;

[0087] (5) After entering the data frame receiving state, the state machine starts to receive the valid data part in the data packet, and records the starting receiving clock of the frame of data, during the receiving process, the state machine performs full-range check sequence calculation on the valid data part, and statistically calculates the actual number of data bytes in real time;

[0088] (6) After receiving the valid data part, the state machine records the end-receiving clock of the frame data, calculates the byte amount transmitted per unit time according to the actual byte number, obtains the transmission rate parameter of the current frame, and compares the check result of the entire data frame with the check sequence at the tail of the data packet to obtain the integrity parameter reflecting whether the data is complete, such as the bit error rate or the packet loss identifier;

[0089] (7) After the data frame parameter calculation is completed, the state machine enters the parameter judgment state, compares the transmission rate parameter with the preset transmission rate threshold range: if it is within the transmission rate threshold range, it is determined that the transmission rate is normal; if it is lower or higher than the transmission rate threshold range, it is marked that the transmission rate is abnormal, and the integrity parameter such as the bit error rate is compared with the preset integrity parameter threshold: if the bit error rate is lower than the preset integrity parameter threshold and there is no packet loss identifier, it is determined that the data is complete; if the bit error rate is higher than the preset integrity parameter threshold or there is packet loss, it is marked that the integrity is abnormal;

[0090] (8) According to the parameter judgment result, the state machine generates a data validity flag: when the transmission rate is normal and the data is complete, an effective flag is generated; if any parameter is abnormal, an invalid flag is generated, and the specific abnormal type information such as low rate and check error is embedded in the flag; the validity flag generated is bound with the key parameters of the frame data, and is stored in the internal register of the controller, then the state machine is reset to the idle state, and is ready to receive the next frame data.

[0091] S1.3: Each frame data from the dual SERDES controller is mapped and filled into a two-dimensional dynamic data processing matrix according to its data type, data validity flag, transmission rate and time stamp information at the time of collection as input attributes; the rows of the dynamic data processing matrix represent different data sources and data types, the columns represent data frame instances arranged in time sequence, and each cell stores the above state attribute set of the corresponding data frame.

[0092] Further, the specific steps of S1.3 include:

[0093] (1) The dynamic data processing matrix is started and initialized to configure the matrix row structure according to the data source type and data type received by the dual SERDES controller: one row is allocated for RAW image data type and another row is allocated for hyperspectral cube data type, the identification information of each row is bound with the corresponding data type and data source, and the time sequence reference of the column is set to determine the arrangement interval and initial index of the column, and the matrix basic framework is built;

[0094] (2) When the dual SERDES controller outputs each frame of data, the input attributes of each frame of data are extracted and analyzed: the data type identifier is separated from the data frame header information, the data validity flag is read, the transmission rate value is extracted, and the nanosecond-level timestamp at the time of acquisition is obtained. The attribute information is standardized in format, the timestamp is converted into a system time format consistent with the matrix array reference, and the transmission rate is converted into a fixed unit value, ensuring the uniformity of the attribute information format;

[0095] (3) Based on the analyzed data type identifier, the corresponding row index in the dynamic data processing matrix is matched: when the data type is RAW graph, the corresponding row of the RAW graph is located; when it is hyperspectral cube, the corresponding row of the hyperspectral cube is located, and if there is an undefined new data type, the matrix row expansion mechanism is triggered to automatically add a row and mark the corresponding data source and data type, ensuring that the data frame can find a matching row.

[0096] (4) The standardized timestamp is compared with the time sequence reference of the matrix array, and the corresponding column index is calculated: if the timestamp is within the time range of the existing column, it is directly located to the corresponding column; if it exceeds the maximum time range of the existing column, a new column is added at the tail of the matrix and the column time sequence identifier is updated; if it is between two columns, it is inserted into a new column or merged into the adjacent column according to the preset interpolation rule, ensuring that the columns are arranged in chronological order;

[0097] (5) After the row and column positioning is completed, the standardized attribute set of the frame of data is filled into the corresponding cell: the old data in the cell is emptied first, and then the attribute information is written in sequence; a secondary check is performed during filling to check the matching of the data validity flag and the data, the rationality of the transmission rate, and the consistency of the timestamp and the column sequence, and if they do not match, the cell is marked as abnormal and the reason is recorded; the standardized attribute set is a four-tuple of data type, data validity flag, transmission rate, and timestamp;

[0098] (6) After filling is completed, the global state information of the matrix is updated: the filling situation of each row and column, the proportion of valid data frames, the transmission rate distribution of each data type, etc. are counted and stored in the matrix metadata area, and the storage space usage is monitored. If it approaches the preset upper limit, the data aging mechanism is triggered to delete the cell content of the earliest data frame according to the time sequence, making room for new data frames. The global state information includes valid data frame time distribution, different data type transmission rate range, and data validity flag statistical results;

[0099] (7) Based on the data stored in the dynamic data processing matrix, a mapping table of data type, timestamp, and cell position is established and updated in real time: when a new data frame is filled or an old data frame is deleted, the index table is updated synchronously to ensure that the index information is consistent with the actual data of the matrix. At this time, the dynamic data processing matrix enters a state of waiting to receive the next batch of data frames.

[0100] The generation process of the exchange instruction set includes:

[0101] S2.1: Read the built dynamic data processing matrix, and predefine three data granularity scales of fine granularity, medium granularity and coarse granularity based on the dynamic data processing matrix;

[0102] Further, the specific steps of S2.1 include:

[0103] (1) The system starts the reading mechanism of the dynamic data processing matrix, accesses the matrix storage area through the internal bus interface, reads the corresponding data source type, data frame number and state attribute set of each cell in row priority order, simultaneously parses the global state information in the matrix metadata, and temporarily stores it in the system temporary buffer area to form the basic data set for data feature analysis;

[0104] (2) Based on the basic data set in the temporary buffer area, the system performs classification feature analysis on the data attributes: for RAW image data type, the resolution, pixel depth and effective pixel ratio in each frame are extracted, and the pixel change rate of adjacent frames is calculated; for hyperspectral cube data type, the number of wavebands, spatial dimensions and spectral resolution of each waveband are analyzed, the data redundancy between wavebands is counted, and by comparing the data features at different timestamps, the change law of data in spatial and temporal dimensions is identified, such as large inter-frame difference in RAW image fast motion scene and high stability of specific waveband data in hyperspectral cube;

[0105] (3) According to the data feature analysis results, the system predefines the division rules of three data granularity scales of fine granularity, medium granularity and coarse granularity:

[0106] The fine granularity scale: the processing unit is the local sub-region within the data frame, the RAW image corresponds to a 128x128 pixel block, and the hyperspectral cube corresponds to a single waveband and a 256x256 spatial region block, the division is based on the local feature difference within the data frame, and when the pixel change rate of any region exceeds the preset pixel change rate threshold, it is automatically divided into a fine granularity unit, and the unit attribute includes the original data position coordinates, data size, and validity flag;

[0107] The medium granularity scale: the processing unit is a complete data frame after moderate compression or dimension simplification, the RAW image is a complete frame without invalid pixels on the edge, and the hyperspectral cube is a multi-waveband combination by merging consecutive wavebands, such as 10 adjacent wavebands merged into one comprehensive waveband, the division standard is the balance between data transmission rate and processing efficiency, and it is enabled when the data transmission rate is in the medium range;

[0108] The coarse granularity scale: the processing unit is a set of multiple continuous data frames, the RAW graph is an average frame of 10 consecutive frames, and the hyperspectral cube is a simplified cube extracted from key bands, such as retaining 5 core spectral information bands, and the spatial resolution is reduced to 1 / 4 of the original, and the division is based on data time continuity and redundancy, and when the change rate of multiple consecutive frames is lower than the preset frame change rate threshold and the transmission rate is higher, the coarse granularity scale is used;

[0109] (4) The system establishes a mapping relationship table of granularity scales and data attributes, and associates fine granularity, medium granularity, and coarse granularity with attributes such as local feature difference of data frames, transmission rate range, and time continuity, such as that a local pixel change rate of a RAW graph greater than 30% corresponds to fine granularity, and a transmission rate of 100-500 MB / s corresponds to medium granularity, and that each granularity scale is configured with a processing priority, wherein fine granularity is the highest and coarse granularity is the lowest, to ensure that data flow distribution schedules resources according to priority;

[0110] (5) The system stores the three granularity scale division rules and the mapping relationship table in the extended attribute area of the dynamic data processing matrix, associates it with the original data frame attribute set, and adds a granularity identification column in the matrix, automatically marks the applicable granularity scale type according to the attributes of each data frame, and after completion, releases the temporary buffer area resources, and the matrix enters a state of waiting to receive the next round of data frames to update the granularity scale adaptation state.

[0111] S2.2: With the dynamic data processing matrix as input, a lightweight simulator is run on the PS side, which simulates different allocation strategies of data between the PL side and the PS side based on the three data granularity scales and outputs simulation results, including delay and throughput performance data evaluated;

[0112] Further, the specific steps of S2.2 include:

[0113] (1) The system extracts the data set to be simulated from the dynamic data processing matrix, filters continuous valid data frames according to data type and time sequence, reads the granularity scale identification, transmission rate, and timestamp information corresponding to each frame, packages them according to type, and then transmits them to the specified storage area on the PS side through the on-chip bus to form the input data source of the lightweight simulator;

[0114] (2) Start the lightweight simulator on the PS side and load the preset simulation environment parameters; the simulation environment parameters include resource configuration of the PL side hardware accelerator, operation ability of the PS side CPU core, and transmission bandwidth limitation of the on-chip bus, and the simulation environment parameters are set based on the actual hardware specifications of Zynq UltraScale+MPSoCs to ensure that the simulation environment is consistent with the physical hardware characteristics, and the lightweight simulator is initialized;

[0115] (3) After the lightweight simulator is initialized, a distribution strategy library is constructed based on three data granularity scales: fine-grained data design PL end processing gradient strategy of 80% to 100%, medium-grained data design PL end processing strategy of 50% to 79%, and coarse-grained data design PL end processing strategy of 20% to 49%; each strategy specifies the number of sub-units processed by the PL end, the number of frames processed by the PS end, and the data interaction trigger condition;

[0116] (4) The lightweight simulator reads data in the input data source frame by frame in time sequence, and matches the corresponding strategy subset in the distribution strategy library according to the granularity identifier of each frame of data. For example, for fine-grained RAW image data using the PL end processing 90% strategy, 90% of the local pixel blocks are allocated to the PL end hardware accelerator, and the accelerator startup delay, bus time consumption for data transmission to the accelerator, and processing completion time are recorded. At the same time, the lightweight simulator allocates the remaining 10% of the pixel blocks to the PS end CPU, calculates the CPU scheduling delay, the time for data loading from OCM to memory, and the software algorithm processing time consumption;

[0117] (5) During the simulation process, the lightweight simulator monitors the data interaction node state in real time: when the data processed by the PL end needs to be transmitted to the PS end, the DMA controller channel occupation situation is simulated, and the delay caused by bus competition is calculated; when the PS end processing result needs to be fed back to the PL end, the interrupt response time and data back transmission bandwidth loss are simulated; for multiple consecutive data, the concurrent processing capability of the strategy is evaluated, and the additional delay caused by PL end accelerator resource conflict and PS end CPU core overload is recorded;

[0118] (6) After the simulation of each distribution strategy is completed, the lightweight simulator calculates the key performance indicators under the strategy: the delay indicators include the total time from the entry of single-frame data into the system to the completion of processing and the maximum delay fluctuation of the frame interval, wherein the total time includes distribution delay, transmission delay, and processing delay; the throughput indicator is calculated by counting the amount of effective data successfully processed per unit time, and the throughput difference of different granularity data is analyzed, and the performance data is bound with the strategy parameters to form the preliminary simulation results;

[0119] (7) After the simulation of all strategies is completed, the lightweight simulator compares and analyzes the results of different strategies under the same granularity scale, such as comparing the delay change trend of medium-grained hyperspectral cube data when the PL end occupies 60% and 70%, identifying the optimal allocation ratio corresponding to the throughput peak, and analyzing the strategy synergy across granularities, marking the conflict strategies that cause overall performance decline due to bus resource contention and noting the reasons;

[0120] (8) The lightweight simulator stores the sorted simulation results according to data types and granularity scales, each entry contains allocation strategy parameters, average delay, maximum delay, throughput and performance fluctuation coefficient, and generates a visual performance comparison curve, writes the result into the PS end result cache area through the internal interface, and releases the memory resources after the simulation is completed, and waits for the next round of simulation task based on the updated dynamic data processing matrix.

[0121] S2.3: The lightweight simulator allocates processing units for each data preprocessing task to be executed in the dynamic data processing matrix according to the simulation results, and specifies the corresponding data granularity scale for each data preprocessing task, and finally generates a structured exchange instruction set.

[0122] Further, the specific steps of S2.3 include:

[0123] (1) The lightweight simulator performs in-depth analysis on the generated simulation results, extracts the delay and throughput performance data corresponding to each allocation strategy under different data granularity scales, and establishes a performance evaluation model; the performance evaluation model takes minimizing delay and maximizing throughput as the dual objective function, and calculates the comprehensive performance score of each strategy through weighted calculation, wherein the delay weight is set according to the real-time requirement of data, such as the delay weight of RAW image preprocessing is higher than that of hyperspectral cube, to ensure that the task demand with strong real-time requirement is met first;

[0124] (2) The lightweight simulator reads the list of all data preprocessing tasks to be executed in the dynamic data processing matrix, the list contains task type, associated data frame index and task priority, for each preprocessing task, according to the granularity identifier of its associated data frame in the dynamic data processing matrix, matches the corresponding strategy subset in the performance evaluation model, and selects the allocation strategy with the highest comprehensive performance score as the candidate scheme;

[0125] (3) The candidate scheme is verified for resource adaptability, the current load state of the hardware accelerator on the PL side is checked, if the number of processing units allocated to the PL side in the candidate scheme exceeds the idle resources of the hardware accelerator, the allocation ratio of the PL side is reduced in proportion, and the number of processing units on the PS side is increased accordingly, until the resource allocation matches the actual load; check the CPU core occupancy rate on the PS side, if the calculation amount of the processing task on the PS side in the candidate scheme exceeds the remaining computing power, split the task into multiple sub-tasks and assign them to different CPU cores for parallel processing to ensure that the task can be completed within the preset time;

[0126] (4) After completing resource adaptation, the lightweight simulator specifies the data granularity scale for each preprocessing task: for RAW image denoising task, fine granularity is specified when local pixel change rate of associated data frame is high and transmission rate is fast, medium granularity is specified when overall change of data frame is smooth and transmission rate is medium, coarse granularity is specified when redundancy of continuous multiple frames is high; for hyperspectral cube band fusion task, fine granularity is used when redundancy among bands is low, coarse granularity is used when redundancy is high;

[0127] (5) The lightweight simulator allocates specific processing units for each task: the PL specifies the hardware accelerator model, the occupied operation core number, and the start time window; the PS specifies the CPU core number, process priority, and required memory buffer address, and records the allocation results, including the PL and PS processing proportion, data transmission source and destination addresses, to ensure accurate data routing;

[0128] (6) Based on the processing unit allocation results, the lightweight simulator constructs a structured exchange instruction set: divided into multiple instruction groups according to task execution order, each group corresponding to a preprocessing task, each instruction group containing three types of sub-instructions, such as processing unit configuration instructions, data transmission instructions, and task synchronization instructions, among which, processing unit configuration instructions are PL accelerator register parameter settings, such as filter window size and PS software function call parameters; data transmission instructions are data transmission paths from dynamic data processing matrix to processing units, such as DMA channel number, transmission mode such as burst transmission, and transmission verification method; task synchronization instructions are PL and PS processing unit start timing and completion signal interaction methods, such as interrupt signal number and exception handling mechanism such as timeout retransmission;

[0129] (7) After the exchange instruction set is generated, the lightweight simulator performs integrity verification: checks whether each instruction contains necessary parameters such as processing unit number, valid data address, and conflict-free timing setting, simulates instruction execution flow to verify data transmission path smoothness, processing unit configuration and task demand matching, and synchronization mechanism's ability to avoid data competition, if missing or conflicting instructions are found, backtrack to the processing unit allocation stage to adjust, until the exchange instruction set is completely compliant;

[0130] (8) The lightweight simulator encapsulates the verified exchange instruction set in the preset format, adds instruction header and instruction tail, writes it into the instruction storage area of the dynamic data processing matrix through the on-chip high-speed interface, updates the state identifier of the corresponding task in the matrix to "to be executed", and sends an instruction ready signal to the system control module to inform it to schedule and execute the batch of preprocessing tasks, completing the transformation closed loop from simulation results to execution instructions, wherein the instruction header includes instruction total number, generation timestamp, and verification code, and the instruction tail includes execution completion flag address.

[0131] The forming process of the first data exchange path comprises:

[0132] S3.1: The system configuration manager reads the exchange instruction set, parses the key information therefrom, and calls the on-chip bus topology data of the Zynq UltraScale+MPSoC to determine the connection relationship of each node of the bus and the required hardware accelerator type; the hardware accelerator type includes a RAW image denoising accelerator and a hyperspectral cube band fusion accelerator;

[0133] Further, the specific steps of S3.1 comprise:

[0134] (1) The system configuration manager starts a communication link with the exchange instruction set storage area, reads the complete exchange instruction set data through the on-chip dedicated interface, temporarily stores the data in the internal cache, and then performs hierarchical parsing on the exchange instruction set: first, extract the total number of instructions, the generation timestamp and the check code in the instruction header, and compare them with the preset integrity check value to confirm that the exchange instruction set is not damaged or tampered with; after the check is passed, enter the instruction parsing stage, read the processing unit configuration instructions, data transmission instructions and task synchronization instructions contained in each instruction group in order, separate the processing unit numbers of the PL and PS ends, the source and destination addresses of data transmission, the function identification of the required hardware accelerator, the bus interface type and the transmission bandwidth requirement, and store the key information in the corresponding register group;

[0135] (2) While parsing the instructions, the system configuration manager starts the on-chip bus topology data calling process: access the bus configuration register inside the Zynq UltraScale+MPSoC to read the preset topology structure description information, structure the topology data, build a bus node connection map, and clearly define the upstream connection devices and downstream reachable devices of each node, for example, the DMA controller node is connected to the PL end data buffer upstream, and can access the OCM storage node and hardware accelerator node downstream; the CPU core node is connected to the bus arbiter node through the AXI4-Lite bus; the topology structure description information is a hierarchical record of the physical connection relationship of all bus nodes on the chip, including the intersection nodes of AXI4-Stream and AXI4-Lite buses, device identifiers, supported transmission protocols and maximum bandwidth limits;

[0136] (3) The system configuration manager matches the hardware accelerator function identifier parsed from the register group with the device identifier in the bus node connection map: For each accelerator type specified in the processing unit configuration instruction, the corresponding device node is searched in the bus node connection map, and its physical address, accessed bus type, and connection path with other nodes are recorded. At the same time, the working state register of the accelerator node is checked to confirm whether it is idle. If it is occupied, it is marked as an alternative node and a redundant accelerator node of the same type is searched to ensure that the hardware acceleration requirement is met;

[0137] (4) Based on the source address and destination address in the data transmission instruction, potential transmission paths are planned in the bus node connection map. For example, from the PL end SERDES controller buffer to the RAW graph denoising accelerator, it needs to pass through the arbiter node and the accelerator interface node of the AXI4-Stream bus. For each potential path, the number of nodes contained, the transmission delay between nodes, and the total bandwidth of the path are calculated. The path that meets the bandwidth requirement and has the minimum delay is selected as the candidate transmission path. The configuration parameters of each node in the path are recorded, such as the priority setting of the arbiter and the data width of the interface node.

[0138] (5) The system configuration manager verifies the parsed processing unit number: confirms that the PL end hardware accelerator unit number is consistent with the device node number in the bus topology, and the PS end CPU core number is within the valid range and is not occupied by other high-priority tasks. If the number does not match or there is a resource conflict, an exception handling mechanism is triggered immediately, the parsing process is suspended, and an error signal is sent to the system control module. The conflict position and reason are recorded, and manual intervention or automatic call of redundant resource adjustment is waited.

[0139] (6) When all key information parsing is completed and the bus topology relationship is matched without error, the system configuration manager will arrange the results, including the processing unit allocation details in the exchange instruction set, the node information of the hardware accelerator, the candidate transmission path, and the bus node configuration parameters, etc., to the special configuration information buffer. At the same time, the state register of the system configuration manager is updated, the configuration information ready flag bit is set, and finally the temporary instruction set and topology data cache resources are released to ensure efficient use of system memory.

[0140] S3.2: Based on the key information and on-chip bus topology, the system configuration manager plans the basic path framework of data transmission, determines the initial interaction path between the PL end data output interface and the OCM through the specified DMA controller, and obtains the DMA-OCM interaction path.

[0141] Further, the specific steps of S3.2 include:

[0142] (1) The system configuration manager extracts the physical address and data format parameters of the PL data output interface from the parsed key information, and determines the starting address and available space size of the OCM storage area, ensuring that the source and destination of data transmission are accessible at the physical layer and have sufficient space. According to the DMA controller number specified in the data transmission instruction, the node position of the DMA controller is located in the on-chip bus topology structure, and the supported transmission protocol, data width and maximum burst transmission length are queried. It is confirmed that there is a direct or indirect bus connection path between the controller and the PL data output interface and the OCM storage area;

[0143] (2) After confirming the feasibility of the basic connection, the system configuration manager plans the basic path framework of data transmission: taking the PL data output interface as the starting point, tracing upstream along the connection relationship in the bus node connection graph, identifying the necessary bus arbiter nodes and interface conversion nodes. If the PL output interface uses the AXI4-Stream protocol and the DMA controller supports the AXI4 protocol, the protocol conversion node is included. At the same time, extend from the DMA controller node downstream to determine the specific bus branch connected to the OCM storage area, record the delay parameters and bandwidth limitations of each node, and ensure that each link in the path meets the rate requirements of data transmission;

[0144] (3) The system configuration manager initializes and configures the DMA controller: sets the transmission mode according to the type of transmission data, where continuous data uses the circular buffer mode and block data uses the single burst mode, and configures the source address of data transmission as the buffer address of the PL data output interface and the destination address as the pre-allocated storage block address in the OCM. At the same time, set the length parameter of data transmission. For variable length frame data, enable the automatic length detection function of DMA, and dynamically adjust the transmission length by identifying the data frame tail flag;

[0145] (4) To establish an initial interactive path, the system configuration manager further configures the bus node parameters: for the bus arbiter nodes in the path, set the arbitration weight of the DMA channel according to the priority of data transmission to ensure that the path obtains sufficient bandwidth in bus competition; for the protocol conversion node, configure the data format conversion rule to convert the serial data stream output by the PL into a parallel data format recognizable by the DMA controller, keeping the data bit width consistent; after configuration is completed, send a start command to the DMA controller to make it enter the ready state and wait for the data transmission trigger signal;

[0146] (5) The system configuration manager verifies the connectivity of the DMA-OCM interactive channel, including: sending a test data packet to the PL-side data output interface, triggering the transmission process of the DMA controller, monitoring the entire process of transmitting the test data from the PL-side output to the OCM storage area through the DMA controller, during the transmission process, real-time reading of the status register of the DMA controller, checking whether there are transmission errors, address out-of-bounds and other abnormal states, comparing the consistency of the test data received in the OCM with the sent data, and ensuring the accuracy of the channel transmission;

[0147] (6) If the test finds that the channel is abnormal, the system configuration manager makes targeted adjustments: when the transmission delay exceeds the standard due to insufficient bus bandwidth, the weight parameters of the arbiter are reconfigured to improve the priority of the channel; when data distortion is caused by protocol conversion errors, the format rules of the protocol conversion node are corrected and a verification mechanism is added; when the address mapping of the DMA controller and the OCM is incorrect, the destination address parameters are recalculated and configured; after adjustment, the connectivity test is repeated until the channel runs stably;

[0148] (7) After completing the channel verification, the system configuration manager stores the configuration parameters of the DMA-OCM interactive channel to the path information table, marks the state of the channel as available in the dynamic data processing matrix, and associates it to the corresponding data flow task, and finally releases the temporary resources occupied during the configuration process, keeps the system configuration manager in a ready state, and waits to receive new path planning instructions, wherein the configuration parameters of the DMA-OCM interactive channel include the DMA controller number, the source and destination address range, the transmission mode, the bus node configuration and the maximum transmission rate.

[0149] S3.3: According to the requirements of the preprocessing task in the exchange instruction set, the system configuration manager identifies the hardware accelerator that needs to be enabled, queries the connection port of the hardware accelerator in the on-chip bus topology and connects it to the established DMA-OCM interactive channel, configures the input and output interface parameters, data processing format and handshake protocol of the hardware accelerator with the bus, completes the adaptation of the hardware accelerator and the channel, and forms an integrated channel.

[0150] Further, the specific steps of S3.3 include:

[0151] (1) The system configuration manager extracts the functional requirements of the hardware accelerator from the preprocessing task description in the exchange instruction set, and matches it with the hardware accelerator function list registered by the system to determine the accelerator model and quantity that need to be enabled, and at the same time checks the current running state of the accelerator by reading the accelerator status register, if there is an occupied condition, according to the task priority to judge whether to preempt resources or enable a backup accelerator, to ensure that the hardware acceleration requirements of the preprocessing task are met;

[0152] (2) The system configuration manager calls the bus node connection graph of the on-chip bus topology, locates the determined hardware accelerator node in the bus node connection graph, queries the specific physical port information of the access on-chip bus, such as the bus protocol type such as AXI4-Stream or AXI4-Lite, the data bit width such as 32 bits or 64 bits, the maximum transmission rate, and the interrupt signal pin number, and at the same time traces the connection path of the port in the bus topology, and clearly determines the node that can be directly connected in the established DMA-OCM interaction channel, such as the DMA output end or the OCM input end. For example, when the accelerator port supports the AXI4-Stream protocol and is located in the downstream bus branch of the DMA controller, it can access between the DMA output channel and the OCM input channel;

[0153] (3) After determining the access point, the system configuration manager adjusts the topology structure of the DMA-OCM interaction channel, and connects the hardware accelerator in series or in parallel to the channel: for the scene that needs real-time preprocessing, such as RAW image denoising, the series connection mode is adopted, so that the data is transmitted from the PL output to the accelerator for processing, and then the processed data is transmitted to the OCM by the accelerator; for the auxiliary task that can be processed in parallel, such as hyperspectral cube redundancy detection, the parallel connection mode is adopted, and part of the data is transmitted to the accelerator from the branch of the DMA channel, and the processing result is stored to the specified area of the OCM, without affecting the main data stream; update the bus node routing table during the adjustment process, and add the address mapping relationship of the accelerator port;

[0154] (4) The system configuration manager configures the input and output interface parameters of the hardware accelerator: the input interface sets the input data width according to the DMA output data format, adjusts the input buffer size to match the data frame length to avoid overflow or deficiency; the output interface sets the output data bit sequence and the check mode according to the OCM storage format requirements, such as data alignment mode and compression format, to ensure that the processed data can be directly written to the OCM; at the same time, the interface handshake signal is configured, and the timing relationship of the data valid signal and the ready signal is set, so that the signal interaction of the accelerator with the DMA and the OCM conforms to the bus protocol specification;

[0155] (5) According to the specific requirements of the preprocessing task, the system configuration manager writes the processing parameters into the configuration register of the hardware accelerator through the AXI4-Lite control bus: the RAW image denoising accelerator sets the filter window size, threshold parameter and edge retention strength; the hyperspectral cube band fusion accelerator sets the band weight coefficient, fusion dimension and feature extraction wavelength range; after writing is completed, the configuration confirmation register of the accelerator is read to verify whether the parameters are correctly received and take effect, and if there is an error, the parameters are written again and error logs are recorded;

[0156] (6) To ensure the hardware accelerator and the bus work together, the system configuration manager configures the handshake protocol details: set the accelerator's response timeout for bus data, automatically trigger an interrupt signal when no valid data is received within the preset time, and notify the system to check the channel state; configure the burst length of data transmission to match the accelerator processing rate with the bus transmission rate, such as 128 bytes per burst transmission on the bus, and the accelerator starts a processing flow every 128 bytes received; at the same time, set the interrupt trigger condition, when the accelerator completes a frame of data processing or detects a data error, send an interrupt request to the PS end through the specified interrupt pin, to facilitate real-time monitoring of the processing progress;

[0157] (7) After configuration, the system configuration manager performs integrity testing on the integrated channel: sends a test data frame to the PL end data output interface, the data frame is transmitted to the hardware accelerator through DMA, and the accelerator transmits it to the OCM specified storage area after preprocessing according to the configuration parameters; monitor the state register of each node of the channel in real time during the test, record the transmission delay of data between DMA, accelerator and OCM, and verify whether the handshake signal interaction is conflict-free; if data loss or processing error is found, check the interface parameters, processing format and handshake protocol configuration, and adjust accordingly for retesting until the integrated channel runs stably;

[0158] (8) The system configuration manager stores the configuration information of the integrated channel to the channel configuration table, marks the corresponding preprocessing task state as ready in the dynamic data processing matrix, and sends a channel ready signal to the system, completing the adaptation and integration of the hardware accelerator and the DMA-OCM interaction channel, wherein the configuration information of the channel includes the accelerator access position, interface parameters, processing format and handshake protocol details.

[0159] S3.4: Perform integrity verification on the integrated channel to check whether the configuration of each node is consistent with the exchange instruction set, confirm whether the full path from the PL end output, through the DMA controller scheduling, hardware accelerator processing, and OCM data temporary storage or forwarding is smooth, and form the first data exchange path.

[0160] The quantitative analysis using the bus load model combining temperature feedback and cyclic redundancy check includes:

[0161] S4.1: During the operation of the first data exchange path, real-time acquisition of the temperature sensor data of the on-chip bus exchange node and the data error rate calculated through cyclic redundancy check;

[0162] S4.2: The system calls the bus load model combining temperature feedback and cyclic redundancy check, and uses the acquired temperature sensor data and the calculated data error rate as input parameters of the bus load model, and substitutes them into the built-in bus load evaluation function of the bus load model.

[0163] Further, the construction process of the bus load model includes:

[0164] (1) The system explicitly needs to combine temperature feedback and cyclic redundancy check results in the bus load model to achieve comprehensive evaluation of the first data exchange path load and stability, and then determine the core input parameters of the model. The temperature feedback parameter comes from the temperature sensor of the on-chip bus exchange node, and the type of temperature sensor data collected needs to be explicitly real-time node temperature value and temperature change rate, which is used to reflect the temperature abnormality of the bus hardware due to excessive load. The cyclic redundancy check parameter is the data error rate obtained by cyclic redundancy check calculation on the transmission data in the path, and the distribution frequency of error frames, which is used to reflect the integrity of data transmission and path stability. At the same time, the collection frequency of the two types of parameters needs to match the running rate of the first data exchange path to ensure the timeliness of the input data;

[0165] (2) Enter the parameter weight allocation and associated model construction stage. The system first tests the influence of temperature sensor data and cyclic redundancy check parameters on path performance under different load scenarios through a large number of experiments, for example, in a low load scenario, temperature change has less effect on path stability, while data error rate can better reflect path problems. In a high load scenario, temperature rise will significantly affect hardware performance, and then lead to an increase in data error rate, so the weight of temperature sensor data needs to be increased. Based on the experimental results, machine learning training is used to allocate dynamic weight coefficients for temperature sensor data and cyclic redundancy check parameters to ensure that the two types of parameters can reasonably participate in evaluation under different load scenarios. Then, the associated model between parameters is constructed, for example, when the temperature value exceeds the preset hardware safety threshold, the influence weight of the temperature sensor data on the data error rate prediction is automatically increased, and the quantitative association between temperature abnormality and data transmission error is established, forming the core parameter processing logic of the model. Machine learning is a prior art in the field and is not the inventive scheme of the present application, and will not be described here.

[0166] (3) Bus load evaluation function design and threshold calibration. The system designs the core calculation formula of the bus load evaluation function based on the above parameter processing logic. The function needs to first standardize the input temperature sensor data and cyclic redundancy check parameters to eliminate the influence of different parameter magnitude differences. For example, convert the temperature value to a percentage relative to the hardware safety temperature, and convert the data error rate to a ratio relative to the allowed error rate. Then multiply the standardized parameters by the corresponding weight coefficients, and then get the preliminary load evaluation value by weighted summation. At the same time, introduce a correction factor, which is dynamically adjusted according to the deviation of the path load and the actual performance in the historical running data, to ensure the accuracy of the load evaluation value. Then design the calculation logic of the stability score, combining the fluctuation of the data error rate and the stability of the temperature change. When the data error rate fluctuation is small and the temperature change is stable, the stability score is high, and vice versa. After the function is designed, the system runs the first data exchange path and collects the corresponding temperature and error rate data by simulating different load level test scenarios, such as from no load to full load. The load coefficient and stability score in different scenarios are calculated by substituting the evaluation function, and the threshold range of the load coefficient is calibrated, such as the threshold values corresponding to low load, medium load, and high load, and the grade standard of the stability score, such as the score interval corresponding to excellent, good, and poor, to ensure that the path state can be accurately judged by the function calculation result.

[0167] (4) Finally, model verification and iterative optimization. The system builds a test environment consistent with the actual application scenario, deploys the bus load model built to the test environment, and runs the first data exchange path in different data transmission volume and different data type scenarios. Real-time collection of load coefficient and stability score output by the model, and comparison with real performance indicators such as actual monitored path transmission rate, delay, and hardware failure frequency to verify the consistency of model evaluation results and actual performance. If the bus load model evaluation result deviates greatly from the actual performance, for example, the model predicts low load but the actual path delay is too high, the parameter weight distribution needs to be checked for reasonableness, the evaluation function calculation formula needs to be checked for defects, or the parameter correlation model needs to be checked for whether it accurately reflects the relationship between temperature and error rate. Adjust and optimize the problem points. After multiple rounds of testing and iteration in different scenarios, the error between the bus load model evaluation result and the actual path performance is controlled within the pre-set allowed range.

[0168] S4.3: Calculate the load coefficient and stability score of the current first data exchange path by operating the input temperature sensor data and data error rate through the bus load evaluation function, and use them as the quantitative analysis result of the first data exchange path.

[0169] Further, the specific steps of S4.3 include:

[0170] (1) Obtain temperature sensor data and data error rate, filter the temperature sensor data to remove transient fluctuation noise and retain temperature change trend components, and perform sliding window average calculation on the data error rate to smooth the error code fluctuation in a short time, to obtain stable temperature sensor data and error rate indicators;

[0171] (2) The system calls a preset bus load evaluation function, which includes a load coefficient calculation submodule and a stability score calculation submodule. When calculating the load coefficient, first convert the temperature values of each node into a standardized temperature index. Here, the upper limit of the normal operating temperature range is used as the reference. Temperatures exceeding the upper limit are converted to temperature indices greater than 1, and temperatures below the lower limit are converted to temperature indices less than 0.5. Temperatures within the normal range are mapped to temperature indices between 0.5 and 1. Then, according to the weights of each node in the path, such as the DMA controller weight being higher than the ordinary interface node, the temperature indices are weighted and summed to obtain the basic load value. Then, combine the ratio of data transmission rate to maximum bus bandwidth, i.e. bandwidth utilization, to fuse the basic load value and bandwidth utilization in a 6:4 proportion to generate a load coefficient between 0 and 2.

[0172] (3) Calculate the stability score, including: mapping the data error rate to an initial stability score, where the error rate is 0, the score is 100, and each increase of 0.1% decreases by 10 points, and when it exceeds 1%, it drops to 0. Then calculate the standard deviation of the temperature sensor data to reflect the fluctuation intensity. According to the standard deviation, the initial stability score is deducted, such as exceeding 5℃ by 20 points, and exceeding 10℃ by 50 points. Finally, modify the redundancy of each node in the first data exchange path, such as the existence of a backup path, which reduces the temperature fluctuation impact by 30%, and accordingly reduces the deduction value, so that the stability score is normalized between 0 and 100.

[0173] (4) The system cross- validates the load coefficient and the stability score, and uses the cross-validation result as a supplementary description, which is packaged together with the load coefficient and the stability score to form a complete quantitative analysis result. The cross-validation is a prior art in the field and is not the inventive scheme of the present application, so it is not described here.

[0174] (5) The system writes the quantitative analysis result into the path state register and triggers a state update interrupt to notify the system configuration manager to read the result. After writing, reset the temporary calculation buffer to prepare for receiving the next round of temperature sensor data and data error rate, and enter the continuous path evaluation cycle.

[0175] The adjusting the sub-channel allocation in the first data exchange path and the bus priority according to the quantitative analysis result to obtain the second data exchange path includes:

[0176] A1: The path scheduler obtains the quantization analysis result of the first data exchange path, and compares the load coefficient in the quantization analysis result with a preset load threshold value;

[0177] If the load coefficient exceeds the preset load threshold value, the path scheduler adjusts the sub-channel allocation in the first data exchange path to obtain an adjusted sub-channel allocation scheme; the adjustment includes: splitting the wide sub-channel originally allocated to the hyperspectral cube data into multiple narrow sub-channels, and separately allocating an independent sub-channel to the RAW graph data;

[0178] A2: The path scheduler adjusts the bus priority of the data stream on the basis of the adjusted sub-channel according to the real-time requirement of the data stream, to obtain a bus priority setting; the real-time requirement is that the real-time transmission requirement of the RAW graph data is higher than that of the hyperspectral cube data;

[0179] A3: The path scheduler generates corresponding path configuration parameters according to the adjusted sub-channel allocation scheme and the bus priority setting, and reconstructs the first data exchange path by using the path configuration parameters to obtain a second data exchange path.

[0180] Further, the specific steps of A3 include:

[0181] (1) The path scheduler extracts the sub-channel allocation adjustment requirement and the bus priority update basis from the quantization analysis result: when the load coefficient exceeds the load threshold value, it is clear that the wide sub-channel of the hyperspectral cube data is split into three narrow sub-channels, and the number of sub-channels of the RAW graph data is increased from two to three to improve parallelism; according to the stability score and the real-time requirement of the data, the priority of the RAW graph data stream is adjusted from the original intermediate level to high level, the priority of the hyperspectral cube data stream remains intermediate but is slightly lower than that of the RAW graph in bandwidth competition, and the priority of the auxiliary control signal remains low unchanged;

[0182] (2) The path scheduler generates specific configuration parameters of the sub-channel allocation: allocates independent physical channel numbers to the split hyperspectral narrow sub-channels, sets their maximum transmission bandwidths, i.e. no more than one third of the total bandwidth of the original wide sub-channel, and configures the isolation mechanism between the sub-channels; allocate the newly added RAW graph sub-channel to unoccupied channel resources, set the same data format and verification method as the original sub-channel, and configure an independent buffer area for each sub-channel in the DMA controller to avoid data aliasing; the configuration parameters of all sub-channels are stored by sub-channel type, wherein the configuration parameters of the sub-channel include channel number, bandwidth limit, source and destination address mapping, data frame size threshold;

[0183] (3) The path scheduler generates bus priority configuration parameters: determines priority quantization levels, wherein high, medium and low are respectively mapped to numerical values 3, 2 and 1, priority 3 is allocated to all sub-channels of the RAW graph data stream, priority 2 is allocated to the hyperspectral cube sub-channel, and priority 1 is allocated to the control signal channel; the priority register of the bus arbiter is configured, and the arbitration algorithm is set to weighted round robin, that is, priority 3 accounts for 50% of the weight, priority 2 accounts for 40%, and priority 1 accounts for 10%; the priority preemption mechanism is set, that is, when the RAW graph data of priority 3 arrives, the data of priority 2 or 1 being transmitted on the bus can be paused and preempted, and after the transmission is completed, the transmission of the paused data is resumed, and the preemption timeout is the transmission period of a single data frame, so as to avoid long-term blocking of low-priority data;

[0184] (4) The path scheduler starts the reconstruction process of the first data exchange path: sends a configuration locking signal to all involved bus nodes, temporarily stops data transmission and freezes the current path state; the channel mapping table of each node is updated in turn according to the sub-channel configuration parameters, such as adding a new transmission descriptor of the sub-channel in the DMA controller, writing a new priority weight and arbitration rule in the bus arbiter, and updating the processing queue corresponding to the sub-channel in the hardware accelerator interface;

[0185] (5) The path scheduler reconstructs the physical link of the sub-channel: re-plans the signal routing according to the new channel number, configures the new connection relationship in the cross switch matrix of the on-chip bus, ensures that the split hyperspectral cube sub-channels are connected to the corresponding hardware accelerator processing units respectively, the new RAW graph sub-channel is directly connected to the high-speed storage interface of the OCM, adjusts the signal driving strength and transmission balance parameters of each sub-channel, optimizes the signal integrity according to the channel length and data rate, and reduces signal attenuation and crosstalk during high-speed transmission;

[0186] (6) The path scheduler performs consistency checking on the new configuration, wherein the consistency checking is a prior art content in the field and is not the inventive scheme of the present application, and is not described here;

[0187] (7) After the verification passes, the path scheduler releases the configuration lock of the bus node and starts the trial run of the second data exchange path: inputs test data frames to the path, wherein the test data frames contain RAW graph and hyperspectral cube data of different priorities, monitors the transmission state of each sub-channel, and the trial run lasts for a predetermined time window, such as 100 data frame periods, and if no transmission error, priority preemption failure or other abnormalities occur during the trial run, it is confirmed that the reconstruction of the second data exchange path is successful;

[0188] Further, the process of monitoring the transmission state of each sub-channel includes: verifying the correctness of the physical link through the oscilloscope to sample the sub-channel signal waveform, confirming the data transmission integrity through the DMA state register, and recording the actual bandwidth allocation of the new path through the bus load monitoring module.

[0189] (8) The path scheduler stores the configuration parameters of the second data exchange path to the non-volatile memory, updates the path state identifier to active, sends a path switching notification to the dynamic data processing matrix to make it use the new path to transmit data, and records the key parameters in the reconstruction process, such as the bandwidth change before and after the sub-channel adjustment, the transmission delay comparison before and after the priority setting, as the historical data reference for path optimization, to complete the full-process reconstruction from the first data exchange path to the second data exchange path.

[0190] Embodiment 2:

[0191] Please refer to Figure 3 Another embodiment provided by the application: a high-speed data processing and exchange system based on Zynq UltraScale+MPSoCs, comprising:

[0192] a data acquisition module, a matrix construction module, an instruction generation module, an exchange path construction module, a path optimization module, and a state feedback module;

[0193] The data acquisition module is used to trigger and acquire initial multi-modal data, while ensuring the synchronization and accuracy of data acquisition.

[0194] The matrix construction module is used to receive the initial multi-modal data, analyze the data transmission quality, and construct a structured dynamic data processing matrix.

[0195] The instruction generation module is used to optimize the computing power allocation of the PL end and the PS end based on the information of the dynamic data processing matrix, and generate a structured exchange instruction set.

[0196] The exchange path construction module is used to construct a stable first data exchange path based on the exchange instruction set and the on-chip bus topology, and realize efficient transmission of data between the PL end, the PS end, and the storage unit.

[0197] The path optimization module is used to adjust the sub-channel allocation and bus priority by quantitatively analyzing the running state of the first data exchange path, and generate a second data exchange path.

[0198] The state feedback module is used to collect the running state parameters of the second data exchange path and write them back to the dynamic data processing matrix in real time, forming a closed-loop optimization mechanism.

[0199] The matrix construction module includes a controller unit, a quality analysis unit, and a matrix construction unit.

[0200] A controller unit is configured to receive RAW image data streams and hyperspectral cube data streams through two independent physical links by using a double SERDES hardware interface at the Zynq PL end, avoid mutual interference during transmission of different types of data, and complete preliminary reception and caching of data by real-time analysis of data packet header structures;

[0201] A quality analysis unit is configured to calculate transmission rates by counting the number of data packets transmitted per unit time, judge data integrity by checking CRC codes or checksums of data packets, and generate valid / invalid status flags for each frame of data;

[0202] A matrix construction unit is configured to map information such as data types, transmission rates, integrity states, and collection timestamps to corresponding cells of a matrix in a two-dimensional dimension of data type-time sequence, form a dynamic data processing matrix, and intuitively present the core attributes of each frame of data.

[0203] The instruction generation module includes a granularity scale definition unit, an allocation simulation unit, and an instruction set generation unit.

[0204] The granularity scale definition unit is configured to predefine three data processing granularities, i.e., fine granularity, medium granularity, and coarse granularity, to adapt to processing requirements of different data types.

[0205] The allocation simulation unit is configured to use the dynamic data processing matrix as input, run a lightweight simulator on the PS end, simulate allocation schemes of data on the PL end and the PS end under different granularities, evaluate performance indicators such as delay and throughput of each scheme, and select an optimal allocation strategy.

[0206] The instruction set generation unit is configured to generate a structured set containing three types of instructions according to the optimal allocation strategy.

[0207] The exchange path construction module includes a topology management unit, an interaction configuration unit, an adaptation unit, and a path verification unit.

[0208] The topology management unit is configured to store and retrieve on-chip bus topology data of the Zynq UltraScale+MPSoCs, clearly define node connection relationships of AXI4-Stream high-speed buses and AXI4-Lite control buses, and provide topology basis for path planning.

[0209] The interaction configuration unit is configured to configure transmission modes, data widths, and cache sizes of DMA controllers according to transmission requirements in exchange instructions, establish an initial interaction path from a data output interface on the PL end to the OCM, and realize temporary storage and forwarding of data.

[0210] An adaptation unit is configured to identify a hardware accelerator specified in the exchange instruction, query a connection port of the hardware accelerator on the bus, and access the accelerator into the DMA-OCM interactive channel; meanwhile, the adaptation unit is configured to configure input and output interface parameters of the accelerator and handshake timing with the bus, and complete adaptation of the accelerator and the interactive channel;

[0211] A path verification unit is configured to send a test data packet to the constructed integrated channel, check whether a whole path from PL output, DMA scheduling, accelerator processing, and OCM storage is smooth, verify whether configurations of all nodes are consistent with the exchange instruction, and form a first data exchange path after confirmation.

[0212] The path optimization module comprises a path state monitoring unit, a model operation unit, a parameter adjustment unit, and a path reconstruction unit.

[0213] The path state monitoring unit is configured to collect temperature sensor data of the bus exchange node through an on-chip temperature sensor, and calculate a data error rate through cyclic redundancy check on the transmission data.

[0214] The model operation unit is configured to call a bus load model fused with temperature feedback and cyclic redundancy check, input the temperature sensor data and the data error rate into a bus load evaluation function built in the model, calculate a load coefficient and a stability score of the path, and form a quantitative analysis result.

[0215] The parameter adjustment unit is configured to compare the load coefficient with a preset load threshold value: if the load coefficient exceeds the preset load threshold value, split a wide subchannel of the hyperspectral cube data into multiple narrow subchannels, allocate independent subchannels for RAW image data, improve bus priority of high real-time data flow according to real-time requirements of the data flow, and generate adjusted parameters.

[0216] The path reconstruction unit is configured to reconfigure a DMA controller, a hardware accelerator, and a bus interconnection matrix according to the adjusted subchannel allocation scheme and the bus priority parameters, reconstruct the first data exchange path, and form a second data exchange path.

[0217] The embodiments of the present application are described above with reference to the accompanying drawings, but the present application is not limited to the above-described specific embodiments, and the above-described specific embodiments are merely illustrative rather than limiting, and a person of ordinary skill in the art can make changes, modifications, replacements, and variations to the above-described embodiments without departing from the purpose of the present application and the scope of protection, and these are all within the protection of the present application.

Claims

1. A method for high speed data processing and switching based on Zynq UltraScale+ MPSoCs, characterized in that, The application relates to a method for constructing a dynamic data processing matrix based on a Zynq UltraScale+MPSoCs platform. The method comprises the following steps: A nanosecond-level synchronization pulse is generated by using a PL end of the Zynq to trigger a multi-modal acquisition module to acquire initial multi-modal data; a double SERDES controller of the PL end receives the initial multi-modal data and analyzes the transmission rate and integrity of the initial multi-modal data; and a dynamic data processing matrix is constructed. The initial multi-modal data comprises RAW images and hyperspectral cubes. Based on the dynamic data processing matrix, a preset multi-data granularity scale simulation is used to optimize the data flow allocation of the PL and PS ends, and a set of exchange instructions is generated. According to the set of exchange instructions, a data exchange path is reconstructed in combination with a Zynq UltraScale+MPSoCs on-chip bus topology; through DMA-OCM interaction and hardware accelerator adaptation, a first data exchange path is formed. A bus load model integrating temperature feedback and cyclic redundancy check is used to quantitatively analyze the first data exchange path; according to the quantitative analysis result, a sub-channel allocation and a bus priority in the first data exchange path are adjusted to obtain a second data exchange path.

2. The high speed data processing and switching method based on Zynq UltraScale+ MPSoCs of claim 1, wherein, Running state parameters of the second data exchange path are written back to a data frame state attribute column corresponding to the dynamic data processing matrix in real time; the running state parameters comprise actual throughput, delay and a latest load coefficient. The double SERDES controller of the PL end receives the initial multi-modal data and analyzes the transmission rate and integrity of each initial multi-modal data to construct a dynamic data processing matrix. In the PL end, the double SERDES controller receives RAW image data streams and hyperspectral cube data streams in the initial multi-modal data through independent physical links respectively. A state machine in the double SERDES controller analyzes a packet header structure of input data packets in real time and calculates a check sequence to obtain key parameters of each data frame; and based on the key parameters and a preset threshold, a data validity flag is generated for each data frame; the key parameters comprise transmission rate parameters and integrity parameters.

3. The high speed data processing and switching method based on Zynq UltraScale+ MPSoCs as claimed in claim 1, wherein, Each data frame from the double SERDES controller is mapped and filled into a two-dimensional dynamic data processing matrix as input attributes according to a data type, a data validity flag, a transmission rate and a time stamp information stamped when the data frame is acquired; rows of the dynamic data processing matrix represent different data sources and data types, columns represent data frame instances arranged in time sequences, and each cell stores a set of state attributes of a corresponding data frame. The generation process of the set of exchange instructions comprises the following steps: A constructed dynamic data processing matrix is read; three data granularity scales of fine granularity, medium granularity and coarse granularity are predefined based on the dynamic data processing matrix; The dynamic data processing matrix is taken as input, and a lightweight simulator is run in the PS end; the lightweight simulator simulates different allocation strategies of data between the PL end and the PS end based on the three data granularity scales and outputs simulation results, including delay and throughput performance data obtained through evaluation; The lightweight simulator allocates processing units for each data preprocessing task to be executed in the dynamic data processing matrix according to the simulation results, specifies a corresponding data granularity scale for each data preprocessing task, and finally generates a structured set of exchange instructions.

4. The high speed data processing and switching method based on Zynq UltraScale+ MPSoCs of claim 3, wherein, The exchange instruction set includes preprocessing task instructions, computing power scheduling instructions, and data transmission instructions; the preprocessing task instructions specify bad point repair of a RAW graph and dark current correction operation of a hyperspectral cube; and the computing power scheduling instructions specify the number of accelerators enabled at the PL end and the number of CPUs enabled at the PS end.

5. The high speed data processing and switching method based on Zynq UltraScale+ MPSoCs as claimed in claim 1, wherein, The forming process of the first data exchange path includes: The system configuration manager reads the exchange instruction set, parses the key information therefrom, and determines the connection relationship of the nodes and the type of the hardware accelerator of the bus based on the bus topology data of the Zynq UltraScale+MPSoCs; Based on the key information and the on-chip bus topology, the system configuration manager plans a basic path framework for data transmission, determines an initial interaction channel between the PL end data output interface and the OCM through a specified DMA controller, and obtains a DMA-OCM interaction channel; According to the requirements of the preprocessing tasks in the exchange instruction set, the system configuration manager identifies the enabled hardware accelerator, queries the connection port of the hardware accelerator in the on-chip bus topology, and connects it to the established DMA-OCM interaction channel; by configuring the input and output interface parameters, data processing format, and handshake protocol of the bus of the hardware accelerator, the system configuration manager completes the adaptation of the hardware accelerator and the channel, forms an integrated channel, and forms the first data exchange path. The system configuration manager performs integrity verification on the integrated channel, checks whether the configurations of the nodes are consistent with the exchange instruction set, confirms whether the full path from the PL end output, through the DMA controller scheduling, hardware accelerator processing, and OCM data storage or forwarding, is smooth, and forms the first data exchange path.

6. The high speed data processing and switching method based on Zynq UltraScale+ MPSoCs of claim 5, wherein, The on-chip bus topology of the Zynq UltraScale+MPSoCs includes an AXI4-Stream high-speed bus and an AXI4-Lite control bus; when reconstructing the data exchange path, the bus interconnection matrix is configured to complete data routing between different buses.

7. The high speed data processing and switching method based on Zynq UltraScale+ MPSoCs as claimed in claim 1, wherein, The quantitative analysis using the bus load model combining temperature feedback and cyclic redundancy check includes: During the operation of the first data exchange path, the temperature sensor data of the on-chip bus exchange nodes and the data error rate calculated through cyclic redundancy check are collected in real time; The system calls the bus load model combining temperature feedback and cyclic redundancy check, and uses the collected temperature sensor data and the calculated data error rate as input parameters of the bus load model, and substitutes them into the built-in bus load evaluation function of the bus load model; The bus load evaluation function is used to operate the input temperature sensor data and data error rate to calculate the load coefficient and stability score of the current first data exchange path, which are used as the quantitative analysis results of the first data exchange path.

8. The high speed data processing and switching method based on Zynq UltraScale+ MPSoCs as claimed in claim 1, wherein, The adjustment of the sub-channel allocation and bus priority in the first data exchange path based on the quantitative analysis results to obtain the second data exchange path includes: The path scheduler obtains the quantitative analysis results of the first data exchange path, and compares the load coefficient in the quantitative analysis results with a preset load threshold; If the load factor exceeds the preset load threshold, the path scheduler adjusts the subchannel allocation in the first data exchange path to obtain an adjusted subchannel allocation scheme; the adjustment includes: splitting the original wide subchannel allocated to the hyperspectral cube data into multiple narrow subchannels, and separately allocating an independent subchannel to the RAW image data; The path scheduler adjusts the bus priority of the data stream on the basis of the adjusted subchannel according to the real-time requirement of the data stream, to obtain a bus priority setting; the real-time requirement is that the real-time transmission requirement of the RAW image data is higher than that of the hyperspectral cube data; The path scheduler generates corresponding path configuration parameters according to the adjusted subchannel allocation scheme and the bus priority setting, and reconstructs the first data exchange path by using the path configuration parameters to obtain a second data exchange path.

9. A high-speed data processing and switching system based on Zynq UltraScale+ MPSoCs for implementing the high-speed data processing and switching method based on Zynq UltraScale+ MPSoCs according to any one of claims 1-8, characterized in that, Comprise: Data acquisition module, matrix construction module, instruction generation module, exchange path construction module, path optimization module, state feedback module; The data acquisition module is used for triggering and acquiring initial multi-modal data; The matrix construction module is used for receiving the initial multi-modal data, analyzing the data transmission quality, and constructing a structured dynamic data processing matrix; The instruction generation module is used for optimizing the computing power allocation of the PL end and the PS end based on the information of the dynamic data processing matrix, and generating a structured exchange instruction set; The exchange path construction module is used for constructing a first data exchange path according to the exchange instruction set and combining the on-chip bus topology; The path optimization module is used for adjusting the subchannel allocation and the bus priority by quantitatively analyzing the running state of the first data exchange path, and generating a second data exchange path; The state feedback module is used for collecting the running state parameters of the second data exchange path and writing back to the dynamic data processing matrix in real time.

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