An integrated circuit fault mode recognition method based on deep learning

Abstract

The application discloses an integrated circuit fault mode recognition method based on deep learning, which comprises the following steps: collecting multi-source original data of an integrated circuit to obtain a standardized feature data set; constructing a circuit heterogeneous graph structure based on the standardized feature data set to form an initial feature set of a graph structure; generating a multi-modal input vector set based on the standardized feature data set; inputting the multi-modal input vector set into a circuit topology-aware graph neural network model to output a fusion node embedding representation; performing fault recognition based on the fusion node embedding representation to generate a fault recognition result set; adopting a multi-task loss function to obtain a trained recognition model; and deploying the trained recognition model to a chip test or operation platform to output the fault recognition result set. The application adopts a circuit topology-aware graph neural network to realize real-time recognition of an integrated circuit fault mode.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit testing and fault diagnosis technology, and in particular to a method for integrated circuit fault mode recognition based on deep learning. Background Technology

[0002] Current integrated circuit fault detection methods primarily employ structural testing, functional testing, and timing analysis. Structural testing verifies logic units and interconnects through scan chains and automated test vectors, but its detection coverage is limited when dealing with complex topologies, parasitic parameters, and dynamic timing anomalies. Functional testing relies on comparing stimulus signals with responses to detect logic errors, but its ability to identify latent faults caused by electrical coupling or improper layout is insufficient. While timing analysis can verify critical path delays, its ability to jointly analyze multi-source heterogeneous data is weak, making it difficult to comprehensively characterize the dynamic features of the circuit under real-world operating conditions.

[0003] As process nodes shrink and circuit sizes increase, parasitic effects, electromagnetic coupling, and multi-layer topological relationships become more prominent. Some studies have attempted to apply graph neural networks or convolutional neural networks to fault detection, but the lack of dedicated structures for circuit topology characteristics has prevented the full utilization of temporal dependencies and electrical coupling information between nodes, edges, and critical paths, resulting in insufficient recognition accuracy and robustness.

[0004] Meanwhile, existing deep learning models have large parameter sizes and high computational overhead, making it difficult to meet the requirements of chip testing platforms or operating platforms for real-time inference and low power consumption. They also lack effective pruning and quantization compression mechanisms, which limits their ability to quickly identify fault modes in actual production testing and online operation.

[0005] Therefore, how to provide a deep learning-based integrated circuit fault mode recognition method is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] One objective of this invention is to propose a deep learning-based integrated circuit fault mode recognition method. This invention fully utilizes circuit topology-aware graph neural networks, multimodal feature fusion, and multi-task joint training techniques. It details the complete process of constructing a heterogeneous circuit graph from a standardized feature dataset, generating fused node embedding representations, and performing node-level, edge-level, and subgraph-level fault recognition. It has the advantages of high fault recognition accuracy, high real-time inference efficiency, and adaptability to complex circuit topologies.

[0007] A method for integrated circuit fault mode identification based on deep learning according to an embodiment of the present invention includes the following steps:

[0008] Collect multi-source raw data of integrated circuits and perform time alignment, format standardization, feature normalization and noise filtering to obtain a standardized feature dataset;

[0009] Based on a standardized feature dataset, a heterogeneous graph structure of circuits is constructed, and structural features, physical features and timing parameters are assigned to each node and edge to form an initial feature set of the graph structure.

[0010] Temporal embeddings are extracted from waveform sequences in the standardized feature dataset, and combined with the initial feature set of the graph structure to generate a multimodal input vector set;

[0011] The multimodal input vector set is input into the circuit topology sensing graph neural network model, and graph neural network propagation and embedding update operations are performed to output the fused node embedding representation.

[0012] Fault identification is performed based on the fusion node embedded representation, and a fault identification result set is generated.

[0013] A multi-task loss function is used to train the circuit topology sensing graph neural network model to obtain a trained recognition model;

[0014] The trained recognition model is deployed to a chip test or runtime platform to perform inference operations and output a set of fault recognition results.

[0015] Optionally, the step of acquiring multi-source raw data from integrated circuits and performing time alignment, format standardization, feature normalization, and noise filtering to obtain a standardized feature dataset specifically includes:

[0016] The signal waveform sequence output by the automated testing equipment is collected, and the voltage or current amplitude corresponding to different time points is recorded as continuous time series data. The time series data is then processed by timestamp alignment, noise reduction and normalization to obtain the signal waveform feature set.

[0017] The test vectors generated by the acquisition circuit simulation tool are recorded as logical data, and the logical data is subjected to unified format conversion, encoding and normalization to obtain the test vector feature set.

[0018] The structural data in the circuit netlist is collected, and the circuit unit, pin and network are used as nodes. The connection relationship between the nodes is used as the edge to construct the circuit topology information. At the same time, the logic type and fan-out degree are added to each node and edge. The topology information is then processed by format standardization and feature normalization to obtain the circuit topology feature set.

[0019] The physical data in the circuit layout is collected, the geometric coordinates of each node in the layout are recorded as spatial attributes, and the spatial attributes are standardized and normalized to obtain the physical feature set of the layout.

[0020] Parasitic parameter data in the acquisition circuit are collected, and the resistance, capacitance and coupling coefficients of each connection edge are recorded as electrical attributes. The electrical attributes are then processed for format unification and normalization to obtain the parasitic parameter feature set.

[0021] The timing report data of the acquisition circuit is recorded as timing attributes, and the path delay information and timing margin contained in the critical path set are recorded as timing attributes. The timing attributes are then standardized and normalized to obtain the timing path feature set.

[0022] The signal waveform feature set, test vector feature set, circuit topology feature set, layout physical feature set, parasitic parameter feature set, and timing path feature set are stored in a unified manner to form a standardized feature dataset.

[0023] Optionally, the construction of the heterogeneous graph structure based on the standardized feature dataset, assigning structural features, physical features, and timing parameters to each node and edge to form the initial feature set of the graph structure, specifically includes:

[0024] Based on the circuit topology feature set in the standardized feature dataset, circuit unit nodes, pin nodes and network nodes are extracted, and the three types of nodes are merged to form a node set.

[0025] Based on the circuit topology feature set, the connection relationship between circuit units, pins and networks is extracted, the connection between each node is defined as edge information, and these edges are uniformly organized into a set of connection edges.

[0026] Based on the parasitic parameter feature set, the resistance value, capacitance value and coupling coefficient corresponding to each connection edge are defined as electrical properties to establish a set of coupling edges;

[0027] Based on the physical feature set of the layout, the geometric coordinates of each node in the layout are used as spatial location information to calculate the geometric distance between nodes. When the geometric distance between two nodes meets the preset threshold condition, physical adjacency edges are established to form a set of physical adjacency edges.

[0028] Based on the time-series path feature set, each path in the critical path set is taken as a time-series dependency relationship. The delay information and time-series margin contained in the path are labeled, and time-series dependency edges are established between relevant nodes to form a time-series dependency edge set.

[0029] The sets of connecting edges, coupling edges, physical adjacency edges, and time-dependent edges are merged to generate multi-type edge sets. These multi-type edge sets are then combined with node sets to construct a heterogeneous circuit graph structure.

[0030] Assign a corresponding node feature vector to each node in the node set to form a complete set of node feature vectors;

[0031] Each edge in the edge set is assigned a corresponding edge feature vector. The feature vector of a connecting edge includes connection attribute parameters, the feature vector of a coupled edge includes resistance value, capacitance value and coupling coefficient, the feature vector of a physically adjacent edge includes the geometric distance between nodes, and the feature vector of a temporally dependent edge includes path delay information and temporal margin. This forms the initial feature set of the graph structure.

[0032] Optionally, the step of extracting temporal embeddings from waveform sequences in the standardized feature dataset, combining them with the initial feature set of the graph structure, and fusing them to generate a multimodal input vector set specifically includes:

[0033] Input the set of signal waveform sequences in the standardized feature dataset into a one-dimensional convolutional network or a position-encoded Transformer model to map the continuous voltage or current amplitude sequence into a set of time-series embedding vectors.

[0034] Based on the initial feature set of the graph structure, the structural attributes of circuit unit nodes, pin nodes and network nodes are extracted, and the logic type, fan-out degree and connectivity of each node are integrated into a structural feature vector to form a set of device structural features.

[0035] Based on the edge feature vectors in the initial feature set of the graph structure, physical parameter features are extracted. The resistance value, capacitance value and coupling coefficient corresponding to each coupled edge are recorded as physical attributes to form a set of physical parameter features.

[0036] Based on the heterogeneous circuit graph structure, an adjacency matrix is ​​established according to the connection between nodes. The number of connections of each node in the adjacency matrix is ​​used as the degree value to generate a degree matrix. The degree matrix and the adjacency matrix are then subjected to a difference operation to obtain the Laplace matrix.

[0037] Eigenvalue decomposition is performed on the Laplacian matrix to extract the eigenvectors corresponding to the smallest non-zero eigenvalues. The components of each node in these eigenvectors are combined to form the Laplacian eigenvectors of the node.

[0038] Define the critical path depth parameter and node centrality parameter, and generate a set of topological location codes for each node;

[0039] The critical path depth parameter refers to the maximum ratio of the position depth of a node in its critical path to the total length of the path, and the node centrality parameter refers to the comprehensive value obtained by weighting the node degree centrality and betweenness centrality.

[0040] The time-series embedding vector set, device structure feature set, physical parameter feature set, and topological position encoding set are concatenated according to the node correspondence, and the concatenated result is normalized to generate a multimodal input vector set.

[0041] Optionally, the step of inputting the multimodal input vector set into the circuit topology sensing graph neural network model, performing graph neural network propagation and embedding update operations, and outputting the fused node embedding representation specifically includes:

[0042] The multimodal input vector set is input into the circuit topology-aware graph neural network model, which includes a hyperedge aggregation module, an edge type-aware message passing module, a critical path gating mechanism, and a topology bias attention module.

[0043] The super-edge aggregation module aggregates the feature vectors of pin nodes with the network nodes as the center, obtains the network-level feature representation, and sends it back to the pin nodes to obtain the updated pin node feature set.

[0044] The edge type-aware message passing module sets independent message passing weight matrices for connecting edges, coupled edges, physical adjacency edges, and time-dependent edges based on the updated pin node feature set. It calculates the message vector corresponding to each edge type, aggregates the message vectors of the four edge types, and normalizes them to obtain the edge type-aware node feature set.

[0045] By using a critical path gating mechanism, based on the node feature set that is aware of edge type, the gating factor is calculated using the edge's time margin, path delay, resistance value, capacitance value and coupling coefficient.

[0046] The gating factor is multiplied by the original message vector of the edge, and the message vector is scaled to obtain the gated message vector. All the gated message vectors are aggregated to form a set of gated node features.

[0047] By introducing a topological bias term into the attention calculation of the gated node feature set through the topological bias attention module, a node feature set enhanced by topological bias attention is obtained.

[0048] The updated pin node feature set, edge type-aware node feature set, gated node feature set, and topology bias attention-enhanced node feature set are fused and residual updated in multiple rounds to output a fused node embedding representation.

[0049] Optionally, the step of aggregating the feature vectors of pin nodes using the hyperedge aggregation module, with the network nodes as the center, to obtain a network-level feature representation and then feeding it back to the pin nodes to obtain an updated pin node feature set specifically includes:

[0050] By using the hyperedge aggregation module, in the heterogeneous circuit diagram structure, the network node is used as the center node of the hyperedge, and the set of pin nodes is determined.

[0051] The feature vectors of all pin nodes in the pin node set are averaged and aggregated. The feature information of each pin node is weighted, summed, and divided by the number of pins to obtain the network-level feature representation.

[0052] The feature vectors of network nodes and the feature vectors of associated pin nodes are concatenated according to the node correspondence to obtain a combined feature vector. A linear transformation is performed on the combined feature vector to adjust the dimensionality distribution, and a nonlinear activation function is applied to enhance the feature representation capability. Subsequently, the processed vector is mapped and compressed layer by layer through a multilayer perceptron to obtain the updated pin node feature vector.

[0053] The updated pin node feature vectors are stored in a set according to the pin index, forming the updated pin node feature set.

[0054] Optionally, the step of introducing a topology bias term into the attention calculation of the gated node feature set through the topology bias attention module to obtain the node feature set enhanced by topology bias attention specifically includes:

[0055] The topology bias attention module maps each node feature vector in the gated node feature set to a query vector, a key vector, and a value vector, respectively.

[0056] To avoid relying solely on semantic similarity between nodes when calculating attention scores, a topological bias term is constructed. The topological bias term consists of three parts: the first part is the geometric distance between nodes, the second part is the topological hierarchy difference between nodes, and the third part is the electrical coupling coefficient between nodes. The above three parts are multiplied by the corresponding learnable weight parameters and then added together to form a complete topological bias term.

[0057] The topology bias term is added to the original score obtained by the inner product of the query vector and the key vector to form the topology bias attention score, where the query vector represents the feature mapping result of the current center node and the key vector represents the feature mapping result of the adjacent nodes.

[0058] For each edge pointing from the central node to an adjacent node, the topology bias attention score is used as the input for the exponential operation, and the exponential values ​​of all adjacent edges are normalized to obtain the topology bias attention weight.

[0059] The feature vectors of neighboring nodes are weighted using topological bias attention weights. This involves multiplying the feature vector of each neighboring node by its corresponding attention weight and then summing the results to obtain the updated feature vector of the center node.

[0060] The updated feature vectors of all nodes are combined into a set to form a node feature set with topological bias attention enhancement.

[0061] Optionally, fault identification is performed based on the fused node embedding representation, and the generated fault identification result set specifically includes:

[0062] Based on the fusion node embedding representation, the fusion feature vector of each node is input into the classification function. The node features are linearly mapped using weight parameters and bias parameters. The probability values ​​of each category are output through a normalized probability distribution function to obtain the fault type classification result of each node. The fault type classification results of all nodes are collected in a unified manner to form a set of fault type classification results at the node level.

[0063] At the edge level, connection anomaly scoring is performed. The fused feature vector of the edge, formed by concatenating the fused feature vectors of the two end nodes, is input into the scoring function. The concatenated features are mapped using weight parameters and bias parameters, and the anomaly score value of the edge is obtained through a normalization function. The anomaly score values ​​of all edges are collected to form a set of connection anomaly scoring results at the edge level.

[0064] At the subgraph level, fault path localization is performed by aggregating the node fusion feature vector and edge fusion feature vector corresponding to each path in the critical path set according to the path order, and then weighting the aggregation result with the attention weight obtained in the topology bias attention module to obtain the aggregated feature representation of the path.

[0065] The aggregated feature representation is mapped into the localization function to obtain the fault localization result of the corresponding path. The fault localization results of all critical paths are collected in a unified manner to form a set of fault path localization results at the subgraph level.

[0066] The fault identification result set is generated by merging the node-level fault type classification result set, the edge-level connection anomaly scoring result set, and the subgraph-level fault path location result set.

[0067] Optionally, the step of training the circuit topology sensing graph neural network model using a multi-task loss function to obtain the trained recognition model specifically includes:

[0068] Define a node-level classification loss function, which is calculated in the form of cross-entropy. That is, the log difference between the predicted probability and the true label value of each node under each fault category is measured, and the results of all nodes and all fault categories are summed to obtain the node-level classification loss.

[0069] Define a waveform reconstruction loss function and calculate it in the form of mean squared error. That is, for each time step in the waveform sequence, calculate the squared difference between the true waveform value and the reconstructed waveform value generated by the model, and then average the error values ​​of all time steps in the entire waveform sequence to obtain the waveform reconstruction loss.

[0070] Define a time-series violation prediction loss function and calculate it in the form of mean squared error. That is, for each critical path, calculate the squared difference between the actual time-series margin value and the model-predicted time-series margin value, and calculate the squared difference between the actual path delay value and the model-predicted path delay value. Then, average the above error results on all critical paths to obtain the time-series violation prediction loss.

[0071] Define a graph structure contrastive loss function and calculate it using contrastive learning. Specifically, for node embedding vectors belonging to positive sample pairs, calculate the feature distance between them and try to minimize it. For node embedding vectors belonging to negative sample pairs, calculate the feature distance between them and try to maximize it. By jointly constraining the feature differences between positive and negative sample pairs, the graph structure contrastive loss is obtained.

[0072] Define a network node consistency regularization term and calculate it in the form of mean squared error. That is, for each network node, calculate the squared difference of the prediction results of all the pin nodes connected to it, then average the squared difference results of all network nodes, and finally average the results of all network nodes to obtain the network node consistency regularization term.

[0073] The node-level classification loss function, waveform reconstruction loss function, temporal violation prediction loss function, graph structure comparison loss function, and the node consistency regularization term within the network are weighted and summed to obtain the multi-task loss function. That is, each loss function is assigned a corresponding weight parameter, and the loss values ​​are linearly combined according to the weight ratio to obtain a comprehensive loss value.

[0074] With minimizing the multi-task loss function as the optimization objective, iterative training is performed on the circuit topology perception graph neural network model. In each training round, the multimodal input vector set is used as a sample input to the model. After calculating the predicted output, it is compared with the real label to obtain the values ​​of each loss function. Then, the multi-task loss value obtained by weighted combination is backpropagated to the model parameters to update the weight matrix and bias parameters. After multiple rounds of iteration until the comprehensive loss value converges, the trained recognition model is finally obtained.

[0075] Optionally, the step of deploying the trained recognition model to a chip testing or running platform, performing inference operations, and outputting a fault recognition result set, and optimizing inference efficiency through model pruning and quantization compression, specifically includes:

[0076] The trained recognition model is deployed to a chip test platform or runtime platform, receives a standardized feature dataset and performs inference computation to obtain a fused node embedding representation.

[0077] In the inference computation, based on the fusion node embedding representation, a set of fault type classification results at the node level, a set of connection anomaly scoring results at the edge level, and a set of fault path localization results at the subgraph level are obtained and merged to form a fault identification result set.

[0078] During the inference computation process, pruning operations are performed on the trained recognition model to remove redundant connections with small weights, and quantization compression operations are performed to convert floating-point parameters into low-ratio specific-point representations, resulting in an optimized recognition model.

[0079] By utilizing an optimized recognition model to perform real-time inference on a standardized feature dataset on a chip testing platform or operating platform, a fault identification result set is output, enabling real-time identification of fault modes in the integrated circuit environment.

[0080] The beneficial effects of this invention are:

[0081] This invention constructs a circuit topology-aware graph neural network and introduces hyperedge aggregation, edge type-aware message passing, critical path gating, and topology bias attention structures to achieve accurate modeling of complex temporal dependencies between nodes, edges, and critical paths. The network takes a standardized feature dataset as input and performs multimodal fusion of signal waveform features, circuit structure features, layout physical features, parasitic parameter features, and temporal path features, completing feature aggregation and embedding updates within the graph neural network. Through this structured approach, the model maintains high-precision fault identification performance in heterogeneous topologies and dynamic electrical environments, overcoming the shortcomings of traditional methods in joint analysis of multi-source data and modeling of dynamic behavior on critical paths.

[0082] During the model training phase, this invention designs a multi-task loss function comprising node-level classification loss, waveform reconstruction loss, temporal violation prediction loss, graph structure comparison loss, and a network-internal node consistency regularization term. This multi-task optimization strategy simultaneously constrains the prediction accuracy and internal consistency of nodes, edges, and paths during a single training process, enabling the model to possess higher robustness and generalization ability at the three levels: node-level classification, edge-level connection anomaly detection, and subgraph-level fault path localization. Compared to existing schemes that rely solely on a single loss or a simple combination thereof, this design significantly improves the overall stability and accuracy of complex circuit fault mode recognition.

[0083] In the model deployment and inference stages, this invention combines pruning and quantization compression techniques to optimize the trained recognition model, effectively reducing redundant parameters and computational load. This enables the model to achieve low-latency, low-power real-time inference on chip testing or operating platforms. This optimization ensures timely output of fault identification results at the node, edge, and subgraph levels in actual production testing and online operating environments, meeting the needs for rapid diagnosis and efficient maintenance under large-scale, continuous operation conditions of integrated circuits. Attached Figure Description

[0084] The accompanying drawings are provided to further illustrate the invention and form part of the specification. They are used in conjunction with embodiments of the invention to explain the invention and do not constitute a limitation thereof. In the drawings:

[0085] Figure 1 This is a flowchart of a deep learning-based integrated circuit fault mode recognition method proposed in this invention;

[0086] Figure 2 This is a schematic diagram of the circuit topology sensing graph neural network model structure in the integrated circuit fault mode recognition method based on deep learning proposed in this invention;

[0087] Figure 3 This is a schematic diagram of the topology bias attention module in the deep learning-based integrated circuit fault mode recognition method proposed in this invention. Detailed Implementation

[0088] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, illustrating only the basic structure of the invention, and therefore only show the components relevant to the invention.

[0089] refer to Figure 1-3 A deep learning-based integrated circuit fault mode recognition method includes the following steps:

[0090] Collect multi-source raw data of integrated circuits and perform time alignment, format standardization, feature normalization and noise filtering to obtain a standardized feature dataset;

[0091] Based on a standardized feature dataset, a heterogeneous graph structure of circuits is constructed, and structural features, physical features and timing parameters are assigned to each node and edge to form an initial feature set of the graph structure.

[0092] Temporal embeddings are extracted from waveform sequences in the standardized feature dataset, and combined with the initial feature set of the graph structure to generate a multimodal input vector set;

[0093] The multimodal input vector set is input into the circuit topology sensing graph neural network model, and graph neural network propagation and embedding update operations are performed to output the fused node embedding representation.

[0094] Fault identification is performed based on the fusion node embedded representation, and a fault identification result set is generated.

[0095] A multi-task loss function is used to train the circuit topology sensing graph neural network model to obtain a trained recognition model;

[0096] The trained recognition model is deployed to a chip test or runtime platform to perform inference operations and output a set of fault recognition results.

[0097] In this embodiment, the process of acquiring multi-source raw data from integrated circuits and performing time alignment, format standardization, feature normalization, and noise filtering to obtain a standardized feature dataset specifically includes:

[0098] The signal waveform sequence output by the automated test equipment is collected, and the voltage or current amplitude corresponding to different time points is recorded as continuous time series data. The time series data is then processed by timestamp alignment, denoising and normalization to obtain a signal waveform feature set used to characterize the dynamic behavior of the circuit.

[0099] The test vectors generated by the acquisition circuit simulation tool are recorded as logic data, and the logic data is subjected to unified format conversion, encoding and normalization to obtain a test vector feature set used to characterize the logic characteristics of the circuit.

[0100] The structural data in the circuit netlist is collected, and the circuit unit, pin and network are used as nodes. The connection relationship between the nodes is used as the edge to construct the circuit topology information. At the same time, the logic type and fan-out degree are added to each node and edge. The topology information is processed by format standardization and feature normalization to obtain the circuit topology feature set used to characterize the circuit structure relationship.

[0101] The physical data in the circuit layout is collected, the geometric coordinate position of each node in the layout is recorded as a spatial attribute, and the spatial attribute is subjected to coordinate standardization and normalization to obtain a layout physical feature set used to characterize the physical layout characteristics of the circuit.

[0102] Parasitic parameter data in the circuit are collected, and the resistance, capacitance and coupling coefficients of each connection edge are recorded as electrical attributes. The electrical attributes are then formatted and normalized to obtain a parasitic parameter feature set that characterizes the electrical properties of the circuit.

[0103] The timing report data of the acquisition circuit is collected, and the path delay information and timing margin contained in the critical path set are recorded as timing attributes. The timing attributes are then standardized and normalized to obtain a timing path feature set that characterizes the timing constraint characteristics of the circuit.

[0104] The signal waveform feature set, test vector feature set, circuit topology feature set, layout physical feature set, parasitic parameter feature set, and timing path feature set are stored in a unified manner to form a standardized feature dataset.

[0105] In this embodiment, the step of constructing a heterogeneous circuit graph structure based on a standardized feature dataset, and assigning structural features, physical features, and timing parameters to each node and edge to form an initial feature set of the graph structure, specifically includes:

[0106] Based on the circuit topology feature set in the standardized feature dataset, circuit unit nodes, pin nodes and network nodes are extracted, and the three types of nodes are merged to form a node set, which is used to represent the overall structure of each device, connection port and signal network in the circuit.

[0107] Based on the circuit topology feature set, the connection relationship between circuit units, pins and networks is extracted. The connection between each node is defined as edge information, and these edges are uniformly organized into a set of connection edges to characterize the structural connection features between circuit elements.

[0108] Based on the parasitic parameter feature set, the resistance value, capacitance value and coupling coefficient corresponding to each connection edge are defined as electrical attributes to establish a set of coupling edges, which is used to characterize the electrical characteristics of the circuit at the connection level.

[0109] Based on the physical feature set of the layout, the geometric coordinates of each node in the layout are used as spatial position information to calculate the geometric distance between nodes. When the geometric distance between two nodes meets the preset threshold condition, physical adjacency edges are established, thereby forming a set of physical adjacency edges, which is used to characterize the adjacency relationship of the circuit at the layout level.

[0110] Based on the timing path feature set, each path in the critical path set is taken as a timing dependency relationship. The delay information and timing margin contained in the path are marked, and timing dependency edges are established between relevant nodes accordingly to form a timing dependency edge set, which is used to characterize the dependency characteristics of the circuit at the timing constraint level.

[0111] The set of connecting edges, coupling edges, physical adjacency edges, and time-dependent edges are merged to generate a multi-type edge set. This multi-type edge set is then combined with the node set to construct a circuit heterogeneous graph structure, which is used to uniformly represent the structural, electrical, physical, and time-dependent characteristics of the circuit.

[0112] Each node in the node set is assigned a corresponding node feature vector. The feature vector of the circuit unit node includes the logic type and fan-out parameter, the feature vector of the pin node includes the logic state parameter, and the feature vector of the network node includes the connectivity parameter. This forms a complete set of node feature vectors, which are used to describe the attribute information of the circuit at the node level.

[0113] Each edge in the edge set is assigned a corresponding edge feature vector. The feature vector of a connected edge includes connection attribute parameters, the feature vector of a coupled edge includes resistance value, capacitance value and coupling coefficient, the feature vector of a physically adjacent edge includes the geometric distance between nodes, and the feature vector of a timing-dependent edge includes path delay information and timing margin. This forms the initial feature set of the graph structure, which is used to describe the attribute information of the circuit at the edge level.

[0114] In this embodiment, the step of extracting temporal embeddings from waveform sequences in the standardized feature dataset, combining them with the initial feature set of the graph structure, and fusing them to generate a multimodal input vector set specifically includes:

[0115] The set of signal waveform sequences in the standardized feature dataset is input into a one-dimensional convolutional network or a position-encoded Transformer model, which maps the continuous voltage or current amplitude sequence into a set of time-series embedding vectors to obtain the time-series feature vector corresponding to each time step, which is used to characterize the dynamic characteristics of the circuit in the time dimension.

[0116] Based on the initial feature set of the graph structure, the structural attributes of circuit unit nodes, pin nodes and network nodes are extracted. The logic type, fan-out degree and connectivity of each node are integrated into a structural feature vector to form a set of device structural features, which is used to characterize the characteristics of the circuit at the structural level.

[0117] Based on the edge feature vectors in the initial feature set of the graph structure, physical parameter features are extracted. The resistance value, capacitance value and coupling coefficient corresponding to each coupled edge are recorded as physical attributes, and these physical attributes are organized into a set of physical parameter features to characterize the electrical characteristics of the circuit at the interconnect level.

[0118] Based on the heterogeneous circuit graph structure, an adjacency matrix is ​​established according to the connection between nodes. The number of connections of each node in the adjacency matrix is ​​used as the degree value to generate a degree matrix. The degree matrix and the adjacency matrix are then subjected to a difference operation to obtain a Laplace matrix used to characterize the overall topological structure.

[0119] Eigenvalue decomposition is performed on the Laplacian matrix to extract the eigenvectors corresponding to the smallest non-zero eigenvalues. The components of each node in these eigenvectors are combined to form the Laplacian eigenvectors of the node.

[0120] Define critical path depth parameters and node centrality parameters, and generate a set of topological position codes for each node to characterize the node's positional characteristics in the overall circuit topology;

[0121] The critical path depth parameter refers to the maximum ratio of the position depth of a node in its critical path to the total length of the path, which is used to characterize the hierarchical depth of the node on the critical path. The node centrality parameter refers to the comprehensive value obtained by weighting the node degree centrality and betweenness centrality, which is used to measure the node’s connectivity and its mediating role in information transmission.

[0122] The timing embedding vector set, device structure feature set, physical parameter feature set, and topology location encoding set are concatenated according to the node correspondence, and the concatenated result is normalized to finally generate a multimodal input vector set, which is used as input data for the subsequent circuit topology sensing graph neural network model.

[0123] In this embodiment, the step of inputting the multimodal input vector set into the circuit topology sensing graph neural network model, performing graph neural network propagation and embedding update operations, and outputting the fused node embedding representation specifically includes:

[0124] The multimodal input vector set is input into the circuit topology-aware graph neural network model, which includes a hyperedge aggregation module, an edge type-aware message passing module, a critical path gating mechanism, and a topology bias attention module, used to perform the propagation and update operations of node features in the graph structure.

[0125] The super-edge aggregation module aggregates the feature vectors of pin nodes with the network nodes as the center, obtains the network-level feature representation, and sends it back to the pin nodes to obtain the updated pin node feature set.

[0126] The edge type-aware message passing module sets independent message passing weight matrices for connecting edges, coupled edges, physical adjacency edges, and time-dependent edges based on the updated pin node feature set. It calculates the message vector corresponding to each edge type, where the message vector is a combination of node features and features of adjacent edges. Information is passed to the target node through message passing. The message vectors of the four edge types are aggregated and normalized to obtain the edge type-aware node feature set.

[0127] Through the critical path gating mechanism, based on the node feature set that is aware of edge type, the gating factor is calculated using the edge's timing margin, path delay, resistance value, capacitance value and coupling coefficient. The gating factor takes a value between zero and one and is used to represent the importance of the edge in message passing.

[0128] The gating factor is multiplied by the original message vector of the edge, and the message vector is scaled to obtain the gated message vector. All the gated message vectors are aggregated to form a set of gated node features, which is used to update the feature representation of each node in the graph structure.

[0129] By introducing a topological bias term into the attention calculation of the gated node feature set through the topological bias attention module, a node feature set enhanced by topological bias attention is obtained.

[0130] The updated pin node feature set, edge type-aware node feature set, gated node feature set, and topology bias attention-enhanced node feature set are fused and residual updated in multiple rounds to finally output a fused node embedding representation, which is used to characterize the comprehensive state of each node in the circuit under structural features, electrical characteristics, and timing constraints.

[0131] In this embodiment, the step of aggregating the feature vectors of pin nodes with network nodes as the center through the hyperedge aggregation module to obtain network-level feature representations and then sending them back to the pin nodes to obtain the updated pin node feature set specifically includes:

[0132] In the heterogeneous circuit diagram structure, the network node is used as the center node of the superedge through the superedge aggregation module, and the pin node set is determined. The pin node set includes all pin nodes directly connected to the network node, and the number of pin nodes and index relationship corresponding to each network node are recorded in the form of a set.

[0133] The feature vectors of all pin nodes in the pin node set are averaged and aggregated. The feature information of each pin node is weighted, summed, and divided by the number of pins to obtain the network-level feature representation of the corresponding network node, which is used to characterize the comprehensive state of the network node under the features of all its associated pin nodes.

[0134] The feature vectors of network nodes and the feature vectors of associated pin nodes are concatenated according to the node correspondence to obtain a combined feature vector. A linear transformation is performed on the combined feature vector to adjust the dimensionality distribution, and a nonlinear activation function is applied to enhance the feature representation capability. Subsequently, the processed vector is mapped and compressed layer by layer through a multilayer perceptron to obtain the updated pin node feature vector.

[0135] The updated pin node feature vectors are stored in a set according to the pin index to form an updated pin node feature set, which is used to provide the subsequent edge type-aware message passing module to perform node feature propagation.

[0136] In this embodiment, the step of introducing a topology bias term into the attention calculation of the gated node feature set through the topology bias attention module to obtain a node feature set enhanced by topology bias attention specifically includes:

[0137] The topology bias attention module maps each node feature vector in the gated node feature set to a query vector, a key vector, and a value vector. The query vector represents the feature requirement of the current central node, the key vector represents the feature identifier of the neighboring node, and the value vector represents the feature content that the neighboring node can pass on, providing input for subsequent attention calculation.

[0138] To avoid relying solely on semantic similarity between nodes when calculating attention scores, a topological bias term is constructed. This topological bias term consists of three parts: the first part is the geometric distance between nodes, used to characterize the spatial relative position of nodes in the layout; the second part is the topological hierarchy difference between nodes, used to reflect the depth difference between two nodes in the circuit hierarchy; and the third part is the electrical coupling coefficient between nodes, used to reflect the electrical coupling strength during signal transmission. These three parts are multiplied by their corresponding learnable weight parameters and then added together to form a complete topological bias term. This topological bias term is introduced into the attention calculation to comprehensively consider spatial layout characteristics, structural hierarchy characteristics, and electrical characteristics.

[0139] After obtaining the topology bias term, the topology bias term is added to the original score obtained by the inner product of the query vector and the key vector to form the topology bias attention score. The query vector represents the feature mapping result of the current center node, and the key vector represents the feature mapping result of the adjacent node. The inner product of the two is used to measure the similarity between the two nodes in the feature space. The topology bias term is used to supplement the consideration of spatial distance, hierarchical difference and electrical coupling strength.

[0140] Subsequently, for each edge pointing from the central node to an adjacent node, the topological bias attention score is used as the input for the exponential operation, and the exponential values ​​of all adjacent edges are normalized so that the attention weight of each edge is between zero and one, and the sum of the attention weights of all adjacent edges of the central node is equal to one, thus obtaining the topological bias attention weight, which is used to characterize the relative importance of different adjacent nodes when updating the features of the central node.

[0141] The feature vectors of adjacent nodes are weighted using topological bias attention weights. This involves multiplying the feature vector of each adjacent node by its corresponding attention weight and then summing the results to obtain the updated feature vector of the central node. The updated feature vector integrates the feature information of all adjacent nodes and highlights the features of adjacent nodes that have a greater impact on the central node based on the attention weights.

[0142] The updated feature vectors of all nodes are combined into a set to form a node feature set with topological bias attention enhancement.

[0143] In this embodiment, fault identification is performed based on the fused node embedding representation, and the generation of a fault identification result set specifically includes:

[0144] Based on the fusion node embedding representation, the fusion feature vector of each node is input into the classification function. The node features are linearly mapped using weight parameters and bias parameters. The probability values ​​of each category are output through a normalized probability distribution function, thereby obtaining the fault type classification result of each node. The classification results of all nodes are collected in a unified manner to form a node-level fault type classification result set. The fault type classification result set includes four categories of results: open circuit fault, short circuit fault, time delay abnormal fault, and logic abnormal fault.

[0145] At the edge level, connection anomaly scoring is performed. The fused feature vector of the edge, formed by concatenating the fused feature vectors of the two end nodes, is input into the scoring function. The concatenated features are mapped using weight parameters and bias parameters, and the anomaly score value of the edge is obtained through a normalization function. The anomaly score value is used to characterize the probability of open-circuit faults, short-circuit faults, delay anomalies, or logic anomalies occurring in the connection relationship of the edge. The anomaly score values ​​of all edges are collected to form a set of connection anomaly scoring results at the edge level.

[0146] At the subgraph level, fault path localization is performed by aggregating the node fusion feature vector and edge fusion feature vector corresponding to each path in the critical path set according to the path order, and then weighting the aggregation result with the attention weight obtained in the topology bias attention module to obtain the aggregated feature representation of the path.

[0147] The aggregated feature representation is mapped into the localization function to obtain the fault localization result of the corresponding path. The fault localization results of all critical paths are collected in a unified manner to form a set of fault path localization results at the subgraph level.

[0148] The fault identification result set is generated by merging the node-level fault type classification result set, the edge-level connection anomaly scoring result set, and the subgraph-level fault path location result set.

[0149] In this embodiment, the step of training the circuit topology sensing graph neural network model using a multi-task loss function to obtain a trained recognition model specifically includes:

[0150] Define a node-level classification loss function to constrain the difference between the classification result of the fused node embedding representation at the node level and the true label. It is calculated in the form of cross-entropy, that is, the log difference between the predicted probability and the true label value of each node under each fault category is measured, and the results of all nodes and all fault categories are summed to obtain the node-level classification loss, which is used to measure the prediction accuracy of the model in the node fault type classification task.

[0151] Define a waveform reconstruction loss function to constrain the accuracy of the model when reconstructing the signal waveform feature set. It is calculated in the form of mean square error, that is, for each time step in the waveform sequence, the square of the difference between the real waveform value and the reconstructed waveform value generated by the model is calculated, and then the error values ​​of all time steps in the entire waveform sequence are averaged to obtain the waveform reconstruction loss, which is used to measure the model's fitting ability in recovering the dynamic waveform features of the circuit.

[0152] A temporal violation prediction loss function is defined to constrain the accuracy of the model's temporal margin and delay prediction on critical paths. It is calculated in the form of mean squared error. That is, for each critical path, the squared difference between the actual temporal margin value and the model-predicted temporal margin value is calculated, and the squared difference between the actual path delay value and the model-predicted path delay value is also calculated. The above error results on all critical paths are then averaged to obtain the temporal violation prediction loss, which is used to measure the prediction accuracy of the model under the temporal constraints of critical paths.

[0153] A graph structure contrast loss function is defined to enhance the model's discriminative ability under the characteristics of circuit diagram structure. It is calculated in the form of contrastive learning, that is, for the node embedding vectors belonging to positive sample pairs, the feature distance between them is calculated and minimized as much as possible, and for the node embedding vectors belonging to negative sample pairs, the feature distance between them is calculated and maximized as much as possible. By jointly constraining the feature differences between positive and negative sample pairs, the graph structure contrast loss is obtained, which is used to improve the model's sensitivity and discriminative power to differences in circuit diagram structure.

[0154] Define a network node consistency regularization term to constrain the consistency of prediction results among multiple pin nodes under the same network node. It is calculated in the form of mean squared error. That is, for each network node, the prediction results of all its connected pin nodes are squared for pairwise differences, then the squared differences of all the network node are averaged, and finally the results of all network nodes are averaged to obtain the network node consistency regularization term, which is used to ensure that the pin prediction results under the same network node are consistent.

[0155] The node-level classification loss function, waveform reconstruction loss function, temporal violation prediction loss function, graph structure comparison loss function, and the node consistency regularization term within the network are weighted and summed to obtain the multi-task loss function. That is, each loss function is assigned a corresponding weight parameter, and the loss values ​​are linearly combined according to the weight ratio to obtain a comprehensive loss value, which is used to simultaneously take into account the optimization objectives of node classification, waveform reconstruction, temporal prediction, graph structure discrimination, and node consistency during the training process.

[0156] With minimizing the multi-task loss function as the optimization objective, iterative training is performed on the circuit topology sensing graph neural network model. In each training round, the multimodal input vector set is used as a sample input to the model. The predicted output is calculated and compared with the real label to obtain the values ​​of each loss function. The weighted combination of the multi-task loss value is then backpropagated to the model parameters to update the weight matrix and bias parameters. After multiple iterations until the comprehensive loss value converges, the trained recognition model is finally obtained and used for subsequent fault mode recognition tasks.

[0157] In this embodiment, the step of deploying the trained recognition model to a chip testing or running platform, performing inference operations, and outputting a fault recognition result set, and optimizing inference efficiency through model pruning and quantization compression specifically includes:

[0158] The trained recognition model is deployed to a chip test platform or runtime platform, receives a standardized feature dataset and performs inference computation to obtain a fused node embedding representation.

[0159] In the inference computation, based on the fusion node embedding representation, a set of fault type classification results at the node level, a set of connection anomaly scoring results at the edge level, and a set of fault path localization results at the subgraph level are obtained and merged to form a fault identification result set.

[0160] During the inference computation process, pruning operations are performed on the trained recognition model to remove redundant connections with small weights, and quantization compression operations are performed to convert floating-point parameters into low-ratio specific-point representations, resulting in an optimized recognition model.

[0161] By utilizing an optimized recognition model to perform real-time inference on a standardized feature dataset on a chip testing platform or operating platform, a fault identification result set is output, enabling real-time identification of fault modes in the integrated circuit environment.

[0162] Example 1:

[0163] To verify the feasibility of this invention in practice, it was applied to the combined final testing and system-level testing phase of a mass-produced chip. This scenario corresponds to the post-testing section of a 12-inch production line, where the daily wafer throughput is at a medium-to-high level. The chip contains multiple power domains and clock domains, with a netlist size of approximately 10,000,000 gates. Long-term field records show that structural and functional tests have high coverage of open-circuit and short-circuit faults, but low detection rates for delay and logic anomalies caused by parasitic parameters and electrical coupling. When the critical path approaches the timing margin boundary, both the false positive and false negative rates increase, leading to increased costs of repeated testing and rework. Furthermore, the lack of a unified modeling link between multiple data sources makes it difficult to coordinate waveform, topology, and layout information, resulting in a longer positioning cycle.

[0164] In this scenario, the method of the present invention is implemented according to the claims. First, a standardized feature dataset is constructed based on automated test equipment logs, simulation waveforms, netlists, layout parasitic parameters, and timing reports, forming a signal waveform feature set, a test vector feature set, a circuit topology feature set, a layout physical feature set, a parasitic parameter feature set, and a timing path feature set.

[0165] Subsequently, circuit unit nodes, pin nodes, and network nodes are extracted from the circuit topology feature set, and connection edges, coupling edges, physical adjacency edges, and timing-dependent edges are established to form a heterogeneous circuit graph structure. After aligning waveform encoding, structural features, physical parameters, and topology position encoding, a multimodal input vector set is generated and input into the circuit topology-aware graph neural network model. Hyperedge aggregation, edge type-aware message passing, critical path gating, and topology bias attention are executed sequentially to obtain a fused node embedding representation, and output a set of fault type classification results at the node level, a set of connection anomaly scoring results at the edge level, and a set of fault path localization results at the subgraph level.

[0166] Training employs multi-task optimization using node-level classification loss, waveform reconstruction loss, temporal violation prediction loss, graph structure comparison loss, and intra-network node consistency regularization. Deployment prunes and compresses the trained recognition model with 8-bit quantization, enabling it to run in real time on test production line servers and edge inference devices.

[0167] During the continuous evaluation period, the training set contains 1,200,000 waveform segments, 2,300,000 node samples, 4,800,000 edge samples, and 260,000 critical path samples; the validation set and independent test set are isolated by batch and cover different process corners.

[0168] Using joint structure / functional testing as baseline one and a graph neural network with critical path gating and topology bias attention removed as baseline two, in the node-level fault type classification task, the macro-average precision of this invention is 97.2%, recall is 96.8%, and overall performance is 97.0%. Baseline one yields 92.1%, 88.9%, and 90.5%, respectively, while baseline two yields 94.7%, 93.3%, and 94.0%, respectively. The area under the curve for edge-level connection anomaly scoring is 0.972; baseline one yields 0.884, and baseline two yields 0.942. It decreases to 0.945 when only topology bias attention is removed, to 0.948 when only critical path gating is removed, and to 0.939 when both are removed.

[0169] The first hit rate for subgraph-level fault path localization was 86.3%, and the first three hit rates were 94.1%. The first hit rate for baseline one was 63.8%, and the first hit rate for baseline two was 78.9%. Backtracking of field test samples showed that the false negative rate for delay anomalies and logic anomalies decreased by ≥40.0 percentage points compared to baseline one, while the false positive rate decreased by 32.0 percentage points.

[0170] In terms of deployment performance, the uncompressed model has a single-device inference latency of 480ms; after pruning to approximately 60% and using 8-bit quantization, the single-device latency is reduced to 95ms, throughput is 5600 samples / second, and inference power consumption is reduced by 38%. Under the same shift statistics, the median time from initial fault diagnosis to fault location decreased from 32 minutes to 15 minutes, the repeat test rate decreased from 20.7% to 15.9%, and the first-pass yield improved by an absolute 0.8 percentage points. For subsequent batches sampled under statistical distribution offset conditions, the key indicators decreased by no more than 0.8 percentage points.

[0171] The above data shows that, in mass production testing scenarios, this invention achieves multi-level identification and localization of open circuit faults, short circuit faults, delay abnormal faults, and logic abnormal faults, while ensuring identification accuracy and meeting real-time and resource constraints.

[0172] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A method for integrated circuit fault mode recognition based on deep learning, characterized in that, Includes the following steps: Collect multi-source raw data of integrated circuits and perform time alignment, format standardization, feature normalization and noise filtering to obtain a standardized feature dataset; Based on a standardized feature dataset, a heterogeneous graph structure of circuits is constructed, and structural features, physical features and timing parameters are assigned to each node and edge to form an initial feature set of the graph structure. Temporal embeddings are extracted from waveform sequences in the standardized feature dataset, and combined with the initial feature set of the graph structure to generate a multimodal input vector set; The multimodal input vector set is input into the circuit topology sensing graph neural network model, and graph neural network propagation and embedding update operations are performed to output the fused node embedding representation. Fault identification is performed based on the fusion node embedded representation, and a fault identification result set is generated. A multi-task loss function is used to train the circuit topology sensing graph neural network model to obtain a trained recognition model; Deploy the trained recognition model to a chip test or runtime platform, perform inference operations, and output a set of fault recognition results. The construction of a heterogeneous graph structure based on a standardized feature dataset, which assigns structural features, physical features, and timing parameters to each node and edge to form an initial feature set for the graph structure, specifically includes: Based on the circuit topology feature set in the standardized feature dataset, circuit unit nodes, pin nodes, and network nodes are extracted and merged to form a node set. Based on the circuit topology feature set, the connection relationship between circuit units, pins and networks is extracted to form a set of connection edges; Based on the parasitic parameter feature set, the resistance value, capacitance value and coupling coefficient corresponding to each connection edge are defined as electrical properties to establish a set of coupling edges; Based on the physical feature set of the layout, the geometric coordinates of each node in the layout are used as spatial location information to establish physical adjacency edges and form a set of physical adjacency edges. Based on the temporal path feature set, each path in the key path set is taken as a temporal dependency relationship, and temporal dependency edges are established to form a temporal dependency edge set. The sets of connecting edges, coupling edges, physical adjacency edges, and time-dependent edges are merged to generate multiple types of edge sets, which are then combined with the node set to construct a heterogeneous circuit graph structure. Assign a corresponding node feature vector to each node in the node set to form a node feature vector set, and assign a corresponding edge feature vector to each edge in the edge set to form an initial feature set of the graph structure.

2. The integrated circuit fault mode recognition method based on deep learning according to claim 1, characterized in that, The standardized feature dataset includes signal waveform sequence feature set, test vector feature set, circuit topology feature set, layout physical feature set, parasitic parameter feature set, and timing path feature set.

3. The integrated circuit fault mode recognition method based on deep learning according to claim 1, characterized in that, The step of extracting temporal embeddings from waveform sequences in the standardized feature dataset, combining them with the initial feature set of the graph structure, and fusing them to generate a multimodal input vector set specifically includes: Temporal features are extracted from the set of signal waveform sequences in the standardized feature dataset, and continuous voltage or current amplitude sequences are mapped into a set of temporal embedding vectors. Based on the initial feature set of the graph structure, the structural attributes of circuit unit nodes, pin nodes and network nodes are extracted to form a set of device structural features. Based on the edge feature vectors in the initial feature set of the graph structure, physical parameter features are extracted to form a physical parameter feature set. Based on the Laplacian matrix of the circuit heterogeneous graph structure, the Laplacian eigenvectors of the nodes are calculated, and the critical path depth parameter and node centrality parameter are defined to generate a set of topological location codes for each node. A multimodal input vector set is generated based on the temporal embedding vector set, the device structure feature set, the physical parameter feature set, and the topological position encoding set.

4. The integrated circuit fault mode recognition method based on deep learning according to claim 1, characterized in that, The step of inputting a multimodal input vector set into a circuit topology sensing graph neural network model, performing graph neural network propagation and embedding update operations, and outputting a fused node embedding representation specifically includes: The multimodal input vector set is input into the circuit topology-aware graph neural network model, which includes a hyperedge aggregation module, an edge type-aware message passing module, a critical path gating mechanism, and a topology bias attention module. The super-edge aggregation module aggregates the feature vectors of pin nodes with the network nodes as the center, obtains the network-level feature representation, and sends it back to the pin nodes to obtain the updated pin node feature set. By using the edge type-aware message passing module, based on the updated pin node feature set, independent message passing weight matrices are set for connecting edges, coupled edges, physical adjacency edges, and time-dependent edges, respectively, and the message vector corresponding to each edge type is calculated to obtain the edge type-aware node feature set. Through the critical path gating mechanism, based on the edge type-aware node feature set, the gating factor is calculated by combining the edge's timing margin, path delay, resistance, capacitance and coupling coefficient. The message vector of the edge is scaled based on the gating factor to form a gating-adjusted node feature set. By introducing a topological bias term into the attention calculation of the gated node feature set through the topological bias attention module, a node feature set enhanced by topological bias attention is obtained. The updated pin node feature set, edge type-aware node feature set, gated node feature set, and topology bias attention-enhanced node feature set are fused and residual updated in multiple rounds to output a fused node embedding representation.

5. The integrated circuit fault mode recognition method based on deep learning according to claim 4, characterized in that, The process of aggregating the feature vectors of pin nodes using the hyperedge aggregation module, centered on the network nodes, to obtain network-level feature representations, which are then fed back to the pin nodes, resulting in an updated pin node feature set, specifically includes: By using the hyperedge aggregation module, in the heterogeneous circuit diagram structure, the network node is used as the center node of the hyperedge to obtain the pin node set; The feature vectors of all pin nodes in the pin node set are averaged and aggregated to obtain the network-level feature representation; The feature vectors of network nodes are concatenated with the feature vectors of associated pin nodes according to the node correspondence relationship to obtain a combined feature vector; A linear transformation is performed on the combined feature vector, and a nonlinear activation function is applied. The processed vector is then mapped and compressed layer by layer through a multilayer perceptron to obtain the updated pin node feature vector. The updated pin node feature vectors are stored in a set according to the pin index, forming the updated pin node feature set.

6. The integrated circuit fault mode recognition method based on deep learning according to claim 4, characterized in that, The step of introducing a topological bias term into the attention calculation of the gated node feature set through the topological bias attention module to obtain a node feature set enhanced by topological bias attention specifically includes: The topology bias attention module maps each node feature vector in the gated node feature set to a query vector, a key vector, and a value vector, respectively. To avoid relying solely on semantic similarity when calculating attention scores, a topological bias term is constructed. This bias term is jointly defined by the geometric distance between nodes, the topological hierarchy difference, and the electrical coupling characteristics. The topological bias term is superimposed with the original attention scoring function to obtain the topological bias attention score, and the normalized attention weight is obtained through Softmax operation; The value vectors of adjacent nodes are weighted and summed using topological bias attention weights to obtain the node update feature vector enhanced by topological bias attention. The updated feature vectors of all nodes are combined into a set to form a node feature set with topological bias attention enhancement.

7. The integrated circuit fault mode recognition method based on deep learning according to claim 1, characterized in that, The fault identification based on the fused node embedding representation, and the generation of the fault identification result set, specifically includes: Based on the fused node embedding representation, fault type classification is performed at the node level. The fused feature vector of each node is input into the classification function to obtain the fault type classification result set for each node. At the edge level, connection anomaly scoring is performed by concatenating the fused feature vectors of the two end nodes to form the fused feature vector of the edge, which is then input into the scoring function to form a set of connection anomaly scoring results at the edge level. At the subgraph level, fault path localization is performed by aggregating the node fusion feature vector and edge fusion feature vector corresponding to each path in the critical path set according to the path order, and obtaining the subgraph path feature vector by weighted summation. The subgraph path feature vectors are input into the localization function for mapping, forming a set of fault path localization results at the subgraph level; The fault identification result set is generated by merging the node-level fault type classification result set, the edge-level connection anomaly scoring result set, and the subgraph-level fault path location result set.

8. The integrated circuit fault mode recognition method based on deep learning according to claim 1, characterized in that, The process of training the circuit topology sensing graph neural network model using a multi-task loss function to obtain the trained recognition model specifically includes: Define a node-level classification loss function and calculate it using the form of cross-entropy to obtain the node-level classification loss; Define a waveform reconstruction loss function and calculate it using the mean square error method to obtain the waveform reconstruction loss; Define the temporal violation prediction loss function and calculate it using the mean squared error method to obtain the temporal violation prediction loss; Define a graph structure contrastive loss function and calculate it using contrastive learning to obtain the graph structure contrastive loss; Define a node consistency regularization term within the network and calculate it using the mean squared error method to obtain the node consistency regularization term within the network. The multi-task loss function is obtained by weighted summing of the node-level classification loss function, waveform reconstruction loss function, temporal violation prediction loss function, graph structure comparison loss function and the node consistency regularization term in the network. With minimizing the multi-task loss function as the optimization objective, iterative training is performed on the circuit topology perception graph neural network model to obtain the trained recognition model.

9. The integrated circuit fault mode recognition method based on deep learning according to claim 1, characterized in that, The step of deploying the trained recognition model to a chip testing or operating platform, performing inference operations, and outputting a fault recognition result set specifically includes: The trained recognition model is deployed to a chip test platform or running platform, receives a standardized feature dataset and performs inference computation to obtain a fused node embedding representation; In inference computation, a fault identification result set is formed based on the fusion node embedding representation; During the inference computation process, pruning and quantization compression operations are performed on the trained recognition model to obtain an optimized recognition model; The optimized recognition model is used to perform real-time inference on a standardized feature dataset on a chip testing platform or operating platform, and output a fault recognition result set.

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