Approximate calculation method and related device

Abstract

The invention provides an approximate calculation method and a related device, and the method comprises the steps: selecting at least two circuit nodes with smaller errors from a circuit model through obtaining error information of a plurality of circuit nodes in the circuit model, and simplifying the circuit model through deleting the selected at least two circuit nodes. Therefore, the efficiency of automatic approximate calculation is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of electronics, and in particular, to a method for approximate calculation and related apparatus. BACKGROUND

[0002] Approximate calculation is a basic idea of modifying circuit structure by introducing errors to ensure normal operation of the circuit, thereby obtaining smaller area, lower power consumption and delay. Approximate calculation is mainly divided into approximate calculation achieved by artificial design (or artificial approximate calculation) and approximate calculation achieved by automatic method under the condition of given error constraint and circuit model (or automatic approximate calculation). The circuit model is a text file that can be recognized by a computer to describe the circuit, and the circuit model generally represents a plurality of circuit elements in the circuit through a plurality of circuit nodes.

[0003] Approximate logic synthesis (ALS) is an important method in the field of automatic approximate calculation, which aims to automatically generate an optimal approximate circuit for fault-tolerant applications under the condition of given error constraint. Due to the complexity of the circuit topology structure and the very large exploration space, the current ALS process usually adopts a greedy algorithm. For example, in each round of iteration selection, a local approximate change (LAC) is automatically performed on a node in the circuit model until the given error constraint is met.

[0004] However, as the size of the circuit continues to increase, the number of circuit nodes in the circuit model continues to increase, and the simplification efficiency of the ALS process continues to decrease. Therefore, how to improve the efficiency of automatic approximate calculation has become a problem to be solved. SUMMARY

[0005] The present application provides a method for approximate calculation and related apparatus, which relates to the technical field of electronics, but is not limited to the above technical field. For example, embodiments of the present application can be applied to the technical fields of approximate calculation, functional verification of approximate circuit, accurate circuit simplification, artificial intelligence (AI) application, circuit design, electronic design automation (EDA) tool and communication technology.

[0006] The scheme provided by the present application selects at least two circuit nodes with smaller errors from the circuit model by respectively obtaining error information of a plurality of circuit nodes in the circuit model, and simplifies the circuit model by deleting the selected at least two circuit nodes, thereby improving the efficiency of automatic approximate calculation.

[0007] In a first aspect, the present application provides a method for approximate calculation, which can be performed by an approximate calculation device. The approximate calculation device can be a computer device, or can be a part of a computer device (e.g., a processor, a chip, or a chip system, etc.), or can be a logic module or software for implementing the whole or part of a computer device.

[0008] In the method, the approximate calculation device obtains task information. The task information is used to indicate simplification of a circuit, and includes an error constraint and a circuit model for describing the circuit. The error constraint is used to indicate a condition that the simplified circuit satisfies, and the circuit model includes a plurality of circuit nodes representing a plurality of circuit elements in the circuit. Then, the approximate calculation device respectively simulates the circuit model using a plurality of sets of input signals, and respectively determines error information of each circuit node in the circuit model according to simulation results. Assuming that the plurality of circuit nodes include circuit node 1, circuit node 2, …, and circuit node n, the approximate calculation device can respectively determine error information of circuit node 1, error information of circuit node 2, …, and error information of circuit node n according to the simulation results. The error information of a single circuit node includes an error (referred to as a first error) generated by logically negating an output signal of the circuit node in the output signal of the circuit model under the plurality of sets of input signals. In this way, the error information of each circuit node in the circuit model includes the first error generated by logically negating the output signal of the corresponding circuit node in the output signal of the circuit model under the plurality of sets of input signals, or in other words, the error information of each circuit node includes the first error corresponding to the circuit node. Then, the approximate calculation device determines a target node set according to the error information of each circuit node in the circuit model. The target node set includes at least two circuit nodes in the circuit model corresponding to smaller first errors. When the circuit model after deleting the target node set satisfies the error constraint, the approximate calculation device can delete the target node set from the circuit model.

[0009] By obtaining the first error corresponding to each circuit node in the circuit model, it is beneficial to efficiently select a plurality of circuit nodes having a smaller impact on the output error after deletion in a global range. When the circuit model after deleting the selected plurality of circuit nodes satisfies the error constraint, the plurality of circuit nodes are deleted from the circuit model at one time, thereby benefiting to improve the simplification efficiency or area benefit of automatic approximate calculation while ensuring the circuit quality of the simplified circuit.

[0010] The first error can refer to a value of a first error indicator, and the present application does not limit the type of the first error indicator. Optionally, the circuit model further includes directed connections between different circuit nodes, and the directed connections are used to represent a signal input / output relationship between circuit elements represented by the connected circuit nodes.

[0011] Optionally, in the process of determining the target node set according to the error information of each circuit node in the circuit model, the approximation computing device can determine a first node set according to the error information of each circuit node in the circuit model and a first error threshold, and determine the target node set from the first node set. The first node set includes each circuit node in the circuit model corresponding to the first error less than the first error threshold. In this way, it is convenient for the user to personalize the area benefit of automatic approximation calculation by setting the first error threshold.

[0012] Optionally, the method further includes: when the circuit model after deleting the target node set does not satisfy the error constraint, the approximation computing device can reduce the value of the first error threshold and return to determine the first node set according to the error information of each circuit node in the circuit model and the first error threshold. In this way, when the simplified circuit model does not satisfy the error constraint due to the initial value of the first error threshold being too large, it is convenient to remove the circuit nodes with larger first error from the selected multiple circuit nodes by automatically reducing the value of the first error threshold, so as to obtain a simplified circuit satisfying the error constraint.

[0013] Optionally, the value of the first error threshold satisfies 2 k-1 , where k is a positive integer.

[0014] Optionally, the method further includes: the approximation computing device determines a replacement scheme corresponding to each circuit node in the target node set according to the error information of each circuit node in the circuit model. For example, the approximation computing device can determine a replacement scheme corresponding to circuit node 1, a replacement scheme corresponding to circuit node 2, …, and a replacement scheme corresponding to circuit node n, respectively. Correspondingly, in the process of deleting the target node set from the circuit model, the approximation computing device can delete each circuit node in the target node set in the circuit model according to the corresponding replacement scheme. For example, the approximation computing device deletes circuit node 1 according to the replacement scheme corresponding to circuit node 1, deletes circuit node 2 according to the replacement scheme corresponding to circuit node 2, …, and deletes circuit node n according to the replacement scheme corresponding to circuit node n.

[0015] Optionally, the replacement scheme corresponding to the circuit node is used to indicate that the circuit node is replaced by a constant (such as 0 or 1). In this way, it is convenient for the approximation computing device to determine the replacement scheme corresponding to each circuit node in the target node set within a smaller replacement scheme range, thereby improving the simplification efficiency.

[0016] Optionally, for any circuit node in the target node set, the residual error of the circuit node in the circuit model under the plurality of sets of input signals respectively according to the corresponding replacement scheme is greater than or equal to 0 or less than or equal to 0. For the convenience of description, the application will refer to the residual error of the circuit node in the circuit model under the plurality of sets of input signals respectively according to the corresponding replacement scheme as the residual error of the circuit node. When the residual error of the circuit node in the circuit model under the plurality of sets of input signals is greater than or equal to 0 or less than or equal to 0, it is considered that the circuit node has polarity. And for the convenience of description, when the residual error of the circuit node in the circuit model under the plurality of sets of input signals is greater than or equal to 0, it is considered that the polarity of the circuit node is positive, and when the residual error of the circuit node in the circuit model under the plurality of sets of input signals is less than or equal to 0, it is considered that the polarity of the circuit node is negative. Therefore, optionally, each circuit node in the target node set has polarity. The polarities of different circuit nodes in the target node set can be the same or different.

[0017] As previously described, the approximation computing device can determine the target node set from the first node set. Optionally, the approximation computing device can select a circuit node with polarity from the first node set as a circuit node in the target node set.

[0018] Optionally, the condition indicated by the error constraint includes that the target error of the output signal of the simplified circuit satisfies a target condition. Optionally, the error constraint can also include conditions satisfied by other parameters related to circuit quality (such as one or more of area, delay, and power consumption parameters).

[0019] Optionally, the circuit model after deleting the target node set satisfying the error constraint can include that the target error of the output signal of the circuit model after deleting the target node set satisfies the target condition after compensation. Or, optionally, the circuit model after deleting the target node set satisfying the error constraint can include that the target error of the output signal of the circuit model after deleting the target node set is less than or equal to the target error threshold.

[0020] When the error constraint also includes conditions satisfied by other parameters, the circuit model after deleting the target node set satisfying the error constraint can also include that the value of the other parameter of the circuit model after deleting the target node set satisfies the corresponding condition, whether or not the circuit is compensated.

[0021] Optionally, after the approximation computing device deletes the target node set from the circuit model, the approximation computing device can also perform a local approximation change (LAC) on the circuit model based on the compensation parameters of the circuit model.

[0022] The application does not limit the calculation method of the compensation parameters of the circuit model. Generally, the compensation parameters of the circuit model are changed after the circuit model is updated. Therefore, in the iteration process of different rounds, the compensation parameters of the circuit model used by the approximate calculation device are generally different because the circuit model is updated due to LAC. The approximate calculation device can record the compensation parameters of the circuit model and update the compensation parameters of the circuit model after each update of the circuit model.

[0023] Optionally, after each LAC of the circuit model, the approximate calculation device can perform circuit compensation on the circuit model according to the updated compensation parameters of the circuit model.

[0024] Alternatively, after each LAC of the circuit model, the approximate calculation device can only update the recorded compensation parameters and estimate the target error of the LAC scheme using the recorded compensation parameters, without performing circuit compensation on the circuit model, until the given error constraint, and then performing circuit compensation on the circuit model according to the current compensation parameters of the circuit model. Specifically, in the process of performing local approximate change LAC on the circuit model based on the compensation parameters of the circuit model, the approximate calculation device can determine a plurality of local approximate change LAC schemes of the circuit model, estimate the evaluation scores of the plurality of LAC schemes using the compensation parameters of the circuit model, wherein the evaluation score of the LAC scheme is positively correlated with the target error generated by the output signal of the compensated circuit model, and then perform local approximate change LAC on the circuit model according to the evaluation scores of the plurality of LAC schemes and return to determine the plurality of LAC schemes of the circuit model, until the plurality of LAC schemes do not meet the error constraint, and perform circuit compensation on the circuit model according to the compensation parameters of the circuit model.

[0025] The application does not limit the specific determination method of the evaluation score. For example, the evaluation score can be related to at least one of the parameters related to the quality of the circuit, such as circuit area, circuit delay, circuit power consumption, etc.

[0026] For ease of description, the circuit model obtained after LAC of the circuit model 0 according to a certain LAC scheme is denoted as circuit model', and the circuit model obtained after circuit compensation of the circuit model' according to the compensation parameters of the circuit model 0 is denoted as circuit model". Estimating the target error of the output signal of the circuit model 0 generated by the LAC scheme using the compensation parameters of the circuit model 0 can refer to estimating the target error of the output signal of the circuit model". Specifically, the approximate calculation device can obtain the output signal of the circuit model' under a plurality of groups of input signals, and then compensate the obtained plurality of groups of output signals using the compensation parameters of the circuit model 0, and determine the target error according to the compensated plurality of groups of output signals.

[0027] In the method described above, after the approximation computing device obtains the circuit model, the approximation computing device can update the circuit model for multiple times in sequence. In the process of the first update, the circuit model mentioned or the circuit model to be updated can refer to the circuit model in the task information. In the process of the i+1th update, the circuit model mentioned or the circuit model to be updated can refer to the circuit model obtained by the approximation computing device after the i th update. Wherein, i is a positive integer.

[0028] In a second aspect, the present application provides an approximation computing device, which comprises an input module and a first simplification module. The input module is configured to obtain task information used to indicate simplification of a circuit, wherein the task information comprises an error constraint and a circuit model used to describe the circuit, the error constraint is used to indicate a condition satisfied by the circuit after simplification, and the circuit model comprises a plurality of circuit nodes representing a plurality of circuit elements in the circuit. The first simplification module is configured to simulate the circuit model using a plurality of groups of input signals, and determine error information of each circuit node in the circuit model according to simulation results, wherein the error information of each circuit node comprises a first error generated by logically negating an output signal of the circuit node under the plurality of groups of input signals at the output signal of the circuit model. The first simplification module is further configured to determine a target node set according to the error information of each circuit node in the circuit model, wherein the target node set comprises at least two circuit nodes in the circuit model corresponding to smaller first errors. The first simplification module is further configured to delete the target node set from the circuit model when the circuit model after deletion of the target node set satisfies the error constraint.

[0029] Optionally, in the process of determining the target node set according to the error information of each circuit node in the circuit model, the first simplification module is specifically configured to determine a first node set according to the error information of each circuit node in the circuit model and a first error threshold, wherein the first node set comprises each circuit node in the circuit model corresponding to a first error smaller than the first error threshold; and then determine the target node set from the first node set.

[0030] Optionally, when the circuit model after deletion of the target node set does not satisfy the error constraint, the first simplification module is further configured to decrease a value of the first error threshold and return to determine the first node set according to the error information of each circuit node in the circuit model and the first error threshold.

[0031] Optionally, the value of the first error threshold satisfies 2 k-1 wherein k is a positive integer.

[0032] Optionally, the first simplification module is further configured to determine a replacement scheme of each circuit node in the target node set according to the error information of each circuit node in the circuit model.

[0033] Optionally, the replacement scheme of the circuit node indicates that the circuit node is replaced by a constant.

[0034] Optionally, for any circuit node in the target node set, the residual error generated by the output signal of the circuit model when the circuit node is deleted according to the corresponding replacement scheme under the multiple sets of input signals is greater than or equal to 0, or less than or equal to 0.

[0035] Optionally, the condition indicated by the error constraint includes that the target error of the output signal of the simplified circuit satisfies a target condition.

[0036] Optionally, the circuit model after the target node set is deleted satisfies the error constraint includes that the target error of the output signal of the circuit model after the target node set is deleted satisfies the target condition.

[0037] Optionally, the approximation computing device further includes a second simplification module, and the second simplification module is configured to perform local approximation change (LAC) on the circuit model based on the compensation parameter of the circuit model after the target node set is deleted from the circuit model.

[0038] Optionally, the second simplification module is configured to determine multiple LAC schemes of the circuit model, estimate evaluation scores of the multiple LAC schemes using the compensation parameter of the circuit model, the evaluation score is related to the target error generated by the output signal of the circuit model after compensation of the corresponding LAC scheme, and then perform LAC on the circuit model according to the evaluation scores of the multiple LAC schemes and return to determine the multiple LAC schemes of the circuit model until the multiple LAC schemes do not satisfy the error constraint, and perform circuit compensation on the circuit model according to the compensation parameter of the circuit model.

[0039] A third aspect of the embodiment of the present application provides a computer storage medium, which stores one or more instructions, and the instructions cause one or more computers to implement the method described in the first aspect or any possible implementation manner of the first aspect when executed by the one or more computers.

[0040] A fourth aspect of the embodiments of the present application provides a computer program product, which stores instructions, and the instructions, when executed by a computer, cause the computer to implement the method according to the first aspect or any possible implementation manner of the first aspect.

[0041] A fifth aspect of the embodiments of the present application provides a computer device, which comprises a memory and a processor, the memory stores codes, and the processor is configured to execute the codes, and when the codes are executed, the computer device executes the method according to the first aspect or any possible implementation manner of the first aspect.

[0042] The apparatus provided by the present application is used for executing the method according to the first aspect or any possible implementation manner of the first aspect, therefore, the beneficial effects of the apparatus provided by the present application can be understood with reference to the beneficial effects of the corresponding method. BRIEF DESCRIPTION OF DRAWINGS

[0043] Figure 1-1 Possible flow of ALS is schematically shown;

[0044] Figure 1-2 An example of selecting a target LAC in one iteration is schematically shown;

[0045] Figure 2-1 Another method of automatic approximation calculation, a direct truncation method, is schematically shown;

[0046] Figure 2-2 A structure diagram of an addition tree in a 6-bit by 6-bit multiplier is shown;

[0047] Figure 3-1 And Figure 3-2 A schematic diagram of Figure 2-2 Defects of the method shown;

[0048] Figure 4 A logic structure of the approximation calculation apparatus provided by the present application is schematically shown;

[0049] Figure 5 A method performed by the approximation calculation apparatus shown is schematically shown; Figure 4

[0050] An AIG of a circuit acquired by the input module shown is schematically shown; Figure 6-1 Figure 5 A circuit in which the output signal of a circuit node I1 in the input circuit shown is inverted is schematically shown;

[0051] Figure 6-2 Figure 6-1 A circuit in which the output signal of a circuit node I1 in the input circuit shown is inverted is schematically shown; ​​

[0052] Figure 6-3 An example of determining the target node set and the replacement scheme corresponding to each node from three circuit nodes E, F, and G is shown;

[0053] Figure 6-4 and Figure 6-5 Two methods of making a local approximate change (LAC) to the circuit model based on the compensation parameter of the circuit model are respectively shown schematically;

[0054] Figure 7 A method of determining the compensation parameter after truncation is shown schematically;

[0055] Figure 8 The circuit name, input and output quantity, and the area of the accurate circuit of the experimental circuit are shown schematically;

[0056] Figure 9 and 10 The normalized area and power consumption of the circuit obtained by the three schemes under the same error upper limit are respectively shown;

[0057] Figure 11 The running speed of the circuit obtained by the three schemes under the same error upper limit is shown;

[0058] Figure 12 A method of finding the logically equivalent part in the approximate circuit and the accurate circuit by solving SAT is shown schematically;

[0059] Figure 13 The structure of the computer device provided in the present application is shown schematically. DETAILED DESCRIPTION

[0060] As the transistor size becomes smaller and smaller, the integrated circuit design becomes more and more complex, and it is increasingly difficult to improve the performance of the circuit and reduce the energy consumption by traditional design methods. Many applications that have appeared in recent years, such as artificial intelligence, audio image processing, and big data pushing, have fault tolerance characteristics, and the error within a certain range does not affect the actual application function. Approximate computing technology is to take advantage of these fault tolerance characteristics, by reducing the calculation precision, and then obtaining the optimization of circuit power consumption, delay, and area. By using approximate computing technology, under the given approximate constraint conditions, such as error rate, error distance, average error, etc., a higher performance circuit can be designed.

[0061] Some embodiments of approximate computing are introduced below.

[0062] An important area of ​​automated approximation computation is ALS (Automatic Linear Reduction), which aims to generate approximate circuits with low hardware cost while satisfying given error constraints. Due to the complexity of circuit topologies and the vast exploration space, current ALS processes typically employ greedy algorithms. At each step, a greedy algorithm selects what appears to be the best choice, hoping to eventually reach the global optimum.

[0063] Figure 1-1 The diagram illustrates a possible ALS (Advanced Logic Response) process. In each iteration, several LACs (Local Area Codes) are generated for the circuit. Then, based on the evaluation scores of each LAC, the optimal LAC (called the target LAC) is selected and applied until a given error constraint is met. The evaluation score is typically composed of parameters related to circuit quality, such as circuit area, circuit delay, circuit power consumption, and output error, among others. Applying an LAC to the current circuit can be equivalent to performing some local approximation transformation on the current circuit (e.g., deleting a node, changing the logic gates of that node, etc.).

[0064] Figure 1-2 This illustration shows an example of selecting a target LAC during one round of iteration. Figure 1-2 In the circuit model, circles represent circuit nodes, and hexagons pointing to these nodes represent replacement schemes. The value 'S' above the hexagon represents the LAC (Local Area Classification) score for deleting the corresponding circuit node according to the replacement scheme. Figure 1-2 Of the six LACs shown, the LAC within the dashed box has the highest evaluation score. Figure 1-2 As shown in this iteration process, the LAC can be selected to update the circuit model.

[0065] Figure 2-1 This illustration demonstrates another method of automatic approximation (called the direct truncation method). Direct truncation is a widely used circuit approximation simplification technique that simplifies the circuit by setting the lower bits to a constant. Essentially, direct truncation adjusts the bit width of the circuit. For example... Figure 2-1 As shown, if the output error of setting the first 3 bits of the circuit (e.g., y0, y1, and y2) to 0 does not exceed the condition (or upper limit) indicated by the error constraint, but the output error exceeds the upper limit of the error constraint after setting the first 4 bits of the circuit (i.e., y0, y1, y2, and y3) to 0, then the output approximate circuit is to directly truncate the lowest 3 bits (i.e., y0, y1, and y2).

[0066] Next, an approximate calculation method (referred to as vertical truncation method) is introduced. Tso-Bing Juang et al. proposed an approximate simplification method with greater area benefit in the document “Low-Error Carry-Free Fixed-Width Multipliers With Low-Cost Compensation Circuits”. Figure 2-2 A structure diagram of an addition tree in a 6-bit by 6-bit multiplier is shown. The rightmost end represents the lowest bit, and the weight of the partial product corresponding to the i-th column from right to left is 2 i-1 . If 4 bits are truncated, all partial products with a weight of 2 k (k = 0, 1,..., 4) (such as the partial products on the right side of the dashed line in Figure 2-2 ) are deleted. Compared with the direct truncation circuit, such truncation can delete all partial products that bring smaller errors, and no longer reserve the carry chain, thereby achieving a greater degree of area benefit. Since it divides the truncated partial products by a vertical line, the present application refers to this technology as vertical truncation.

[0067] Next, another method of automatic approximate calculation is introduced. He et al. proposed an iterative approximate circuit simplification method (referred to as automatic pruning method) in the patent “An Automatic Pruning Method for Circuits Based on Global Optimization Algorithm”. In this method, first, a circuit is converted into a form containing only 2-input logic gates, and then according to an approximate weight model derived from the output end in reverse, the influence of each node on the output is obtained. Subsequently, according to the sorting of the reduction function value, a plurality of nodes are selected, and after a series of random cross combination, the circuit is simulated multiple times to obtain the final set of deleted nodes. The definition of the reduction function can be shown in the following formula:

[0068] TR0 = W x T0;

[0069] TR1 = W x T1;

[0070] func0 = TR0 x TR1 + TR02 + TR0 x mse;

[0071] func1 = TR0 x TR1 + TR12 + TR1 x mse.

[0072] In the above formula, W represents the node weight information, T0 and T1 represent the number of times of simulation when all nodes are randomly excited to 0 and 1, respectively, TR0 represents the error that may be caused by setting the node to 1, TR1 represents the error that may be caused by setting the node to 0, mse represents the mse error value of the last iteration, and func0 and func1 are the corresponding reduction function values.

[0073] Another method of automatic approximation is introduced as follows. Venkataramani et al. proposed an iterative-based approximation simplification method (referred to as the iterative simplification method) in the document “Substitute-and-Simplify: A Unified Design Paradigm for Approximate and Quality Configurable Circuits”. The flow of the iterative simplification method can be referred to as Figure 1-1 In each iteration round, the evaluation score of each LAC is evaluated in detail considering the transitive fanout (TFO), transitive fanin (TFI), arrival time, area, and error of the node, and finally an optimal LAC is selected according to the evaluation score for application.

[0074] The defects of the above approximation methods are analyzed as follows.

[0075] For the direct truncation method, especially for the widely used multiplier and adder units, only a certain node (logic gate) connected to the output is deleted, and the carry chain in the circuit is completely retained, which has little area benefit after introducing approximation.

[0076] For the vertical truncation method, the technology relies on the adder tree structure of the circuit, and it is difficult to simplify other arithmetic circuits (such as sin / sqrt circuits) with high area benefits. If the approximation design is performed first and then mapped into a netlist, the manual design is difficult and cannot be expanded or reused, and each circuit needs a certain design time under different error constraints. If the approximation design is performed after mapping into a netlist, due to the uncertainty of the optimization algorithm of logic synthesis, some partial products may not exist explicitly, and the vertical truncation cannot be achieved. For example Figure 3-1 and Figure 3-2 . Figure 3-1 The sub-circuit and partial product node E under theoretical analysis are schematically shown. If the node E is theoretically a partial product that needs to be deleted, when the synthesis tool simplifies the sub-circuit shown in Figure 3-1 into another equivalent sub-circuit (as shown in Figure 3-2 ), the node E may not exist. In addition, the compensation module of this technology is limited to adders, and the application in the iterative flow will significantly increase the additional area overhead. That is, the compensation module based on theoretical analysis has limited application scenarios, and the overhead of introducing the compensation circuit in the iterative flow is large.

[0077] For the direct truncation method and the vertical truncation method, although some initialization strategies are proposed, there are problems of low area gain, inability to significantly accelerate the ALS process (such as the direct truncation method), and inability to be automated and high difficulty and time cost of manual design (such as the vertical truncation method).

[0078] For the automatic pruning method, the technology only supports processing circuits containing 2-input logic gates, while the general application scenario is a netlist containing multi-input and multi-output logic gates. Moreover, the error estimation of each node is not accurate enough, and inaccurate error estimation often leads to worse quality of the approximate circuit. On the one hand, the weight model cannot reflect the real influence of the node on the output. On the other hand, the reduction function is only a qualitative expression, which is not conducive to the implementation of automatic approximation calculation. Although a scheme of deleting multiple nodes in each round is proposed to improve the simplification efficiency, the use of the error evaluation model with large error may affect the final circuit quality.

[0079] For the iterative simplification method, the search space of the technology is large, and only one node is selected for deletion after a large amount of calculation in each round, so the area reduction is small and the simplification efficiency is low. Through analysis, it is found that a good and automated circuit pre-simplification scheme is lacking to speed up the process.

[0080] In order to improve the simplification efficiency or area gain of automatic approximation calculation while ensuring the quality of the simplified circuit, the present application provides an automatic approximation calculation method. The error information (or statistical characteristics) of the node is extracted to represent the information of the node in the circuit structure, and multiple nodes are deleted in one update process of the circuit model based on the error information of each node. The simultaneous deletion of multiple nodes in the circuit realizes fast simplification of the circuit while ensuring the quality of the circuit. Not only does it overcome the technical limitations of the vertical truncation method with high area gain in automated design, but also expands the application scope.

[0081] The method provided by the present application can be executed by an approximation calculation device. The approximation calculation device can be a computer device, or can be a part of the computer device (such as a processor, a chip, or a chip system, etc.), or can be a logic module or software that implements all or part of the computer device. Figure 4 The logical structure of the approximation calculation device is schematically shown. As shown in Figure 4 The approximation calculation device can include an input module, a first simplification module, a second simplification module, and an output module. The approximation calculation device is used to execute a general efficient approximation logic synthesis method, which can obtain a high-quality approximate circuit under the given accurate circuit and error constraint. The generated approximate circuit can be widely used in application scenarios that have a certain tolerance to error but have strict restrictions on calculation efficiency, power consumption, and resource usage, including but not limited to neural networks, image processing, machine learning, etc.

[0082] The approximate calculation method provided in the present application is described below. As shown in Figure 5 The method can include S501-S502.

[0083] S501, the input module obtains task information;

[0084] The input module can obtain task information. The task information is used to indicate simplification of a circuit, and the task information includes error constraints and a circuit model used to describe the circuit. Alternatively, the circuit described by the circuit model in the task information is an accurate circuit.

[0085] The circuit model includes a plurality of circuit nodes (or simply nodes) representing a plurality of circuit elements in the circuit, and can also include directed connections between different circuit nodes, which are used to represent the signal input / output relationship between the circuit elements represented by the connected circuit nodes. The present application does not limit the type of circuit model. Optionally, the circuit model can be a text describing the circuit, such as an and-inverter-graph (AIG) or a berkeley logic interchange format (BLIF) or a netlist, etc. Hereinafter, the description text is taken as an example of AIG.

[0086] Figure 6-1 The AIG of the circuit is schematically shown. Figure 6-1 The triangle represents the input signal I of the circuit, the circle represents the circuit node or circuit element Z, and the square represents the output signal O. As shown in Figure 6-1 The circuit includes 4 input signals (denoted as I1-I4), 3 circuit nodes (denoted as Z1-Z3), and 1 output signal (denoted as O1). Moreover, Figure 6-1 The arrow direction of the connection line represents the input / output relationship of the signal, for example, the arrow direction of the connection line between I1 and Z1 represents that the input signal corresponding to I1 is input to the circuit element corresponding to Z1. Figure 6-1 The serial number of each node is an example of the identification of the node, which is only used to distinguish different nodes, and the present application does not limit the specific way of identifying the node by AIG.

[0087] Figure 6-1 Only as an example, the present application does not limit the size of the circuit. Hereinafter, it is assumed that the circuit has m input signals, n circuit elements and p output signals. Correspondingly, the AIG of the circuit can include n circuit nodes (denoted as Z).

[0088] The error constraint is used to indicate a condition that the simplified circuit satisfies. For example, the error constraint can indicate a condition that one or more parameters of the simplified circuit satisfy. The present application does not limit the specific type of the one or more parameters, for example, the one or more parameters can include one or more of parameters related to the quality of the circuit, such as circuit area, circuit delay, circuit power consumption, and output error.

[0089] The present application refers to the error index of the output error indicated by the error constraint as a target error index, and the present application does not limit the type of the target error index, for example, the target error index can include but is not limited to at least one of error rate (ER), mean-square error (MSE), and mean error distance (MED) and maximal error distance (MaxED). The target error can refer to the value of the target error index. Hereinafter, the threshold value of the target error index indicated by the error constraint is taken as an example.

[0090] S502, the first simplification module performs first simplification processing on the circuit model;

[0091] After the input module obtains the task information, the first simplification module can perform simplification processing on the circuit model (for example, AIG) therein to obtain a simplified circuit that satisfies the error constraint. In order to distinguish different simplification processing of the circuit by different simplification modules, the present application refers to the simplification processing of the circuit by the first simplification module as first simplification processing, and refers to the simplified circuit that satisfies the error constraint as an initialization simplified circuit.

[0092] In the first simplification processing, the first simplification module selects N circuit nodes from n circuit nodes, and then deletes the N circuit nodes. Wherein, N is a positive integer greater than 0 and less than n. The present application refers to the number of circuit nodes in the circuit model after the first simplification processing as N0, and N0 is a positive integer greater than 0 and less than n. The first simplification processing can also be referred to as quasi-vertical simplification processing.

[0093] The present example will illustrate the mechanism and implementation steps of quasi-vertical truncation. This technology performs fast and high-area-yield simplification on the input accurate circuit according to the given error constraint, greatly reduces the number of iterations required for the ALS process to converge.

[0094] Due to the uncertainty of the synthesis tool, vertical truncation faces certain challenges in automatic implementation. Therefore, the present example analyzes the relevant properties of the nodes in the vertical truncation, and formulates similar properties to identify the nodes in the actual netlist, and finally achieves quasi-vertical truncation close to vertical truncation.

[0095] In vertical cut, for the kth node, it satisfies the following properties: (1) for all input combinations, if the logic of the node is negated, the MaxED error caused by the corresponding 2 k-1 weight is always 2 k-1 (see the specific example in Figure 2-2 ).(2) after the node is deleted (equivalent to the node is replaced by a constant 0), for all input combinations, the residual error it causes is always non-positive. In particular, when a node with a weight of 2 k-1 is deleted, if the accurate value of the node under a certain input combination is 0, no residual error is introduced; if the accurate value of the node under a certain input combination is 1, a residual error of -2 k-1 is introduced. Wherein, k is a positive integer.

[0096] Considering that the actual circuit expression form (AIG / SOP / netlist) has the following situations: 1) a partial product in the traditional sense may be split and expressed in different nodes after mapping. 2) a certain signal may exist in the form of negation in the circuit. Therefore, the first simplification processing method provided in the present application approximates to identify the nodes that can be deleted by the following indicators (assuming that the circuit is truncated by k bits): (1) after the logic of the node is negated, the MaxED error introduced is less than or equal to 2 k-1 .(2) after being replaced by a constant 0 or 1, the residual error of the node under all input combinations has polarity (having polarity means that the residual error under all inputs is non-negative or non-positive).

[0097] The above scheme cannot guarantee the same final effect as the vertical cut, but the related properties of the screened nodes are close to the vertical cut, so the first simplification processing method can be called quasi-vertical cut. The possible implementation of the quasi-vertical cut method is introduced as follows. S502 can include the following S5021-S5024.

[0098] S5021, the first simplification module simulates the circuit model using multiple groups of input signals respectively;

[0099] The first simplification module can determine M groups of input signals, and each group of input signals can also be called an input combination. A single input combination includes m input signals. Wherein, M is a positive integer greater than 0 and less than or equal to m. In order to simplify the description, the circuit and the circuit model mentioned in the following have the same meaning.

[0100] As introduced in the foregoing, assuming that the circuit model in the task information includes m input signals, and the possible value of each input signal is 0 or 1, then the m input signals include 2^m input combinations, and each input combination respectively indicates a value of each input signal, for example, the input combination can be {value of I1, value of I2, …, value of Im}.

[0101] The first simplification module can determine M input combinations from 2^m input combinations. The application does not limit the determination of M, for example, it can be specified by a user or determined by the first simplification module according to the circuit.

[0102] The application does not limit the way the first simplification module determines M input combinations. For example, the first simplification module can determine the M input combinations by random sampling. The application does not limit the specific method of random sampling, for example, the random sampling can be a Monte Carlo method.

[0103] After the first simplification module determines the M input combinations, it can simulate the circuit using the M input combinations respectively and record the simulation results. For example, the first simplification module can simulate the circuit using input combination 1, simulate the circuit using input combination 2, …, and simulate the circuit using input combination M.

[0104] The simulation results can be used to indicate the output signals (or output combinations) of each circuit node under each input combination. For example, the simulation results recorded when simulating the circuit using input combination q (denoted as simulation results q) can be used to indicate the output signals of each circuit node and the output signals of each circuit node when the input signals of the circuit are input combination q. Wherein, q is a positive integer greater than 0 and less than or equal to M.

[0105] S5022, the first simplification module determines the error information of each circuit node in the circuit model according to the simulation results;

[0106] Assuming that the plurality of circuit nodes include circuit node 1, circuit node 2, …, circuit node n, the approximate calculation device can determine the error information of circuit node 1, the error information of circuit node 2, …, and the error information of circuit node n according to the simulation results respectively.

[0107] The error information of a single circuit node can include the error (referred to as the first error) generated by logically negating the output signal of the circuit node at the output signal of the circuit model under a plurality of input signals. In this way, the error information of each circuit node in the circuit model includes the first error generated by logically negating the output signal of the corresponding circuit node at the output signal of the circuit model under a plurality of input signals, or in other words, the error information of each circuit node includes the first error corresponding to the circuit node.

[0108] The application does not limit the way the first simplification module determines the first error in the error information of circuit node j. Wherein, circuit node j can be any circuit node in the circuit model.

[0109] For example, the first reduction module can obtain the output signal of the circuit model when the output signal of the circuit node j is logically negated by simulation, and then determine the first error in the error information of the circuit node j.

[0110] Alternatively, for example, the first reduction module can determine the first error in the error information of the circuit node j by obtaining the Boolean difference of the circuit node j by simulation. The possible implementation of this example is described below.

[0111] The first reduction module can obtain the Boolean difference of the circuit node j at each output signal (or output bit) under each input combination by simulation. The Boolean difference of the circuit node j at the output bit o under the input combination q can be denoted as D[q, j, o]. When D[q, j, o] is 1, it indicates that the signal value at the output bit o after logically negating the output signal of the circuit node j under the input combination q is different from the signal value of the output bit o in the output combination q. When D[q, j, o] is 0, it indicates that the signal value at the output bit o after logically negating the output signal of the circuit node j under the input combination q is the same as the signal value of the output bit o in the output combination q.

[0112] Then, the first reduction module can determine the signal value of each output bit after logically negating the circuit node j under each input combination according to the output combination under each input combination in the simulation result and the Boolean difference of the circuit node j at each output bit under each input combination. For ease of description, the circuit after logically negating the circuit node j is referred to as circuit j, and the output combination of the circuit j under the input combination q is denoted as output combination qj. Therefore, the first reduction module can determine output combination 1j, output combination 2j, …, and output combination Mj. Figure 6-2 The circuit after logically negating the output signal of the circuit node I1 in the input circuit shown in Figure 6-1 The circuit after logically negating the output signal of the circuit node I1 in the input circuit shown in Figure 6-2 The output signal of the circuit node I1 is negated by a dashed line, which can be equivalent to connecting the output port of I1 to an inverter.

[0113] After the first reduction module determines the signal value of each output bit after logically negating the circuit node j under each input combination, the output error of the circuit j under each input combination can be calculated. For example, the output error of the circuit j under the input combination q can be output combination qj-output combination q.

[0114] Then, the first simplification module can determine the error of the circuit j (i.e., the first error) under the M input combinations according to the output error of the circuit j under each input combination, such as the output error of the circuit j under the input combination 1, the output error of the circuit j under the input combination 2, …, and the output error of the circuit j under the input combination M. The first error can refer to the value of the first error indicator, and the application does not limit the type of the first error indicator. For example, the first error indicator can be MED.

[0115] S5023, the first simplification module determines a target node set according to the error information of each circuit node in the circuit model, and the target node set includes at least two circuit nodes in the circuit model corresponding to smaller first errors;

[0116] After the first simplification module determines the error information of each circuit node in the circuit model, the first simplification module can determine a target node set according to the error information of each circuit node in the circuit model, and the target node set includes at least two circuit nodes in the circuit model corresponding to smaller first errors.

[0117] In the process of determining the target node set according to the error information of each circuit node in the circuit model, the first simplification module can determine a first node set according to the error information of each circuit node in the circuit model and the first error threshold, and then determine the target node set from the first node set. The first node set includes each circuit node in the circuit model corresponding to a first error less than the first error threshold. Optionally, the first node set can also include each circuit node in the circuit model corresponding to a first error equal to the first error threshold. In this way, it is beneficial for the user to personalize the area benefit of automatic approximation calculation by setting the first error threshold. Examples of the first simplification module determining the target node set from the first node set will be described below, which will not be expanded here.

[0118] When the circuit model after deleting the target node set does not satisfy the error constraint, the first simplification module can reduce the value of the first error threshold and return to determine the first node set according to the error information of each circuit node in the circuit model and the first error threshold. In this way, when the simplified circuit model does not satisfy the error constraint due to the initial value of the first error threshold being too large, it is beneficial to remove the circuit node with a larger first error from the selected multiple circuit nodes by automatically reducing the value of the first error threshold, thereby facilitating to obtain a simplified circuit satisfying the error constraint.

[0119] S5024, when the circuit model after deleting the target node set satisfies the error constraint, the first simplification module can delete the target node set from the circuit model;

[0120] When the circuit model after deleting the target node set satisfies the error constraint, the first simplification module can delete the target node set from the circuit model to obtain a circuit with fewer circuit nodes.

[0121] Optionally, the first error threshold satisfies 2 k-1 , where k is a positive integer.

[0122] The specific number of truncated bits (i.e., the value of k) can be given by the user, and if not given, the upper limit of the error is approximated by fast direct truncation to obtain a suitable number of truncated bits. Assuming that the quasi-vertical truncated error exceeds after truncating k bits, the number of truncated bits is reduced by one, and the upper limit of MaxED corresponding to the deleted node becomes 2 1 (2 k-1 → 2 k-2 ). Since the first error (e.g., MaxED) of each node can be saved by the first calculation, the calculation overhead of this step is very low. After iteration according to the above method, a quasi-vertical truncated circuit that does not exceed the error upper limit can be quickly obtained.

[0123] The circuit model after deleting the target node set satisfies the error constraint can include that the target error of the output signal of the circuit model after deleting the target node set satisfies the target condition after compensation. Alternatively, the circuit model after deleting the target node set satisfies the error constraint can include that the target error of the output signal of the circuit model after deleting the target node set is less than or equal to the target error threshold.

[0124] When the error constraint also includes conditions that other parameters satisfy, the circuit model after deleting the target node set satisfies the error constraint can also include that the value of the other parameter of the circuit model after deleting the target node set satisfies the corresponding condition after circuit compensation, or can also include that the value of the other parameter of the circuit model after deleting the target node set satisfies the corresponding condition.

[0125] As introduced in the foregoing, the other parameter can include one or more parameters related to the quality of the circuit, such as one or more of the circuit area, circuit delay, and circuit power consumption.

[0126] The first simplification module can generally delete the circuit node by using various replacement schemes. For example, the circuit node 1 can be replaced by the circuit node 2 to delete the circuit node 1, or the circuit node 1 can be replaced by a constant (e.g., 0 or 1) to delete the circuit node 1.

[0127] The first simplification module can determine the target node set according to the error information of each circuit node in the circuit model, and can also determine the replacement scheme corresponding to each circuit node in the target node set according to the error information of each circuit node in the circuit model. For example, the first simplification module can determine the replacement scheme corresponding to circuit node 1, the replacement scheme corresponding to circuit node 2, …, and the replacement scheme corresponding to circuit node n, respectively.

[0128] Correspondingly, in the process of deleting the target node set from the circuit model, the first simplification module can delete each circuit node in the target node set in the circuit model according to the corresponding replacement scheme. For example, the first simplification module deletes circuit node 1 according to the replacement scheme corresponding to circuit node 1, deletes circuit node 2 according to the replacement scheme corresponding to circuit node 2, …, and deletes circuit node n according to the replacement scheme corresponding to circuit node n.

[0129] The replacement scheme corresponding to the circuit node is used to indicate that the circuit node is replaced by a constant (for example, 0 or 1). In this way, it is beneficial for the first simplification module to determine the replacement scheme corresponding to each circuit node in the target node set within a smaller replacement scheme range, thereby improving the simplification efficiency.

[0130] For any circuit node in the target node set, the residual error generated by deleting the circuit node according to the corresponding replacement scheme under multiple groups of input signals is greater than or equal to 0, or less than or equal to 0. For ease of description, the residual error generated by deleting the circuit node according to the corresponding replacement scheme under the circuit model is referred to as the residual error corresponding to the circuit node. When the residual error of the circuit node under a certain replacement scheme under multiple groups of input signals is greater than or equal to 0, or less than or equal to 0, it is considered that the circuit node has polarity under the replacement scheme. Moreover, for ease of description, when the residual error of the circuit node under multiple groups of input signals is greater than or equal to 0, it is considered that the polarity of the circuit node under the replacement scheme is positive, and when the residual error of the circuit node under multiple groups of input signals is less than or equal to 0, it is considered that the polarity of the circuit node under the replacement scheme is negative. Therefore, optionally, each circuit node in the target node set has polarity under the corresponding replacement scheme. The polarities of different circuit nodes in the target node set can be the same or different.

[0131] Specifically, for each replacement scheme of each circuit node in the first node set, the first simplification module can determine the residual error generated by the circuit node under each input combination according to the simulation result. For example, for the scheme of replacing circuit node j with constant 0, the first simplification module can determine the residual error generated by circuit node j under input combination 1, the residual error generated by circuit node j under input combination 2, …, and the residual error generated by circuit node j under input combination M according to the simulation result, and then determine the polarity of circuit node j under the replacement scheme of replacing circuit node j with constant 0. For example, the first simplification module can set a sign flag (1 or -1) which is defined by the sign of the first non-zero residual error read by the first simplification module. For example, when the first non-zero residual error is greater than 0, the sign flag is -1, and when the first non-zero residual error is less than 0, the sign flag is 1. When the product of the residual error read subsequently by the first simplification module and the sign flag is negative, the first simplification module can determine that circuit node j does not have polarity under the replacement scheme of replacing circuit node j with constant 0, and is excluded, i.e., does not belong to the target node set.

[0132] For circuit node j, if circuit node j has polarity under the replacement scheme of replacing circuit node j with constant 1 and under the replacement scheme of replacing circuit node j with constant 0, the first simplification module can determine one replacement scheme corresponding to circuit node j from the plurality of replacement schemes. The present application does not limit the specific method of selecting the replacement scheme. For example, the first simplification module can determine the error of circuit node j deleting the error generated by the output signal of the circuit according to the plurality of replacement schemes respectively, and select the replacement scheme with the minimum error as the replacement scheme corresponding to circuit node j. The present application does not limit the type of error index of the error, and hereinafter the error index of the error can be the target error index.

[0133] As introduced in the foregoing, the first simplification module can first determine the first node set according to the first error threshold, and then determine the target node set from the first node set. Alternatively, the first simplification module can select the circuit nodes with polarity from the first node set as the circuit nodes in the target node set, or in other words, the circuit nodes in the target node set need to have polarity in addition to satisfying the condition of not exceeding the first error threshold.

[0134] For example, Figure 6-3 An example of determining the target node set and the replacement scheme corresponding to each node from the three circuit nodes E, F, and G is shown, assuming that the error index corresponding to the error constraint is MSE. As shown in Figure 6-3 , the target node set includes circuit node E and circuit node F, and the replacement scheme corresponding to circuit node E is to replace with constant 1, and the replacement scheme corresponding to circuit node F is to replace with constant 0.

[0135] As introduced above, the number of circuit nodes in the target node set can be N, the number of circuit nodes in the circuit after deleting each circuit node in the target node set can be N0, and N+N0=n.

[0136] After S502, the circuit deletes N circuit nodes, and the circuit after deleting the N circuit nodes satisfies the error constraint. It can be seen that by extracting the statistical features of the circuit nodes to represent the information of the circuit nodes in the circuit structure, the technical limitation of the high-area-yield circuit approximation method in the automatic design is overcome. In the method, multiple circuit nodes of the circuit are deleted at the same time, and the circuit is simplified quickly while the quality of the circuit is ensured.

[0137] In the examples of the present application, the purpose of deleting a circuit node is achieved by replacing the circuit node with a certain constant (or constant). After the circuit node is replaced, it can no longer be deleted. Alternatively, in some examples, the deletion of the circuit node can also be achieved by other means, for example, by replacing circuit node B with an existing circuit node A in the circuit, the purpose of deleting circuit node B can also be achieved. However, by reducing the search space to only consider replacing with a constant (such as 0 or 1), it is beneficial to significantly speed up and the final circuit quality is also quite good.

[0138] In order to further simplify the circuit by fully utilizing the difference (referred to as error margin) between the threshold value indicated by the target error of the initialized simple circuit and the error constraint, as shown in Figure 4 As shown, the approximation computing device can further include a second simplification module for performing a second simplification process. The second simplification process can include one or more rounds of iterative simplification processes, such as the ALS process. In each round of iteration, the second simplification module generates a plurality of LACs for the current circuit, and then selects the optimal LAC according to the evaluation scores of the LACs to apply to the circuit to obtain a more simplified circuit.

[0139] That is, after the input module obtains the description text of the circuit and the error constraint, the first simplification module performs the first simplification process on the circuit, and the second simplification module continues to perform the second simplification process on the circuit after the first simplification process, which is beneficial to further improve the area yield of the circuit simplification.

[0140] In order to increase the number of iterations to improve the degree of simplification, after the approximation computing device deletes the target node set from the circuit model, the approximation computing device can also perform a local approximation change LAC on the circuit model based on the compensation parameters of the circuit model.

[0141] This application does not limit the calculation method of the circuit compensation parameters. Generally, after the circuit is updated, its compensation parameters also change accordingly. Therefore, in different iterations, because the circuit is updated due to LAC (Local Aspect-Oriented Computation), the compensation parameters of the circuit used by the second simplification module are generally different. The second simplification module can record the compensation parameters of the circuit model and update the compensation parameters of the circuit model after each update.

[0142] Optionally, after each LAC (Local Averaging) of the circuit model, the second simplification module can perform circuit compensation according to the compensation parameters of the updated circuit model (e.g., ...). Figure 6-4 The flowchart shown is based on the introduction of a compensation circuit. Compensating the circuit according to the compensation parameters of the updated circuit model means determining the compensation circuit (i.e., an additional hardware module) based on the circuit information, and then updating the circuit using the compensation circuit. Figure 6-4 The illustrated process can be understood as moving the circuit compensation method into the iterative ALS process. This means that each iteration may require additional hardware overhead. Since any additional compensation needs to be passed to the highest bit, it can be approximated that the compensation overhead is not absolutely related to the size of the compensation number; each additional compensation requires a certain amount of additional overhead.

[0143] To reduce hardware overhead, this application proposes that after each LAC (Local Aspect-Oriented Computation) operation on the circuit model, the second simplification module can only update the recorded compensation parameters and use them to estimate the target error of the LAC scheme, without performing circuit compensation on the circuit model until a given error constraint is reached, at which point circuit compensation is performed according to the current circuit model's compensation parameters (e.g., ...). Figure 6-5 The flowchart shown introduces compensation parameters. By introducing dynamic compensation coefficients, not only is the accuracy of the estimated evaluation score improved, but the additional overhead of the compensation circuit is also minimized.

[0144] like Figure 6-5 As shown, in the iterative process, compensation information tied to the circuit is added and used as input to the error evaluation module along with the circuit model. For each iteration, only the compensation information corresponding to the current circuit is updated, rather than modifying the actual approximate circuit. Furthermore, a new error evaluation strategy is proposed: for the circuit C in the i-th iteration... i and the corresponding compensation P i When evaluating errors, the corresponding compensation coefficient P should also be considered. i After the ALS process is completed (when the circuit error reaches the upper limit of the error constraint), a compensation circuit is introduced again.

[0145] Compared to Figure 6-4 The introduced compensation circuit is shown. Figure 6-5The dynamic compensation coefficients shown have the following advantages: If there are X compensation updates in the iterative process, then when introducing compensation circuits, the circuit needs to successively add at most X compensation circuits; while when introducing dynamic compensation coefficients, at most only 1 compensation circuit needs to be added, which simplifies the iterative process and yields a higher quality output circuit. Here, X is a positive integer.

[0146] In the second simplification module, during the Local Approximation Change (LAC) of the circuit model based on the compensation parameters of the circuit model, multiple LAC schemes for local approximation changes of the circuit model can be determined. The evaluation scores of each LAC scheme are estimated using the compensation parameters of the circuit model. Then, based on the evaluation scores of the multiple LAC schemes, the circuit model undergoes local approximation changes (LAC), and the process returns to determine the multiple LAC schemes for the circuit model. This continues until all multiple LAC schemes fail to meet the error constraints. Finally, circuit compensation is performed on the circuit model according to the compensation parameters of the circuit model. The following examples, using S503 to S508, illustrate this method of performing LAC on the circuit based on the compensation parameters of the circuit.

[0147] S503, the second simplification module calculates and records the compensation parameters of the target simplified circuit;

[0148] like Figure 5 As shown, after S502 and after each iteration of circuit simplification and update, S503 can be executed. For ease of description of the iterative process, the current circuit is referred to as the target simplified circuit. In this application, the circuit obtained in the i-th iteration is denoted as simplified circuit i, and the number of nodes in simplified circuit i is denoted as Ni. Here, i is any positive integer greater than or equal to 0. Simplified circuit 0 refers to the circuit obtained after S502. As mentioned earlier, the number of circuit nodes in simplified circuit 0 is N0. Therefore, Ni is a positive integer less than or equal to N0. Optionally, a single LAC is used to delete a single circuit node; in this case, Ni = N0 + i.

[0149] After obtaining the simplified circuit i, the second simplification module can use the simplified circuit i as the object of iterative simplification (referred to as the target simplified circuit), and calculate and record the compensation parameters of the target simplified circuit. For ease of description, this application refers to the compensation parameters of the simplified circuit i as compensation parameters i (denoted as Ai).

[0150] This application does not limit the method by which the second simplification module calculates the compensation parameters. For example, the second simplification module can calculate the error of the simplified circuit i and determine Ai based on the error. This application does not limit the type of error index; for example, the error index can be ME.

[0151] The second simplification module can obtain the ME (denoted as MEi) of the simplified circuit i through simulation. Optionally, Ai = -MEi. This can then guide the addition of appropriate compensation parameters i to the simplified circuit i. For example, if k bits are truncated as described above, The actual compensation (denoted as B) is rounded to the nearest value according to the output requirement.

[0152] If the circuit output requirement is truncated by h bits, the last h bits of Ai can be set to 0. As shown, for the circuit whose output is truncated by 4 bits and the circuit after the output is truncated by 4 bits, i.e., k = 4 and h = 4, the second simplification module can first test the MEi corresponding to the simplification circuit i, and then obtain the theoretical compensation MEi, and then obtain the compensation (i.e., B) whose last 4 bits are 0 according to the number of truncated bits. Figure 7

[0153] S504, the second simplification module generates a plurality of LACs for the target simplification circuit;

[0154] Taking the simplification circuit i as the target simplification circuit, the second simplification module can generate a plurality of LACs i for the simplification circuit i. As introduced in the foregoing, the simplification circuit i includes Ni circuit nodes. For ease of description, the LAC obtained by deleting the circuit node j in the simplification circuit i is denoted as LACij. Wherein, j is a positive integer less than or equal to Ni.

[0155] In the Ni LACs i generated, a single LAC i corresponds to a single node in the simplification circuit i, and a single node can correspond to a single LAC i. For example, LACij corresponds to the jth node (denoted as node j), and LACij can refer to the simplification scheme for setting node j in the simplification circuit i to 0 or 1. At this time, the second simplification module can generate Ni LACs i.

[0156] Alternatively, in the plurality of LACs i generated, a single LAC i corresponds to a single node in the simplification circuit i, but a single node can correspond to two LACs i. For example, LACij_0 and LACij_1 both correspond to node j, wherein LACij_0 refers to the simplification scheme for setting node j in the simplification circuit i to 0 (denoted as simplification scheme ij_0), and LACij_1 refers to the simplification scheme for setting node j in the simplification circuit i to 1 (denoted as simplification scheme ij_1). At this time, the second simplification module can generate 2Ni LACs i.

[0157] Alternatively, in a part of the plurality of LACs i generated, a single LAC i corresponds to a single node in the simplification circuit i and a single node can correspond to a single LAC i, and in another part of the plurality of LACs i, a single LAC i corresponds to a single node in the simplification circuit i and a single node can correspond to two LACs i. At this time, the number of LACs i generated by the second simplification module is greater than Ni and less than 2Ni.

[0158] ​S505, the second simplification module estimates the evaluation scores of the plurality of LACs using the recorded compensation parameters respectively, and determines a target LAC with the optimal evaluation score from the plurality of LACs;

[0159] Continuing to take the target simplification circuit as the simplification circuit i as an example, the evaluation scores of the plurality of LACs i can be estimated using the compensation parameters of the simplification circuit i recorded in S503, and a target LAC i with the minimum evaluation score can be determined from the Ni LACs i. The evaluation score of the LAC scheme is positively correlated with the target error of the output combination generated by the compensation output signal of the circuit model.

[0160] The target error of the LAC i estimated using the compensation parameters can refer to the target error of the output combination obtained by applying the LAC i and the compensation parameter i (i.e., Ai) to the simplification circuit i relative to the output combination of the circuit. The target error is the value of the error indicator indicated by the error constraint.

[0161] The specific method of estimating the target error of one circuit relative to other circuits can refer to the related technical solutions disclosed in the prior art or in the future, and the application does not limit the specific way of estimating the target error of one circuit relative to other circuits.

[0162] S506, determining whether the target LAC satisfies the error constraint, if yes, performing S507, if not, performing S508;

[0163] Continuing to take the target simplification circuit as the simplification circuit i as an example, when the target LAC i satisfies the error constraint, S507 can be performed, and when the target LAC i does not satisfy the error constraint, S508 can be performed.

[0164] S507, the second simplification module updates the target simplification circuit according to the target LAC, and returns to S503;

[0165] Continuing to take the target simplification circuit as the simplification circuit i as an example, when the target LAC i satisfies the error constraint, the simplification circuit i can be simplified according to the target LAC i to obtain a simplification circuit i+1, and correspondingly, the target simplification circuit is updated from the simplification circuit i to the simplification circuit i+1. Then, S503 can be returned to execute S503 again with the target simplification circuit as the simplification circuit i+1.

[0166] Figure 5 S503 and S504 are executed in series. That is, after S503 is executed again with the current simplification circuit as the simplification circuit i+1, S504-S506 are executed in series again.

[0167] Alternatively, S503 and S504 can be executed in parallel, for example, after S502 or after S507, and before S505, S503 and S504 are executed in parallel. Correspondingly, after S507, S503 and S504 can be returned respectively, that is, the current simplified circuit is taken as the simplified circuit i+1, and S503 and S504 are executed in parallel. After S503 and S504 are completed, S505 and S506 are executed in series again.

[0168] By replacing i in S503-S506 with i+1, the content of the corresponding steps executed by taking the current simplified circuit as the simplified circuit i+1 can be determined, which will not be described here.

[0169] S508, the second simplification module performs circuit compensation on the target simplified circuit according to the compensation parameter of the target simplified circuit.

[0170] Taking the target simplified circuit as the simplified circuit i as an example, when the target LACi does not meet the error constraint, the simplified circuit i can be compensated according to the compensation parameter i, for example, a compensation circuit is added in the simplified circuit i to obtain the compensated simplified circuit i. Moreover, the output signal of the compensated simplified circuit i is the result of compensating the output signal of the simplified circuit i according to the compensation parameter i, or the output signal of the compensated simplified circuit i is closer to the result of compensating the output signal of the simplified circuit i according to the compensation parameter i than the output signal of the simplified circuit i before compensation.

[0171] S509, the output module outputs the compensated target simplified circuit.

[0172] As shown in Figure 4 , the approximate calculation device can further include an output module, after the second simplification module performs circuit compensation on the target simplified circuit according to the compensation parameter of the target simplified circuit, the output module can output the compensated circuit.

[0173] S503-S508 provide an ALS flow containing a compensation parameter, supporting processing of any arithmetic circuit at any time. Dynamic error optimization is performed on the circuit in the iterative flow, while only introducing minimal additional area overhead. In some examples, Figure 5 The flow shown in can not include S502, that is, after S501, S502 is not executed, but S503-S509 are executed.

[0174] Figure 5 The flow shown in is an efficient and high-quality approximate simplification method for a general approximate logic synthesis framework. Compared with a general ALS flow (such as the method shown in Figure 1-1 ), the method shown in Figure 5The method shown adds a pre-simplification process for the input circuit to improve operating efficiency and introduces an iterative process including compensation parameters to improve circuit quality. In some examples, to further improve simplification efficiency, after executing S502, S503 to S508 can be omitted, and the output module can output the circuit after the first simplification process. Alternatively, after S502, although S503 to S508 are not executed, other simplification processes can be performed to further simplify the circuit after the first simplification process, and / or circuit compensation can be performed on the circuit after the first simplification process.

[0175] The above example uses a single LAC to delete a single circuit node. In some examples, a single LAC can also be used to delete multiple circuit nodes. In other words, a single LAC or multiple LACs can be introduced during a single iteration.

[0176] As described above, this application provides a rapid circuit simplification method based on quasi-vertical truncation, overcoming the dependence of existing approximate circuit design methods on circuit structure and achieving fast and low-hardware-overhead automated approximate design for any arithmetic circuit. Furthermore, this application proposes an error optimization method based on dynamic compensation parameters. In each iteration, the compensation parameters used to estimate the evaluation parameters are dynamically updated, further optimizing the current error through error compensation, while introducing minimal additional hardware overhead and improving the overall quality of the output circuit.

[0177] This application combines the aforementioned improvements with a general approximation circuit iterative process into a hybrid approximation logic synthesis method (denoted as MIX), which can efficiently obtain high-quality approximation circuits. This application solves the technical problems arising from direct truncation and vertical truncation methods by automating the processing of arbitrary circuits. Simultaneously, this application uses compensation parameters for LAC error evaluation, which helps improve the accuracy of error evaluation and addresses the potential impact on circuit quality caused by inaccurate error estimation in automatic pruning methods. Furthermore, this method improves the efficiency of the circuit simplification process, solving the problem of excessive processing time for large-scale circuits in iterative simplification methods, and providing a feasible method for the approximate design of large-scale circuits. The beneficial effects obtained are demonstrated below through actual circuit testing.

[0178] The experimental circuit is Figure 8 The circuit shown includes the circuit name, number of inputs and outputs, and the exact circuit area. All experiments were conducted within the same ALS iterative framework, but the specific implementation schemes differed slightly. The schemes compared are the iterative simplification method described earlier (denoted as SASIMI) and its accelerated version (denoted as Const). Const refers to the fact that the replacement scheme used by LAC is limited to replacing nodes with constants.

[0179] existFigure 9 And 10 Among them, the column marked with identification number 1 represents the Mix scheme, the column marked with identification number 2 represents the Const scheme, and the column marked with identification number 3 represents the SASIMI scheme. The results show that the scheme proposed in the application can achieve the optimal circuit quality on all circuits.

[0180] In addition to slightly improving the quality of the finally obtained approximate circuit, the outstanding advantage of the scheme is to significantly improve the running speed (i.e., shorten the running time) of the approximate circuit, especially in large-scale circuits. In the above circuits, the circuit with an area of more than 1000 square microns is selected for testing. As shown in Figure 11 , the column marked with identification number 1 represents the Mix scheme, the column marked with identification number 2 represents the Const scheme, and the column marked with identification number 3 represents the SASIMI scheme. In the four circuits shown in Figure 11 , compared with the SASIMI scheme, the scheme can bring hundreds of times of efficiency improvement for some circuits. Compared with the Const scheme, it can at least bring 1.9 times improvement, and the highest can bring 15.5 times improvement.

[0181] It can be seen that the application designs an efficient and high-quality approximation simplification method for a general approximate logic synthesis framework. For any input circuit and error constraint, multiple nodes can be deleted at the same time through accurate error estimation, and the circuit can be greatly pre-simplified without affecting the quality of the final circuit, which significantly speeds up the convergence speed of the ALS process. In addition, while considering compensation to optimize the error, the application also minimizes the additional hardware overhead.

[0182] The approximate calculation method provided by the application only deletes nodes and connections in the graph, without adding nodes and connections. Therefore, the approximate circuit generated according to the approximate calculation method of the application will be a sub-circuit of the accurate circuit, and therefore, the method of solving the satisfiability problem (SAT) can be used to find the logically equivalent part (as shown in Figure 12 ) between the approximate circuit and the accurate circuit, and whether there is a constant compensation sub-circuit. Among them, the connection refers to the connection between different nodes mentioned above.

[0183] For a given approximate circuit, the nodes of the final approximate circuit can be marked in the original accurate circuit using the method described above. Furthermore, the error can be evaluated using simulation, and then the theoretical truncation number and the error threshold for node deletion can be obtained using the approximate calculation method provided in this application. Using the method provided in this application, the marked nodes are tested in the accurate circuit. The errors of all marked nodes exceed the derived error threshold, and it is detected that only one constant-compensated submodule exists at the output.

[0184] The method provided in this application can be used not only for automatic approximation calculations but also for functional verification of manually designed approximation circuits. Since this architecture is based on Monte Carlo sampling simulations and supports custom input distributions and custom error metrics, error verification for manually programmed, high-level approximation calculation modules can be performed within this framework for corresponding scenarios.

[0185] Furthermore, the proposed method architecture can also be used for accurate circuit simplification in specific application environments. For example, for an accurate multiplier, all logic gates are indispensable because the function must be correct under all possible inputs. However, in specific application scenarios, the probability of some input combinations may be zero, in which case not all logic gates are necessary. This framework can find and remove nodes that do not affect the output under a given input distribution, further optimizing the accurate circuit in specific scenarios.

[0186] The above is a detailed description of the method provided in the embodiments of this application. The approximate computing device provided in the embodiments of this application will be described below.

[0187] This application is not limited to Figure 4 The implementation methods of the modules shown are not limited to the same implementation method for different modules. For example, a module can be a component of a computer device (such as a processor, chip, or chip system), or it can be a logic module or software that implements all or part of a computer device, or it can be a computer device itself.

[0188] Taking the function of the approximate computing device as an example, Figure 13 The diagram illustrates the structure of a computer device. For example... Figure 13 As shown, an example of a computer device may include one or more central processing units 1301 and memory 1302. Optionally, the computer device may also include at least one of an input / output interface 1303, a wired or wireless network interface 1304, and a power supply 1305.

[0189] The memory 1302 can be temporary or persistent storage. Furthermore, the central processing unit 1301 can be configured to communicate with the memory 1302 and execute a series of instructions stored in the memory 1302.

[0190] All or part of the functions of the approximate computing device mentioned above can be implemented by the central processing unit 1301 by executing instructions in the memory 1302. Alternatively, the approximate computing device is implemented by the computer device shown in the figure. Figure 13 The computer device shown in the figure.

[0191] The embodiments of the present application also relate to a computer storage medium, which stores a program for performing approximate computing, and when the program runs on a computer, the computer is caused to execute the steps performed by the approximate computing device introduced above.

[0192] The embodiments of the present application also relate to a computer program product, which stores instructions, and when the instructions are executed by a computer, the computer is caused to execute the steps performed by the approximate computing device introduced above.

[0193] The terms "first", "second", etc. in the specification and claims of the present application and the above-described figures are used to distinguish similar objects, and do not necessarily indicate a specific order or sequence. It should be understood that the terms used in this way can be interchanged, which is only a distinguishing way adopted in the description of the embodiments of the present application for the objects with the same attribute in the description. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, so that the processes, methods, systems, products or devices containing a series of units do not have to be limited to those units, but can include other units not clearly listed or inherent to these processes, methods, products or devices.

[0194] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described systems, devices and units can refer to the corresponding processes in the foregoing method embodiments, which will not be described here.

[0195] In several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0196] The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the embodiment scheme.

[0197] In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0198] The integrated unit, if realized in the form of a software functional unit and sold or used as an independent product, can be stored in a computer readable storage medium. Based on such understanding, the technical scheme of the present application essentially or the part that contributes to the prior art or the whole or part of the technical scheme can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various program code storage media.

Claims

1. A method for approximate calculation, characterized in that, include: Obtain task information for indicating the simplification of a circuit, the task information including error constraints and a circuit model for describing the circuit, the error constraints indicating the conditions satisfied by the simplified circuit, and the circuit model including multiple circuit nodes representing multiple circuit elements in the circuit; The circuit model is simulated using multiple sets of input signals, and the error information of each circuit node in the circuit model is determined based on the simulation results. The error information of the circuit node includes the first error generated by logically inverting the output signal of the circuit node under the multiple sets of input signals in the output signal of the circuit model. The target node set is determined based on the error information of each circuit node in the circuit model, and the target node set includes at least two circuit nodes in the circuit model that correspond to the smaller first error; When the circuit model after deleting the target node set satisfies the error constraint, the target node set is deleted from the circuit model.

2. The method according to claim 1, characterized in that, The step of determining the target node set based on the error information of each circuit node in the circuit model includes: A first node set is determined based on the error information of each circuit node in the circuit model and a first error threshold. The first node set includes each circuit node in the circuit model whose first error is less than the first error threshold. The target node set is determined from the first node set.

3. The method according to claim 2, characterized in that, The method further includes: When the circuit model after deleting the target node set does not meet the error constraint, the value of the first error threshold is reduced and the process returns to determine the first node set based on the error information of each circuit node in the circuit model and the first error threshold.

4. The method according to claim 2 or 3, characterized in that, The value of the first error threshold satisfies 2 k-1 , where k is a positive integer.

5. The method according to any one of claims 1-4, characterized in that, The method further includes: Based on the error information of each circuit node in the circuit model, determine the replacement scheme corresponding to each circuit node in the target node set; Deleting the target node set from the circuit model includes: Each circuit node in the target node set of the circuit model is deleted according to the corresponding replacement scheme.

6. The method according to claim 5, characterized in that, The replacement scheme corresponding to the circuit node is used to indicate that the circuit node should be replaced with a constant.

7. The method according to claim 5 or 6, characterized in that, For any circuit node in the target node set, the residuals generated by deleting it from the output signal of the circuit model under the corresponding replacement scheme under the multiple sets of input signals are all greater than or equal to 0, or are all less than or equal to 0.

8. The method according to any one of claims 1-7, characterized in that, The error constraint indicates that the target error of the simplified circuit's output signal satisfies the target condition.

9. The method according to claim 8, characterized in that, The circuit model after deleting the target node set satisfies the error constraint, which means that the target error after compensating the output signal of the circuit model after deleting the target node set satisfies the target condition.

10. The method according to claim 8 or 9, characterized in that, After removing the target node set from the circuit model, the method further includes: The circuit model is subjected to a local approximation transformation (LAC) based on the compensation parameters of the circuit model.

11. The method according to claim 10, characterized in that, The local approximation transformation (LAC) of the circuit model based on the compensation parameters of the circuit model includes: Determine multiple local approximation variations (LAC) schemes for the circuit model; The evaluation scores of the plurality of LAC schemes are estimated using the compensation parameters of the circuit model, and the evaluation scores are related to the target error generated by the output signal of the corresponding LAC scheme after compensation by the circuit model. Based on the evaluation scores of the multiple LAC schemes, the circuit model is subjected to a local approximation change LAC, and the execution of the multiple LAC schemes that determine the circuit model is repeated until none of the multiple LAC schemes satisfy the error constraint. Then, the circuit model is compensated according to the compensation parameters of the circuit model.

12. An approximate calculation device, characterized in that, include: An input module is used to acquire task information for indicating the simplification of a circuit. The task information includes error constraints and a circuit model for describing the circuit. The error constraints are used to indicate the conditions satisfied by the simplified circuit. The circuit model includes multiple circuit nodes representing multiple circuit elements in the circuit. The first simplification module is used to simulate the circuit model using multiple sets of input signals, and determine the error information of each circuit node in the circuit model according to the simulation results. The error information of the circuit node includes the first error generated by logically inverting the output signal of the circuit node under the multiple sets of input signals in the output signal of the circuit model. The first simplification module is further configured to determine a target node set based on the error information of each circuit node in the circuit model, wherein the target node set includes at least two circuit nodes in the circuit model that correspond to the smaller first error; The first simplification module is further configured to delete the target node set from the circuit model when the circuit model after deleting the target node set satisfies the error constraint.

13. A computer storage medium, characterized in that, The computer storage medium stores one or more instructions that, when executed by one or more computers, cause the one or more computers to perform the method described in any one of claims 1 to 11.

14. A computer program product, characterized in that, The computer program product stores instructions that, when executed by a computer, cause the computer to perform the method described in any one of claims 1 to 11.

15. A computer device, characterized in that, The computer device includes a memory and a processor, the memory storing code, and the processor being configured to execute the code, wherein when the code is executed, the computer device performs the steps of the method as described in any one of claims 1 to 11.

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