Port-driven low-latency routing method and system based on PCIe network architecture

Abstract

This invention discloses a port-driven low-latency routing method and system based on a PCIe network architecture. The method includes pre-assigning a unique port code to each port, constructing a global port mapping table, which includes the port code and port information corresponding to each port, including the address information of the device connected to the port; when a source device sends a data packet to a target device, the source device determines the source port code and the target port code according to the global port mapping table; based on the topology of the PCIe network architecture, the target path from the source port to the target port is determined and written into a custom prefix of the data packet; the switch parses the target path in the custom prefix, determines the current target transmission port according to the target path, and transmits the data packet to the current target transmission port. This invention can significantly reduce switching latency and forwarding complexity, and improve communication efficiency and link controllability in high-density interconnection scenarios.

Description

Technical Field

[0001] This invention relates to the fields of communication network congestion control and compilation principles, and in particular to a port-driven low-latency routing method and system based on PCIe network architecture. Background Technology

[0002] In the current field of high-performance computing and data center interconnects, PCI Express (PCIe) technology has become the mainstream high-bandwidth, low-latency interconnect standard. With the rapid development of AI training, cloud computing, large-scale distributed storage and other services, the traditional tree-like or hierarchical PCIe architecture is gradually becoming unable to meet the system's requirements for horizontal scalability, flexibility and end-to-end performance determinism.

[0003] Existing PCIe interconnect architectures generally employ routing methods based on BDF (Bus-Device-Function) or GID (Global ID) addressing. In this approach, packet forwarding between switching chips relies on address lookup tables (such as D-LUTs or GID-Tables) maintained internally by each device level. The next-hop port is determined by parsing and matching the destination address in the TLP header. Especially in mesh-based PCIe architectures (PCIe Fabric), the BDF or GID addressing and routing mechanisms require dynamic forwarding based on the address lookup tables of each switching chip. This not only increases the complexity of routing table maintenance and synchronization but also leads to opaque paths and imprecise control of packets during multi-hop forwarding, making it difficult to achieve fine-grained traffic scheduling and port-level QoS guarantees.

[0004] The PCIe protocol also introduces Virtual Channel (VC) and Traffic Class (TC) mechanisms to achieve basic Quality of Service (QoS) control at the link layer and within the channel. Some high-end systems combine multi-path routing and dynamic load balancing technologies to attempt to improve bandwidth utilization and traffic isolation capabilities to some extent. However, these mechanisms are limited to priority scheduling within the channel and cannot meet the application requirements of end-to-end, path-level QoS control and high-density, multi-host, and multi-port collaborative scenarios in the Internet. Moreover, these traditional solutions essentially rely on automatically generated and synchronized large-scale lookup tables, which cannot achieve explicit path-level control. The end-to-end routing process lacks transparency and programmability, and QoS assurance capabilities are limited to the physical link and channel granularity. For high-density interconnection environments with large-scale, dynamic, and multi-host collaborative network architectures, it remains difficult to overcome the technical bottlenecks such as complex lookup tables, uncontrollable paths, and limited QoS isolation granularity.

[0005] Therefore, how to implement a port routing mechanism that is compatible with the PCIe protocol and can efficiently manage port addressing, path selection and QoS scheduling in a network structure is a technical challenge that the industry and academia urgently need to overcome.

[0006] The above background information is provided only to assist in understanding the inventive concept and technical solution of this invention. It does not necessarily belong to the prior art of this application, nor does it necessarily provide technical teaching. In the absence of clear evidence that the above information was disclosed before the filing date of this application, the above background information should not be used to evaluate the novelty and inventiveness of this application. Summary of the Invention

[0007] The purpose of this invention is to provide a port-driven low-latency routing method and system based on PCIe network architecture, which can significantly reduce switching latency and forwarding complexity, and improve communication efficiency and link controllability in high-density interconnection scenarios.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0009] A port-driven low-latency routing method based on a PCIe network architecture includes the following steps:

[0010] A unique port code is pre-assigned to each port of each switch in the PCIe network architecture, and a global port mapping table is constructed, which includes the port code corresponding to each port;

[0011] When a source device sends a data packet to a target device, the source device determines the source port code corresponding to the source port and the target port code corresponding to the target port according to the global port mapping table. The source port is the port to which the source device is connected, and the target port is the port to which the target device is connected.

[0012] The topology based on the PCIe network architecture determines the target path from the source port to the destination port. The target path includes at least the source port code and the destination port code. The source device writes the target path into the custom prefix of the data packet. The custom prefix is ​​a field that can be defined by the vendor in the extended header of the TLP data packet. It is also called the Vendor Defined Prefix (VDP).

[0013] During the transmission of data packets, the switch parses the target path in the custom prefix and determines the current target transmission port based on the target path. The switch then transmits the data packet to the current target transmission port until the data packet is transmitted to the target device.

[0014] Furthermore, following any one or a combination of the aforementioned technical solutions, the method further includes the following steps:

[0015] Based on the topology of the PCIe network architecture and the port mapping table, a path table is pre-built. The path table includes the path from the source port to the target port, and the path includes the port code corresponding to each port it passes through.

[0016] The source device determines the target path from the source port to the target port based on the path table.

[0017] Furthermore, following any one or a combination of the aforementioned technical solutions, the port connected to the device to be communicated in the PCIe network architecture is determined as the terminal port. One terminal port is used as the source port, and another terminal port is used as the target port to determine multiple communication port groups. For each communication port group, the path from the source port to the target port, i.e., the transmission path, is determined. All communication port groups are traversed to construct the path table, which includes corresponding communication port groups and paths.

[0018] Furthermore, following any one or a combination of the aforementioned technical solutions, the source device determines the target path from the source port to the target port according to the path table, configures a cursor for indicating valid port codes, and transmits the data packets in the following manner:

[0019] Parse the target path in the custom prefix, determine the current target transmission port according to the effective port code indicated by the cursor, and transmit the data packet to the current target transmission port;

[0020] Upon completion of the current data packet transmission, the cursor is controlled to indicate the next port code of the valid port code along the target path direction to update the valid port code.

[0021] Furthermore, following any one or a combination of the aforementioned technical solutions, when the data packet reaches the source port, the cursor is configured to indicate the source port, and the port following the port corresponding to the valid port code on the target path is configured as the target transmission port;

[0022] or,

[0023] When the data packet arrives at the source port, the cursor is configured to indicate the next port code corresponding to the source port code on the target path, and the port corresponding to the valid port code is configured as the target transmission port.

[0024] Furthermore, following any one or a combination of the aforementioned technical solutions, the method further includes the following steps:

[0025] The source device determines the target path from the source port to the target port according to the path table, the port code includes first information, the first information being the information of the switch where the port is located, and transmits the data packet in the following manner:

[0026] The switch parses the target path in the custom prefix and determines two port codes that match the first information and the switch's own information. It then determines the port corresponding to the port code that is later in the two port codes as the current target transmission port and transmits the data packet to the current target transmission port.

[0027] Furthermore, following any one or a combination of the aforementioned technical solutions, if there are multiple target paths from the source port to the target port, the data transmission status of the multiple target paths is evaluated, and the target path with the optimal data transmission status is written into the custom prefix of the data packet.

[0028] Furthermore, following any one or a combination of the aforementioned technical solutions, if there are multiple target paths from the source port to the target port, the data transmission status of the multiple target paths is evaluated, and the priority of the multiple target paths is determined according to the rule that the better the data transmission status, the higher the priority of the target path.

[0029] The highest priority target path is written into the custom prefix of the data packet as the primary target path, and one or more other priority target paths are written into the custom prefix as alternative target paths. The primary target path is configured as the transmission path of the data packet.

[0030] Furthermore, following any of the aforementioned technical solutions or combinations thereof, when transmitting the data packet based on the primary target path, if the current data transmission status does not meet the preset data transmission requirements, then an alternative target path is activated to transmit the data packet.

[0031] Furthermore, following any one or a combination of the aforementioned technical solutions, the method further includes the following steps:

[0032] During the transmission of the data packet, the switch parses the source port code and destination port code in the custom prefix, and determines the destination path corresponding to the source port and destination port according to the path table. The switch is one of the switches in the path of the destination path.

[0033] The switch determines two port codes that match the port codes of its own port and the port codes included in the target path, and determines the port corresponding to the later port code as the current target transmission port.

[0034] The switch transmits the data packet to the target transmission port.

[0035] Furthermore, following any one or a combination of the aforementioned technical solutions, the method further includes the following steps:

[0036] During the transmission of data packets, the switch parses the source port code and destination port code in the custom prefix. If the ports corresponding to the source port code and destination port code belong to the same switch, the data packets are transmitted directly through the cross switch matrix inside the switch.

[0037] Furthermore, based on any or a combination of the aforementioned technical solutions, the port encoding further includes second information, which is configured as the location information of the port in the switch;

[0038] During the transmission of the data packet, the switch / device transmits the data packet to the port corresponding to the port encoding according to the second information.

[0039] Furthermore, following any one or a combination of the aforementioned technical solutions, the global port mapping table includes port BDF parameters and port codes that have a one-to-one correspondence. During the transmission of the data packet, each of the switches does not look up the BDF value corresponding to the target port.

[0040] According to another aspect of the present invention, a port-driven low-latency communication system based on a PCIe network architecture is provided, including one or more switches and multiple devices to be communicated, wherein the switches include multiple ports, each port is configured with a unique port code, and one of the devices is configured to be electrically connected to one of the ports;

[0041] Each of the aforementioned devices and switches is configured with a preset global port mapping table, which includes the port code corresponding to each port;

[0042] The source device is configured to determine the source port code corresponding to the source port and the target port code corresponding to the target port according to the global port mapping table, wherein the source port is the port to which the source device is connected, the target port is the port to which the target device is connected, and the source device and the target device are two different devices among the devices;

[0043] The source device is also configured to determine a target path from the source port to the destination port and write the target path into a custom prefix of the data packet, the target path including at least the source port code and the destination port code;

[0044] The switch is configured to parse the target path in the custom prefix, determine the current target transmission port based on the target path, and transmit the data packet to the current target transmission port.

[0045] Furthermore, in accordance with any or a combination of the aforementioned technical solutions, each of the aforementioned devices and switches is also configured with a preset path table, the path table including the path from the source port to the target port, and the path including the port codes corresponding to each port it passes through;

[0046] The source device is also configured to determine a target path from the source port to the destination port according to the path table, and to write the target path into a custom prefix of the data packet;

[0047] The switch is configured to parse the target path in the custom prefix and determine the current target transmission port for data transmission based on the target path.

[0048] The beneficial effects of the technical solution provided by this invention are as follows:

[0049] a. This invention sets the target path represented by port encoding in the custom prefix of the data packet, and directly uses the explicit port encoding for forwarding during data transmission. This effectively avoids the additional delay and complexity caused by looking up the BDF routing table in the traditional method. This improvement significantly reduces the forwarding delay of data packets inside the switching chip, improves data throughput efficiency, and simplifies the chip logic structure, thereby reducing power consumption. At the same time, this scheme makes the link delay more deterministic and stable, improves the applicability of real-time applications, and facilitates dynamic path optimization at the system level. It is more suitable for the high-speed data transmission needs of emerging fields such as artificial intelligence, high-performance computing, and real-time communication.

[0050] b. This invention can determine the target path from the source port to the destination port through a global port encoding table and a path table, and write the target path into the custom prefix of the data packet. This enables the explicitness and determinism of the entire path of the data packet from the source port to the destination port. Furthermore, by using a cursor to indicate the valid port encoding, the current target transmission port corresponding to each data transmission is realized. This reduces data transmission latency and also makes the data transmission path controllable and transparent.

[0051] c. This invention determines the priority of multiple target paths based on their data transmission quality, and designates the target path with the best data transmission quality as the primary target path, while designating one or more other target paths as alternative target paths. When the data transmission quality of the primary target path does not meet the preset requirements, it can quickly and timely switch to an alternative target path, thereby improving the utilization of system resources, further reducing latency, and adapting to the dynamic numbering of the system. Attached Figure Description

[0052] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0053] Figure 1 A flowchart illustrating a first port-driven routing method provided as an exemplary embodiment of the present invention;

[0054] Figure 2 A flowchart illustrating a second port-driven routing method provided as an exemplary embodiment of the present invention;

[0055] Figure 3 A flowchart illustrating a third port-driven routing method provided as an exemplary embodiment of the present invention;

[0056] Figure 4 This is a schematic diagram of a PCIe network architecture topology provided as an exemplary embodiment of the present invention. Detailed Implementation

[0057] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0058] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, apparatus, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0059] To address the shortcomings of existing technologies, this invention proposes a port-driven low-latency routing method and system based on a PCIe network architecture, suitable for PCIe Mesh / Fabric topologies with multiple switching chips and interconnected devices. This invention effectively avoids the additional latency and complexity caused by looking up the BDF routing table in traditional methods by directly using explicit port encoding in the data packets for forwarding. This improvement significantly reduces the forwarding latency of data packets within the switching chip, improves data throughput efficiency, and simplifies the chip logic structure, thereby reducing power consumption. Simultaneously, this approach makes link latency more deterministic and stable, enhancing the applicability to real-time applications and facilitating dynamic path optimization at the system level, making it more suitable for the high-speed data transmission needs of emerging fields such as artificial intelligence, high-performance computing, and real-time communication.

[0060] In one embodiment of the present invention, a port-driven low-latency routing method based on a PCIe network architecture is provided, see [link to relevant documentation]. Figures 1 to 3 The method includes the following steps: First, a unique port code is pre-assigned to each port of each switch in the PCIe network architecture, and a global port mapping table is constructed, the global port mapping table including the port code corresponding to each port; when a source device sends a data packet to a target device, the source device determines the source port code corresponding to the source port and the target port code corresponding to the target port according to the global port mapping table, the source port being the port connected to the source device and the target port being the port connected to the target device; based on the topology of the PCIe network architecture, a target path is determined from the source port to the target port, the target path including at least the source port code and the target port code, and the source device writes the target path into a custom prefix of the data packet; during the transmission of the data packet, the switch parses the target path in the custom prefix and determines the current target transmission port according to the target path, and the switch transmits the data packet to the current target transmission port until the data packet is transmitted to the target device.

[0061] In one embodiment of the present invention, the global port mapping table is constructed as follows.

[0062] Port coding and global port mapping table configuration phase: In each PCIe switching chip, a unique port code (Port ID) is assigned to all physical output ports, and a static one-to-one mapping table between port codes and physical ports is established, namely the global port mapping table (PMT). Preferably, the global port mapping table includes port BDF (Bus-Device-Function) parameters and port codes corresponding one-to-one with each port.

[0063] The global port mapping table is generated and distributed to each node by the management unit (usually the system manager, Root Complex) during system initialization, device enumeration, or topology configuration. The global port mapping table maps port codes one-to-one with local physical port codes. All port information is collected and recorded in the global port mapping table at the management unit's end, and the global port mapping table is broadcast and synchronized to each device and switching chip through the control protocol.

[0064] Preferably, the port encoding includes first information and second information. The first information is information about the switch where the port is located, and the second information is configured as the port's location information within the switch. Based on the first and second information, during data packet transmission, the switch can quickly and directly transmit the data packet to the current target transmission port.

[0065] The management unit polls each switch, reading the total number of local physical ports and the status of each port via the management protocol. It records all [Switch ID, Local Port Number] tuples and writes them to a port collection table (typically implemented using an array, linked list, or database). The management unit assigns a unique port code to each physical port, for example, setting the port code in the format of "switch serial number + local port number," where the switch serial number is the first piece of information, and the local port number is the second piece of information. For example, the port code corresponding to the fifth port of the third switch is set to 0x305, i.e., Port ID=0x305. The global port mapping table is distributed to all hosts and endpoint devices. The management unit distributes this port table to the drivers, BIOS, or internal registers of each host and endpoint device via management protocols (MCTP, PCIe VDM, SMBus, control plane API, etc.). The management unit synchronizes the mapping between its local port ID and physical port for each switch (writing it to the switch's internal register). Specifically, the first eight bits of the Vendor Defined Prefix (VDP) are encoded as follows: the high four bits (1000) represent the Vendor Defined Prefix, and the low four bits (1111) represent the Port ID routing method. Figure 4 Taking the PCIe network architecture topology shown as an example, the constructed global port mapping table is shown in Table 1, where A represents the first functional type, such as a terminal device, and B represents the second functional type, such as a switch. It should be noted that... Figure 4 Both dashed lines and solid lines with arrows represent electrical connections. Dashed lines indicate no data transmission, solid lines indicate data transmission, and arrows indicate the direction of data transmission.

[0066] Table 1 Global Port Mapping Table

[0067]

[0068] Target Port ID Acquisition and Distribution Phase: The system manager can generate a global port mapping table, which maps the BDF address of all terminal devices to the Port ID of the ports they are connected to. This table is then distributed to all source devices (Root Complex or Endpoint) via configuration space writing, VDM, or VDP (Vendor Defined Prefix) mechanisms for subsequent TLP packet construction. Devices without prefixes are ignored, while devices with prefixes are parsed first, ensuring full backward compatibility.

[0069] During the TLP packet construction and port ID filling phase: When a source device needs to send a TLP to a target device, its driver or firmware consults the globally mapped port table (BDF→Port ID mapping table) distributed locally to obtain the target port code corresponding to the target port connected to the target device, and embeds this Port ID into the Vendor Defined Prefix field of the TLP extension header when constructing the TLP packet. If necessary, the source port code and priority field can also be written simultaneously to support static QoS functions. When constructing the TLP packet, while writing the target port ID and source port ID into the extension header, a priority field can be optionally added. The format of the port code is shown in Table 2.

[0070] Table 2 Port Encoding Format

[0071]

[0072] Switching chip port routing execution phase: After each PCIe switching chip receives the TLP data packet, it parses the extended header, extracts the destination port code, and looks up the physical port corresponding to the Port ID in its local PMT. The data packet is then forwarded directly to that port without parsing the BDF or looking up traditional routing tables such as D-LUT and GID, thus greatly reducing routing latency.

[0073] The following further explains how the present invention enables direct data transmission without resolving BDF or searching traditional routing tables such as D-LUT or GID, but instead through the global port mapping table.

[0074] In one embodiment of the present invention, for the port-driven low-latency routing method based on the PCIe network architecture, a path table is pre-constructed based on the topology of the PCIe network architecture and the port mapping table. The path table includes paths from source ports to target ports, and each path includes the port codes corresponding to the ports it passes through. During data transmission, the source device directly determines the target path from the source device to the target device according to the path table. Specifically, the port connected to the device to be communicated with in the PCIe network architecture is determined as the terminal port. Multiple communication port groups are determined, with one terminal port as the source port and another terminal port as the target port. For each communication port group, the path from the source port to the target port, also called the transmission path, is determined. All communication port groups are traversed to construct the path table, which includes corresponding communication port groups and paths.

[0075] In this embodiment, the source device determines the target path corresponding to the communication port group from the source port to the target port according to the path table, configures a cursor to indicate the valid port code, and transmits the data packet in the following manner: parses the target path in the custom prefix, determines the current target transmission port according to the valid port code indicated by the cursor, and transmits the data packet to the current target transmission port; when the current data packet transmission is completed, controls the cursor to indicate the next port code of the valid port code along the direction of the target path to update the valid port code. In the traditional PCIe architecture, routing depends on table lookups at each level. This solution proposes to introduce a set of target path fields in the custom prefix (VDP), which is equivalent to a "port-vector" field, used to explicitly describe the complete physical path of the data packet from the source to the target. Each hop forwarding only indicates the currently effective port index by incrementing the cursor, and the switching chip can complete the forwarding without resolving addresses or dynamically looking up tables. This mechanism enables: fixed and predictable forwarding delays; paths to be determined entirely by the source, ensuring end-to-end determinism; and significantly reduced routing table size, requiring only a local PMT.

[0076] In this application, the cursor refers to a small counting field in the packet header (VDP extension field) used to indicate the position of the port code index currently being used in the current path sequence. This cursor can be understood as a hop-by-hop pointer, logically similar to the "next-hop index" or "stack-based routing pointer" in network fragmentation. For example, suppose a multi-hop port vector is defined in the packet header: Port-Vector=[0x12, 0x34, 0x56, 0x78], Hop-Cursor=0. When the packet is sent from the source device, the cursor points to the 0th entry (i.e., port 0x12). The switch chip / switching chip reads this value, looks it up in the local PMT table, and forwards the packet to the current target transmission port corresponding to that port code (either the port corresponding to 0x12 or the port corresponding to 0x34). Subsequently, the switching chip automatically increments the cursor by 1, i.e., Hop-Cursor=1. After receiving the packet, the next-hop switching chip reads the 1st entry (0x34) and continues forwarding, and so on.

[0077] It should be noted that there are two ways to configure the cursor. (The last part is a repetition of the previous one and can be omitted.) Figure 4 Taking the PCIe network architecture shown as an example, one configuration method is as follows: when the data packet is transmitted to the source port, the cursor is configured to indicate the source port, and the next port of the port corresponding to the valid port code on the target path is configured as the target transmission port.

[0078] For example, the target path is: source device, switch 1 port 2, switch 1 port 3, switch 2 port 1, switch 2 port 4, switch 3 port 4, switch 3 port 2, and target device; the target path is represented as: 0x0102, 0x0103, 0x0201, 0x0204, 0x0302, 0x0303. Here, switch 1 port 2 is the source port code, and switch 3 port 2 is the target port code. When the source device initiates a data packet, it configures the target path in a custom prefix of the data packet and sends the data packet to the source port. When the source port receives the data packet, it configures a cursor to indicate 0x0102. At this time, the valid port code is 0x0102, the current target transmission port is 0x0103, and the data packet is transmitted to switch 1 port 3 corresponding to 0x0103. After completing this data transmission, the cursor increments to indicate the next port code. This process of transmitting the data packet is repeated until the data packet is transmitted to the target device. Preferably, in each data transmission, the switch / port only parses the current port code and the next port code indicated by the cursor. This further reduces data transmission latency.

[0079] Another configuration method is as follows: when the data packet is transmitted to the source port, the cursor is configured to indicate the next port code corresponding to the source port code on the target path, and the port corresponding to the valid port code is configured as the target transmission port.

[0080] For example, the target path is: source device, switch 1 port 2, switch 1 port 3, switch 2 port 1, switch 2 port 4, switch 3 port 4, switch 3 port 2, and target device; the target path is represented as: 0x0102, 0x0103, 0x0201, 0x0204, 0x0302, 0x0303. Here, switch 1 port 2 is the source port code, and switch 3 port 2 is the target port code. When the source device initiates a data packet, it configures the target path in the data packet's custom prefix and sends the data packet to the source port. When the source port receives the data packet, it configures a cursor to indicate 0x0103. At this time, the valid port code and the current target transmission port are both 0x0103, and the data packet is transmitted to switch 1 port 3 corresponding to 0x0103. After completing this data transmission, the cursor increments to indicate the next port code, 0x0201. This process of transmitting the data packet is repeated until the data packet is transmitted to the target device. Preferably, in each data transmission, the switch / port only parses the current port code indicated by the cursor. This further reduces data transmission latency.

[0081] Based on the "multi-hop port vector" proposed in this application, the port codes of each switching chip that a data packet needs to pass through from the source port to the destination port are written sequentially into a fixed-length array and embedded in the Vendor Defined Prefix. A cursor is used to indicate the valid port, and the current target transmission port can be locked based on the valid port. This multi-hop port vector is similar to a "full-journey ticket". The entire path of the data packet is clear, and which port it passes through when it arrives at each switch is also clear. The combinational logic cursor advancement structure: input TLP → extract Hop-Cursor → query PMT → select the current data transmission port, and the current data packet forwarding is completed in only one clock cycle. Instead of the traditional BDF routing, which requires addressing and routing every time it reaches a switch, the traditional "hop-by-hop routing" is transformed into "navigation driving", which ensures end-to-end determinism and greatly reduces data transmission latency (fixed latency per hop, completed within one cycle). The routing latency and topology depth are linearly controllable, and power consumption and logic complexity are also greatly reduced.

[0082] If there are multiple target paths from the source port to the target port, the data transmission status of the multiple target paths is evaluated, and the target path with the best data transmission status is written into the custom prefix of the data packet.

[0083] If there are multiple target paths from the source port to the destination port, when the source device initiates a data packet, it pre-evaluates the data transmission status of the multiple target paths and determines their priorities according to the rule that the better the data transmission status, the higher the priority of the target path. The target path with the highest priority is written into the custom prefix of the data packet as the primary target path, and one or more of the other priority target paths are written into the custom prefix as alternative target paths. The primary target path is configured as the transmission path of the data packet.

[0084] Specifically, a path programming module is added to the source device (Root Complex or smart terminal device). This module selects the optimal path from a set of candidate paths (multiple target paths) based on task type, latency constraints, and bandwidth requirements, and writes the selected optimal path into the VDP (Virtual Distribution Path). Simultaneously, a Delay-Budget field is added to the VDP to represent the end-to-end latency budget. Each switching chip deducts its own hop delay, and can proactively trigger alternative paths or rate limiting when the budget is insufficient. This approach enables programmable path control at the transmitting end, making end-to-end latency controllable and quantifiable, and supports real-time task QoS priority scheduling.

[0085] When transmitting the data packet based on the primary target path, if the current data transmission status does not meet the preset data transmission requirements, for example, if the data transmission quality score is lower than the preset score threshold, the data transmission quality score can be determined based on data transmission delay, bit error rate, etc., then an alternative target path is activated to transmit the data packet.

[0086] When a port or link fails during data transmission along the primary target path, the switching chip can immediately switch to a backup port of the same level locally via an alternative target path, also known as a detour table, without requiring global rerouting. This is marked in the VDP using a detour bit. Furthermore, the VDP embeds a hop-by-hop micro-telemetry buffer, recording the current queuing delay, congestion bits, or packet loss count for each hop, forming a closed-loop path state upon returning to the source. Based on this local fast bypass and hop-by-hop micro-telemetry mechanism, fault recovery time can be reduced from milliseconds to microseconds, enhancing network observability and providing data support for subsequent path rewriting.

[0087] Optionally, during the transmission of data packets, the switch parses the source port code and destination port code in the custom prefix. If the ports corresponding to the source port code and destination port code belong to the same switch, the data packets are transmitted directly through the cross-connect matrix inside the switch.

[0088] In another embodiment of the present invention, unlike the port-driven low-latency routing method based on PCIe network architecture provided in the above embodiments which configures a cursor to incrementally indicate the valid port code, in this embodiment, the cursor is not configured, but the current target transmission port is directly determined based on the first and second information in the port code.

[0089] In this embodiment, the source device determines the target path from the source port to the target port according to the path table. The switch parses the target path in the custom prefix and determines two port codes that match the first information and the switch's own information. The switch determines the port corresponding to the port code that is later in the two port codes as the current target transmission port and transmits the data packet to the current target transmission port.

[0090] For example, the target path is: source device, switch 1 port 2, switch 1 port 3, switch 2 port 1, switch 2 port 4, switch 3 port 4, switch 3 port 2, and target device; the target path is represented as: IN, 0x0102, 0x0103, 0x0201, 0x0204, 0x0302, 0x0303, and OUTPUT. When the data packet is transmitted to switch 2, switch 2 parses the data packet and identifies the port codes 0x0201 and 0x0204 in the target path that match its own information, then directly transmits the data packet to switch 2 port 4 corresponding to 0x0204. It should be noted that the port of the switch and the port path outside the switch are unique, and there is no need to look up matching information; it can be sent directly.

[0091] In another embodiment of the present invention, unlike the port-driven low-latency routing method based on PCIe network architecture provided in the above embodiments which pre-builds a path table, in this embodiment, no path table is pre-built. The source device simply uses the source port encoding and the destination port encoding to determine the target path and configures the target path in a custom prefix of the TLP data packet.

[0092] In this embodiment, during the transmission of the data packet, the switch parses the source port code and destination port code in the custom prefix, and determines the target path corresponding to the source port and destination port according to the path table. The switch is one of the switches along the target path. The switch determines the port codes included on the target path and determines the current target transmission port based on the port codes; the switch transmits the data packet to the target transmission port. If there are multiple target paths from the source port to the target port, the switch evaluates the data transmission status of the multiple target paths and selects the path with the optimal data transmission status as the target path.

[0093] The difference between this embodiment and the previous embodiment is that each switch determines the target path in real time based on the source port code and destination port code in the custom prefix written to the data packet and a preset path table, instead of the source device directly determining the target path and writing it into the data packet. Therefore, the data transmission latency in this embodiment is higher than that in the previous embodiment, but it is better suited to the dynamic performance of the system.

[0094] In one embodiment of the present invention, a port-driven low-latency communication system based on a PCIe network architecture is provided, including one or more switches and multiple devices to be communicated. The switches include multiple ports, each port is configured with a unique port code, and one of the devices is configured to be electrically connected to one of the ports.

[0095] Each of the aforementioned devices and switches is configured with a preset global port mapping table, which includes the port code corresponding to each port. A source device is configured to determine the source port code corresponding to a source port and the target port code corresponding to a target port based on the global port mapping table. The source port is the port connected to the source device, and the target port is the port connected to the target device. The source device and the target device are two different devices. The source device is also configured to determine a target path from the source port to the target port and write the target path into a custom prefix of the data packet. The target path includes at least the source port code and the target port code. The switch is configured to parse the target path in the custom prefix, determine the current target transmission port based on the target path, and transmit the data packet to the current target transmission port.

[0096] Each of the aforementioned devices and switches is also configured with a preset path table, which includes a path from a source port to a destination port, and the path includes the port codes corresponding to each port it passes through; the source device is also configured to determine the target path from the source port to the destination port according to the path table, and write the target path into a custom prefix of the data packet; the switch is configured to parse the target path in the custom prefix, and determine the current target transmission port for data transmission according to the target path.

[0097] It should be noted that the port-driven low-latency communication system based on PCIe network architecture provided by this invention has the same inventive concept as the above-described port-driven low-latency routing method embodiment based on PCIe network architecture. The entire contents of the port-driven low-latency routing method embodiment based on PCIe network architecture are incorporated into the port-driven low-latency communication system embodiment based on PCIe network architecture by means of introduction.

[0098] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0099] The above description is only a specific embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A port-driven low-latency routing method based on PCIe network architecture, characterized in that, Includes the following steps: A unique port code is pre-assigned to each port of each switch in the PCIe network architecture, and a global port mapping table is constructed. The global port mapping table includes the port code corresponding to each port. The switch includes a PCIe switching chip. The global port mapping table includes port BDF parameters and port codes that have a one-to-one correspondence. The port code includes first information and second information. The first information is the information of the switch where the port is located, and the second information is configured as the location information of the port in the switch. Based on the topology of the PCIe network architecture and the port mapping table, a path table is pre-built. The path table includes the path from the source port to the target port, and the path includes the port code corresponding to each port it passes through. When a source device sends a data packet to a target device, the source device determines the source port code corresponding to the source port and the target port code corresponding to the target port according to the global port mapping table. The source port is the port to which the source device is connected, and the target port is the port to which the target device is connected. The source device determines the target path from the source port to the target port according to the path table and writes the target path into the custom prefix of the data packet. If there are multiple target paths from the source port to the destination port, the data transmission status of the multiple target paths is evaluated, and the priority of the multiple target paths is determined according to the rule that the better the data transmission status, the higher the priority of the target path; the target path with the highest priority is written into the custom prefix of the data packet as the primary target path, and one or more of the other priority target paths are written into the custom prefix as alternative target paths, and the primary target path is configured as the transmission path of the data packet; During the transmission of data packets, each of the switches does not look up the BDF parameters corresponding to the target port. The switch parses the target path in the custom prefix and determines the current target transmission port based on the target path, including: determining two port codes that match the first information and the switch's own information, and determining the port corresponding to the port code that is later in the two port codes as the current target transmission port. The data packet is transmitted to the current target transmission port, and the switch transmits the data packet to the current target transmission port according to the second information until the data packet is transmitted to the target device.

2. The port-driven low-latency routing method based on PCIe network architecture according to claim 1, wherein, The source device determines the target path from the source port to the target port according to the path table, configures a cursor to indicate the valid port code, and transmits the data packet in the following manner: Parse the target path in the custom prefix, determine the current target transmission port according to the effective port code indicated by the cursor, and transmit the data packet to the current target transmission port; Upon completion of the current data packet transmission, the cursor is controlled to indicate the next port code of the valid port code along the target path direction to update the valid port code.

3. The port-driven low-latency routing method based on PCIe network architecture according to claim 2, wherein, When the data packet arrives at the source port, the cursor is configured to indicate the source port encoding, and the port next to the port corresponding to the valid port encoding on the target path is configured as the target transmission port; or, When the data packet arrives at the source port, the cursor is configured to indicate the next port code corresponding to the source port code on the target path, and the port corresponding to the valid port code is configured as the target transmission port.

4. The port-driven low-latency routing method based on PCIe network architecture according to claim 1, characterized in that, When transmitting the data packet based on the primary target path, if the current data transmission status does not meet the preset data transmission requirements, an alternative target path is activated to transmit the data packet.

5. The port-driven low-latency routing method based on PCIe network architecture according to claim 1, characterized in that, It also includes the following steps: During the transmission of the data packet, the switch parses the source port code and destination port code in the custom prefix, and determines the destination path corresponding to the source port and destination port according to the path table. The switch is one of the switches in the path of the destination path. The switch determines two port codes that match the port codes of its own port and the port codes included in the target path, and determines the port corresponding to the later port code as the current target transmission port. The switch transmits the data packet to the target transmission port.

6. The port-driven low-latency routing method based on PCIe network architecture according to claim 1, characterized in that, It also includes the following steps: During the transmission of data packets, the switch parses the source port code and destination port code in the custom prefix. If the ports corresponding to the source port code and destination port code belong to the same switch, the data packets are transmitted directly through the cross switch matrix inside the switch.

7. A port-driven low-latency communication system based on a PCIe network architecture, characterized in that, The port-driven low-latency routing method based on the PCIe network architecture as described in claim 1 includes one or more switches and multiple devices to communicate with. The switches include multiple ports, each port is configured with a unique port code, and one of the devices is configured to be electrically connected to one of the ports. Each of the aforementioned devices and switches is configured with a preset global port mapping table, which includes the port code corresponding to each port; The source device is configured to determine the source port code corresponding to the source port and the target port code corresponding to the target port according to the global port mapping table, wherein the source port is the port to which the source device is connected and the target port is the port to which the target device is connected; The source device is also configured to determine a target path from the source port to the target port and write the target path into a custom prefix of the data packet to be sent, the target path including at least the source port code and the target port code; The switch is configured to parse the target path in the custom prefix, determine the current target transmission port based on the target path, and transmit the data packet to the current target transmission port.

8. The port-driven low-latency communication system based on PCIe network architecture according to claim 7, characterized in that, Each of the aforementioned devices and switches is also configured with a preset path table, which includes a path from the source port to the destination port, and the path includes the port codes corresponding to each port it passes through. The source device is also configured to determine a target path from the source port to the destination port according to the path table, and to write the target path into a custom prefix of the data packet; The switch is configured to parse the target path in the custom prefix and determine the current target transmission port for data transmission based on the target path.

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