An address deployment method, device, system and related equipment of a charging module

Abstract

The application provides an address deployment method, device and system of a charging module and related equipment, and is applied to a communication power supply device. The method comprises the following steps: acquiring a sampling voltage output by a dial code address circuit through a voltage sampling module; determining a plurality of theoretical voltage intervals corresponding to different opening and closing states of a plurality of dial code switches according to the sampling voltage; if the sampling voltage is in a target theoretical voltage interval, then generating a first dial code address according to the sampling voltage, and deploying the address of the charging module according to the first dial code address; and if the sampling voltage is not in the target theoretical voltage interval, then determining a compensation voltage according to the plurality of theoretical voltage intervals and the sampling voltage, determining a target sampling voltage according to the compensation voltage and the sampling voltage, generating a second dial code address according to the target sampling voltage, and deploying the address of the charging module according to the second dial code address. The address deployment efficiency of the power supply module when connected in parallel and the resource utilization rate of the GPIO port are improved.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to a method, apparatus, system and related equipment for address deployment of a charging module. Background Technology

[0002] Currently, with the rapid development of the new energy electric vehicle sector, electricity has become the energy source for most urban commuting tools, leading to higher demands from users for charging stations in terms of charging speed and power. DC charging stations on the market typically use multiple charging modules in parallel, simultaneously outputting power from multiple power modules to meet the needs of higher power output and fast charging. In this process, effective management of each power module requires address deployment for each module.

[0003] Existing power modules use different switches corresponding to different general purpose input / output (GPIO) ports to set the charging module's address, or they add DIP switches to the charging module and use different DIP switches for address deployment. However, using the traditional method of assigning different switches to different GPIO ports to set the module's address results in an excessive number of connection lines, and the number of lines increases with the number of modules connected in parallel. Furthermore, as the number of charging modules increases, the controller requires more GPIO pins to detect the DIP switch positions, increasing the controller's size and impacting development costs. Additionally, using one GPIO pin to detect one DIP switch position results in low resource utilization for the controller.

[0004] Therefore, it is urgent to solve the problem of how to improve the address deployment efficiency of power modules when operating in parallel and the resource utilization of GPIO ports during address deployment. Summary of the Invention

[0005] This application provides a method, apparatus, system, and related equipment for address deployment of a charging module. By setting specific values ​​for the resistors corresponding to each DIP switch, the address of the charging module can correspond one-to-one with the state of the DIP switch. At the same time, the DIP circuit has high sampling accuracy. The main controller of the communication power supply equipment adjusts the address of the charging module based on the sampled voltage value, reducing the number of connection lines in the module within the charging pile, improving the efficiency of address deployment, and increasing the resource utilization of GPIO ports during address deployment.

[0006] In a first aspect, embodiments of this application provide an address deployment method for a charging module, applied to the main controller of a communication power supply device. The communication power supply device includes a charging module, a DIP switch address circuit disposed on the output terminal of the charging module, and a voltage sampling module in the main controller disposed on the output terminal of the DIP switch address circuit. The DIP switch address circuit is disposed on the backplane of the communication power supply device, and the DIP switch address circuit includes multiple DIP switches and multiple DIP resistors. The method includes:

[0007] The voltage sampling module obtains the sampling voltage output by the DIP switch address circuit;

[0008] Based on the sampled voltage, the theoretical voltage ranges corresponding to different on / off states of the multiple DIP switches are determined, resulting in multiple theoretical voltage ranges.

[0009] Determine whether the sampled voltage is within the target theoretical voltage range; the target theoretical voltage range is any one of the plurality of theoretical voltage ranges;

[0010] If the sampled voltage is within the target theoretical voltage range, then a first DIP address is generated based on the sampled voltage; and the address of the charging module is deployed based on the first DIP address.

[0011] If the sampled voltage is not within the target theoretical voltage range, then a compensation voltage is determined based on the plurality of theoretical voltage ranges and the sampled voltage; a target sampled voltage is determined based on the compensation voltage and the sampled voltage; a second DIP address is generated based on the target sampled voltage, and the address of the charging module is deployed based on the second DIP address.

[0012] Secondly, embodiments of this application provide a charging module address deployment device applied to a communication power supply device. The communication power supply device includes a main controller, a charging module, a DIP switch address circuit disposed on the output terminal of the charging module, and a voltage sampling module in the main controller disposed on the output terminal of the DIP switch address circuit. The DIP switch address circuit is disposed on the backplane of the communication power supply device, and the DIP switch address circuit includes multiple DIP switches and multiple DIP resistors. The device includes:

[0013] The acquisition unit is used to acquire the sampled voltage output by the DIP switch address circuit through the voltage sampling module;

[0014] The calculation unit is used to determine the theoretical voltage range corresponding to different on / off states of the plurality of DIP switches based on the sampled voltage, and obtain a plurality of theoretical voltage ranges.

[0015] A judgment unit is used to determine whether the sampled voltage is within the target theoretical voltage range; the target theoretical voltage range is any one of the plurality of theoretical voltage ranges;

[0016] The conversion unit is configured to: generate a first DIP address based on the sampled voltage if the sampled voltage is within the target theoretical voltage range; determine a compensation voltage based on the plurality of theoretical voltage ranges and the sampled voltage if the sampled voltage is not within the target theoretical voltage range; determine a target sampled voltage based on the compensation voltage and the sampled voltage; and generate a second DIP address based on the target sampled voltage.

[0017] Output unit; used to deploy the address of the charging module according to the first DIP switch address; and to deploy the address of the charging module according to the second DIP switch address.

[0018] Thirdly, embodiments of this application provide an address deployment system for a charging module, which performs some or all of the steps described in any method of the first aspect of embodiments of this application.

[0019] Fourthly, embodiments of this application provide a communication power supply device, including a processor, a memory, a communication interface, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the processor, and the programs include instructions for performing steps in any method of the first aspect of this application.

[0020] Fifthly, embodiments of this application provide a computer program product, wherein the computer program product includes a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps described in any method of the first aspect of this application. The computer program product may be a software installation package.

[0021] By implementing the embodiments of this application, the following beneficial effects are achieved:

[0022] This application provides an address deployment method, apparatus, system, and related equipment for a charging module. The method is applied to the main controller of a communication power supply device. The communication power supply device includes a charging module, a DIP switch address circuit disposed on the output terminal of the charging module, and a voltage sampling module in the main controller disposed on the output terminal of the DIP switch address circuit. The DIP switch address circuit is disposed on the backplane of the communication power supply device and includes multiple DIP switches and multiple DIP resistors. The method includes: acquiring a sampling voltage output by the DIP switch address circuit through the voltage sampling module; determining multiple theoretical voltage ranges corresponding to different on / off states of the multiple DIP switches based on the sampling voltage; determining whether the sampling voltage is within a target theoretical voltage range; if the sampling voltage is within the target theoretical voltage range, generating a first DIP address based on the sampling voltage and deploying the address of the charging module based on the first DIP address; if the sampling voltage is not within the target theoretical voltage range, determining a compensation voltage based on the multiple theoretical voltage ranges and the sampling voltage; determining a target sampling voltage based on the compensation voltage and the sampling voltage; generating a second DIP address based on the target sampling voltage; and deploying the address of the charging module based on the second DIP address. Thus, on the one hand, by pre-setting the address of the corresponding charging module on the output line, after the charging module is connected to the output line, it can determine and deploy the address by the voltage value corresponding to the state of the DIP switch after power-on, eliminating the need for manual address setting on the panel via buttons and improving the address deployment efficiency of power modules in parallel operation; on the other hand, by taking specific values ​​for the resistors corresponding to each DIP switch, the address of the charging module can correspond one-to-one with the sampled voltage, so that the address deployment of multiple charging modules can be performed using only one GPIO port, thereby improving the resource utilization of the GPIO port during address deployment. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is an architecture diagram of an address deployment system for a charging module provided in an embodiment of this application;

[0025] Figure 2 This is a schematic diagram of the structure of a communication power supply device provided in an embodiment of this application;

[0026] Figure 3 This is a flowchart illustrating an address deployment method for a charging module provided in an embodiment of this application;

[0027] Figure 4This is a schematic diagram of a DIP switch address circuit provided in an embodiment of this application;

[0028] Figure 5 This is a schematic diagram of a two-output DIP address circuit provided in an embodiment of this application;

[0029] Figure 6 This is a schematic diagram of an isolated differential operational amplifier circuit provided in an embodiment of this application;

[0030] Figure 7 This is a flowchart illustrating the address deployment of another charging module provided in an embodiment of this application;

[0031] Figure 8 This is a functional module block diagram of an address deployment device for a charging module provided in an embodiment of this application. Detailed Implementation

[0032] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0033] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0034] It should be understood that the term "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this document indicates that the preceding and following related objects are in an "or" relationship. In the embodiments of this application, "multiple" refers to two or more.

[0035] In this application, the term "connection" refers to various connection methods, such as direct connection or indirect connection, to achieve communication between devices. This application does not impose any limitations on this.

[0036] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0037] The following is an explanation of the relevant terms used in this application:

[0038] DIP switch: A DIP switch is an electronic switching element consisting of multiple independent DIP switches. By manually moving the DIP switches, the on / off state is switched to realize the setting of circuit parameters or the selection of functions. No tools are required for operation. It is widely used in hardware configuration and device address setting scenarios.

[0039] Existing power modules use different switches corresponding to different GPIOs to set the charging module's address, or add DIP switches to the charging module and use different DIP switches for address deployment. However, using the traditional method of assigning different switches to different GPIO ports to set the module's address results in an excessive number of connection lines, and the number of lines increases with the number of modules connected in parallel. Furthermore, as the number of charging modules increases, the controller requires more GPIO pins to detect the DIP switch positions, increasing the controller's size and impacting development costs. Additionally, using one GPIO pin to detect one DIP switch position results in low resource utilization for the controller.

[0040] To address the aforementioned issues, this application provides an address deployment method, apparatus, system, and related equipment for a charging module, applied to communication power supply equipment. The method includes: acquiring a sampled voltage output from a DIP switch address circuit via a voltage sampling module; determining multiple theoretical voltage ranges corresponding to different on / off states of multiple DIP switches based on the sampled voltage; if the sampled voltage falls within a target theoretical voltage range, generating a first DIP address based on the sampled voltage, and deploying the charging module address based on the first DIP address; if the sampled voltage does not fall within the target theoretical voltage range, determining a compensation voltage based on the multiple theoretical voltage ranges and the sampled voltage; determining a target sampled voltage based on the compensation voltage and the sampled voltage; generating a second DIP address based on the target sampled voltage; and deploying the charging module address based on the second DIP address. This improves the address deployment efficiency and GPIO port resource utilization of the power supply module when operating in parallel.

[0041] The following is combined Figure 1 The system architecture of a charging module address deployment method according to an embodiment of this application will be described. Figure 1This is an architecture diagram of an address deployment system for a charging module provided in an embodiment of this application. The address deployment system 100 for the charging module includes a charging module 110, a DIP switch address circuit 120, and a main controller 130.

[0042] The charging module 110 is the power execution unit of the charging pile, used to receive address information deployed by the main controller 130, complete its own address configuration, and thus realize communication identification, power allocation, and status coordination in the scenario of multiple charging modules operating in parallel. In one possible embodiment, the charging module 110 may have an integrated CAN bus interface or other communication interfaces, which are not limited here. After the main controller 130 completes the address deployment, the charging module 110 feeds back an address confirmation signal through the CAN bus interface, and at the same time receives the power command issued by the main controller 130 based on the deployed address, so as to realize coordinated charging with other modules.

[0043] The DIP switch address circuit 120 converts the on / off state of the DIP switch into a voltage signal that can be acquired by the main controller. The DIP switch address circuit 120 includes a DIP switch 121 and DIP resistors 122. The DIP resistors 122 adopt a series topology, with each DIP resistor 122 connected in parallel with one DIP switch 121. The series-connected DIP resistors are designed according to a resistance multiple relationship; for example, when N=6, the resistance values ​​of the DIP resistors 122 are 1kΩ, 2kΩ, 4kΩ, 8kΩ, 16kΩ, and 32kΩ respectively, and the total resistance dynamically changes with the on / off state of the DIP switch. The DIP switch 121 is a single-pole single-throw switch; when the switch is closed, it short-circuits the corresponding DIP resistor; when the switch is open, the resistor is connected to the circuit. Different on / off combinations achieve 2 N These resistance states correspond to 2 N Each address is encoded. In one possible embodiment, the power supply terminal of the DIP switch address circuit 120 is connected to a DC voltage VCC (e.g., 24V) and connected to a pull-up resistor R. a (e.g., 61.48kΩ) and the DIP switch resistor in series form a voltage divider circuit. The difference in total resistance corresponding to different DIP switch addresses will cause the output voltage (i.e., the voltage signal to be acquired) to fall within different theoretical ranges. For example, when the DIP switch address is 000001, only the DIP switch of the resistor corresponding to the 1kΩ resistance value is closed, and the total resistance is 2kΩ+4kΩ+8kΩ+16kΩ+32kΩ=62kΩ. After voltage division, the output voltage is about 1.3V, which is used as the characteristic voltage of address 000001 and acquired by the main controller.

[0044] The main controller 130 is used to acquire the voltage signal from the DIP switch address circuit 120, parse the DIP switch address, and deploy the address to the charging module 110. The main controller 130 includes a voltage sampling module 131. The voltage sampling module 131 is an analog-to-digital signal conversion unit used to acquire the voltage signal output by the DIP switch address circuit 120, convert it into a digital quantity, and then provide it to the main controller for analysis and processing. The main controller can be composed of an ADC (analog-to-digital converter) and a signal conditioning circuit, possessing a certain sampling accuracy (such as 12-bit resolution) and anti-interference capability to ensure accurate acquisition of the voltage signal. In one possible embodiment, the main controller 130 is implemented using a digital signal processor, and the voltage sampling module 131 is integrated into the ADC channel inside the DSP. When the DIP switch address circuit 120 outputs a voltage signal, the voltage sampling module 131 filters and amplifies the signal, then converts it into a digital value through the ADC. The main controller 130 matches this digital value with a preset theoretical voltage range to determine the corresponding DIP switch address, and then generates an address deployment command, which is sent to the charging module 110. Furthermore, the charging module 110 and the DIP switch address circuit 120 are associated with the DIP switch address and module identity through hardware connection; the voltage signal output by the DIP switch address circuit 120 serves as the carrier of the address code and is collected by the voltage sampling module 131 of the main controller 130 to form a signal acquisition path; after the main controller 130 parses the voltage signal to obtain the DIP switch address, it sends an address deployment command to the charging module 110 to form an address configuration path.

[0045] As can be seen, through the architecture of the above-described charging module address deployment system 100, the address deployment system 100 realizes address encoding and voltage conversion through the DIP address circuit 120, and the main controller 130 completes voltage signal acquisition and address parsing, ultimately realizing the address deployment of the charging module 110. It only requires one voltage sampling channel to identify 2 N The single address significantly reduces the number of hardware interfaces and connecting lines in the charging pile, solving the cumbersome wiring problem of multi-GPIO address recognition schemes. At the same time, the resistance multiple design of the DIP address circuit combined with the software parsing of the main controller utilizes the physical stability of the DIP switch, and ensures high address recognition accuracy through voltage range matching and compensation mechanisms, which has high engineering practicality and economy.

[0046] The following is combined Figure 2 The communication power supply device in the embodiments of this application will be described. Figure 2 This is a schematic diagram of the structure of a communication power supply device provided in an embodiment of this application, as shown below. Figure 2As shown, the communication power supply device 200 includes one or more processors 210, a memory 220, a communication interface 230, and one or more programs 221. The processor 210 is communicatively connected to the memory 220 and the communication interface 230 through an internal communication bus.

[0047] The processor 210 is primarily used to perform the following actions: acquiring the sampled voltage output by the DIP switch address circuit through the voltage sampling module; determining the theoretical voltage ranges corresponding to different on / off states of multiple DIP switches based on the sampled voltage, thereby obtaining multiple theoretical voltage ranges; determining whether the sampled voltage is within a target theoretical voltage range; the target theoretical voltage range being any one of the multiple theoretical voltage ranges; if the sampled voltage is within the target theoretical voltage range, generating a first DIP address based on the sampled voltage; and deploying the address of the charging module based on the first DIP address; if the sampled voltage is not within the target theoretical voltage range, determining a compensation voltage based on the multiple theoretical voltage ranges and the sampled voltage; determining a target sampled voltage based on the compensation voltage and the sampled voltage; generating a second DIP address based on the target sampled voltage; and deploying the address of the charging module based on the second DIP address.

[0048] The one or more programs 221 are stored in the memory 220 and configured to be executed by the processor 210. The one or more programs 221 include instructions for performing any step in the above method embodiments.

[0049] The processor 210 can be a central processing unit (CPU), a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, units, and circuits described in conjunction with the disclosure of this application. The processor can also be a combination that implements computational functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc. The communication unit can be a communication interface, transceiver, transceiver circuit, etc., and the storage unit can be a memory.

[0050] The memory 220 can be volatile memory or non-volatile memory, or it can include both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous DRAM (DDR SDRAM), enhanced synchronous DRAM (ESDRAM), synchronous linked DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0051] It is understood that the communication power supply device 200 may include more or fewer structural elements than those shown in the above block diagram, such as a power module, physical buttons, a Wi-Fi module, a speaker, a Bluetooth module, a sensor, a display module, etc., without limitation. It is understood that the communication power supply device 200 may be equipped with... Figure 1 The architecture of the address deployment system for the charging module.

[0052] After understanding the software and hardware architecture of this application, the following will be combined with... Figure 3 This application describes an address deployment method for a charging module according to an embodiment. Figure 3 This is a flowchart illustrating an address deployment method for a charging module according to an embodiment of this application. The method is applied to the main controller of a communication power supply device. The communication power supply device includes a charging module, a DIP switch address circuit disposed on the output terminal of the charging module, and a voltage sampling module in the main controller disposed on the output terminal of the DIP switch address circuit. The DIP switch address circuit is disposed on the backplane of the communication power supply device and includes multiple DIP switches and multiple DIP resistors. The method specifically includes the following steps:

[0053] Step S310: Obtain the sampling voltage output by the DIP switch address circuit through the voltage sampling module.

[0054] In this embodiment, the voltage sampling module is used to detect and quantize the output voltage signal of the DIP address circuit in real time, so as to realize the address identification and deployment of the charging module. The DIP address circuit consists of several DIP resistors and DIP switches. Each DIP resistor is connected in series, and each DIP switch is connected in parallel to the corresponding DIP resistor. By changing the on / off state of the DIP switches, different voltage division combinations can be formed in the circuit, thereby generating a voltage signal at the output of the DIP address circuit that corresponds one-to-one with the DIP state.

[0055] In a specific embodiment, to ensure the accuracy and safety of the sampled signal, the voltage sampling module and the DIP switch address circuit are isolated by an electrical isolation circuit. The analog voltage signal output by the DIP switch circuit first passes through an isolation operational amplifier circuit to achieve electrical isolation and preliminary amplification of the signal, so as to avoid the sampling process from causing load effects or interference to the DIP switch circuit itself. Before sampling, the main controller reads the calibration variable Calib to determine whether the upper-point calibration has been completed. When Calib is equal to zero, it indicates that the calibration is not yet completed. At this time, the controller will execute the upper-point detection process, sample several preset DIP switch states one by one and record the sampling results to generate compensation parameters. This compensation parameter is used to correct the measurement deviation caused by resistance error, temperature drift and signal path inconsistency, to ensure the accuracy of the sampled voltage. When Calib is not equal to zero, it indicates that the calibration is completed and the normal sampling stage can be directly entered. Through this dynamic calibration mechanism, the consistency of sampling accuracy and voltage mapping relationship can be maintained under different environments and component differences.

[0056] As can be seen, by acquiring and digitizing the output voltage of the DIP switch address circuit through the voltage sampling module, the DIP switch status of the charging module is identified. Compared with the commonly used multi-pin detection scheme, only a single sampling channel is needed to complete the address identification of multiple modules, which not only improves the resource utilization of the GPIO port of the main controller, but also reduces the system complexity and cost, thereby enhancing the flexibility and working efficiency of the parallel control system of charging modules.

[0057] In one possible embodiment, each of the plurality of DIP switches corresponds one-to-one with each of the plurality of DIP resistors, and obtaining the sampling voltage output by the DIP address circuit specifically includes the following steps:

[0058] 311. Obtain the number of DIP switch bits in the DIP switch address circuit;

[0059] 312. Obtain the resistance value of each of the plurality of DIP resistors to obtain a plurality of resistance values;

[0060] 313. Based on the preset charging module design address, the multiple resistance values, and the number of DIP switch bits, determine the voltage division relationship corresponding to the multiple DIP switch resistors to obtain multiple voltage division relationships;

[0061] 314. Determine the sampling voltage signal based on the multiple voltage division relationships, and use the voltage sampling module to sample the voltage in the DIP address circuit based on the sampling voltage signal to obtain the sampling voltage.

[0062] In this embodiment, the DIP address circuit is a signal generation circuit that achieves address differentiation based on the principle of resistor voltage division. The number of DIP bits refers to the number of DIP switches in the DIP address circuit. Each DIP bit can affect the total resistance in the circuit by being on or off, thereby changing the output voltage. The resistance values ​​of the DIP resistors are usually designed according to fixed rules to ensure that a sufficient number of voltage combinations can be generated with a limited number of bits to meet the module address allocation requirements. For example, in a four-bit DIP state, up to 16 (2^3) voltage combinations can be achieved through different resistor values. 4 =16) Different voltage output states, each state corresponds to a unique module address.

[0063] In a specific embodiment, the topology and number of DIP switch bits of the DIP circuit are first obtained to determine the number of nodes participating in voltage division. Next, the nominal resistance value of each DIP resistor is obtained by measuring or reading design parameters, and error correction or temperature compensation is applied to eliminate the influence of environmental factors on the resistance value. After determining the resistance parameters, based on the address encoding scheme preset during the charging module design phase, the combination of resistors participating in voltage division is determined according to the on / off state of each DIP switch bit. Each DIP switch state forms a unique voltage division path, resulting in different voltage amplitudes at the output. Then, by substituting the resistance combination of each voltage division path into the voltage division formula, the theoretical output voltage in that state can be calculated. This process is repeated to obtain a set of theoretical output voltages corresponding to multiple DIP switch states. To establish a mapping relationship between voltage and address, the calculated voltage values ​​are arranged in ascending order of amplitude, ensuring a monotonic correspondence between voltage and DIP switch state. During the sampling process, the voltage sampling module samples the output of the DIP switch address circuit according to the established voltage division relationship. To ensure the stability and accuracy of the sampled signal, the sampling circuit typically includes an isolation operational amplifier and a differential amplifier circuit. The output voltage of the DIP switch circuit is first processed by the isolation operational amplifier to prevent interference from the original circuit during signal sampling and to achieve electrical isolation between different modules. Subsequently, the differential amplifier circuit suppresses common-mode interference in the signal and amplifies the small differential voltage to obtain a stable signal suitable for analog-to-digital conversion. This amplified sampled signal is then input to the ADC module of the main controller for analog-to-digital conversion, ultimately yielding the digitized sampled voltage value.

[0064] It is evident that by establishing a mapping relationship between the resistor voltage divider and the DIP switch state in the DIP address circuit, and by using a voltage sampling module to achieve high-precision sampling and voltage identification, not only can the accuracy and consistency of the charging module address deployment be guaranteed, but the occupancy rate of the main controller I / O port resources is also significantly reduced, thereby improving the system integration and address configuration efficiency.

[0065] In one possible embodiment, determining the voltage division relationship corresponding to the multiple DIP resistors based on the preset charging module design address, the multiple resistance values, and the number of DIP switch bits to obtain multiple voltage division relationships specifically includes the following steps:

[0066] 3131. Obtain the topological connection of the plurality of DIP switches and the plurality of DIP resistors in the DIP address circuit;

[0067] 3132. Determine the open / closed state of the plurality of DIP switches according to the design address of the charging module;

[0068] 3133. Determine the resistors participating in voltage division among the plurality of DIP resistors according to the open / closed state, and obtain the voltage dividing resistors;

[0069] 3134. Determine the voltage divider of the DIP switch address circuit based on the topology connection and the voltage divider resistor;

[0070] 3135. Based on the mapping relationship between the voltage divider in the preset DIP switch state and the design address under the charging module, determine the relationship corresponding to the voltage divider, and obtain the multiple voltage divider relationships.

[0071] In this embodiment, topology refers to the relative positions and electrical connections of the resistive elements and switches in the circuit, including series and parallel connections between resistors and connection nodes with switches. The DIP switch address circuit consists of multiple series or parallel resistive elements and corresponding DIP switches. Different on / off combinations will change the total impedance distribution of the circuit, thereby affecting the output voltage. By performing logical derivation and voltage calculation on these combination states, a set of independent voltage division relationships can be formed to represent the correspondence between each DIP switch state and its output voltage.

[0072] In a specific embodiment, firstly, it is necessary to obtain the topological connection relationship between the DIP switches and DIP resistors in the DIP address circuit. For different circuit designs, the topology may differ, for example, using a single-string voltage divider, branch voltage divider, or matrix voltage divider structure. By analyzing this topology, the influence area of ​​each switch action on the voltage distribution can be clearly identified. Next, based on the address number preset during the charging module design phase, the on / off state of the DIP switches is determined. The design address is a logical address used to distinguish different charging module numbers. Each DIP bit corresponds to a binary 0 or 1. When the switch is in the ON state, the corresponding resistor is short-circuited or participates in voltage division, thereby forming a specific voltage output mode. For example, when the address code is 0101, it indicates that the second and fourth DIP switches are closed, and the rest are open. Next, based on the determined on / off state, the resistor elements that actually participate in voltage division in the current DIP state are selected, resulting in a set of voltage-dividing resistors. Different combinations of voltage-dividing resistors lead to different voltage division ratios, thus outputting different voltage values. For example, if three DIP switch resistors R11, R22, and R33 are connected in series, and R22 is shorted in a certain DIP switch state, the output voltage will be redistributed according to the ratio of R11 to R33. Then, based on the topology and the combination of voltage divider resistors, the output voltage of the DIP switch address circuit in this state is calculated using the voltage divider principle. Taking a series voltage divider structure as an example: the output voltage Vout can be calculated using the formula Vout = Vcc × (Rout / Rt), where Vcc is the input voltage, Rout is the output branch resistance, and Rt is the total resistance participating in the voltage divider. For more complex network structures, the voltage divider result can be solved using the node voltage method or the equivalent resistance method, which will not be elaborated here. Finally, based on the preset mapping relationship between the DIP switch state and the charging module design address, the calculated voltage divider voltage is matched with the corresponding logical address to establish a voltage-address correspondence table, i.e., multiple voltage divider relationships. This preset mapping relationship can be established through theoretical calculations or corrected through measured data during the calibration phase to eliminate deviations caused by device errors or environmental drift. During operation, the main controller can find the corresponding design address in the mapping table by measuring the sampled voltage, thus realizing automatic address identification of the module.

[0073] It should be noted that dynamic calibration and error compensation mechanisms can be introduced during the calculation and establishment of the voltage divider relationship. Since actual resistance has tolerances, and temperature changes can cause slight drift in resistance values, multiple sets of measured voltages under known DIP switch states can be collected during initial operation and compared with the theoretical voltage divider to generate compensation coefficients. In subsequent operation, the main controller corrects the correspondence between the sampled voltage and the theoretical voltage based on the compensation coefficients, thereby ensuring the accuracy and stability of address recognition. Furthermore, to improve robustness, the voltage-address mapping curve can be smoothed using linear interpolation or polynomial fitting algorithms to address slight drifts caused by device aging or environmental changes.

[0074] It is evident that by establishing a multi-dimensional mapping relationship between the voltage divider characteristics and the DIP switch state, the output characteristics of the DIP circuit can be accurately reflected, achieving a high degree of consistency between voltage sampling and module address. Through the calculation and dynamic compensation of the voltage divider relationship, identification errors caused by component deviations can be effectively suppressed, improving the accuracy of charging module address identification.

[0075] For ease of understanding, see Figure 4 , Figure 4 This is a schematic diagram of a DIP switch address circuit provided in an embodiment of this application. As can be seen, this circuit converts the on / off state of the DIP switch into a voltage signal that can be acquired by the main controller, thereby realizing the hardware encoding of the charging module address. Specifically, the DIP switch address circuit mainly includes a DC power supply VCC and a pull-up resistor R. a The circuit consists of series-connected DIP resistors R1-R6, DIP switches S1-S6 connected in parallel with each resistor, a voltage output terminal Vsamp, and a ground terminal. R1 is the initial resistor. The resistors R2-R6 are designed according to a resistance multiple relationship (preferably, multiple K=2), for example, R1=1kΩ, R2=2kΩ, R3=4kΩ, R4=8kΩ, R5=16kΩ, and R6=32kΩ, forming a resistance branch with dynamically changing resistance values ​​through series connection. The DIP switches S1-S6 are single-pole single-throw switches. When the switch is closed, the corresponding DIP resistor is short-circuited; when the switch is open, the resistor is connected to the series branch. Different switch on / off combinations (i.e., DIP addresses) can achieve 2 6 =64 resistance value states. When the circuit is working, the power supply VCC is connected through the pull-up resistor R. a The 61.48kΩ resistor, connected in series with the DIP switch resistor, forms a voltage divider circuit. The output voltage Vsamp is determined by the total resistance of the series branch. When a switch is closed, the corresponding resistor is short-circuited, the total resistance decreases, and Vsamp voltage decreases. When the switch is open, the resistor is connected, the total resistance increases, and Vsamp voltage increases. Different DIP switch addresses correspond to unique total resistance values, causing Vsamp to fall within different theoretical voltage ranges. The voltage sampling module of the main controller can extract the corresponding DIP switch address by collecting Vsamp and matching these ranges, thus realizing the address identification of the charging module. This circuit only requires one voltage sampling channel to identify multiple sets of addresses, significantly reducing the complexity of the charging pile hardware interface and wiring. At the same time, the high-precision (0.1% accuracy) selection and software compensation mechanism of the high-level resistors (R4~R6) can effectively avoid the interference of factors such as resistor accuracy deviation and switch contact resistance on address identification, ensuring the accuracy and reliability of charging module address deployment in multi-module parallel operation scenarios.

[0076] Furthermore, this solution can also use multiple ADC ports for sampling; for example, N channels. And the pull-up resistor R is calculated using the formula for the lowest bit interval. a Differentiation yields:

[0077]

[0078] By deriving the above formula, we can obtain R. a The derived formula is:

[0079]

[0080] Where N is the number of channels, i.e., the number of DIP switch resistors; R total R is the total resistance value in the encoding address circuit, R1 is the initial resistance value, and R a Where is the resistance value of the pull-up resistor, and K is a multiple of the resistance value of the DIP switch resistor.

[0081] Therefore, after determining the initial resistance R1 using the above formula, the pull-up resistance R... a It can also be determined by N and K, taking a six-way DIP address circuit with N=6 as an example (e.g.) Figure 4 The optimal resistance factor is 2, and the pull-up resistor R can be obtained from the above. a =61.48R1, if R1=1kΩ, then R a =61.48kΩ. By determining these three parameters, the optimal sampling accuracy can be guaranteed. Even with other initial resistors R1, the optimal pull-up resistor can still be selected using the above formula to achieve the highest accuracy sampling configuration. The number of bits N in this circuit can be selected based on the DSP's sampling accuracy. When using ADC channels with higher resolution and accuracy, a higher number of bits N can be used because as the number of bits N increases, the voltage judgment interval for each address becomes smaller, especially the sampling interval for lower address bits. If using ADC channels with lower resolution and accuracy, the number of bits N should not be too high to ensure normal circuit operation. If the number of module addresses is too large, the number of bits in the DIP switch must be increased. An N-bit DIP switch will encounter situations where the sampling interval for lower address bits is too small, and the ADC's sampling accuracy no longer meets the corresponding accuracy, leading to address misidentification. In this case, the accuracy of the original N-bit DIP switch can be improved by using multiple ADC outputs, thereby enabling more address bits to be identified. Taking adding one ADC as an example, the original resistor value method... Will become K represents the resistance multiple of the DIP switch resistors. From the resistor values, it can be seen that the resistors from bits N / 2+1 to N are the same as those from bits 1 to N / 2, thus achieving the same N-bit DIP switch but with higher recognition accuracy. For easier understanding, an example using two ADC ports for address deployment is given below. See [link / reference] Figure 5 , Figure 5This is a schematic diagram of a two-output DIP address circuit provided in an embodiment of this application. As can be seen, this circuit adopts a two-way parallel DIP address sub-circuit design, which can realize the expansion of the number of addresses or redundancy verification, improve the flexibility and reliability of the charging module address deployment, and adapt to the complex address encoding requirements of large-scale multi-module parallel operation scenarios. Specifically, the circuit includes two parallel DIP address sub-circuits, which output voltage signals VsampH and VsampL respectively. The structure of each sub-circuit is completely symmetrical, each consisting of a DC power supply VCC and a pull-up resistor R. a The circuit consists of resistors arranged in series, following a resistance ratio relationship. For example, when K=2, the first sub-circuit of the DIP switch connected in parallel with the resistors is composed of S1, S2…S(N / 2), and the second sub-circuit is composed of S(N / 2+1), S(N / 2+2)…SN. Each sub-circuit is terminated by a resistor with a resistance of RN / 2 and grounded (or at a reference potential). During operation, the first sub-circuit forms two circuits through the on / off combinations of S1…(SN / 2). N / 2 The resistance states cause VsampH to fall within different theoretical voltage ranges; similarly, the second sub-circuit forms 2 through the on / off combinations of S(N / 2+1)…SN. N / 2 The resistance states allow VsampL to correspond to different voltage ranges. The main controller, by simultaneously acquiring VsampH and VsampL, can identify the voltage range based on the combined mapping of the two sampled voltages. N Compared to a single-channel DIP sampling structure, the dual-channel voltage sampling method significantly improves sampling accuracy while maintaining the same number of address recognitions. This is because in the dual-channel combined structure, the original input voltage range is divided into fewer sampling intervals, and the voltage range corresponding to each interval is increased. This reduces the risk of interval crossover caused by resistance error, sampling noise, or temperature drift, thus improving the resolution stability of voltage determination. It is worth noting that when expanding to multi-channel sampling, although higher voltage recognition accuracy and interval discrimination can be achieved through combination expansion, it will also consume more ADC sampling channel resources. Therefore, in practical design, a trade-off needs to be made between sampling accuracy and the number of ADC channels to control hardware resource consumption while ensuring address determination accuracy.

[0082] Step S320: Determine the theoretical voltage ranges corresponding to different on / off states of the multiple DIP switches based on the sampled voltage, thereby obtaining multiple theoretical voltage ranges.

[0083] In this embodiment, the theoretical voltage range is the output voltage range under ideal conditions with different DIP switch combinations. By modeling the voltage range, the accuracy and scalability of address identification can be guaranteed even with a large number of charging modules.

[0084] In a specific embodiment, the theoretical output voltage corresponding to each DIP switch state is first calculated. Since the resistor combination of the DIP switch circuit has deterministic characteristics, the theoretical voltage division can be calculated through the resistor ratio relationship. The theoretical voltage division of each DIP switch state is arranged in ascending order of value to obtain an ordered voltage sequence. By analyzing the difference between two adjacent theoretical voltage divisions, the voltage transition region between adjacent states can be determined. To improve the stability of interval division and the robustness of identification, an interval boundary voltage can be set at the midpoint of adjacent voltages to avoid voltage overlap caused by noise or resistance deviation in actual measurement. Specifically, each theoretical voltage division value is regarded as the voltage reference point of the ideal state, and the upper and lower limits of the interval are determined based on the average value of adjacent voltage points. For example, if two adjacent theoretical voltages are Vn and Vn+1, the upper limit of the corresponding interval can be (Vn+1+Vn) / 2, and the lower limit can be (Vn+Vn-1) / 2, and so on to form a continuous and non-overlapping theoretical voltage interval sequence. Through this interval division method, each DIP switch combination state has a unique corresponding theoretical voltage interval. When the actual sampled voltage falls within a certain range, the logic address corresponding to the current DIP switch state can be determined. Furthermore, considering that the sampled voltage may be affected by temperature drift, component aging, or noise interference during actual measurement, a margin factor is introduced when calculating the theoretical voltage range. This margin factor can be set according to the sampling voltage resolution and noise level, generally taking 2% to 5% of the theoretical range width, to expand the range boundary and improve recognition tolerance. For example, if the theoretical range width is Vb, then a compensation of ±0.02Vb is added to the upper and lower limits of the range to ensure that the voltage sampling result can still be correctly identified in the boundary region.

[0085] It can be seen that by establishing the theoretical voltage range corresponding to different states of the DIP switch based on the sampling voltage, the quantitative boundary division of the DIP switch state is realized, ensuring the accuracy and stability of the charging module address recognition.

[0086] In one possible embodiment, the DIP switch address circuit further includes pull-up resistors. The step of determining the theoretical voltage ranges corresponding to different on / off states of the plurality of DIP switches based on the sampled voltage, to obtain a plurality of theoretical voltage ranges, specifically includes the following steps:

[0087] 321. Obtain the set of open / closed state combinations of the plurality of DIP switches;

[0088] 322. Based on the preset relationship between the DIP switch and the resistor, and the resistance value of the pull-up resistor, calculate the theoretical voltage value corresponding to each open / closed state combination in the set of open / closed state combinations to obtain multiple theoretical voltage values.

[0089] 323. Sort the multiple theoretical voltage values ​​in ascending order to obtain a theoretical voltage value sequence;

[0090] 324. Calculate the median of any two adjacent theoretical voltage values ​​in the theoretical voltage value sequence to obtain the boundary value sequence;

[0091] 325. Determine the theoretical voltage range corresponding to each open / closed state combination in the open / closed state combination set according to the boundary value sequence, and obtain the plurality of theoretical voltage ranges.

[0092] In this embodiment, the pull-up resistor is used to enable the circuit to form a stable voltage divider structure under different on / off states, so that the theoretical voltage value can be derived based on the resistor connection rules and voltage sampling results.

[0093] In a specific embodiment, the set of on / off state combinations of multiple DIP switches is first obtained. The on / off state of the DIP switches determines the conduction or disconnection of the corresponding voltage divider branch; therefore, each DIP switch combination corresponds to a voltage divider path. For a circuit containing n DIP switches, the number of on / off combinations is 2^n. nA complete set of states can be obtained through enumeration, with each combination representing the electrical topology connection of voltage sampling nodes under a given resistor network. Next, based on the preset relationship between the DIP switches and resistors, and by adjusting the pull-up resistors, the theoretical voltage value for each on / off state combination is calculated. This relationship is determined by the basic voltage divider principle of series and parallel resistors. When a DIP switch is closed, the corresponding resistor participates in the voltage divider network; when the switch is open, the resistor is isolated and does not participate in voltage distribution. The pull-up resistor serves as a reference resistor connected in series with the DIP resistor, forming a calculable equivalent resistance structure for the entire circuit topology. The main controller calculates the theoretical voltage value based on the power supply voltage Vcc and the resistance distribution relationship using the voltage divider formula Vout = Vcc × (R_down / (R_up + R_down)), where R_up is the pull-up branch resistance and R_down is the equivalent resistance of the pull-down branch connected to the DIP switch. Through the voltage divider formula calculation, the theoretical voltage values ​​corresponding to multiple DIP states can be obtained. Then, the calculated theoretical voltage values ​​are sorted in ascending order to obtain a theoretical voltage value sequence. After sorting, the median of adjacent voltage values ​​in the theoretical voltage sequence is calculated to obtain a boundary value sequence. The introduction of the median can effectively buffer the risk of voltage overlap between adjacent states, especially in actual circuits affected by resistance errors or temperature changes. The median method can serve as a dynamic threshold, improving the stability and anti-interference capability of voltage interval division. For example, when adjacent theoretical voltages are Va and Vb, the boundary value is (Va+Vb) / 2, which is the voltage judgment boundary between them. Finally, after obtaining the boundary value sequence, the theoretical voltage interval corresponding to each DIP switch state combination is determined based on the boundary value interval. Specifically, for the i-th theoretical voltage value Vi, its corresponding theoretical voltage interval can be defined as [Vi-1 / 2, Vi+1 / 2], where Vi-1 / 2 and Vi+1 / 2 are adjacent boundary points, ensuring that all theoretical voltage intervals are independent, continuous, and non-overlapping. In addition, to further enhance the robustness of the boundary point division, a boundary correction mechanism is added when calculating the theoretical voltage range. This mechanism is based on the statistical distribution of sampled voltages during long-term operation to fine-tune the boundary of the range in order to cope with the effects of resistance deviation and noise interference.

[0094] It should be noted that pull-up resistors are used to provide a voltage reference and load balancing function, and their resistance value must be selected in conjunction with the input impedance of the voltage sampling module and the system resolution requirements. If the pull-up resistor is too small, it may lead to uneven voltage distribution or increased power consumption; if the resistance value is too large, it may cause unstable sampling signals. Therefore, the parameters of the pull-up resistor must be matched with the DIP switch resistor network to ensure the accuracy of the voltage divider calculation and the precision of the voltage range division.

[0095] It is evident that by introducing a voltage calculation mechanism that combines pull-up resistors with the on / off states of DIP switches, precise division of theoretical voltage ranges under different DIP switch states can be achieved, forming a voltage-address mapping relationship. This not only improves the accuracy of voltage range determination and anti-interference capability but also effectively prevents voltage overlap through a boundary value algorithm.

[0096] Step S330: Determine whether the sampled voltage is within the target theoretical voltage range; the target theoretical voltage range is any one of the plurality of theoretical voltage ranges.

[0097] In a specific embodiment, the main controller first reads the sampled voltage signal acquired by the voltage sampling module. This voltage signal, after isolation amplification and analog-to-digital conversion, is input to the control logic unit in digital form. The main controller compares the sampled voltage with the upper and lower limit voltage values ​​of each interval according to the established theoretical voltage interval mapping table. For example, for a certain interval [i], its upper limit voltage is Vmax_i, and its lower limit voltage is Vmin_i. When the sampled voltage Vsample satisfies Vmin_i≤Vsample≤Vmax_i, it is determined that the sampled voltage is within the target theoretical voltage interval. Furthermore, to improve the stability of voltage interval judgment, a dynamic moving average strategy is adopted when performing interval comparison. That is, within a time window (e.g., 10ms to 50ms), multiple sets of continuously sampled voltage data are averaged to reduce the influence of transient noise or external interference signals. The smoothed sampled voltage is used for interval matching calculation, thereby avoiding erroneous judgments caused by instantaneous jumps. Meanwhile, the main controller sets a judgment counter in the judgment logic. Only when the sampling results fall into the same interval multiple times consecutively is the sampled voltage confirmed to be stably within the target theoretical voltage range.

[0098] Step S340: If the sampled voltage is within the target theoretical voltage range, then generate a first DIP address based on the sampled voltage; and deploy the address of the charging module based on the first DIP address.

[0099] In this embodiment, the generation of the DIP switch address not only reflects the physical switching state of the DIP switch circuit, but also demonstrates the controller's ability to digitally identify and logically encode voltage signals. By establishing a mapping relationship between the sampled voltage value and the theoretical voltage range number, the main controller can automatically address multiple modules without requiring multiple GPIO pins, thereby significantly improving address deployment efficiency and system resource utilization.

[0100] In a specific embodiment, after determining that the sampled voltage falls within a certain target theoretical voltage range, the main controller first extracts the range's numbering information. The theoretical voltage range numbering is pre-defined based on the set of DIP switch state combinations, with each number uniquely corresponding to a set of DIP states. For example, in a four-position DIP switch structure, if the states of the first to fourth positions are 1011, the theoretical voltage range number corresponding to this state combination can be set to 11. The main controller can read this number using a lookup table and, based on a pre-defined voltage range and address mapping table, convert the number into an initial address code. This mapping table typically defines the correspondence between DIP states and module addresses in binary form, ensuring a one-to-one correspondence between the voltage range number and the final DIP address. Next, the main controller generates the first DIP address based on this initial address code. During the generation process, to ensure the stability and correctness of the addressing result, the main controller calls an address verification algorithm. The verification algorithm typically employs parity checking or CRC checking to perform bit-level verification of the generated address code, ensuring that no abnormal fluctuations or logical errors occur during signal sampling or conversion. When the verification result is correct, the address is confirmed as the first DIP address and written into the address register of the communication power supply device to realize the recording of address deployment.

[0101] As can be seen, by using voltage sampling and logic judgment of the main controller, multiple DIP switch states can be identified and encoded with only one sampling channel, thereby significantly reducing the controller pin resource usage and lowering system hardware complexity and cost. Simultaneously, by introducing voltage compensation and verification mechanisms, the accuracy and stability of the addressing results are effectively improved, enhancing the reliability of the charging module configuration.

[0102] In one possible embodiment, generating the first DIP address based on the sampled voltage specifically includes the following steps:

[0103] 341. Obtain the theoretical voltage range numbers corresponding to the multiple theoretical voltage ranges;

[0104] 342. Determine the number corresponding to the target theoretical voltage range from the plurality of theoretical voltage range numbers to obtain the target theoretical voltage range number;

[0105] 343. Determine the address code corresponding to the target theoretical voltage range number based on the preset theoretical voltage range number and address mapping relationship;

[0106] 344. The main controller generates an initial DIP switch address based on the address encoding;

[0107] 345. Perform format verification on the initial DIP switch address using preset verification rules to obtain the verification result;

[0108] 346. When the verification result indicates that the initial DIP switch address is correct, the initial DIP switch address is confirmed as the first DIP switch address.

[0109] In this embodiment, by establishing a mapping relationship between the theoretical voltage range number and the module address, the main controller can quickly determine the module logical address based on the range to which the sampled voltage belongs, thus completing the automatic identification and deployment of the module.

[0110] In a specific embodiment, firstly, the main controller calls the interval index table to obtain the numbering information corresponding to multiple theoretical voltage intervals. This index table is automatically generated by circuit design parameters during the system initialization phase, where each number uniquely corresponds to the upper and lower limit voltage values ​​of a theoretical voltage interval. For example, when the DIP switch has a three-position structure, the system can generate eight theoretical voltage interval numbers, each representing a different DIP switch combination state. At this time, the logical order of the numbers is consistent with the ascending order of the voltage intervals, thus ensuring a linear mapping relationship between voltage changes and address numbers. Next, the main controller compares the sampled voltage with the interval table to determine the number corresponding to the target theoretical voltage interval, i.e., the target theoretical voltage interval number. When the sampled voltage is within a certain interval range, the number of that interval is directly read as the input parameter for subsequent addressing calculations. After determining the target interval number, the main controller determines the address code corresponding to that number based on the preset theoretical voltage interval number-address mapping relationship. This mapping relationship is automatically generated by a software algorithm during the system design phase, typically using a one-to-one binary encoding form, such as address code 0101 for number 5, and 0111 for number 7, etc. The mapping table can use either sequentially increasing encoding or custom allocation based on the topology to meet the address uniqueness requirements when multiple modules are paralleled. Then, the main controller generates an initial DIP address based on this address encoding. This process can be implemented by writing to a logic register, loading the address encoding into the address register of the communication power supply device to form a unique logical address. Simultaneously, the main controller can also generate an address check bit for identification and integrity verification in subsequent data communication. After generating the initial address, a format verification operation is performed to ensure that the address conforms to the preset format specifications (such as binary length, parity, and correctness of identifier bits). If the format verification passes, the verification result is output as "correct"; if the verification fails, a re-encoding mechanism is triggered to reprocess or renumber the voltage sampling data. Finally, under the condition that the verification result is correct, the main controller confirms the initial DIP address as the first DIP address and writes it to the device management unit, realizing the formal address deployment of the charging module. At this time, the first DIP address serves as the unique identifier of the module in the communication network and will be used for subsequent data interaction, status monitoring, and collaborative control between the main controller and the charging module.

[0111] As can be seen, in the execution of this specific embodiment, no manual dialing or multiple GPIO pins are required. Addressing operations for multiple modules can be completed solely through voltage signals and preset mapping relationships, thereby effectively reducing hardware design complexity and controller resource consumption. Simultaneously, the combination of number mapping, format verification, and duplicate verification mechanisms ensures the accuracy and uniqueness of address generation, significantly improving system configuration efficiency and operational stability.

[0112] Step S350: If the sampled voltage is not within the target theoretical voltage range, then determine the compensation voltage based on the plurality of theoretical voltage ranges and the sampled voltage; determine the target sampled voltage based on the compensation voltage and the sampled voltage; generate a second DIP address based on the target sampled voltage, and deploy the address of the charging module based on the second DIP address.

[0113] In this embodiment, multiple theoretical voltage ranges are parameters of the DSP based on the DIP switch address circuit (initial resistor R1, pull-up resistor R...). a The reference interval is pre-calculated using the resistance multiple K, specifically by first applying the resistance law (R... k+1 =K R k )calculate The theoretical ADC sample value Vadc_th(n) corresponding to each address is used as the boundary, and the voltage range of each address is divided by the midpoint of the theoretical sample values ​​of adjacent addresses, providing a reference for error judgment. The determination of the compensation voltage aims to correct inherent hardware errors (such as high-level resistor accuracy deviation, isolation op-amp temperature drift, ADC sampling noise, etc.). Its calculation is based on preset test points and curve fitting. That is, firstly, h user-defined test point addresses (set H) are selected, the actual sample voltage of these test points is collected, and the difference ΔV is calculated with the corresponding theoretical value Vadc_th. Then, the variation law of ΔV is determined by curve fitting (such as linear or polynomial fitting), and finally, the compensation voltage adapted to the current circuit state is determined. The target sampling voltage is the correction voltage after eliminating hardware errors by superimposing the actual sampling voltage and the compensation voltage, ensuring that it can return to the theoretical voltage range. The second DIP address matches the target sampled voltage with multiple pre-divided theoretical voltage ranges to locate the DIP state corresponding to its range; the charging module address deployment writes the second DIP address into the module address register to complete the configuration, and at the same time needs to update the calibration variable Calib (set to 1 if the match is successful, marking the calibration as complete) and the compensation variable k (k is incremented by 1 for each compensation process, and k>4 is judged as a fault).

[0114] In a specific embodiment, for easier explanation, the following example uses a DIP switch circuit with N=6 (resistance parameters are K=2, R1=1kΩ, R...). a=61.48kΩ (corresponding to 64 addresses), assuming the target address of the charging module is 000001, its theoretical sampled value Vadc_th=1.3V, and the target theoretical voltage range is 1.2~1.4V. When the module powers on and samples, if the actual sampled voltage is 1.1V (lower than the target range lower limit, the deviation originates from the 0.1% accuracy offset of R6), select h=3 test point addresses (000001, 000010, 000100), whose theoretical Vadc_th are 1.3V, 2.6V, and 5.2V respectively. The actual sampled values ​​of the 3 test points are 1.1V, 2.4V, and 5.0V, and the calculated difference ΔV is -0.2V. The compensation voltage is determined to be 0.2V through linear fitting. The target sampled voltage is calculated to be 1.1V + 0.2V = 1.3V. This value falls within the target theoretical voltage range of 1.2~1.4V. Match the corresponding DIP switch state 000001, generate the second DIP switch address, and write 000001 into the charging module address register to complete the deployment. At this time, the compensation variable k increases from 0 to 1, and Calib is set to 1. If the target sampling voltage is 1.15V after the first compensation (still deviating from the range), repeat the above process until matching is achieved when k=3. If matching is still not achieved when k=4, it is determined to be a hardware fault, triggering manual troubleshooting.

[0115] In one possible embodiment, determining the compensation voltage based on the plurality of theoretical voltage ranges and the sampled voltage specifically includes the following steps:

[0116] 351. Determine the upper limit and lower limit of each theoretical voltage range in the plurality of theoretical voltage ranges to obtain a plurality of upper limits and a plurality of lower limits; each upper limit in the plurality of upper limits corresponds one-to-one with each lower limit in the plurality of lower limits;

[0117] 352. Calculate the difference between the upper limits of the multiple intervals and the lower limits of the multiple intervals to obtain multiple differences;

[0118] 353. Fit the multiple differences according to the preset fitting algorithm to obtain the fitting curve;

[0119] 354. Determine the compensation voltage range corresponding to the target theoretical voltage range based on the fitted curve;

[0120] 355. Determine the compensation voltage based on the compensation voltage range.

[0121] In this embodiment, multiple theoretical voltage ranges are determined by the DSP based on the DIP switch circuit parameters (initial resistor R1, pull-up resistor R...). a The resistance multiple K=2) is calculated and generated based on the resistance law R. k+1 =K R kDerivation The theoretical sampled value Vadc_th(n) of the ADC at each address is used as the interval boundary, with the midpoint between two adjacent theoretical sampled values ​​as the interval boundary. That is, the upper limit of the theoretical voltage interval for the nth address is (Vadc_th(n)-Vadc_th(n+1)) / 2, and the lower limit is (Vadc_th(n-1)-Vadc_th(n)) / 2 (n=1,2,...). When n=0, the lower limit is 0; n= The upper limit of the time interval is taken as the upper limit of the VCC voltage divider, ultimately forming a one-to-one correspondence between the upper and lower limits of each interval. The difference is essentially the width of each theoretical voltage interval (i.e., the upper limit minus the lower limit). Since the resistors in the DIP switch circuit are designed with a multiple relationship of K=2, the interval widths corresponding to different addresses exhibit a regular difference. Calculating this difference quantifies the accuracy requirements of different intervals. The preset fitting algorithm needs to adapt to the circuit error characteristics, typically using linear fitting or polynomial fitting. Linear fitting is suitable for scenarios where the error changes linearly with the address, while polynomial fitting is suitable for non-linear error scenarios such as resistor accuracy deviation and op-amp temperature drift. No limitation is made here. Linear fitting is preferred.

[0122] In a specific embodiment, taking a DIP switch circuit with N=6 as an example (resistance parameters K=2, R1=1kΩ, R... a=61.48kΩ, corresponding to 64 addresses, VCC=24V). Assuming the target theoretical voltage range of the charging module to be deployed is 1.2~1.4V corresponding to address 1 (DIP switch state 000001), and the actual sampled voltage is 1.1V (deviation from the target range), then first determine the theoretical voltage range of the first 5 addresses (because the error of the lower address is more significant, it needs to be analyzed in detail). Address 0 (000000) is 0~1.2V (upper limit 1.2V, lower limit 0V), address 1 is 1.2~ The voltage levels are calculated as follows: 1.4V (upper limit 1.4V, lower limit 1.2V), address 2 (000010) is 1.4~1.8V (upper limit 1.8V, lower limit 1.4V), address 3 (000011) is 1.8~2.6V (upper limit 2.6V, lower limit 1.8V), and address 4 (000100) is 2.6~4.2V (upper limit 4.2V, lower limit 2.6V), resulting in 5 sets of upper and lower limits (e.g., (0,1.2), (1.2,1.4), (1.4,1.8), etc.). Then, the difference between the upper and lower limits of each set (the interval width) is calculated. The voltage differences for addresses 0, 1, 2, 3, 4, and 5 are 1.2V, 0.2V, 0.4V, 0.8V, and 1.6V, respectively. A linear fitting algorithm is then used to fit the address number-difference data ((0,1.2), (1,0.2), (2,0.4), (3,0.8), (4,1.6)), resulting in a fitted curve equation y=0.38x-0.22 (R²=0.98, the fit meets engineering requirements). This curve reflects that for every 1 increase in address number, the average change in interval width is 0.38V, consistent with the increasing interval width trend caused by the multiple law of resistance K=2. The target theoretical voltage range corresponds to address 1. Substituting x=1 into the fitted curve equation, the fitted value of the theoretical range width is 0.38×1-0.22=0.16V. Combining this with the actual range width of 0.2V, the calculated error fluctuation range is ±0.05V. Therefore, the compensation voltage range corresponding to the target range is determined to be 0.15~0.25V. If the actual sampled voltage 1.1V deviates from the lower limit of the target range (1.2V) by 0.1V, a value within the compensation voltage range that can cover this deviation needs to be selected. Therefore, the midpoint of the range, 0.2V, is taken as the compensation voltage. If the sampled voltage deviation is 0.18V, the upper limit of the range, 0.25V, is taken to ensure that the corrected target sampled voltage (1.1+0.25=1.35V) falls within the target range of 1.2~1.4V.

[0123] In one possible embodiment, each of the plurality of DIP resistors is connected in series, and each of the plurality of DIP switches is connected in parallel with a DIP resistor; the communication power supply device further includes an electrical isolation circuit, the output of which is connected to the main controller. Before obtaining the sampled voltage output by the DIP address circuit through the voltage sampling module, the method further includes the following steps:

[0124] A1. Obtain calibration variables; the calibration variables are used to represent the calibration status of the main controller;

[0125] A2. When the calibration variable is zero, obtain the sampling channel of the voltage sampling module;

[0126] A3. Determine the sampling accuracy based on the plurality of DIP resistors and the sampling channel;

[0127] A4. Determine the sampling parameters of the voltage sampling module according to the sampling accuracy, and sample the DIP address circuit to obtain the first sampling signal;

[0128] A5. The first sampling signal output by the DIP switch address circuit is electrically isolated through the electrical isolation circuit to obtain an isolated sampling signal;

[0129] A6. Send the isolation sampling signal to the voltage sampling module to control the voltage sampling module to perform voltage sampling on the DIP address circuit according to the isolation sampling signal.

[0130] In this embodiment, the series-connected DIP resistors need to follow R... k+1 =K R k (K=2 is the optimal multiple) follows a pattern (e.g., when N=6, R1=1kΩ, R2=2kΩ, ..., R6=32kΩ), the total resistance Rtotal=R1+K R1+…+K n-1 R1 ensures differentiated total resistance under different DIP switch states, thus achieving a one-to-one correspondence between the sampled voltage and the DIP switch address. The DIP switch and the DIP resistor are connected in parallel, short-circuiting the corresponding resistor when the switch is closed (the resistor is short-circuited when the switch is closed, and the total resistance decreases; the resistor is connected when the switch is open, and the total resistance increases), providing the hardware basis for state differentiation in voltage sampling. The calibration variable Calib takes a value of 0 to indicate that the main controller has not completed address calibration, and a value of 1 to indicate that calibration has been completed. Its function is to avoid repeating the calibration process after the module powers on, reducing DSP resource usage. The sampling channel is the ADC channel of the main controller. Determining the sampling accuracy requires considering both the characteristics of the DIP resistor and the performance of the sampling channel. On one hand, the accuracy of the series DIP resistors (e.g., the high-order resistors R4~R6 require 0.1% accuracy) and the total resistance range will affect the width of the voltage range after voltage division; on the other hand, the ADC resolution of the sampling channel (e.g., 12-bit, 16-bit) determines the voltage quantization accuracy (resolution = reference voltage / 2). HH represents the resolution in bits, and both together determine the final sampling accuracy (e.g., resolution 2.93mV + resistor accuracy error 2mV, total accuracy ±5mV). Sampling parameters include sampling frequency and reference voltage, which need to be determined in reverse order of sampling accuracy. For example, to avoid signal distortion, the sampling frequency must meet the Nyquist criterion; the reference voltage must match the maximum voltage division value of the DIP switch circuit (e.g., when VCC=24V, the reference voltage is set to 12V to cover the 0.1~12V range of Vsamp), ensuring that the first sampled signal can be completely quantized. The electrical isolation circuit uses an isolation operational amplifier (e.g., ADUM1200), whose function is to achieve electrical isolation between the DIP switch circuit and the main controller, eliminate common-mode interference and electric shock risk in subsequent circuits, and ensure the purity of the sampled signal; the isolated sampled signal is the differential signal processed by the isolation operational amplifier, whose amplitude is consistent with the first sampled signal, but noise interference is suppressed, to ensure that the final sampled voltage can accurately reflect the DIP switch state and provide reliable data for subsequent address determination.

[0131] In a specific embodiment, firstly, the isolated differential signal is input to the differential amplifier circuit in the form of Vsamp+ and Vsamp-. The differential amplifier circuit can effectively suppress common-mode interference and amplify small differential signals. Its amplification factor is set according to the ratio of the input resistance to the feedback resistance, thereby obtaining a sampling voltage Vadc that meets the requirements of analog-to-digital conversion. Then, the Vadc signal is input to the analog-to-digital converter (ADC) unit inside the main controller, and after digital processing, it is converted into a calculable digital quantity. By reading the output value of the ADC and combining it with calibration parameters, the main controller can obtain the actual voltage value output by the DIP switch circuit, which is used for subsequent address determination and deployment.

[0132] For ease of understanding, see Figure 6 , Figure 6This is a schematic diagram of an isolated differential operational amplifier circuit provided in an embodiment of this application. As can be seen, this circuit is used to differentially isolate, amplify, and filter the sampled voltage signal output by the DIP switch address circuit, improving the signal's anti-interference capability and accuracy, and providing a reliable analog input for the charging module's address resolution. Specifically, the circuit mainly consists of differential input interfaces Vsamp+ and Vsamp-, input resistor R8, feedback resistor R9, compensation capacitors C1 and C2, an amplifier circuit, output resistor R10, filter capacitor C3, and output interface Vadc. The differential input interfaces Vsamp+ and Vsamp- are used to receive the differential voltage signal (or single-ended signal to differential form) output from the DIP address circuit. Input resistor R8 limits the current and matches the impedance of the input signal, preventing excessive load on the front-end circuit. Feedback resistor R9, along with compensation capacitors C1 and C2, forms a frequency compensation network to suppress high-frequency self-oscillation of the operational amplifier, ensuring stable operation of the circuit over a wide frequency band. Simultaneously, in conjunction with the internal feedback branch of the operational amplifier, the amplification factor of the circuit is set (e.g., amplification factor Av = 1 + R9 / R8), achieving accurate amplification of the sampled signal. The amplifier circuit employs an isolated operational amplifier architecture (e.g., magnetically coupled or optically coupled isolation) to achieve electrical isolation between the input and output sides, effectively blocking common-mode interference (e.g., power frequency interference, ground potential difference), ensuring the purity of the sampled signal. At the output, R10 and C3 form an RC low-pass filter circuit to filter out high-frequency noise in the amplified signal, making the output Vadc a smooth DC voltage signal, which meets the accuracy requirements of the main controller's voltage sampling module for the input signal. The differential isolation and amplification design of this circuit eliminates the interference path between the DIP address circuit and the main controller through electrical isolation, solving the problem of address misjudgment caused by common-mode interference in traditional single-ended sampling. On the other hand, through precise amplification and filtering, the sampled voltage signal is conditioned to the effective range that the main controller ADC can recognize, ensuring the accuracy and stability of the charging module address deployment.

[0133] As can be seen, the structure of series-connected DIP resistors and parallel-connected switches ensures differentiated identification of multiple addresses (e.g., 64 addresses when N=6) without the need for additional GPIO ports; on the other hand, the precise sampling pre-process enables a single ADC channel to stably identify 2 This single address reduces the number of internal connection cables in the charging pile, lowers wiring complexity and maintenance costs, and provides reliable hardware and process support for the high-power, multi-module charging needs of the new energy electric vehicle sector.

[0134] For ease of understanding, see Figure 7 , Figure 7This is a flowchart of address deployment for another charging module provided in this application embodiment. As can be seen, the address deployment of the charging module includes processes such as calibration triggering, theoretical voltage calculation, sampling verification, error compensation, and address identification. The hardware error is adaptively corrected through logic to ensure the accuracy and reliability of the charging module address deployment and adapt to the complex requirements of multi-module parallel operation scenarios.

[0135] Specifically, starting with "module power-on," the system first enters the calibration trigger phase: it checks whether the "Calib calibration variable is 0." The Calib variable is used to identify the calibration status of the main controller. If Calib is not equal to 0, it indicates that the address has been successfully deployed, and the address deployment is complete. If Calib is 0, the address calibration process is triggered, entering the theoretical voltage calculation phase. In the theoretical voltage calculation phase, the system executes "calculate Vadc_th(n), n=0,…,63; set k=0," where Vadc_th(n) is the theoretical sampled value of the ADC corresponding to the nth address in the DIP switch address circuit. This value is determined by the main controller based on the DIP switch resistor parameters (such as initial resistor R1, resistance multiple K=2, pull-up resistor R...). aThe voltage divider formula is used for pre-calculation, resulting in 64 addresses (n∈[0,63]) when N=6. Next, the formula "Calculate Vup(n)=[Vadc_th(n+1)-Vadc_th(n)] / 2; Vlow(n)=[Vadc_th(n)-Vadc_th(n-1)] / 2; n=0,…,63" is used. This means dividing the theoretical voltage range for each address into its own range (Vlow(n) is the lower limit of the range, and Vup(n) is the upper limit) by using the midpoint of the theoretical sampled values ​​of two adjacent addresses. After defining the theoretical range, the sampling verification process begins: The formula "If k==0{sample Vadc(m), m∈M}Else{Vadc(m)=Vadc(m)+ΔV(m), m∈M}" is executed, where M is the preset set of test point addresses, and k is the number of compensation attempts (initially 0). When k=0, the actual sampling voltage Vadc(m) corresponding to test point M is directly collected; when k>0, the previously fitted compensation voltage ΔV needs to be superimposed to correct the hardware error before the sampling value is calculated. Then, the interval judgment stage is entered: it is judged whether "Vup(m)<=Vadc(m)<=Vlow(m)" is true. If yes, it means that the sampling voltage falls into the target theoretical voltage range, and directly enters the "sample Vadc and judge address" stage. The main controller determines the DIP address and deploys it to the charging module according to the Vadc matching theoretical range, and sets Calib to 1, and the process ends; if no, it means that there is a hardware error (such as resistor accuracy deviation, isolation operational amplifier temperature drift, etc.), and the error compensation stage needs to be entered. In the error compensation stage, "sample Vadc(h), h∈H" is executed, and then "ΔV(h)=Vadc(h)-Vadc_th(h), h∈H; fit ΔV; k=k+1" is executed. Here, H is another set of test point addresses (used to collect more error data to improve fitting accuracy). The difference ΔV(h) between the actual sampled voltage at test point H and the theoretical value Vadc_th(h) is calculated. A curve fitting algorithm (such as linear fitting or polynomial fitting) is used to fit the variation of ΔV, obtaining a compensation voltage model adapted to the current circuit state. k is incremented by 1 to record the number of compensations. Then, the compensation count judgment stage is entered: it is determined whether "k<=4" is true. If yes, it means the compensation count has not exceeded the limit, and the process returns to the sampling verification stage, recalc(m) based on the newly fitted ΔV and verifies the interval; if no, it means that even after multiple compensations, the theoretical interval still cannot be matched, indicating a hardware fault (such as resistor damage or operational amplifier failure), the process terminates, and manual troubleshooting is triggered.

[0136] As can be seen, by using the above-mentioned address deployment method for charging modules, and by setting specific values ​​for the resistors corresponding to each DIP switch, the address of the charging module can correspond one-to-one with the state of the DIP switch. At the same time, the DIP circuit has high sampling accuracy. The main controller of the communication power supply equipment adjusts the address of the charging module based on the sampled voltage value, reducing the number of connection lines of the modules in the charging pile, improving the efficiency of address deployment, and improving the resource utilization of GPIO ports during address deployment.

[0137] The above mainly describes the solution of the embodiments of this application from the perspective of the method execution process. It is understood that, in order to achieve the above functions, the communication power supply device includes hardware structures and / or software modules corresponding to each function. The embodiments of this application can divide the communication power supply device into functional units based on the above method examples. For example, each function can be divided into separate functional units, or two or more functions can be integrated into one processing unit. The integrated unit can be implemented in hardware or as a software functional unit. It should be noted that the unit division in the embodiments of this application is illustrative and only represents one logical functional division; other division methods may be used in actual implementation.

[0138] When dividing each function into modules according to its corresponding function. Figure 8 This is a functional block diagram of an address deployment device for a charging module provided in an embodiment of this application. The address deployment device is applied to a communication power supply device. The communication power supply device includes a main controller, a charging module, a DIP switch address circuit disposed on the output terminal of the charging module, and a voltage sampling module in the main controller disposed on the output terminal of the DIP switch address circuit. The DIP switch address circuit is disposed on the backplane of the communication power supply device and includes multiple DIP switches and multiple DIP resistors. The address deployment device 800 for the charging module includes:

[0139] The acquisition unit 810 is used to acquire the sampled voltage output by the DIP switch address circuit through the voltage sampling module;

[0140] The calculation unit 820 is used to determine the theoretical voltage range corresponding to different on / off states of the plurality of DIP switches based on the sampled voltage, and obtain a plurality of theoretical voltage ranges.

[0141] The judgment unit 830 is used to determine whether the sampled voltage is within the target theoretical voltage range; the target theoretical voltage range is any one of the plurality of theoretical voltage ranges;

[0142] The conversion unit 840 is configured to: generate a first DIP address based on the sampled voltage if the sampled voltage is within the target theoretical voltage range; determine a compensation voltage based on the plurality of theoretical voltage ranges and the sampled voltage if the sampled voltage is not within the target theoretical voltage range; determine a target sampled voltage based on the compensation voltage and the sampled voltage; and generate a second DIP address based on the target sampled voltage.

[0143] Output unit 850; used to deploy the address of the charging module according to the first DIP switch address; and to deploy the address of the charging module according to the second DIP switch address.

[0144] In one possible embodiment, each of the plurality of DIP switches corresponds one-to-one with each of the plurality of DIP resistors, and the acquisition unit 810 is specifically used for: acquiring the sampling voltage output by the DIP address circuit.

[0145] Obtain the number of DIP switch bits in the DIP switch address circuit;

[0146] Obtain the resistance value of each of the multiple DIP resistors to obtain multiple resistance values;

[0147] Based on the preset charging module design address, the multiple resistance values, and the number of DIP switch bits, the voltage division relationship corresponding to the multiple DIP switch resistors is determined, and multiple voltage division relationships are obtained.

[0148] The sampling voltage signal is determined based on the multiple voltage division relationships, and the voltage in the DIP address circuit is sampled by the voltage sampling module based on the sampling voltage signal to obtain the sampling voltage.

[0149] In one possible embodiment, the acquisition unit 810, in determining the voltage division relationship corresponding to the plurality of DIP switch resistors based on the preset charging module design address, the plurality of resistance values, and the number of DIP switch bits, and obtaining the plurality of voltage division relationships, is specifically used for:

[0150] Obtain the topological connection of the plurality of DIP switches and the plurality of DIP resistors in the DIP address circuit;

[0151] The on / off state of the plurality of DIP switches is determined according to the design address of the charging module;

[0152] Based on the open / closed state, determine the resistors among the plurality of DIP resistors that participate in voltage division, and obtain the voltage dividing resistors;

[0153] The voltage divider voltage of the DIP switch address circuit is determined based on the topology connection and the voltage divider resistor.

[0154] The relationships corresponding to the voltage dividers are determined based on the mapping relationship between the voltage dividers in the preset DIP switch state and the design address under the charging module, thus obtaining the multiple voltage divider relationships.

[0155] In one possible embodiment, the DIP switch address circuit further includes a pull-up resistor, and the calculation unit 820, in determining the theoretical voltage ranges corresponding to different on / off states of the plurality of DIP switches based on the sampled voltage, and obtaining a plurality of theoretical voltage ranges, is specifically used for:

[0156] Obtain the set of open / closed state combinations of the plurality of DIP switches;

[0157] Based on the preset relationship between the DIP switch and the resistor, and the resistance value of the pull-up resistor, the theoretical voltage value corresponding to each open / closed state combination in the set of open / closed state combinations is calculated to obtain multiple theoretical voltage values.

[0158] The multiple theoretical voltage values ​​are sorted in ascending order to obtain a sequence of theoretical voltage values;

[0159] The median of any two adjacent theoretical voltage values ​​in the theoretical voltage value sequence is calculated to obtain the boundary value sequence.

[0160] Based on the boundary value sequence, the theoretical voltage range corresponding to each open / closed state combination in the open / closed state combination set is determined, thus obtaining the plurality of theoretical voltage ranges.

[0161] In one possible embodiment, the conversion unit 840, in generating the first DIP address based on the sampled voltage, is specifically configured to:

[0162] Obtain the theoretical voltage range numbers corresponding to the multiple theoretical voltage ranges;

[0163] The target theoretical voltage range number is obtained by determining the number corresponding to the target theoretical voltage range from the plurality of theoretical voltage range numbers;

[0164] The address code corresponding to the target theoretical voltage range number is determined based on the preset theoretical voltage range number and address mapping relationship;

[0165] The main controller generates an initial DIP switch address based on the address encoding.

[0166] The initial DIP switch address is format-verified using preset verification rules to obtain the verification result;

[0167] When the verification result indicates that the initial DIP switch address is correct, the initial DIP switch address is confirmed as the first DIP switch address.

[0168] In one possible embodiment, the conversion unit 840 is specifically configured to, in determining the compensation voltage based on the plurality of theoretical voltage ranges and the sampled voltage, as follows:

[0169] Determine the upper and lower limits of each theoretical voltage range among the plurality of theoretical voltage ranges to obtain a plurality of upper and lower limits; each upper limit of the plurality of upper limits corresponds one-to-one with each lower limit of the plurality of lower limits.

[0170] Calculate the difference between the upper limits and lower limits of the multiple intervals to obtain multiple differences;

[0171] The multiple differences are fitted according to a preset fitting algorithm to obtain a fitting curve;

[0172] The compensation voltage range corresponding to the target theoretical voltage range is determined based on the fitted curve;

[0173] The compensation voltage is determined based on the compensation voltage range.

[0174] In one possible embodiment, each of the plurality of DIP resistors is connected in series, and each of the plurality of DIP switches is connected in parallel with a DIP resistor; the communication power supply device further includes an electrical isolation circuit, the output of which is connected to the main controller, and the acquisition unit 810, before acquiring the sampling voltage output by the DIP address circuit through the voltage sampling module, is specifically used for:

[0175] Obtain calibration variables; the calibration variables are used to represent the calibration status of the main controller;

[0176] When the calibration variable is zero, the sampling channel of the voltage sampling module is obtained;

[0177] The sampling accuracy is determined based on the plurality of DIP resistors and the sampling channel;

[0178] The sampling parameters of the voltage sampling module are determined according to the sampling accuracy, and the DIP switch address circuit is sampled to obtain the first sampling signal;

[0179] The first sampling signal output by the DIP switch address circuit is electrically isolated by the electrical isolation circuit to obtain an isolated sampling signal;

[0180] The isolation sampling signal is sent to the voltage sampling module to control the voltage sampling module to perform voltage sampling on the DIP address circuit according to the isolation sampling signal.

[0181] It should be noted that the specific functional implementation of the address deployment device 800 for the charging module is described above. Figure 3 The description of an address deployment method for a charging module, for example, the determination unit 830 is used to implement the relevant content of S330, which will not be repeated here. Each unit or module in the address deployment device 800 of the charging module can be individually or entirely merged into one or more other units or modules, or some of the units or modules can be further divided into multiple functionally smaller units or modules. This achieves the same operation without affecting the technical effect of the embodiments of the present invention. The above-mentioned units or modules are based on logical function division. In practical applications, the function of one unit (or module) is implemented by multiple units (or modules), or the function of multiple units (or modules) is implemented by one unit (or module).

[0182] It can be seen that by implementing the address deployment device for a charging module provided in the embodiments of this application, the address deployment efficiency of the power module when operating in parallel and the resource utilization of GPIO ports during address deployment can be improved.

[0183] This application also provides an address deployment system for a charging module, which performs some or all of the steps of any of the methods described in the above method embodiments.

[0184] This application also provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program operable to cause a computer to perform some or all of the steps of any of the methods described in the above method embodiments. The computer program product may be a software installation package, and the computer includes a communication power supply device.

[0185] It should be noted that, for the sake of simplicity, the above embodiments are all described as a series of actions. Those skilled in the art should understand that this application is not limited to the described order of actions, as some steps in the embodiments of this application can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions, steps, modules, or units involved are not necessarily essential to the embodiments of this application.

[0186] In the above embodiments, the descriptions of each embodiment in this application have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0187] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. This program can be stored in a computer-readable storage medium, and when executed, it can include the processes described in the above method embodiments. The aforementioned storage medium includes various media capable of storing program code, such as ROM or random access memory (RAM), magnetic disks, or optical disks.

[0188] The steps of the methods or algorithms described in the embodiments of this application can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in RAM, flash memory, ROM, EPROM, electrically erasable programmable read-only memory (EEPROM), registers, hard disk, portable hard disk, read-only optical disk (CD-ROM), or any other form of storage medium well known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium.

[0189] Those skilled in the art will recognize that, in one or more of the examples above, the functions described in the embodiments of this application can be implemented, in whole or in part, by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented, in whole or in part, in the form of a computer program product. This computer program product includes one or more computer instructions. When these computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another. The various modules / units included in the devices and products described in the above embodiments can be software modules / units, hardware modules / units, or a combination of both.

[0190] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the embodiments of this application. It should be understood that the above descriptions are merely specific embodiments of the embodiments of this application and are not intended to limit the protection scope of the embodiments of this application. Any modifications, equivalent substitutions, improvements, etc., made on the basis of the technical solutions of the embodiments of this application should be included within the protection scope of the embodiments of this application.

Claims

1. A method for address deployment of a charging module, characterized in that, The method is applied to the main controller of a communication power supply device. The communication power supply device includes a charging module, a DIP switch address circuit disposed on the output terminal of the charging module, and a voltage sampling module in the main controller disposed on the output terminal of the DIP switch address circuit. The DIP switch address circuit is disposed on the backplane of the communication power supply device, and the DIP switch address circuit includes multiple DIP switches and multiple DIP resistors. The method includes: The voltage sampling module obtains the sampling voltage output by the DIP switch address circuit; Based on the sampled voltage, the theoretical voltage ranges corresponding to different on / off states of the multiple DIP switches are determined, resulting in multiple theoretical voltage ranges. Determine whether the sampled voltage is within the target theoretical voltage range; the target theoretical voltage range is any one of the plurality of theoretical voltage ranges; If the sampled voltage is within the target theoretical voltage range, then a first DIP address is generated based on the sampled voltage; and the address of the charging module is deployed based on the first DIP address. If the sampled voltage is not within the target theoretical voltage range, then a compensation voltage is determined based on the plurality of theoretical voltage ranges and the sampled voltage; a target sampled voltage is determined based on the compensation voltage and the sampled voltage; a second DIP address is generated based on the target sampled voltage, and the address of the charging module is deployed based on the second DIP address.

2. The method as described in claim 1, characterized in that, Each of the plurality of DIP switches corresponds one-to-one with each of the plurality of DIP resistors, and obtaining the sampling voltage output by the DIP address circuit includes: Obtain the number of DIP switch bits in the DIP switch address circuit; Obtain the resistance value of each of the multiple DIP resistors to obtain multiple resistance values; Based on the preset charging module design address, the multiple resistance values, and the number of DIP switch bits, the voltage division relationship corresponding to the multiple DIP switch resistors is determined, and multiple voltage division relationships are obtained. The sampling voltage signal is determined based on the multiple voltage division relationships, and the voltage in the DIP address circuit is sampled by the voltage sampling module based on the sampling voltage signal to obtain the sampling voltage.

3. The method as described in claim 2, characterized in that, The voltage division relationship corresponding to the multiple DIP switch resistors is determined based on the preset charging module design address, the multiple resistance values, and the number of DIP switch bits, resulting in multiple voltage division relationships, including: Obtain the topological connection of the plurality of DIP switches and the plurality of DIP resistors in the DIP address circuit; The on / off state of the plurality of DIP switches is determined according to the design address of the charging module; Based on the open / closed state, determine the resistors among the plurality of DIP resistors that participate in voltage division, and obtain the voltage dividing resistors; The voltage divider voltage of the DIP switch address circuit is determined based on the topology connection and the voltage divider resistor. The relationships corresponding to the voltage dividers are determined based on the mapping relationship between the voltage dividers in the preset DIP switch state and the design address under the charging module, thus obtaining the multiple voltage divider relationships.

4. The method as described in claim 1, characterized in that, The DIP switch address circuit further includes pull-up resistors. The theoretical voltage ranges corresponding to different on / off states of the multiple DIP switches are determined based on the sampled voltage, resulting in multiple theoretical voltage ranges, including: Obtain the set of on / off state combinations of the plurality of DIP switches; Based on the preset relationship between the DIP switch and the resistor, and the resistance value of the pull-up resistor, the theoretical voltage value corresponding to each open / closed state combination in the set of open / closed state combinations is calculated to obtain multiple theoretical voltage values. The multiple theoretical voltage values ​​are sorted in ascending order to obtain a sequence of theoretical voltage values; The median of any two adjacent theoretical voltage values ​​in the theoretical voltage value sequence is calculated to obtain the boundary value sequence. Based on the boundary value sequence, the theoretical voltage range corresponding to each open / closed state combination in the open / closed state combination set is determined, thus obtaining the plurality of theoretical voltage ranges.

5. The method according to any one of claims 1-4, characterized in that, The step of generating the first DIP address based on the sampled voltage includes: Obtain the theoretical voltage range numbers corresponding to the multiple theoretical voltage ranges; The target theoretical voltage interval number is obtained by determining the corresponding number of the target theoretical voltage interval from the plurality of theoretical voltage interval numbers; The address code corresponding to the target theoretical voltage range number is determined based on the preset theoretical voltage range number and address mapping relationship; The main controller generates an initial DIP switch address based on the address encoding. The initial DIP switch address is format-verified using preset verification rules to obtain the verification result; When the verification result indicates that the initial DIP switch address is correct, the initial DIP switch address is confirmed as the first DIP switch address.

6. The method according to any one of claims 1-4, characterized in that, The step of determining the compensation voltage based on the plurality of theoretical voltage ranges and the sampled voltage includes: Determine the upper and lower limits of each theoretical voltage range among the plurality of theoretical voltage ranges to obtain a plurality of upper and lower limits; each upper limit of the plurality of upper limits corresponds one-to-one with each lower limit of the plurality of lower limits. Calculate the difference between the upper limits and lower limits of the multiple intervals to obtain multiple differences; The multiple differences are fitted according to a preset fitting algorithm to obtain a fitting curve; The compensation voltage range corresponding to the target theoretical voltage range is determined based on the fitted curve; The compensation voltage is determined based on the compensation voltage range.

7. The method as described in claim 1, characterized in that, Each of the plurality of DIP resistors is connected in series, and each of the plurality of DIP switches is connected in parallel with a DIP resistor; the communication power supply device further includes an electrical isolation circuit, the output of which is connected to the main controller. Before obtaining the sampled voltage output by the DIP address circuit through the voltage sampling module, the method further includes: Obtain calibration variables; the calibration variables are used to represent the calibration status of the main controller; When the calibration variable is zero, the sampling channel of the voltage sampling module is obtained; The sampling accuracy is determined based on the plurality of DIP resistors and the sampling channel; The sampling parameters of the voltage sampling module are determined according to the sampling accuracy, and the DIP switch address circuit is sampled to obtain the first sampling signal; The first sampling signal output by the DIP switch address circuit is electrically isolated by the electrical isolation circuit to obtain an isolated sampling signal; The isolation sampling signal is sent to the voltage sampling module to control the voltage sampling module to perform voltage sampling on the DIP address circuit according to the isolation sampling signal.

8. An address deployment device for a charging module, characterized in that, An application is made in communication power supply equipment, the communication power supply equipment including a main controller, a charging module, a DIP switch address circuit disposed on the output terminal of the charging module, a voltage sampling module in the main controller disposed on the output terminal of the DIP switch address circuit, the DIP switch address circuit being disposed on the backplane of the communication power supply equipment, the DIP switch address circuit including multiple DIP switches and multiple DIP resistors, the device comprising: The acquisition unit is used to acquire the sampled voltage output by the DIP switch address circuit through the voltage sampling module; The calculation unit is used to determine the theoretical voltage range corresponding to different on / off states of the plurality of DIP switches based on the sampled voltage, and obtain a plurality of theoretical voltage ranges. A judgment unit is used to determine whether the sampled voltage is within the target theoretical voltage range; the target theoretical voltage range is any one of the plurality of theoretical voltage ranges; The conversion unit is configured to: generate a first DIP address based on the sampled voltage if the sampled voltage is within the target theoretical voltage range; determine a compensation voltage based on the plurality of theoretical voltage ranges and the sampled voltage if the sampled voltage is not within the target theoretical voltage range; determine a target sampled voltage based on the compensation voltage and the sampled voltage; and generate a second DIP address based on the target sampled voltage. Output unit; used to deploy the address of the charging module according to the first DIP switch address; and to deploy the address of the charging module according to the second DIP switch address.

9. A communication power supply device, characterized in that, include: Processor, memory, communication interface, and one or more programs; The one or more programs are stored in the memory and configured to be executed by the processor, the programs including instructions for performing the steps of the method as described in any one of claims 1-7.

10. An address deployment system for a charging module, characterized in that, The address deployment system of the charging module performs the method as described in any one of claims 1-7.

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