Semiconductor device, chip, and electronic apparatus

Abstract

The invention provides a semiconductor device, a chip and electronic equipment, relates to the technical field of semiconductor chips, and aims to solve the problem of dynamic on-resistance degradation of the semiconductor device. The semiconductor structure comprises a substrate, a nucleating layer, a buffer layer and a channel layer which are sequentially stacked, wherein the buffer layer comprises a first buffer layer, the material of the first buffer layer comprises Al < x > Ga < 1-x > N, x is smaller than or equal to 1, and the concentration of carbon in the first buffer layer is smaller than or equal to 5 * 10 < 17 > cm <-3 >.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor chips, and particularly relates to a semiconductor device, a chip and an electronic device. BACKGROUND

[0002] GaN material has advantages of large band gap and high electron mobility, and has strong application advantages in the field of high-frequency and high-power power electronic devices.

[0003] In a semiconductor device using GaN material, when the semiconductor device is in an off state, carbon elements in the region between the channel layer and the substrate of the semiconductor device form trap states to capture electrons to form a back gate effect. When the semiconductor device switches from the off state to the on state at a faster speed, the electrons captured by the carbon elements fail to be released or neutralized in time, which causes the net negative charge in the region to repel the two-dimensional electron gas in the channel, resulting in a decrease in the electron concentration in the channel and an increase in the on-resistance, that is, dynamic on-resistance degradation occurs. SUMMARY

[0004] Embodiments of the present disclosure provide a semiconductor device, a chip and an electronic device, aiming to solve the problem of dynamic on-resistance degradation of the semiconductor device.

[0005] To achieve the above-mentioned purpose, embodiments of the present disclosure adopt the following technical solutions: In one aspect, a semiconductor device is provided. The semiconductor device comprises: a substrate, a nucleation layer, a buffer layer and a channel layer which are sequentially stacked. The buffer layer comprises: a first buffer layer, the material of the first buffer layer comprises: Al x Ga 1-x N, x≤1, and the concentration of carbon elements in the first buffer layer is less than or equal to 5×10 17 cm -3 .

[0006] The semiconductor device provided by the above-mentioned embodiments of the present disclosure controls the concentration of carbon elements to be less than or equal to 5×10 17 cm -3 , so that the concentration of carbon elements is low, the number of captured electrons when the semiconductor device is in an off state can be reduced, thereby reducing the repelling effect of the accumulation of negative charges on the 2DEG (two-dimensional electron gas) in the channel region during the switching process of the semiconductor device 100 from the off state to the on state, so that the electron concentration in the channel remains stable, thereby reducing the influence on the resistance in the channel layer, so that the semiconductor device can be immune to the problem of dynamic on-resistance degradation caused by carbon elements in the buffer layer.

[0007] In some embodiments, the buffer layer further includes at least one second buffer layer. The at least one second buffer layer is disposed between the first buffer layer and the nucleation layer. The material of the second buffer layer includes: Al. y Ga 1-y N, y < x, and the carbon concentration in the second buffer layer is greater than 5 × 10⁻⁶. 17 cm -3 .

[0008] In some embodiments, the buffer layer includes at least two second buffer layers stacked along a first direction, which is the thickness direction of the semiconductor device. Of any two adjacent second buffer layers, the second buffer layer farther from the nucleation layer is a first buffer sublayer, and the second buffer layer closer to the nucleation layer is a second buffer sublayer. The material of the first buffer sublayer includes: Al. y1 Ga 1-y1 N, the second buffer sublayer material includes: Al y2 Ga 1-y2 N; and y1≥y2.

[0009] In some embodiments, the buffer layer includes two second buffer layers. The material of the second buffer layer relatively farthest from the channel layer includes: Al. 0.5 Ga 0.5 N, the material of the second buffer layer relatively close to the channel layer includes: Al 0.75 Ga 0.25 N.

[0010] In some embodiments, the concentration of carbon in the second buffer layer ranges from 1 × 10⁻⁶. 18 cm -3 ~1×10 20 cm -3 .

[0011] In some embodiments, the semiconductor device further includes: a barrier layer, a capping layer, a source, a drain, and a gate, disposed on the side of the channel layer away from the buffer layer; the barrier layer is disposed on the side of the channel layer away from the substrate; the capping layer is disposed on the side of the barrier layer away from the channel layer; the gate is disposed between the source and the drain, and the gate is disposed on the side of the capping layer away from the substrate, and the source and drain are disposed on the side of the barrier layer or the channel layer away from the substrate.

[0012] In some embodiments, the material of the channel layer includes GaN.

[0013] In some embodiments, the barrier layer material includes Al z Ga 1-z N, 0 < z ≤ 1.

[0014] On the other hand, a chip is provided. The chip includes: a semiconductor device.

[0015] On the other hand, an electronic device is provided. This electronic device includes: a chip.

[0016] It is understood that the beneficial effects of the chips and electronic devices provided in the above embodiments of this disclosure can be referred to the beneficial effects of the semiconductor devices described above, and will not be repeated here. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0018] Figure 1 A schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure; Figure 2 A schematic diagram of the structure of a semiconductor device provided according to an embodiment of the present disclosure; Figure 3 A schematic diagram of the structure of a semiconductor device provided according to an embodiment of the present disclosure; Figure 4 This is a flowchart illustrating a method for fabricating a semiconductor device according to embodiments of the present disclosure. Detailed Implementation

[0019] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0020] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0021] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0022] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0023] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0024] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0025] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0026] As used herein, the term "substrate" refers to a material on which subsequent layers of material can be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire substrate.

[0027] The technical terms used in the embodiments of this disclosure are explained below: Semiconductor: A semiconductor is a material whose conductivity at room temperature is between that of a conductor and an insulator; semiconductors include intrinsic semiconductors and impurity semiconductors. A pure semiconductor without impurities or defects, in which the concentration of electrons and holes is equal, is called an intrinsic semiconductor. A semiconductor doped with a certain amount of impurities is called an impurity semiconductor or an intrinsic semiconductor. Among them, when the impurities doped into an impurity semiconductor can provide a certain concentration of charge carriers (such as holes or electrons), the conductivity of the intrinsic semiconductor can be improved. Generally, the higher the charge carrier concentration, the lower the resistivity of the semiconductor and the better the conductivity. In the embodiments of this disclosure, this type of impurity semiconductor is also called a conductive semiconductor, for example, a conductive silicon carbide material doped with impurities such as nitrogen (N), boron (B), and aluminum (Al). Furthermore, when impurities doped into an impurity semiconductor can compensate for impurities, the donor electrons are just enough to fill the acceptor level, but cannot provide electrons and holes to the conduction and valence bands, resulting in a semiconductor material with a wide bandgap having a resistivity similar to that of an insulator. For example, in the embodiments of this disclosure, doping silicon carbide with transition metals achieves impurity compensation, thereby increasing the resistivity of the silicon carbide material. This type of impurity semiconductor is also called a semi-insulating semiconductor or a semi-insulator, or has semi-insulating characteristics.

[0028] Furthermore, in this disclosure, directional terms such as "upper" and "lower" are defined relative to the indicated placement of the components in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the placement of the components in the accompanying drawings.

[0029] It should be noted that in this disclosure, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this disclosure should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0030] The technical solutions disclosed herein can be applied to electronic devices, including various types of user equipment or terminal devices such as computers, mobile phones, tablets, wearable devices, and vehicle-mounted devices; these electronic devices can also be network equipment such as base stations. The electronic devices can also be devices such as power amplifiers used in the aforementioned electronic devices. The embodiments of this disclosure do not impose any special limitations on the specific form of the aforementioned electronic devices.

[0031] likeFigure 1 As shown, embodiments of this disclosure provide an electronic device 1000. This electronic device 1000 can be a fast charger, an uninterruptible power supply (UPS), a power motor, or other electronic equipment.

[0032] Continue to refer to Figure 1 The electronic device 1000 includes a chip 1001 and a circuit board 1002. The chip 1001 and the circuit board 1002 are electrically connected. The circuit board 1002 converts the external power supply into the voltage or current required for the chip 1001 to operate.

[0033] For example, circuit board 1002 may include a printed circuit board (PCB) or the like.

[0034] For example, circuit board 1002 may include multiple conductive layers. The multiple conductive layers within circuit board 1002 may be separated from each other by dielectric layers.

[0035] The aforementioned chip 1001 includes semiconductor devices.

[0036] The above-mentioned semiconductor devices will be described in detail below.

[0037] Gallium nitride (GaN) materials possess advantages such as a large bandgap and high electron mobility, making them highly advantageous for applications in high-frequency, high-power power electronic devices. GaN films can be formed on Si substrates, offering advantages such as large size, low cost, and compatibility with Complementary Metal-Ooxide-Semiconductor (CMOS) processes.

[0038] like Figure 2 The semiconductor device 100 shown includes a substrate 101, a nucleation layer 102, and a channel layer 103. The substrate 101, the nucleation layer 102, and the channel layer 103 are stacked sequentially.

[0039] In some examples, the semiconductor device 100 further includes a barrier layer 104. The barrier layer 104 is disposed on the side of the channel layer 103 away from the substrate 101.

[0040] In some examples, a capping layer 105 is introduced between the barrier layer 104 and the gate 108 to realize an enhancement-mode semiconductor device 100. Therefore, the semiconductor device 100 further includes a capping layer 105, a source 106, a drain 107, and a gate 108. The capping layer 105 is disposed on the side of the barrier layer 104 away from the channel layer 103. The gate 108 is disposed between the source 106 and the drain 107, and the gate 108 is disposed on the side of the capping layer 105 away from the substrate 101. The source 106 and the drain 107 are disposed on the side of the barrier layer 104 or the channel layer 103 away from the substrate 101.

[0041] That is, the channel layer 103 and the barrier layer 104 are sequentially stacked on the substrate 101. The capping layer 105 is disposed on the side of the barrier layer 104 away from the channel layer 103. The gate 108 is disposed on the side of the capping layer 105 away from the substrate 101, and the source 106 and the drain 107 are disposed on both sides of the capping layer 105 along the second direction X and are in contact with the barrier layer 104. The second direction X is perpendicular to the thickness direction of the substrate 101.

[0042] For example, the source 106 and the drain 107 may be disposed on the side of the barrier layer 104 away from the substrate 101.

[0043] For example, the source 106 and the drain 107 may be located on the side of the channel layer 103 away from the substrate 101.

[0044] Substrate 101 is the basis of semiconductor device 100, and substrate 101 provides physical and electrical support.

[0045] For example, the substrate 101 can be a Si substrate, a SiC substrate, a sapphire substrate, etc.

[0046] The nucleation layer 102 provides an initial region for crystal nuclei, promotes uniform orientation and growth rate of grains, and controls grain size and crystal quality of the film.

[0047] For example, the thickness of the nucleation layer 102 can be 10nm to 2μm, such as 10nm, 200nm, 300nm, 500nm, 700nm, 1000nm, 1200nm, 1500nm, 170nm or 2000nm, etc.

[0048] The source 106 and drain 107 are electrodes of the semiconductor device 100, and voltage can be applied to regulate the flow of charge carriers in the channel layer 103.

[0049] For example, the material of the source electrode 106 can be Ti, Al, Cu, TiN, etc.

[0050] For example, the material of the drain electrode 107 can be Ti, Al, Cu, TiN, etc.

[0051] The gate 108 is used to control the flow of charge carriers at the heterojunction interface between the channel layer 103 and the barrier layer 104. When a voltage is applied, a channel for boosting electrons or holes is formed in the channel layer 103, thereby realizing the switching function of the semiconductor device 100.

[0052] For example, the material of the channel layer 103 can be GaN.

[0053] For example, the thickness of the channel layer 103 can be 30nm to 500nm, such as 30nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 150nm or 500nm.

[0054] For example, the material of gate 108 can be one or more of Ti, TiN, Al, Ni, and Au. The material of gate 108 can also be Mg-doped, with a Mg doping concentration of 1 × 10⁻⁶. 18 cm -3 ~1×10 20 cm -3 .

[0055] For example, the thickness of the gate 108 can be 30nm~200nm, such as 30nm, 50nm, 70nm, 90nm, 100nm, 130nm, 150nm, 170nm, 190nm or 200nm.

[0056] The material of barrier layer 104 can be Al z Ga 1-z N, 0 <z≤1,Al z Ga 1-z Nitrogen (N) is an ultra-wide bandgap semiconductor material that combines the advantages of AlN (aluminum nitride) and GaN, such as good chemical stability, extremely high melting point, high thermal conductivity, hard texture, and high luminous efficiency.

[0057] The band gap of the barrier layer 104 is larger than that of the channel layer 103, which allows the barrier layer 104 and the channel layer 103 to form a heterojunction structure, such as in an AlGaN / GaN heterostructure. The polarization charge of the material of the barrier layer 104 (such as AlGaN) (generated by the polarization difference of the material) causes a large electric field, which causes electrons to accumulate near the interface between the channel layer 103 and the barrier layer 104 to form a two-dimensional electron gas. The source electrode 106 and the drain electrode 107 can form an ohmic contact with the 2DEG.

[0058] For example, the thickness of the barrier layer 104 can be 3nm to 50nm, such as 3nm, 10nm, 20nm, 30nm, 40nm or 50nm.

[0059] The capping layer 105 generates a positive charge through p-type doping, which can reduce the 2DEG concentration in the channel layer 103, so that the semiconductor device 100 is in the off state when there is no bias voltage.

[0060] For example, the capping layer 105 can be a Mg-doped p-GaN layer with a Mg concentration ranging from 5 × 10⁻⁶. 18 cm -3 ~1×10 20 cm -3 .

[0061] For example, the thickness of the capping layer 105 can be 30nm to 200nm, such as 30nm, 50nm, 70nm, 90nm, 110nm, 130nm, 150nm, 170nm, 190nm or 200nm.

[0062] In some examples, the side of the barrier layer 104 away from the substrate 101 also includes a dielectric layer, which can effectively protect the surface of the semiconductor device 100, prevent environmental factors (such as oxygen and moisture) from affecting the semiconductor device 100, and reduce the impact of surface defects and impurities, thereby improving the stability and long-term reliability of the semiconductor device 100.

[0063] The following description refers to a semiconductor device 100 with source 106 and drain 107 disposed on the side of barrier layer 104 away from substrate 101. The same applies to a semiconductor device 100 with source 106 and drain 107 disposed on the side of channel layer 103 away from substrate 101.

[0064] In some implementations, due to the remelting etching effect of Ga atoms on the substrate 101 (such as Si), the GaN material of the channel layer 103 cannot be directly deposited on the substrate 101. Instead, a nucleation layer 102 (which can be made of AlN) is used as an intermediate layer for transition. Furthermore, because there is also a lattice mismatch between the nucleation layer 102 and the channel layer 103, a buffer layer 109 is typically placed between them to reduce stress, ensure lattice matching between the materials of the nucleation layer 102 and the channel layer 103, reduce thermal stress and physical strain caused by temperature changes, and thus reduce defect formation.

[0065] To reduce longitudinal leakage current and improve the withstand voltage performance of semiconductor device 100, carbon doping is performed in buffer layer 109 to make it semi-insulated. However, when semiconductor device 100 is in the off state, the drain 107 side of semiconductor device 100 will be subjected to a high voltage, and electrons will enter buffer layer 109 under the action of high voltage. At this time, the carbon elements in buffer layer 109 will form a trap state to capture electrons and form a back gate effect. When semiconductor device 100 switches from the off state to the on state at a relatively fast speed, the electrons captured by the carbon elements in buffer layer 109 may not be released or neutralized in time. This will cause the net negative charge in buffer layer 109 to repel the two-dimensional electron gas in the channel, resulting in a decrease in electron concentration in the channel and an increase in on resistance, i.e., dynamic on resistance degradation.

[0066] Based on this, embodiments of the present disclosure provide a semiconductor device 100. For example... Figure 3 As shown, the semiconductor device 100 includes a substrate 101, a nucleation layer 102, a buffer layer 109 and a channel layer 103 stacked sequentially.

[0067] Here, the configuration and description of the substrate 101, nucleation layer 102 and channel layer 103 are consistent with those in the above text, and will not be repeated here.

[0068] The buffer layer 109 includes a first buffer layer 91, the material of which includes Al. x Ga 1-x N, x≤1, and the concentration of carbon in the first buffer layer 91 is less than or equal to 5×10 17 cm -3 .

[0069] For example, the carbon concentration in the first buffer layer 91 can be 1×10⁻⁶. 17 cm -3 2×10 17 cm -3 3×10 17 cm -3 4×10 17 cm -3 Or 5×10 17 cm -3 There are no restrictions here.

[0070] Understandably, the concentration of the element should be controlled to be less than or equal to 5 × 10⁻⁶. 17 cm -3This results in a lower concentration of carbon, which reduces the number of electrons trapped when the semiconductor device 100 is in the off state. This reduces the negative charge accumulation during the switching process between the off and on states of the semiconductor device 100, thus reducing the repulsive effect on the 2DEG in the channel region. This keeps the electron concentration in the channel stable, thereby reducing the impact on the resistance in the channel layer 103. This allows the semiconductor device 100 to be protected from the degradation of on-resistance caused by the carbon in the buffer layer 109.

[0071] In some implementations, such as Figure 2 As shown, along the direction from the nucleation layer 102 to the channel layer 103, the Al content of the buffer layer 109 gradually decreases. This generates a negative polarization charge between two adjacent second buffer layers 92. When the semiconductor device 100 is in the off state, the carbon elements in the buffer layer 109 trap electrons. When the semiconductor device 100 switches from the off state to the on state, the electrons trapped by the carbon elements are not released in time. At this time, the net negative charge in the buffer layer 109 repels the two-dimensional electron gas in the channel, causing a decrease in the electron concentration in the channel, an increase in resistance, and a poor effect of the back barrier. Furthermore, when the gate 108 of the semiconductor device 100 is small, the gate control capability of the semiconductor device 100 weakens due to the short-channel effect, and punch-through may still occur in the off state.

[0072] In some embodiments, the buffer layer further includes at least one second buffer layer 92. The at least one second buffer layer 92 is disposed between the first buffer layer 91 and the nucleation layer 102. The material of the second buffer layer 92 includes: Al. y Ga 1-y N, y < x, and the carbon concentration in the second buffer layer 92 is greater than 5 × 10⁻⁶. 17 cm -3 .

[0073] For example, the carbon concentration in the second buffer layer 92 can be 6 × 10⁻⁶. 17 cm -3 7×10 17 cm -3 8×10 17 cm -3 9×10 17 cm -3 Or 1×10 18 cm -3 There are no restrictions here.

[0074] Understandably, the above setup, firstly, relies on the carbon concentration in the second buffer layer 92 being greater than 5 × 10⁻⁶. 17 cm -3It can be seen that the carbon concentration in the second buffer layer 92 is greater than that in the first buffer layer 91, which can maintain the semi-insulating properties of the buffer layer 109. This allows the second buffer layer 92 to form an impedance region between the channel layer 103 and the nucleation layer 102, thereby increasing the resistivity. This helps to avoid leakage coupling, reduce the risk of leakage penetration of the semiconductor device 100, and thus helps to control the punch-through current and dynamic on-resistance degradation.

[0075] Secondly, since y < x, it can be seen that the Al content in the material of the second buffer layer 92 is less than the Al content in the material of the first buffer layer 91, which can generate a positive polarization charge between the first buffer layer 91 and the second buffer layer 92. On the one hand, when the semiconductor device 100 switches from the off state to the on state, the electrons captured by the carbon element in the second buffer layer 92 will be shielded by the positive polarization charge generated between the first buffer layer 91 and the second buffer layer 92, neutralizing the repulsion of the negative charge on the channel 2DEG, thereby suppressing the degradation of the on-resistance. On the other hand, since the material of the first buffer layer 91 is Al x Ga 1-x The bandgap of GaN relative to the channel layer 103 is larger, and the Al content of the first buffer layer 91, which is in direct contact with the channel layer 103, is higher than that of the second buffer layer 92. This allows for the formation of a larger bandgap in the conduction band, resulting in a stronger polarization effect. This can act as a back barrier to effectively confine the 2DEG at the channel, suppressing the short-channel effect of the semiconductor device 100 and reducing the punch-through effect.

[0076] In other words, while the carbon concentration in the first buffer layer 91 is lower than that in the second buffer layer 92, the Al content in the material of the first buffer layer 91 is higher than that in the material of the second buffer layer 92. This makes it easier to form high resistance, making it difficult for carbon to ionize, thus effectively suppressing the short-channel effect of the semiconductor device 100.

[0077] In some embodiments, the buffer layer 109 includes at least two second buffer layers 92 stacked along a first direction Y, where Y is the thickness direction of the semiconductor device 100. Of any two adjacent second buffer layers 92, the second buffer layer 92 farther from the nucleation layer 102 is a first buffer sub-layer 921, and the second buffer layer 92 closer to the nucleation layer 102 is a second buffer sub-layer 922. The material of the first buffer sub-layer 921 includes: Al. y1 Ga 1-y1 N, the second buffer sublayer 922 material includes: Al y2 Ga 1-y2 N; and y1≥y2.

[0078] For example, in the case where the buffer layer 109 includes two second buffer layers 92. The material of the second buffer layer 92 that is relatively far from the channel layer 103 includes: Al. 0.5 Ga 0.5 N, the material of the second buffer layer 92, which is relatively close to the channel layer 103, includes: Al 0.75 Ga 0.25 N.

[0079] Understandably, as can be seen from the above configuration, the Al content of the buffer layer 109 gradually increases along the direction from the nucleation layer 102 to the channel layer 103. As a result, a positive polarization charge can be generated between two adjacent second buffer layers 92. Therefore, when the semiconductor device 100 switches from the off state to the on state, the electrons captured by the carbon elements in the second buffer layer 92 will be further shielded by the positive polarization charge generated between the second buffer layer 92 and the second buffer layer 92, neutralizing the repulsion of the negative charge on the channel 2DEG, thereby suppressing the degradation of the on-resistance. Similarly, when the buffer layer 109 includes three or more second buffer layers 92, the positive polarization charge generated between two adjacent second buffer layers 92 can shield the electrons captured by the carbon elements in one of the second buffer layers 92, neutralizing the repulsion of the negative charge on the channel 2DEG, thereby suppressing the degradation of the on-resistance.

[0080] In summary, in the semiconductor device 100 disclosed herein, such as Figure 3 As shown, along the direction from the nucleation layer 102 to the channel layer 103, the Al content of the buffer layer 109 gradually increases. As a result, a positive polarization charge can be generated between two adjacent buffer layers 109. Therefore, when the semiconductor device 100 switches from the off state to the on state, the electrons captured by the carbon element in the second buffer layer 92 are shielded by the positive polarization charge generated between the two adjacent buffer layers 109, neutralizing the repulsion of the negative charge on the channel 2DEG, thereby suppressing the degradation of the on-resistance.

[0081] In some embodiments, the carbon concentration in the second buffer layer 92 ranges from 1 × 10⁻⁶. 18 cm -3 ~1×10 20 cm -3 .

[0082] For example, the carbon concentration in the second buffer layer 92 can be 1×10⁻⁶. 18 cm -3 5×10 18 cm -3 1×10 19 cm -3 5×10 19 cm -3 Or 1×1020 cm -3 There are no restrictions here.

[0083] Understandably, as can be seen from the above settings, the semi-insulating properties of the buffer layer 109 can be maintained, so that the second buffer layer 92 forms an impedance region between the channel layer 103 and the nucleation layer 102, thereby increasing the resistivity, which helps to avoid leakage coupling, reduce the risk of leakage penetration of the semiconductor device 100, and thus helps to control the punch-through current and dynamic on-resistance degradation.

[0084] In some embodiments, such as Figure 4 As shown, the method for fabricating the semiconductor device 100 includes: S1~S7.

[0085] S1: A nucleation layer 102 is formed on the substrate 101.

[0086] For example, the material for the nucleation layer 102 is deposited by metal-organic chemical vapor deposition (MOCVD), such as using trimethylaluminum and ammonia as precursors and hydrogen as carrier gas, at a growth temperature of 700°C to 1250°C, a pressure of 30 mbar to 400 mbar, and a 5:3 ratio (molar ratio between group III and group V elements) of 50 to 5000, to form an AlN nucleation layer 102 with a thickness ranging from 100 nm to 2 μm.

[0087] Here, the nucleation layer 102 can be carbon-doped or not; in the case of carbon doping, the carbon concentration is less than 1 × 10⁻⁶. 20 cm -3 .

[0088] In addition, the nucleation layer 102 can also be formed by methods including but not limited to molecular beam epitaxy (MBE) and physical vapor deposition (PVD).

[0089] S2: A buffer layer 109 is formed on the side of the nucleation layer 102 away from the substrate 101.

[0090] For example, the buffer layer 109 is at least two layers of AlGaN with different compositions or combinations thereof.

[0091] For example, S2 includes: first depositing an Al layer on the side of the nucleation layer 102 away from the substrate 101. 0.5 Ga 0.5 N, thickness 0.5nm~500nm, carbon doping concentration 1×10 18 ~1×1020 cm -3 Then, in Al 0.5 Ga 0.5 Al is deposited on the side of N away from substrate 101. 0.75 Ga 0.25 N, thickness 0.5nm~500nm, carbon doping concentration 1×10 18 cm -3 ~1×10 20 cm -3 Finally in Al 0.75 Ga 0.25 AlN is deposited on the side of N away from substrate 101, with a thickness of 100 nm to 1 μm and a carbon doping concentration of less than or equal to 5 × 10⁻⁶. 17 cm -3 .

[0092] S3: A channel layer 103 is formed on the side of the buffer layer 109 away from the substrate 101.

[0093] For example, using trimethylgallium and ammonia as precursors and hydrogen as carrier gas, a GaN channel layer 103 with a thickness ranging from 30 nm to 500 nm (most preferably 100 nm to 300 nm) is formed at a growth temperature of 950 °C to 1100 °C, a pressure of 100 mbar to 400 mbar, and a 5:3 ratio of 500 to 15000 (optimally 2000 to 10000).

[0094] S4: A barrier layer 104 is formed on the side of the channel layer 103 away from the substrate 101.

[0095] For example, an InAlGaN barrier layer 104 is stacked on the side of the channel layer 103 away from the substrate 101, and the thickness of the barrier layer 104 ranges from 3 nm to 50 nm.

[0096] In some examples, an AlN insertion layer of 0.5 nm to 2 nm may be stacked between the channel layer 103 and the barrier layer 104.

[0097] S5: A capping layer 105 is formed on the side of the barrier layer 104 away from the substrate 101.

[0098] For example, the capping layer 105 is made of p-GaN, and the capping layer 105 can also be Mg-doped. The precursor used for Mg doping can be Cp2Mg (magnesium pyrocene), and the growth temperature can be 800℃~1000℃.

[0099] S6: A gate 108 is formed on the side of the capping layer 105 away from the substrate 101.

[0100] For example, by etching, the side of the capping layer 105 away from the substrate 101 is etched to form a gate region, and gate metal is deposited on the gate region to form a gate 108. The metal includes, but is not limited to, a mixture of one or more materials such as Ti, TiN, Al, Ni, and Au.

[0101] S7: Form source 106 and drain 107. Source 106 and drain 107 are disposed on both sides of capping layer 105 along the second direction X and are in contact with barrier layer 104. The second direction X is perpendicular to the thickness direction of substrate 101.

[0102] For example, by etching, the barrier layer 104 is etched along the second direction X on both sides of the gate 108, and metal is deposited to form an ohmic contact, forming the source 106 and the drain 107. The metal includes, but is not limited to, a mixture of one or more materials such as Ti, TiN, Al, Ni, and Au.

[0103] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: A substrate, a nucleation layer, a buffer layer, and a channel layer are sequentially stacked; wherein, the buffer layer includes: a first buffer layer, the material of which includes: Al x Ga 1-x N, x≤1, and the concentration of carbon in the first buffer layer is less than or equal to 5×10⁻⁶. 17 cm -3 .

2. The semiconductor device according to claim 1, characterized in that, The buffer layer further includes: at least one second buffer layer disposed between the first buffer layer and the nucleation layer; the material of the second buffer layer includes: Al y Ga 1-y N, y < x, and the carbon concentration in the second buffer layer is greater than 5 × 10⁻⁶. 17 cm -3 .

3. The semiconductor device according to claim 2, characterized in that, The buffer layer includes at least two layers of the second buffer layer stacked along a first direction, which is the thickness direction of the semiconductor device; In any two adjacent second buffer layers, the second buffer layer farther away from the nucleation layer is the first buffer sublayer, and the second buffer layer closer to the nucleation layer is the second buffer sublayer; The first buffer sublayer material includes: Al y1 Ga 1-y1 N, the second buffer sublayer material includes: Al y2 Ga 1- y2 N; and y1≥y2.

4. The semiconductor device according to claim 2, characterized in that, The buffer layer includes two second buffer layers; The material of the second buffer layer, which is relatively far from the channel layer, includes: Al 0.5 Ga 0.5 N, the material of the second buffer layer relatively close to the channel layer includes: Al 0.75 Ga 0.25 N.

5. The semiconductor device according to claim 4, characterized in that, The carbon concentration in the second buffer layer ranges from 1×10⁻⁶. 18 cm -3 ~1×10 20 cm -3 .

6. The semiconductor device according to any one of claims 1 to 5, characterized in that, Also includes: A barrier layer is disposed on the side of the channel layer away from the substrate; A capping layer is disposed on the side of the barrier layer away from the channel layer; The device comprises a source, a drain, and a gate, wherein the gate is disposed between the source and the drain, and the gate is disposed on the side of the capping layer away from the substrate, and the source and the drain are disposed on the side of the barrier layer or the channel layer away from the substrate.

7. The semiconductor device according to claim 6, characterized in that, The channel layer is made of GaN; and / or the barrier layer is made of Al. z Ga 1-z N, 0 < z ≤ 1.

8. A chip, characterized in that, include: The semiconductor device as described in any one of claims 1 to 7.

9. An electronic device, characterized in that, include: The chip as described in claim 8.

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