Semiconductor structure and method of fabricating the same, high voltage mos device

Abstract

The application provides a semiconductor structure and a preparation method thereof, and a high-voltage MOS device. The semiconductor structure comprises: a substrate; a source-drain region and a channel active region between the source-drain region are formed in the substrate; a field oxide layer is located between the channel active region and the source-drain region and defines a boundary of the channel active region; a gate oxide layer covers the channel active region and the field oxide layer; wherein a recess is formed on the surface of the gate oxide layer at a position corresponding to the adjacent boundary of the channel active region; the thickness of the gate oxide layer at the recess position is smaller than that at other positions; a gate layer is located on the surface of the gate oxide layer; wherein the gate layer forms a through opening at a position corresponding to the recess. In this way, the leakage and breakdown caused by the thinner gate oxide layer at the recess position can be reduced to a certain extent, and the reliability is improved.

Description

TECHNICAL FIELD

[0001] Embodiments in the present application relate to the technical field of semiconductor devices, and particularly relate to a semiconductor structure, a preparation method thereof, and a high-voltage MOS device. BACKGROUND

[0002] Currently, in a high-voltage MOS device, when the working voltage is high, such as the drain voltage exceeding 20V, a field oxide is usually introduced between the gate and the drain to disperse the surface electric field of the depletion region of the drain PN junction, thereby increasing the width of the depletion region, so as to improve the voltage resistance performance of the MOS device.

[0003] However, the technical personnel found through tests that the high-voltage MOS device in the prior art is prone to leakage and even gate breakdown, and has poor reliability. SUMMARY

[0004] Therefore, the embodiments of the present application aim to provide a semiconductor structure, a preparation method thereof, and a high-voltage MOS device, which can reduce the leakage and gate breakdown phenomenon and improve the reliability.

[0005] One embodiment of the present application provides a semiconductor structure, comprising: a substrate; an active drain region and a channel active region between the active drain region in the substrate; a field oxide layer between the channel active region and the active drain region and defining the boundary of the channel active region; a gate oxide layer covering the channel active region and the field oxide layer; wherein the surface of the gate oxide layer forms a recess at a position corresponding to the intersection of the adjacent boundaries of the channel active region; the thickness of the gate oxide layer at the recess position is less than the thickness of the gate oxide layer at other positions; a gate layer on the surface of the gate oxide layer; wherein the gate layer forms an opening corresponding to the recess.

[0006] Optionally, the gate layer defines an uncovered area on the surface of the gate oxide layer through the opening; and the recess is located in the uncovered area.

[0007] Optionally, the adjacent boundaries of the channel active region intersect to form a boundary point; the opening has a central axis perpendicular to the surface of the substrate, and the central axis passes through the boundary point.

[0008] Optionally, the semiconductor structure corresponds to a target design file obtained after Boolean operation and in accordance with the manufacturing process rules; wherein the shape and size of the opening in the target design file can be adjusted through the Boolean operation.

[0009] Optionally, the ratio of the area occupied by the opening on the surface of the gate layer to the total area of the surface of the gate layer falls within the range of 1% to 5%.

[0010] Optionally, the profile shape of the opening formed on the surface of the gate layer is a circle or a hexagon.

[0011] Optionally, the profile shape of the opening formed on the surface of the gate layer is a rectangle, and the length-to-width ratio of the rectangle falls within the range of 2.5-3.5.

[0012] Another embodiment of the present application provides a preparation method of a semiconductor structure, comprising: providing a substrate; the substrate comprising a substrate and a field oxide layer; wherein the substrate is formed with a channel active region defined by the field oxide layer; forming a gate oxide layer on the surface of the substrate; wherein the surface of the gate oxide layer is formed with a recess at a position corresponding to the intersection of an adjacent boundary of the channel active region; the thickness of the gate oxide layer at the recess position is smaller than the thickness of the gate oxide layer at other positions; depositing a gate material on the surface of the gate oxide layer, and forming an opening penetrating the gate material at a position corresponding to the recess through a photolithography and etching process, to obtain a gate layer.

[0013] Optionally, the preparation method further comprises: forming a contact etching stop layer, an interlayer dielectric layer, and a contact structure penetrating the contact etching stop layer and the interlayer dielectric layer on the gate layer; wherein the contact etching stop layer seals the opening between the interlayer dielectric layer and the gate layer.

[0014] Still another embodiment of the present application provides a high-voltage MOS device comprising the semiconductor structure as described in any of the preceding embodiments or prepared by the preparation method as described in any of the preceding embodiments.

[0015] The unexpected effect of the embodiments provided by the present application is that the source and drain regions and the channel active region located between the source and drain regions are formed on the substrate, and the boundary of the channel active region defined by the field oxide layer located between the channel active region and the source and drain regions is introduced, so that the surface of the gate oxide layer covering the channel active region and the field oxide layer is formed with a recess at a position corresponding to the intersection of the adjacent boundary of the channel active region, and then in the gate layer formed on the surface of the gate oxide layer, the opening penetrating the gate layer at a position corresponding to the recess of the surface of the gate oxide layer is formed, which can reduce the electric field intensity distribution at the intersection of the adjacent boundary of the channel active region, avoid electric field concentration, and to some extent reduce the leakage and breakdown caused by the thinner gate oxide layer at the recess position, and improve the reliability. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1a A schematic diagram of the planar structure of a symmetric high-voltage MOS tube in the related art.

[0017] Figure 1bA schematic diagram of a planar structure of a non-symmetrical high-voltage MOS tube in the prior art.

[0018] Figure 2 A schematic diagram of a cross-sectional structure of a non-symmetrical high-voltage MOS tube. Figure 1b

[0019] Figure 3 A schematic diagram of etching to form a trench in a method for manufacturing a semiconductor structure provided by an embodiment of the present application. Figure 4

[0020] Figure 5 A schematic diagram of growth of a liner oxide layer and oxide filling in a method for manufacturing a semiconductor structure provided by an embodiment of the present application. Figure 6

[0021] Figure 7 A schematic diagram of forming a field oxide layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present application. Figure 8

[0022] Figure 9 A schematic diagram of forming a substrate in a method for manufacturing a semiconductor structure provided by an embodiment of the present application. Figure 10

[0023] Figure 11 A schematic diagram of forming a gate oxide layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present application.

[0024] Figure 12 A schematic diagram of depositing a gate material in a method for manufacturing a semiconductor structure provided by an embodiment of the present application.

[0025] Figure 13 A schematic diagram of forming a gate layer in a method for manufacturing a semiconductor structure provided by an embodiment of the present application. Figure 14

[0026] Figure 15 A schematic diagram of forming a contact etching stop layer, an interlayer dielectric layer, and a contact structure in a method for manufacturing a semiconductor structure provided by an embodiment of the present application.

[0027] Figure 16a A schematic diagram of a planar structure of a symmetrical high-voltage MOS tube provided by an embodiment of the present application.

[0028] Figure 16b A schematic diagram of a planar structure of a non-symmetrical high-voltage MOS tube provided by an embodiment of the present application.

[0029] Figure 17 A schematic diagram of etching to form a trench in a method for manufacturing a semiconductor structure provided by an embodiment of the present application. Figure 18 A schematic diagram of etching to form a trench in a method for manufacturing a semiconductor structure provided by an embodiment of the present application.​​​​​​

[0030] Reference Signs List:

[0031] 101, trench; 102, liner oxide; 103, pad oxide; 104, silicon nitride mask; 105, oxide; 106, field oxide; 107, masking layer; 110, substrate; 111, substrate; 112, channel active region; 113, source / drain region; 120, gate oxide; 121, recess; 122, gate material; 130, gate layer; 131, opening; 140, contact etch stop layer; 150, interlayer dielectric layer; 160, contact structure; 170, metal layer; 115, source; 116, drain; 117, contact metal; 200, semiconductor structure; 210, uncovered region; 220, boundary point. DETAILED DESCRIPTION

[0032] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments of the present application.

[0033] In the present application, the drawings are not necessarily drawn to scale, and local features can be enlarged or reduced to more clearly show the details of the local features.

[0034] Unless otherwise defined, all technical and scientific terms used in the present application have the same meanings as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used in the present application are only for the purpose of describing specific embodiments and are not intended to limit the scope of the present application. The term "and / or" used in the present application includes any and all combinations of one or more of the listed items. The singular forms "a", "an" and "the" used in the embodiments of the present application are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0035] In the description of the present application, it should be understood that the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0036] In the description of this application, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "height", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the purpose of simplifying the description of this application and do not indicate that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. In other words, they should not be construed as limitations on this application.

[0037] In the description of this application, unless otherwise expressly defined, the terms "installation," "connection," "linking," "fixing," "setting," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can also refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0038] In related technologies, high-voltage MOSFETs (high-voltage metal-oxide-semiconductor field-effect transistors) suitable for high-voltage operating scenarios require the addition of a field oxide layer 13 (i.e., STI) between the gate 10 and the source 11 and drain 12 to improve the voltage withstand performance of the high-voltage MOSFET. Figure 1a and Figure 1b Symmetrical high-voltage MOSFETs and asymmetric high-voltage MOSFETs are shown respectively, such as... Figure 1a , Figure 1b As shown, regardless of whether it is a symmetrical high-voltage MOSFET or an asymmetrical high-voltage MOSFET, the active region 14 of the channel between its source 11 and drain 12 has a boundary point 15 formed by the intersection of adjacent boundaries.

[0039] However, due to the process characteristics of the field oxide layer 13 and the gate oxide layer 16 covering the gate 10, the thickness of the gate oxide layer 16 at the boundary point 15 where it connects to the field oxide layer 13 is relatively thin. Specifically, refer to... Figure 2 , Figure 2 for Figure 1b The diagram shown is a cross-sectional view of the high-voltage MOSFET at boundary point 15 along the source and drain arrangement direction. Figure 2 It can be seen that, at the boundary point 15, the thickness T2 at the junction of the gate oxide layer 16 and the field oxide layer 13 is significantly smaller than the gate oxide layer thickness T1 at other locations.

[0040] The thin thickness is weak in reliability when the high-voltage MOS tube is in a high-voltage working state. For example, when the electric field is enhanced, there can be defect points such as holes (pinholes or blind holes), cracks, impurities, and fiber filaments, which can cause gas discharge, electrothermal decomposition, and the like, and further cause dielectric leakage or even breakdown. In particular, the electric field is concentrated at the boundary point of the channel active region, which can cause the electric field strength at the position to locally increase, and more easily cause the defect points to occur at the thin gate oxide layer. In a time-dependent dielectric breakdown (TDDB) test, the defect points can form a conduction channel from the gate to the substrate after a certain time, thereby causing a larger current and breakdown.

[0041] Therefore, it is necessary to provide a semiconductor structure capable of improving the reliability of a high-voltage MOS tube.

[0042] Referring to Figures 3 to 15 One embodiment of the present application provides a preparation method of a semiconductor structure. The semiconductor structure can be a component of a high-voltage MOS tube. Specifically, the preparation method of the semiconductor structure can include the following steps.

[0043] S110: providing a substrate.

[0044] In the embodiment, referring to Figure 10 The substrate 110 can include a substrate 111 and a field oxide layer 106. The channel active region 112 is formed in the substrate 111 and is defined by the field oxide layer 106. The channel active region 112 is located between adjacent field oxide layers 106. The field oxide layer 106 is located on one side of the channel active region 112 and the source / drain region 113 is located on the other side of the channel active region 112.

[0045] In some embodiments, the step of providing the substrate can be implemented by referring to the process steps of Figures 3 to 10 Specifically, first, as shown in Figure 3 and Figure 4 , a trench 101 is etched on the surface of a silicon wafer by using a lithography and etching process. Then, as shown in Figure 5 and Figure 6 , a liner oxide layer 102 is grown on the channel sidewall, and an oxide 105 is filled in the trench 101 by a TEOS deposition process, wherein a pad oxide layer 103 and a silicon nitride mask 104 are provided on the surface of the silicon wafer. Next, as shown in Figure 7 and Figure 8 , the excess oxide 105 is removed by a CMP process, and the pad oxide layer 103 and the silicon nitride mask 104 are removed, thereby forming the field oxide layer 106 (STI) in the trench 101. Finally, as shown in Figure 9 and Figure 10As shown, a masking layer 107 is formed on the surface of the silicon wafer and the field oxide layer 106, and the substrate 110 is obtained after ion implantation.

[0046] S120: A gate oxide layer is formed on the substrate surface.

[0047] In some embodiments, such as Figure 11 As shown, the photoresist and masking layer 107 during the ion implantation process can be removed first, and then the gate oxide layer 120 can be re-formed on the surface of the substrate 110 to prevent the masking layer 107 from being damaged by ion implantation as part of the gate oxide layer 120.

[0048] refer to Figure 11 In some embodiments, during the formation of the gate oxide layer 120 via a thermal oxidation process, oxygen diffuses along the silicon surface at high temperature and reacts to generate silicon dioxide. However, because a corner is formed at the intersection of adjacent boundaries of the channel active region 112, the oxygen diffusion and reaction rates at this location differ from those at other locations during the oxidation process. Furthermore, the field oxide layer 106 also exhibits a certain degree of depression at this location after CMP. Consequently, a depression 121 is formed on the surface of the gate oxide layer 120 at the location corresponding to the intersection of adjacent boundaries of the channel active region 112. This depression is relatively thinner than those at other locations; that is, the thickness of the gate oxide layer 120 at the depression 121 is less than the thickness of the gate oxide layer 120 at other locations.

[0049] S130: Deposit gate material on the surface of the gate oxide layer, and form an opening through the gate material at the position corresponding to the recess through photolithography and etching processes to obtain the gate layer.

[0050] In some embodiments, such as Figure 12 As shown, a gate material 122, such as polysilicon, is deposited on the surface of the gate oxide layer 120 using a chemical vapor deposition process, followed by... Figure 13 and Figure 14 As shown, a gate layer 130 is formed by etching a photoresist on the surface of the gate material 122 at a position corresponding to the recess 121. The gate layer 130 has a through-hole 131 formed at a position corresponding to the recess 121.

[0051] In some embodiments, the method for fabricating a semiconductor structure may further include: forming a contact etch stop layer, an interlayer dielectric layer, and a contact structure penetrating the contact etch stop layer and the interlayer dielectric layer on a gate layer.

[0052] Specifically, in some embodiments, in Figure 14 Based on the structure shown, subsequent manufacturing processes can be carried out to form, such as... Figure 15 The structure shown is illustrated. Where, reference... Figure 15A source 115 and a drain 116 are formed on both sides of the active region 112 of the channel, respectively. Contact metal 117, such as NiSi, is formed on the surface of the source, drain, and gate layer 130, and a contact structure 160 is formed on the contact metal 117. A contact etch stop layer 140 (CESL) and an interlayer dielectric layer 150 (ILD) are also provided on the gate layer 130 and the surfaces of the source and drain. The contact structure 160 penetrates the interlayer dielectric layer 150 and is connected to the metal layer 170 disposed on the interlayer dielectric layer 150 to form a conduction path.

[0053] In some embodiments, the contact etch stop layer 140 seals the opening 131 between the interlayer dielectric layer 150 and the gate layer 130. Specifically, as shown... Figure 15 As shown, the space inside the opening 131 can be filled with an insulating material, such as the same material as the interlayer dielectric layer 150, silicon nitride, etc. In some embodiments, the space inside the opening 131 may not be filled with material, and an air gap is formed under the sealing effect of the contact etch stop layer 140, thereby reducing parasitic capacitance.

[0054] In this embodiment, an unexpected effect is that source / drain regions 113 and a channel active region 112 located between the source / drain regions 113 are formed on the substrate 111, and a field oxide layer 106 is introduced between the channel active region 112 and the source / drain regions 113 to define the boundary of the channel active region 112. This results in a recess 121 being formed on the surface of the gate oxide layer 120 covering the channel active region 112 and the field oxide layer 106 at a position corresponding to the intersection of the adjacent boundary of the channel active region 112. Consequently, in the gate layer 130 formed on the surface of the gate oxide layer 120, an opening 131 penetrating the gate layer 130 is formed at a position corresponding to the recess 121 on the surface of the gate oxide layer 120. This reduces the electric field intensity distribution at the intersection of the adjacent boundary of the channel active region 112, avoids electric field concentration, and thus reduces leakage and breakdown caused by the thin gate oxide layer 120 at the position of the recess 121 to a certain extent, thereby improving reliability.

[0055] Please refer to Figure 14 , Figure 16a and Figure 16b Another embodiment of this application provides a semiconductor structure 200, including a substrate 111, a field oxide layer 106, a gate oxide layer 120, and a gate layer 130. In some embodiments, the semiconductor structure 200 can be fabricated using the semiconductor structure fabrication method described in the foregoing embodiments, and the semiconductor structure 200 can also be a component of a high-voltage MOSFET.

[0056] In this embodiment, the substrate 111 can serve as the basic structure of the semiconductor structure 200, not only providing mechanical support but also influencing the electrical properties of the semiconductor structure 200, such as threshold voltage and carrier mobility, through doping with ions. Specifically, the substrate 111 can be made of silicon (Si), or, depending on the requirements, of other semiconductor materials, such as silicon carbide (SiC) or gallium nitride (GaN).

[0057] In this embodiment, an active drain region 113 and a channel active region 112 located between the source and drain regions 113 can be formed in the substrate 111. The source and drain regions 113 can be heavily doped to form source or drain electrodes. The channel active region 112 is part of the active region and can serve as a portion of the active region used to form a carrier flow channel.

[0058] In this embodiment, the field oxide layer 106 can achieve lateral electrical isolation and is used to adjust the electric field distribution, thereby improving the voltage withstand capability of the high-voltage MOSFET. Specifically, as shown... Figure 14 As shown, the field oxide layer 106 can be connected to the bottom of the gate oxide layer 120 and extends from the surface of the substrate 111 to the bottom.

[0059] In this embodiment, the field oxide layer 106 is located between the channel active region 112 and the source / drain region 113, and defines the boundary of the channel active region 112. Specifically, as shown... Figure 14 As shown, the active channel region 112 is the region in the substrate 111 located between adjacent field oxide layers 106. The region in the substrate 111 located outside the field oxide layer 106 is the source / drain region 113.

[0060] In this embodiment, the gate oxide layer 120 covers the channel active region 112 and the field oxide layer 106, and is connected to the field oxide layer 106 to jointly form the gate dielectric layer. Wherein, reference... Figure 14 As mentioned above, due to the process characteristics of fabricating the field oxide layer 106 and the gate oxide layer 120, a depression 121 is formed on the surface of the gate oxide layer 120 at the position corresponding to the intersection with the adjacent boundary of the channel active region 112. As a result, the gate oxide layer 120 at the position of the depression 121 is relatively thin, and its thickness is less than that of the gate oxide layer 120 at other positions.

[0061] In this embodiment, the gate layer 130 is located on the surface of the gate oxide layer 120. The gate layer 130 has a through-hole 131, the position of which corresponds to the position of the recess 121, such that the projection of the gate layer 130 onto the surface of the gate oxide layer 120 does not overlap with at least a portion of the surface of the recess 121. Specifically, refer to... Figure 16a and Figure 16bFrom the perspective of the planar structure, it can be seen that the position of the opening 131 formed by the gate layer 130 corresponds to the intersection of the adjacent boundary of the channel active region 112 in the direction perpendicular to the substrate 111.

[0062] An unexpected effect is that by forming a through-hole 131 in the gate layer 130 at a position corresponding to the recess 121 on the surface of the gate oxide layer 120, the gate material 122 is absent in at least a portion of the relatively thin area of ​​the gate oxide layer 120. This reduces the electric field intensity distribution at that position, avoids electric field concentration, and thus reduces leakage and breakdown caused by the thin gate oxide layer 120 at the recess 121 position to a certain extent, thereby improving reliability.

[0063] Optionally, the gate layer 130 defines an uncovered region 210 on the surface of the gate oxide layer 120 through an opening 131, and the recess 121 is located within the uncovered region 210. That is, the projection of the gate layer 130 onto the surface of the gate oxide layer 120 does not overlap with the surface of the recess 121 at all. In this way, the electric field intensity in the thinner region of the gate oxide layer 120 can be further reduced.

[0064] In some embodiments, adjacent boundaries of the active region 112 of the channel intersect to form a boundary point 220. The aperture 131 has a central axis perpendicular to the substrate surface, and this central axis passes through the boundary point 220. Aligning the central axis of the aperture 131 of the gate layer 130 corresponding to the boundary point 220 with the boundary point 220 can further optimize the local electric field distribution and alleviate electric field concentration by improving the electric field symmetry near the boundary point 220. When the central axis passes through the boundary point 220, a symmetrical potential gradient can be formed at this location, causing the electric field originally concentrated at the tip of the boundary point 220 to diffuse uniformly to the surrounding area. This significantly reduces the electric field intensity near the boundary point 220, suppresses carrier tunneling and oxide trap formation, and further improves the stability and gate breakdown voltage of the semiconductor structure 200 under high-voltage operating conditions.

[0065] In some embodiments, the ratio of the area occupied by the aperture 131 on the surface of the gate layer 130 to the total area of ​​the gate layer 130 falls within the range of 1% to 5%. Setting the ratio of the area occupied by the aperture 131 on the surface of the gate layer 130 to the total area within the range of 1% to 5% can achieve a balance between electric field distribution control and structural stability. Since if the aperture 131 is set too large, it may not only excessively weaken the gate's control over the channel, causing problems such as a drop in threshold voltage, but also affect the overall mechanical strength of the gate layer 130. Therefore, setting the aperture 131 size within the above range achieves electric field regulation, alleviates electric field concentration, while taking into account the performance and mechanical strength of the gate structure, and prevents material peeling or stress mismatch problems caused by excessively large apertures 131 during the process. Furthermore, the 1% to 5% aperture 131 ratio has high compatibility with existing photolithography and etching processes, balancing manufacturing yield and cost control, making it highly practical.

[0066] In some embodiments, the outline shape of the aperture 131 formed on the surface of the gate layer 130 is circular or hexagonal. Thus, when the aperture 131 is circular or hexagonal, stress concentration caused by etching can be reduced, stress distribution can be uniform, and edge effects can be reduced.

[0067] In some embodiments, the outline shape of the aperture 131 formed on the surface of the gate layer 130 is rectangular, and the ratio of the length to the width of the rectangle falls within the range of 2.5 to 3.5. Thus, when the shape of the aperture 131 is rectangular or square, the shape is more regular, which is beneficial for the alignment and control of photolithography and etching processes, and facilitates subsequent process optimization.

[0068] To illustrate the technical effects of this application, the technicians conducted experiments, measuring the gate current IG and gate voltage VG of high-voltage NMOS and high-voltage PMOS respectively. The experimental results are as follows: Figure 17 and Figure 18 As shown. Figure 17 and Figure 18 Examples 1 to 3 show the IG-VG curves for gate layer 130 with rectangular openings 131 of different sizes, respectively, while the comparative example shows the IG-VG curves for gate layer 130 without openings 131. The experimental results show that when the linear scan voltage VG is 40V, the gate leakage current is significantly reduced, and the gate breakdown voltage can be increased from 72V to over 80V.

[0069] In some embodiments, the semiconductor structure 200 corresponds to a target design file that conforms to manufacturing process rules after Boolean operation.

[0070] Because the initial design files (GDS) of the semiconductor structure 200 obtained by technicians before fabrication often do not conform to the manufacturing process rules in actual production, it is necessary to consider the errors in the actual production process and perform Boolean operations (Auto Generation) on the initial design files to optimize them and obtain target design files that conform to the manufacturing process rules. Only then can the manufacturing process be implemented based on the target design files. For example, for the gate layer 130 in the initial design file, Boolean operations can be used to calculate the boundaries of each region to optimize it and make it conform to the manufacturing process rules in actual production.

[0071] In some embodiments, the shape and size of the aperture 131 can be adjusted in the target design file using Boolean operations, without modifying the initial design file or adding a photomask, thus reducing process costs.

[0072] Another embodiment of this application provides a high-voltage MOS device, including the semiconductor structure described in the foregoing embodiments, or prepared using the semiconductor structure preparation method described in the foregoing embodiments.

[0073] It is understood that the specific examples in this document are only intended to help those skilled in the art better understand the embodiments of this application, and are not intended to limit the scope of the invention.

[0074] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0075] It is understood that the various embodiments described in this application can be implemented individually or in combination, and the embodiments of this application are not limited in this respect.

[0076] It is understood that in the description of this application, when describing the structure of a component, when referring to a layer or region as being "above" or "on top of" another layer or region, it may mean that it is directly above another layer or region, or that it contains other layers or regions between itself and another layer or region. Furthermore, if the component is flipped, the layer or region will be located "below" or "under" another layer or region.

[0077] The above description is merely a specific embodiment of this application, but the protection scope of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the protection scope of this application.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate, wherein a source-drain region and a channel active region between the source-drain region are formed in the substrate; a field oxide layer between the channel active region and the source-drain region, and defining a boundary of the channel active region; a gate oxide layer covering the channel active region and the field oxide layer, wherein a recess is formed on the surface of the gate oxide layer at a position corresponding to the intersection of adjacent boundaries of the channel active region, and the thickness of the gate oxide layer at the recess position is less than that at other positions; a gate layer on the surface of the gate oxide layer, wherein an opening is formed in the gate layer at a position corresponding to the recess.

2. The semiconductor structure of claim 1, wherein, The gate layer defines an uncovered area on the surface of the gate oxide layer through the opening, and the recess is located in the uncovered area.

3. The semiconductor structure of claim 1, wherein, Adjacent boundaries of the channel active region intersect to form a boundary point, and the opening has a central axis perpendicular to the surface of the substrate, and the central axis passes through the boundary point.

4. The semiconductor structure of claim 1, wherein, The semiconductor structure corresponds to a target design file obtained after Boolean operation, and the shape and size of the opening in the target design file can be adjusted through the Boolean operation.

5. The semiconductor structure of claim 3, wherein, The ratio of the area occupied by the opening on the surface of the gate layer to the total area of the surface of the gate layer falls within the range of 1% to 5%.

6. The semiconductor structure of claim 3 or 4, wherein, The contour shape of the opening on the surface of the gate layer is circular or hexagonal.

7. The semiconductor structure of claim 3 or 4, wherein, The contour shape of the opening on the surface of the gate layer is rectangular, and the ratio of the length to the width of the rectangle falls within the range of 2.5 to 3.

5.

8. A method of fabricating a semiconductor structure, characterized by, The preparation method comprises: providing a substrate, wherein the substrate comprises a substrate and a field oxide layer, and a channel active region defined by the field oxide layer is formed in the substrate; forming a gate oxide layer on the surface of the substrate, wherein a recess is formed on the surface of the gate oxide layer at a position corresponding to the intersection of adjacent boundaries of the channel active region, and the thickness of the gate oxide layer at the recess position is less than that at other positions; depositing a gate material on the surface of the gate oxide layer, and forming an opening through the gate material at a position corresponding to the recess by a photolithography and etching process to obtain a gate layer.

9. The method of claim 8, wherein the semiconductor structure is prepared by a method comprising: The preparation method further comprises: forming a contact etching stop layer, an interlayer dielectric layer, and a contact structure through the contact etching stop layer and the interlayer dielectric layer on the gate layer, wherein the contact etching stop layer seals the opening between the interlayer dielectric layer and the gate layer.

10. A high voltage MOS device, characterized by, The semiconductor structure as claimed in any one of claims 1 to 7 or prepared by the preparation method of the semiconductor structure as claimed in any one of claims 8 to 9.

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