Display device and electronic device

Abstract

The invention relates to a display device and an electronic device. The display device includes a display area including first to third pixels emitting light having different colors, respectively, and a display transmissive area on a side surface of the first to third pixels, and a first non-display area on a first side of the display area. The first non-display area includes a scan line area including a plurality of lines extending in a first direction and spaced apart from each other in a second direction, a scan circuit between the scan line area and the display area and receiving a signal from the lines to supply a scan signal to the display area, an anti-static element at an outermost portion of the first non-display area; and a non-display transmissive area between the scan line area and the anti-static element to transmit light. The plane area of the non-display transmission area is larger than the plane area of the scanning circuit.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a display device and an electronic device. Background Technology

[0002] With the development of the information society, display devices are being used in an increasing number of electronic devices. For example, display devices are used in electronic devices such as smartphones, digital cameras, laptops, navigation devices, and smart TVs. Display devices can include display panels with self-emitting pixels. Therefore, the pixels of the display panel can emit light themselves, eliminating the need for a backlight to supply light to the display panel.

[0003] The display device includes multiple pixels, data lines and scan lines connected to the multiple pixels, a data driver that applies data voltage to the data lines, and a scan driver that provides scan signals to the scan lines. Summary of the Invention

[0004] At least one embodiment of this disclosure provides a display device and an electronic device that have a transparent display panel by making the non-display area less noticeable.

[0005] According to embodiments of this disclosure, a display device includes: a display area comprising first to third pixels that emit light of different colors to each other and display transmissive areas located on the sides of the first to third pixels; and a first non-display area located on a first side of the display area. The first non-display area includes: a scan line area comprising a plurality of lines extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a scan circuit disposed between the scan line area and the display area, receiving signals from the plurality of lines and providing scan signals to the display area; an anti-static element disposed at the outermost portion of the first non-display area; and a non-display transmissive area located between the scan line area and the anti-static element to transmit light. The area of ​​the non-display transmissive area in a plan view is larger than the area of ​​the scan circuit in a plan view.

[0006] In this embodiment, the non-display transmissive area may not include a metal layer, transistors, signal lines, or voltage lines.

[0007] In this embodiment, the multiple lines include: a clock line, disposed adjacent to the non-display transmissive area and providing a clock signal to the scanning circuit; a carry line, disposed adjacent to the scanning circuit and providing a carry signal to the scanning circuit; and a scan input line, disposed between the clock line and the carry line and providing a scan input signal to the scanning circuit.

[0008] In one embodiment, the first pixel to the third pixel are adjacent to each other in a first direction, and the transmission region is located on the first side of the first pixel to the third pixel in a second direction.

[0009] In an embodiment, the display device may further include: a low-level voltage line overlapping the scanning circuit; and a bridge contact overlapping the low-level voltage line. Each of the first to third pixels may include a pixel electrode, an emitter layer, and a common electrode. The common electrode may extend beyond the display area to a first non-display area and make direct contact with the low-level voltage line at the bridge contact.

[0010] In an embodiment, the display device may further include: a substrate defining a display area and a first non-display area; a light-emitting element layer disposed on the substrate and including pixel circuitry and a light-emitting element for each of a first to a third pixel; an encapsulation layer disposed on the light-emitting element layer; a counter substrate facing the substrate; a color filter layer disposed on the substrate-facing surface of the counter substrate and including a first to a third color filter corresponding to the first to the third pixel respectively; a wavelength conversion layer disposed on the surface of the color filter layer and including a first to a third transparent member corresponding to the first to the third color filter respectively; a filling layer disposed between the encapsulation layer and the wavelength conversion layer, and filling the space between the encapsulation layer and the wavelength conversion layer; and a sealing member disposed along the edge of the first non-display area. The sealing member can attach the substrate to the counter substrate.

[0011] In an embodiment, the display device may further include a compensation layer disposed at the edge of the surface of the opposing substrate and overlapping with the low-level voltage line, the scan line area, and the non-display transmissive area.

[0012] In an embodiment, the display device may further include: a dam disposed on the surface of the color filter layer and defining first to third transparent members. First to third dummy pixels are defined by the dam. The first to third dummy pixels overlap with the scanning circuitry and have the same shape as the first to third pixels in a planar view.

[0013] In an embodiment, the first dummy pixel to the third dummy pixel may respectively include a first color filter to a third color filter and a first transparent component to a third transparent component, and may not include a light-emitting element.

[0014] In an embodiment, the display device may further include: a second non-display area adjacent to the first non-display area; a third non-display area located opposite to the second non-display area relative to the display area; and a fourth non-display area located opposite to the first non-display area relative to the display area. Low-level voltage lines and anti-static components may be disposed along the first to fourth non-display areas, surrounding the display area in a plan view and spaced apart from the display area.

[0015] According to embodiments of this disclosure, a display device includes: a display area including first to third pixels that emit light having different colors from each other, and a display transmissive area located on the sides of the first to third pixels; a first non-display area located on a first side of the display area in a first direction, and including a scan driver for providing scan signals to the first to third pixels; and a second non-display area adjacent to the first non-display area and located on a second side of the display area in a second direction intersecting the first direction. The second non-display area includes: a first non-display transmissive area adjacent to the display area and transmitting light; a first low-level voltage line disposed on the upper side of the first non-display transmissive area in the second direction and providing a low-level voltage; a second non-display transmissive area disposed on the upper side of the first low-level voltage line in the second direction and transmitting light; a second low-level voltage line disposed on the upper side of the second non-display transmissive area in the second direction, below the first low-level voltage line, and providing a low-level voltage; a third non-display transmissive area disposed on the upper side of the second low-level voltage line in the second direction and transmitting light; and an anti-static element disposed at the outermost portion of the second non-display area.

[0016] In an embodiment, the area of ​​the second non-display transmissive region in the plan view may be larger than the area of ​​the first non-display transmissive region in the plan view. The area of ​​the third non-display transmissive region in the plan view may be larger than the area of ​​the second non-display transmissive region in the plan view.

[0017] In an embodiment, the display device may further include: a voltage connection line extending from the display area to a first low-level voltage line and surrounding a portion of a first non-display transmissive area in a plan view.

[0018] In an embodiment, the display device may further include a bridge contact that overlaps with a first low-level voltage line. Each of the first to third pixels may include a pixel electrode, an emitter layer, and a common electrode. The common electrode may extend beyond the display area to a second non-display area and may be in direct contact with the first low-level voltage line at the bridge contact.

[0019] In an embodiment, the display device may further include: a substrate defining a display area and a first non-display area and a second non-display area; a light-emitting element layer disposed on the substrate and including pixel circuitry and a light-emitting element for each of a first pixel to a third pixel; an encapsulation layer disposed on the light-emitting element layer; a counter substrate facing the substrate; a color filter layer disposed on the substrate-facing surface of the counter substrate and including a first color filter to a third color filter corresponding to the first pixel to the third pixel respectively; a wavelength conversion layer disposed on the surface of the color filter layer and including a first transparent member to a third transparent member corresponding to the first color filter to the third color filter respectively; a filling layer disposed between the encapsulation layer and the wavelength conversion layer, and filling the space between the encapsulation layer and the wavelength conversion layer; and a sealing member disposed along the edge of the second non-display area. The sealing member attaches the substrate to the counter substrate.

[0020] In an embodiment, the pixel circuit may include: a bottom metal layer disposed on a substrate; a semiconductor layer disposed on the bottom metal layer; a gate layer disposed on the semiconductor layer; and a source metal layer disposed on the gate layer. A first low-level voltage line may be disposed in the same layer as the pixel electrode and may include multiple vias. A second low-level voltage line may be disposed in the source metal layer.

[0021] In an embodiment, the display device may further include: a voltage connection line extending from a second low-level voltage line to an anti-static element, and surrounding a portion of a third non-display transmissive area in a plan view. The anti-static element may be disposed in a bottom metal layer and a gate layer.

[0022] According to embodiments of this disclosure, a display device includes: a display area including first to third pixels that respectively emit light having different colors from each other and a display transmissive area located on the sides of the first to third pixels; a first non-display area located on a first side of the display area in a first direction and including a scan driver for providing scan signals to the first to third pixels; a second non-display area adjacent to the first non-display area and located on a second side of the display area in a second direction intersecting the first direction; a third non-display area opposite to the second non-display area relative to the display area; and a substrate defining the display area and the first non-display area. The system comprises: a first dummy pixel to a third dummy pixel; a light-emitting element layer disposed on the substrate and including pixel circuitry and a light-emitting element for each of the first to third pixels; an encapsulation layer disposed on the light-emitting element layer; a counter substrate facing the substrate; a color filter layer disposed on the substrate-facing surface of the counter substrate and including first to third color filters corresponding to the first to third pixels respectively; a wavelength conversion layer disposed on the surface of the color filter layer and including first to third transparent members corresponding to the first to third color filters respectively; and a dam disposed on the surface of the color filter layer to define the first to third transparent members. The third dummy pixel includes the first to third dummy pixels defined by the dam. The first to third dummy pixels have the same shape as the first to third pixels in a plan view. The first to third dummy pixels are adjacent to each other in a second direction. A non-display transmissive region overlaps with the first and second dummy pixels. A low-level voltage line overlaps with the second and third dummy pixels. The low-level voltage line includes a plurality of holes.

[0023] In this embodiment, the first dummy pixel to the third dummy pixel may each include a first color filter, a third color filter, and a first transparent component to a third transparent component. The first dummy pixel to the third dummy pixel may not include a light-emitting element.

[0024] In this embodiment, the low-level voltage line may extend along the first non-display area, the second non-display area, and the third non-display area.

[0025] According to an embodiment of this disclosure, an electronic device includes a display device and a power supply for providing power to the display device. The display device includes: a display area comprising a plurality of pixels that emit light of different colors respectively and display transmissive areas located on the sides of the plurality of pixels; and a first non-display area located on a first side of the display area. The first non-display area includes: a scan line area comprising a plurality of lines extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a scan circuit disposed between the scan line area and the display area, receiving signals from the plurality of lines and providing scan signals to the display area; an anti-static element disposed at the outermost portion of the first non-display area; and a non-display transmissive area located between the scan line area and the anti-static element to transmit light. The area of ​​the non-display transmissive area in a plan view is larger than the area of ​​the scan circuit in a plan view.

[0026] In this embodiment, the non-display transmissive area does not include a metal layer, transistors, signal lines, or voltage lines.

[0027] In this embodiment, the multiple lines include: a clock line, which is disposed adjacent to the non-display transmissive area and provides a clock signal to the scanning circuit; a carry line, which is disposed adjacent to the scanning circuit and provides a carry signal to the scanning circuit; and a scan input line, which is disposed between the clock line and the carry line and provides a scan input signal to the scanning circuit.

[0028] In one embodiment, multiple pixels are spaced apart from each other in a first direction. The display transmissive area is located on the first side of the multiple pixels in a second direction.

[0029] In this embodiment, the low-level voltage line overlaps with the scanning circuitry. The bridge contact also overlaps with the low-level voltage line. Each of the plurality of pixels includes a pixel electrode, an emitter layer, and a common electrode. The common electrode extends beyond the display area to a first non-display area and makes direct contact with the low-level voltage line at the bridge contact.

[0030] In this embodiment, the second non-display area is adjacent to the first non-display area. The third non-display area is located opposite to the second non-display area relative to the display area. The fourth non-display area is located opposite to the first non-display area relative to the display area. Low-level voltage lines and anti-static components are disposed along the first to the fourth non-display areas, surrounding the display area in the plan view and spaced apart from the display area.

[0031] According to embodiments of the present disclosure, the display device includes a non-display transmissive region located in a non-display area and having a predetermined area, thereby avoiding high-density metal patterns in the non-display area and enabling a transparent display panel. Attached Figure Description

[0032] The above and other features of this disclosure will become more apparent from the detailed description of non-limiting embodiments thereof with reference to the accompanying drawings.

[0033] Figure 1 This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0034] Figure 2 This is a view showing the arrangement of lines in a display device according to an embodiment of the present disclosure.

[0035] Figure 3 This is a circuit diagram illustrating the pixels of a display device according to an embodiment of the present disclosure.

[0036] Figure 4 This is a cross-sectional view showing a display device according to an embodiment of the present disclosure.

[0037] Figure 5 This is a cross-sectional view showing in detail a display device according to an embodiment of the present disclosure.

[0038] Figure 6 According to embodiments of this disclosure Figure 1 A magnified view of region A1.

[0039] Figure 7 This illustrates an embodiment according to the present disclosure. Figure 6 A magnified view of a portion of it.

[0040] Figure 8 According to embodiments of this disclosure Figure 1 A magnified view of region A2.

[0041] Figure 9 According to embodiments of this disclosure Figure 8 A magnified view of a portion of it.

[0042] Figure 10 According to embodiments of this disclosure Figure 1 A magnified view of region A3. Detailed Implementation

[0043] Embodiments of this disclosure will be described more fully below with reference to the accompanying drawings. Throughout the specification and drawings, the same reference numerals may refer to the same elements.

[0044] In this document, when two or more elements or values ​​are described as substantially the same or approximately equal to each other, it should be understood that the two or more elements or values ​​are the same, the two or more elements or values ​​are equal to each other within measurement error, or, if measurably unequal, the values ​​of the two or more elements or values ​​are sufficiently close to be functionally equal to each other, as will be understood by one of ordinary skill in the art. For example, taking into account the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the term "approximately" as used herein includes the stated value and means within an acceptable deviation of a particular value as determined by one of ordinary skill in the art. For example, "approximately" may mean within one or more standard deviations as understood by one of ordinary skill in the art. Further, it should be understood that while a parameter may be described herein as having "approximately" a certain value, according to embodiments, the parameter may be precisely that certain value or approximately that certain value within measurement error, as will be understood by one of ordinary skill in the art. Other uses of these terms to describe relationships between components and similar terms should be interpreted in a similar manner.

[0045] It will be understood that when a component, such as a membrane, region, layer, or element, is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another component, the component may be directly on, directly connected to, directly coupled to, or directly adjacent to the other component, or an intermediary component may be present. When a membrane, region, layer, or element is referred to as being “directly” on, directly connected to, directly coupled to, or directly adjacent to another component, an intermediary component may not be present. It will also be understood that when a component is referred to as “covering” another component, the component may be the only component covering the other component, or one or more intermediary components may also cover the other component. Other terms used to describe relationships between components can be interpreted in a similar manner.

[0046] It will be further understood that the description of a feature or aspect within each embodiment can be used for similar features or aspects in other embodiments, unless the context explicitly indicates otherwise. Accordingly, all features and structures described herein can be mixed and matched in any desired manner.

[0047] As used herein, the singular forms “a” and “the (said)” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0048] When a feature is considered to extend, protrude, or otherwise follow a direction, it will be understood that the feature may follow that direction in a negative direction (such as the opposite direction). Accordingly, the feature is not limited to following a direction precisely, and may follow that direction along an axis formed by that direction, unless the context explicitly indicates otherwise.

[0049] In the following, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0050] The display device includes a display area having a transmissive area for transmitting light and a non-display area having at least one transmissive area for transmitting light. The non-display transmissive area can have an area larger than adjacent areas (such as scanning circuits, anti-static components, etc.) in a planar view. Therefore, high-density metallic patterns in the non-display area can be avoided, and the non-display area can be less noticeable to the user. Thus, a transparent display panel can be realized.

[0051] A display device having a non-display area comprising multiple non-display transmissive areas may have a corresponding area added to the portion of the non-display transmissive area facing outwards in a plan view.

[0052] Figure 1 This is a plan view illustrating a display device according to an embodiment of the present disclosure.

[0053] refer to Figure 1 The display device 10 is used to display at least one moving image and / or still image. In embodiments, the display device 10 can be used as a display screen for portable electronic devices (such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, e-notebooks, e-book readers, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs)) and for various products (such as televisions, laptops, monitors, billboards, and Internet of Things devices). However, embodiments of this disclosure are not limited thereto, and the display device 10 can be applied to a variety of different small, medium, or large electronic devices. The electronic device may include a power source that provides power for the operation of the electronic device.

[0054] In an embodiment, when viewed from above, the display device 10 may have a rectangular shape having a long side in a first direction DR1 and a short side in a second direction DR2 intersecting the first direction DR1. Each of the corners where the long side in the first direction DR1 intersects the short side in the second direction DR2 may be rounded to have a predetermined curvature or may be a right angle. However, when viewed from above, the shape (e.g., planar shape) of the display device 10 is not necessarily limited to a quadrilateral shape, but may be formed as a circular shape, an elliptical shape, or other polygonal shape. The display device 10 may be formed as flat. However, the embodiments of this disclosure are not limited thereto. For example, the display device 10 may include curved portions formed at the left and right ends and having a constant or varying curvature. In some embodiments, the display device 10 may be flexible, such that the display device 10 may be bent, folded, or rolled up.

[0055] The display device 10 may include a display area DA for displaying an image and a non-display area NDA disposed around the display area DA (e.g., disposed around the display area DA in a plan view). The display area DA may occupy most of the area of ​​the display device 10. The display area DA may be located in the central portion of the display device 10. The display area DA may include a plurality of pixels PX for displaying the image.

[0056] Each of the plurality of pixels PX may include a light-emitting element. In embodiments, the light-emitting element may include, but is not limited to, at least one of a micro light-emitting diode (micro LED), an organic light-emitting diode including an organic emitting layer, a quantum dot light-emitting diode including a quantum dot emitting layer, and an inorganic light-emitting diode including an inorganic semiconductor.

[0057] The non-display area NDA may be disposed adjacent to the display area DA (e.g., adjacent to it in the first direction DR1 and / or the second direction DR2). The non-display area NDA may be located outside the display area DA. The non-display area NDA may surround the display area DA (e.g., completely surround the display area DA in a plan view). The non-display area NDA may be defined as an edge region of the display device 10. In an embodiment, the non-display area NDA may include a first non-display area NDA1, a second non-display area NDA2, a third non-display area NDA3, and a fourth non-display area NDA4. The first non-display area NDA1 may be located below the display area DA (e.g., below the display area DA in the direction opposite to the second direction DR2), the second non-display area NDA2 may be located above the display area DA (e.g., above the display area DA in the second direction DR2), the third non-display area NDA3 may be located to the left of the display area DA (e.g., to the left of the display area DA in the direction opposite to the first direction DR1), and the fourth non-display area NDA4 may be located to the right of the display area DA (e.g., to the right of the display area DA in the first direction DR1).

[0058] The non-display area NDA may include a scan driver SIC, fan-out lines, and pads. The scan driver SIC provides scan signals to scan lines in the display area DA. The fan-out lines electrically connect the display driver DIC to data lines in the display area DA. The pads may be electrically connected to the flexible film FPC. For example, the pads may be located at one edge of the display device 10, and the scan driver SIC may be located at another edge of the display device 10 adjacent to that edge (e.g., the left edge in the direction opposite to the first direction DR1). However, it should be understood that the embodiments of this disclosure are not limited thereto.

[0059] The display driver DIC can output signals and voltages for driving the display device 10. The display driver DIC can apply data voltages to data lines. The display driver DIC can apply power supply voltages to power supply lines and can supply scan control signals to the scan driver SIC. For example, in an embodiment, the display driver DIC can be implemented as an integrated circuit (IC) and can be mounted on a flexible film FPC using chip-on-film (COF) technology. Alternatively, the display driver DIC can be mounted in the non-display area NDA of the display device 10 using chip-on-glass (COG) technology, chip-on-plastic (COP) technology, or ultrasonic bonding.

[0060] Figure 2 This is a view showing the arrangement of lines in a display device according to an embodiment of the present disclosure.

[0061] refer to Figure 2 The display device 10 may include a scan line SCL, a sensing line SSL, a data line DL, an initialization voltage line VIL, a first voltage line VDL, and a second voltage line VSL.

[0062] The data line DL can extend along a second direction DR2 that intersects with the first direction DR1. The data line DL can extend from the first pad PD1 to the display area DA. The data line DL can provide the data voltage received from the first pad PD1 to the pixel PX.

[0063] Scan line SCL and sensing line SSL can extend longitudinally in the first direction DR1. Scan line SCL and sensing line SSL can extend from scan driver SIC to display area DA. Scan line SCL can provide (e.g., transmit) scan signals to pixel PX, and sensing line SSL can provide sensing signals to pixel PX. Scan driver SIC can include scan input lines and scan driver circuitry. In an embodiment, scan driver SIC can be located in a third non-display area NDA3, but embodiments of this disclosure are not limited thereto. Scan driver SIC can be connected to signal connection line CWL. Signal connection line CWL can provide clock signals and scan input signals received from second pad PD2 to scan driver SIC.

[0064] The first voltage line VDL may include a first portion extending longitudinally in the first direction DR1 and a second portion extending longitudinally in the second direction DR2. The first voltage line VDL may be a high-level voltage line. The first voltage line VDL may provide a high-level voltage received from the third pad PD3 to the pixel PX.

[0065] The second voltage line VSL may include a first portion extending longitudinally in the first direction DR1 and a second portion extending longitudinally in the second direction DR2. The second voltage line VSL may be a low-level voltage line. The second voltage line VSL may provide a low-level voltage received from the fourth pad PD4 to the pixel PX.

[0066] The initialization voltage line VIL may include a first portion extending longitudinally in the first direction DR1 and a second portion extending longitudinally in the second direction DR2. The initialization voltage line VIL can provide the initialization voltage received from the fifth pad PD5 to the pixel PX.

[0067] In this embodiment, the first pad PD1 and the second pad PD2 can be disposed in the first non-display area NDA1 and electrically connected to the flexible film FPC. The first pad PD1 can receive data voltage from the display driver DIC mounted on the flexible film FPC, and the second pad PD2 can receive clock signals and scan input signals from the flexible film FPC.

[0068] The third pad PD3, the fourth pad PD4, and the fifth pad PD5 can be disposed in the second non-display area NDA2 and electrically connected to the flexible film FPC. In an embodiment, the third pad PD3 can receive a high-level voltage from the power supply electrically connected to the flexible film FPC, the fourth pad PD4 can receive a low-level voltage from the power supply, and the fifth pad PD5 can receive an initialization voltage from the power supply.

[0069] Figure 3 This is a circuit diagram illustrating the pixels of a display device according to an embodiment of the present disclosure.

[0070] refer to Figure 3 Pixel PX can be connected to a first voltage line VDL, a data line DL, an initialization voltage line VIL, a scan line SCL, a sensing line SSL, and a second voltage line VSL. Pixel PX may include a first transistor ST1, a second transistor ST2, a third transistor ST3, a capacitor C1, and a light-emitting element ED.

[0071] The first transistor ST1 may include a gate electrode, a drain electrode, and a source electrode. The gate electrode of the first transistor ST1 may be connected to a first node N1, the drain electrode of the first transistor ST1 may be connected to a first voltage line VDL, and the source electrode of the first transistor ST1 may be connected to a second node N2. In an embodiment, the first transistor ST1 may control the drain-source current (e.g., drive current) based on the data voltage applied to the gate electrode.

[0072] The light-emitting element (ED) can receive a driving current to emit light. The amount or brightness of light emitted from the ED can be proportional to the magnitude of the driving current. In embodiments, the ED can be an organic light-emitting diode including an organic emitting layer, a quantum dot LED including a quantum dot emitting layer, a micro LED, or an inorganic LED including inorganic semiconductors. The first electrode of the ED can be connected to a second node N2, and the second electrode of the ED can be connected to a second voltage line VSL. The second electrode of the ED can receive a low-level voltage on the second voltage line VSL.

[0073] In one embodiment, the second transistor ST2 can be turned on by a scan signal from the scan line SCL to electrically connect the data line DL to the first node N1, which is the gate electrode of the first transistor ST1. The second transistor ST2 can be turned on in response to the scan signal to apply a data voltage to the first node N1. The gate electrode of the second transistor ST2 can be connected to the scan line SCL, the drain electrode can be connected to the data line DL, and the source electrode can be connected to the first node N1.

[0074] The third transistor ST3 can be turned on by a sensing signal from the sensing line SSL to electrically connect the initialization voltage line VIL to the second node N2, which is the source electrode of the first transistor ST1. In an embodiment, the third transistor ST3 can be turned on in response to the sensing signal to apply an initialization voltage to the second node N2. The third transistor ST3 can also be turned on in response to the sensing signal to provide a sensing signal to the initialization voltage line VIL.

[0075] Capacitor C1 can be connected between the first node N1 and the second node N2. Capacitor C1 can maintain the potential difference between the first node N1 and the second node N2.

[0076] Figure 4 This is a cross-sectional view showing a display device according to an embodiment of the present disclosure.

[0077] refer to Figure 4 In an embodiment, the display device 10 may include a substrate SUB, an emissive material layer EML (or a light-emitting element layer), an encapsulation layer TFEL, a filler layer FIL, a wavelength conversion layer WCL, a color filter layer CFL, a compensation layer CSL, an opposing substrate TSUB, and a sealing member SEL.

[0078] The substrate SUB can be a base substrate or a base member. The substrate SUB can be a rigid substrate. The substrate SUB can include a transparent insulating material. For example, in embodiments, the substrate SUB can include, but is not limited to, glass or metal materials. As another example, the substrate SUB can be a flexible substrate that can be bent, folded, or rolled. The substrate SUB can include a polymer resin such as polyimide (PI).

[0079] An emissive material layer (EML) can be disposed on a substrate (SUB). The EML may include pixel circuitry and light-emitting elements (EDs). The pixel circuitry may include multiple transistors to drive the EDs, and the EDs may emit light. In an embodiment, the EML may include scan lines (SCL), sensing lines (SSL), data lines (DL), initialization voltage lines (VIL), a first voltage line (VDL), and a second voltage line (VSL). Each of the transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. A scan driver (SIC) may be formed on the side of the non-display area (NDA) and may include multiple transistors.

[0080] The encapsulation layer TFEL can be disposed on the emissive material layer EML. The encapsulation layer TFEL may include at least one inorganic layer to prevent oxygen or moisture from penetrating into the light-emitting element ED. The encapsulation layer TFEL may also include at least one organic film to protect the light-emitting element ED from particles such as dust.

[0081] The opposing substrate TSUB can be opposite to the substrate SUB (e.g., opposite to the substrate SUB on a third-direction DR3). The opposing substrate TSUB can encapsulate the emissive material layer EML together with the substrate SUB. The opposing substrate TSUB can include a transparent material. For example, in an embodiment, the opposing substrate TSUB can include a transparent insulating material such as glass and quartz, and can transmit light emitted from the emissive material layer EML.

[0082] A color filter layer (CFL) can be disposed on the surface of the opposing substrate (TSUB) facing the substrate (SUB). The CFL can include multiple color filters. In an embodiment, each of the color filters selectively transmits light of a specific wavelength and blocks or absorbs light of other wavelengths. The CFL can absorb some of the light introduced from outside the display device 10 to reduce external light reflection. The CFL can also enhance the color characteristics of light emitted through the wavelength conversion layer (WCL).

[0083] A wavelength conversion layer (WCL) can be disposed on the surface of the color filter layer (CFL) facing the substrate (SUB). In embodiments, the wavelength conversion layer (WCL) can convert the wavelength of light emitted from the emissive material layer (EML) to emit red, green, and blue light. However, embodiments of this disclosure are not limited to this, and the color of the light converted by the wavelength conversion layer (WCL) can vary.

[0084] A compensation layer CSL can be disposed on the surface of the opposing substrate TSUB facing the substrate SUB. In an embodiment, the compensation layer CSL can be disposed at the edge of the opposing substrate TSUB and surround the color filter layer CFL and the wavelength conversion layer WCL. In another embodiment, the compensation layer CSL can be disposed at the edge of the opposing substrate TSUB where the color filter layer CFL and the wavelength conversion layer WCL are not disposed to reduce the horizontal difference, thereby stabilizing the structure of the display device 10. The compensation layer CSL may include at least one organic layer, but the constituent material of the compensation layer CSL is not limited to this.

[0085] The filler layer FIL can be disposed between the substrate SUB and the opposing substrate TSUB (for example, disposed between the substrate SUB and the opposing substrate TSUB on the third-direction DR3). The filler layer FIL can be used to fill the space between the substrate SUB and the opposing substrate TSUB to protect the display area DA of the display device 10.

[0086] The sealing member SEL connects the substrate SUB to the opposing substrate TSUB. The sealing member SEL seals the emissive material layer EML by connecting the substrate SUB to the opposing substrate TSUB. The sealing member SEL can be positioned along the edge of the non-display area NDA and can surround the display area DA.

[0087] Figure 5 This is a cross-sectional view showing in detail a display device according to an embodiment of the present disclosure.

[0088] refer to Figure 5 The emissive material layer (EML) can be disposed on the substrate (SUB). In an embodiment, the emissive material layer (EML) may include a buffer layer 120, a bottom metal layer (BML), a first insulating layer 130, a semiconductor layer (ACT), a gate insulator 140, a gate electrode (GE), a second insulating layer 150, a drain electrode (DE), a source electrode (SE), a third insulating layer 155, a fourth insulating layer 160, a light-emitting element (ED), and a pixel defining layer 170.

[0089] The buffer layer 120 may be disposed on the substrate SUB (e.g., directly disposed on the substrate SUB on the third-direction DR3). The buffer layer 120 may include an inorganic material that can prevent the penetration of air or moisture. For example, in an embodiment, the buffer layer 120 may include a plurality of inorganic films that are alternately stacked on top of each other (e.g., a plurality of inorganic films that are alternately stacked on the third-direction DR3).

[0090] The bottom metal layer BML can be disposed on the buffer layer 120 (e.g., directly on the buffer layer 120 on the third-direction DR3). The bottom metal layer BML can block external light from being introduced into the semiconductor layer ACT. The bottom metal layer BML can block light and reduce leakage current generated in the transistor.

[0091] The first insulating layer 130 may be disposed on the bottom metal layer BML. The first insulating layer 130 can insulate the bottom metal layer BML from the semiconductor layer ACT. The first insulating layer 130 may include an inorganic insulating material.

[0092] The semiconductor layer ACT can be disposed on the first insulating layer 130 (e.g., directly disposed on the first insulating layer 130 on the third-direction DR3). The semiconductor layer ACT can include the semiconductor region of a transistor. The semiconductor layer ACT can overlap with the bottom metal layer BML (e.g., overlap with the bottom metal layer BML on the third-direction DR3), and the bottom metal layer BML can suppress the generation of photocurrent in the semiconductor layer ACT.

[0093] The semiconductor layer ACT may include an oxide semiconductor. For example, in embodiments, the semiconductor layer ACT may be, but is not limited to, being made of zinc oxide, indium zinc oxide, gallium indium zinc oxide, or other zinc oxide-based materials, and may be an IGZO (In-Ga-Zn-O) semiconductor containing metals such as indium (In) and gallium (Ga) in ZnO. As another example, the semiconductor layer ACT may include amorphous silicon or polycrystalline silicon.

[0094] A gate insulator 140 may be disposed between the semiconductor layer ACT and the gate electrode GE (e.g., disposed on a third-direction DR3 between the semiconductor layer ACT and the gate electrode GE) to insulate the semiconductor layer ACT from the gate electrode GE. For example, in an embodiment, the gate insulator 140 may be composed of multiple layers and may have a partially patterned shape. The area of ​​the gate insulator 140 may be smaller than the area of ​​the semiconductor layer ACT and larger than the area of ​​the gate electrode GE, but the embodiments of this disclosure are not limited thereto. The gate insulator 140 may comprise an inorganic insulating material.

[0095] The gate electrode GE can be disposed on the gate insulator 140 (e.g., directly disposed on the gate insulator 140 on the third-direction DR3). The gate electrode GE can overlap with the semiconductor layer ACT (e.g., overlap with the semiconductor layer ACT on the third-direction DR3). For example, the gate electrode GE can receive a scan signal from the scan line SCL or a sensing signal from the sensing line SSL.

[0096] The second insulating layer 150 may be disposed on the gate electrode GE and cover the semiconductor layer ACT and the gate electrode GE. The second insulating layer 150 may have a flat top surface. For example, the second insulating layer 150 may comprise an organic insulating material or an inorganic insulating material.

[0097] The drain electrode DE and the source electrode SE can be spaced apart from each other on the second insulating layer 150. In an embodiment, the drain electrode DE and the source electrode SE can be connected to (e.g., directly connected to) the semiconductor layer ACT through contact holes penetrating the second insulating layer 150. The drain electrode DE can penetrate the second insulating layer 150 and the first insulating layer 130 to connect to the bottom metal layer BML.

[0098] A third insulating layer 155 may be disposed on the drain electrode DE and the source electrode SE to cover the transistor. For example, the third insulating layer 155 may be a passivation layer. In an embodiment, the third insulating layer 155 may include an inorganic insulating material.

[0099] The fourth insulating layer 160 may be disposed on the third insulating layer 155 to cover the third insulating layer 155. For example, the fourth insulating layer 160 may include an organic insulating material and may have a flat upper surface.

[0100] The light-emitting element ED can be disposed on the fourth insulating layer 160. In an embodiment, the light-emitting element ED may include a pixel electrode ANO, an emitting layer EL, and a common electrode CE.

[0101] The pixel electrode ANO may overlap with each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 (e.g., overlap with each of the first emission region EA1, the second emission region EA2, and the third emission region EA3 on the third-direction DR3), and at least a portion of the pixel electrode ANO may extend to the light-blocking region BA. The pixel electrode ANO may be connected to the source electrode SE of the transistor. For example, in an embodiment, the pixel electrode ANO may include at least one of aluminum (Al), silver (Ag), copper (Cu), nickel (Ni), and lanthanum (La). As another example, the pixel electrode ANO may include materials such as indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). As yet another example, the pixel electrode ANO may include multiple layers having a transparent conductive material layer and a highly reflective metal layer, or may include a single layer comprising a transparent conductive material and a highly reflective material. In an embodiment, the pixel electrode ANO may have a stacked structure such as ITO / Ag / ITO, ITO / Ag / IZO, or ITO / Ag / ITZO / ITO.

[0102] A pixel defining layer 170 may be disposed on a pixel electrode ANO. The pixel defining layer 170 may include an opening exposing the pixel electrode ANO to define a first emitting region EA1, a second emitting region EA2, and a third emitting region EA3. The pixel defining layer 170 may overlap with a dam BK and a light-blocking region BA on a third-direction DR3. The pixel defining layer 170 may include an organic insulating material.

[0103] The emitting layer EL can be disposed on the pixel electrode ANO. For example, the emitting layer EL can extend across the first emitting region EA1, the second emitting region EA2, and the third emitting region EA3, as well as the light-blocking region BA. The emitting layer EL can be disposed only in the display region DA, but embodiments of this disclosure are not limited thereto. In embodiments, the light-emitting element ED can emit light with a peak wavelength of 440 nm to 480 nm. The light emitted from the light-emitting element ED can be, but is not limited to, blue light.

[0104] For example, the emitter layer EL can be an organic emitter layer comprising organic materials. The emitter layer EL may include a hole transport layer, an organic emitter layer, and an electron transport layer. When the pixel electrode ANO receives voltage through a transistor and the common electrode CE receives a cathode voltage, holes can move through the hole transport layer to the organic emitter layer, and electrons can move through the electron transport layer to the organic emitter layer, causing holes and electrons to recombine in the organic emitter layer to emit light. For example, the pixel electrode ANO can be an anode electrode, and the common electrode CE can be a cathode electrode. However, it should be understood that the embodiments of this disclosure are not limited thereto.

[0105] As another example, the light-emitting element ED may include a micro light-emitting diode, a quantum dot light-emitting diode, each including a quantum dot emission layer, or an inorganic light-emitting diode, each including an inorganic semiconductor.

[0106] The common electrode CE can be disposed on the emitting layer EL. For example, the common electrode CE can be disposed on the emitting layer EL and can extend across the first emitting region EA1, the second emitting region EA2, the third emitting region EA3, and the light-blocking region BA. The common electrode CE can completely cover the emitting layer EL.

[0107] The common electrode CE can be translucent or transmissive. In embodiments where the thickness of the common electrode CE ranges from tens to hundreds of angstroms, the common electrode CE can be translucent. For example, if the common electrode CE is translucent, it can include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, Mo, Ti, or compounds thereof (e.g., LiF) or mixtures thereof (e.g., mixtures of Ag and Mg), or materials having a multilayer structure such as LiF / Ca or LiF / Al. As another example, the common electrode CE can include a transparent conductive oxide and can be transparent. In embodiments where the cathode electrode CE is transparent, the common electrode CE can be made of tungsten oxide (W). x O y It is formed from titanium oxide (TiO2), indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide, magnesium oxide (MgO), etc.

[0108] The encapsulation layer TFEL can be disposed on the emitting material layer EML. The encapsulation layer TFEL can be disposed on the common electrode CE (e.g., directly disposed on the common electrode CE on the third-direction DR3) to cover the light-emitting element ED. In an embodiment, the encapsulation layer TFEL may include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3 sequentially stacked on the common electrode CE (e.g., sequentially stacked on the common electrode CE on the third-direction DR3).

[0109] The first encapsulation layer TFE1 can be disposed on the common electrode CE (e.g., directly disposed on the common electrode CE on the third-party DR3). In embodiments, the first encapsulation layer TFE1 may include inorganic materials to prevent oxygen or moisture from penetrating into the emitter material layer EML. For example, the first encapsulation layer TFE1 may include, but is not limited to, at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, aluminum oxide, and amorphous silicon.

[0110] The second encapsulation layer TFE2 may be disposed on the first encapsulation layer TFE1 (e.g., directly disposed on the first encapsulation layer TFE1 on a third-party DR3) to provide a flat surface over the emissive material layer EML. In embodiments, the second encapsulation layer TFE2 may include an organic material to protect the emissive material layer EML from foreign matter such as dust. For example, the second encapsulation layer TFE2 may include an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin. In embodiments, the second encapsulation layer TFE2 may be formed by curing monomers or coating polymers.

[0111] The third encapsulation layer TFE3 may be disposed on the second encapsulation layer TFE2 (e.g., directly disposed on the second encapsulation layer TFE2 on the third-direction DR3). In embodiments, the third encapsulation layer TFE3 may include an inorganic material to prevent oxygen or moisture from penetrating into the emitter material layer EML. For example, the third encapsulation layer TFE3 may be made of the materials listed above that serve as the material of the first encapsulation layer TFE1.

[0112] The opposing substrate TSUB can be opposite to the substrate SUB (e.g., opposite to the substrate SUB on a third-party DR3). The opposing substrate TSUB can encapsulate the emissive material layer EML together with the substrate SUB. The opposing substrate TSUB may include transparent material.

[0113] A color filter layer (CFL) can be disposed on the surface of the opposing substrate (TSUB) facing the substrate (SUB). In an embodiment, the color filter layer (CFL) may include a first color filter 321, a second color filter 322, and a third color filter 323. The first color filter 321 selectively transmits a first light and blocks or absorbs a second and a third light. The second color filter 322 selectively transmits a second light and blocks or absorbs a first and a third light. The third color filter 323 selectively transmits a third light and blocks or absorbs a first and a second light.

[0114] In an embodiment, the first color filter 321 may be a blue color filter and may include a blue colorant. Herein, colorant encompasses both dyes and pigments. The first color filter 321 may include a base resin, and the blue colorant may be dispersed in the base resin. For example, the second color filter 322 may be a red color filter and may include a red colorant. The second color filter 322 may include a base resin, and the red colorant may be dispersed in the base resin. For example, the third color filter 323 may be a green color filter and may include a green colorant. The third color filter 323 may include a base resin, and the green colorant may be dispersed in the base resin.

[0115] The first color filter 321 may include a first filtering region 321a and a first light-blocking region 321b surrounding (e.g., surrounding in a plan view) the first filtering region 321a. The first filtering region 321a may overlap with a first emitting region EA1 on a third-direction DR3. The first light-blocking region 321b may surround the first filtering region 321a that overlaps with the first emitting region EA1, may not overlap with a second emitting region EA2 or a third emitting region EA3, and may overlap with a light-blocking region BA. In an embodiment, the first filtering region 321a of the first color filter 321 may be a blocking filter that blocks red and green light.

[0116] The second color filter 322 may include a second filtering region 322a and a second light-blocking region 322b surrounding (e.g., surrounding in a plan view) the second filtering region 322a. The second filtering region 322a may overlap with the second emitting region EA2 on a third-direction DR3. The second light-blocking region 322b may surround the second filtering region 322a that overlaps with the second emitting region EA2, may not overlap with the first emitting region EA1 or the third emitting region EA3, and may overlap with the light-blocking region BA. In an embodiment, the second filtering region 322a of the second color filter 322 can be used as a blocking filter to block blue and green light.

[0117] The third color filter 323 may include a third filtering region 323a and a third light-blocking region 323b surrounding (e.g., surrounding in a plan view) the third filtering region 323a. The third filtering region 323a may overlap with the third emission region EA3 on the third-direction DR3. The third light-blocking region 323b may surround the third filtering region 323a that overlaps with the third emission region EA3, may not overlap with the first emission region EA1 or the second emission region EA2, and may overlap with the light-blocking region BA. In an embodiment, the third filtering region 323a of the third color filter 323 may be used as a blocking filter to block blue and red light.

[0118] The light-blocking pattern BM can have a structure in which the first light-blocking region 321b of the first color filter 321, the second light-blocking region 322b of the second color filter 322, and the third light-blocking region 323b of the third color filter 323 are stacked on top of each other. Alternatively, the light-blocking pattern BM can be formed via a coating process and an exposure process of individual organic light-blocking materials. The light-blocking pattern BM can absorb all of the first through third light.

[0119] The low-refractive-index layer LR and the first capping layer CPL1 can be disposed between the color filter layer CFL and the wavelength conversion layer WCL (e.g., disposed on the third-direction DR3 between the color filter layer CFL and the wavelength conversion layer WCL). The low-refractive-index layer LR has a lower refractive index than the first transparent member TPL, the second transparent member WCL1, and the third transparent member WCL2, and therefore induces total internal reflection of light traveling from the first transparent member TPL, the second transparent member WCL1, and the third transparent member WCL2 to the low-refractive-index layer LR, thereby allowing light to be recovered.

[0120] The low-refractive-index layer LR may comprise an organic material. For example, in an embodiment, the refractive index of the low-refractive-index layer LR may be less than or equal to about 1.3. Using a low-refractive-index layer LR having a refractive index less than or equal to about 1.3, sufficient total internal reflection can occur because the differences in refractive index between the first transparent member TPL, the second transparent member WCL1, and the third transparent member WCL2 and the low-refractive-index layer LR are large.

[0121] Furthermore, the low-refractive-index layer LR can cover the horizontal difference created by the light-blocking regions 321b, 322b, and 323b of the color filter layer CFL to provide a flat surface. Accordingly, the first capping layer CPL1 can be formed flat on the surface of the low-refractive-index layer LR.

[0122] The first capping layer CPL1 can be disposed between the low refractive layer LR and the wavelength conversion layer WCL to cover the low refractive layer LR. The first capping layer CPL1 can prevent impurities such as moisture and air from penetrating from the outside (e.g., the external environment) into the low refractive layer LR or the color filter layer CFL, thereby damaging or contaminating the low refractive layer LR and the color filter layer CFL.

[0123] The first capping layer CPL1 may include inorganic materials. For example, the first capping layer CPL1 may be, but is not limited to, materials containing, for example, SiO2 or SiN. x It is made by forming at least one layer of inorganic material, SiON.

[0124] The wavelength conversion layer WCL can be disposed between the first capping layer CPL1 and the filler layer FIL (e.g., disposed between the first capping layer CPL1 and the filler layer FIL on a third-direction DR3). In an embodiment, the wavelength conversion layer WCL may include a dam BK, a first transparent member TPL, a second transparent member WCL1, a third transparent member WCL2, and a second capping layer CPL2.

[0125] A dam BK may be disposed on the surface of the first capping layer CPL1 facing the substrate SUB to form a space for accommodating each of the first transparent member TPL, the second transparent member WCL1, and the third transparent member WCL2. The dam BK may define the space where the first transparent member TPL, the second transparent member WCL1, and the third transparent member WCL2 are disposed. In other words, the dam BK may define the first transparent member TPL, the second transparent member WCL1, and the third transparent member WCL2. When viewed from above, the dam BK may surround the first transparent member TPL, the second transparent member WCL1, and the third transparent member WCL2. The dam BK may overlap with the light-blocking region BA and may not overlap with any of the first emitting region EA1, the second emitting region EA2, and the third emitting region EA3. For example, the dam BK may include, but is not limited to, a photocurable organic material or a photocurable organic material containing a light-blocking material.

[0126] The first transparent member TPL can be disposed in the space defined by the embankment BK and can overlap with the first emission region EA1 on the third direction DR3. The upper surface of the first transparent member TPL can be in direct contact with the first capping layer CPL1, and the side surface (e.g., the lateral side surface) of the first transparent member TPL can be in direct contact with the embankment BK.

[0127] The first transparent member TPL can be a light-transmitting pattern that transmits incident light. The first transparent member TPL can transmit light of a first color emitted from the emissive material layer EML as is. For example, in an embodiment, the light emitted from the light-emitting element ED can be blue light, and this light can be output to the outside of the display device 10 through the first transparent member TPL and the first filtering area 321a of the first color filter 321. Correspondingly, the first light L1 emitted to the outside from the first emitting area EA1 can be blue light.

[0128] In an embodiment, the first transparent component TPL may include a base resin 330 and a light diffuser 331. The base resin 330 may include an organic material with high light transmittance. For example, the base resin 330 may include, but is not limited to, organic materials such as epoxy resin, acrylic resin, calorie resin, and imide resin.

[0129] The light scatterer 331 may have a refractive index different from that of the base resin 330 and may form an optical interface with the base resin 330. The light scatterer 331 may be a light scattering particle. The light scatterer 331 may scatter light in random directions regardless of the direction in which the incident light enters, without substantially changing the wavelength of the light transmitted from the first emission region EA1.

[0130] The light scatterer 331 can be a material that scatters at least a portion of the transmitted light, and may comprise metal oxide particles or organic particles. For example, the light scatterer 331 may comprise metal oxides such as titanium dioxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO), and tin oxide (SnO2), and may comprise organic particles such as acrylic resins and urethane resins. However, it should be understood that the embodiments of this disclosure are not limited thereto.

[0131] The second transparent member WCL1 can be disposed in the space defined by the embankment BK and can overlap with the second emission region EA2 on the third direction DR3. The upper surface of the second transparent member WCL1 can be in direct contact with the first capping layer CPL1, and the side surface of the second transparent member WCL1 can be in direct contact with the embankment BK.

[0132] The second transparent member WCL1 can convert or shift the peak wavelength of the incident light to another peak wavelength to output light of that other peak wavelength. The second transparent member WCL1 can also convert light of a first color emitted from the emitting material layer EML into light of a second color to output that light. For example, in an embodiment, the light emitted from the light-emitting element ED can be blue light, and this blue light can be converted into red light with a peak wavelength in the approximate range of 610 nm to 650 nm by the second transparent member WCL1 and the second filtering region 322a of the second color filter 322. Accordingly, the second light L2 emitted from the second emitting region EA2 to the outside can be red light.

[0133] The second transparent component WCL1 may include a base resin 330, a light scatterer 331 dispersed in the base resin 330, and a first wavelength shifter 332 dispersed in the base resin 330.

[0134] The first wavelength shifter 332 can convert or shift the peak wavelength of the incident light to another peak wavelength. In an embodiment, the first wavelength shifter 332 can convert blue light output from the light-emitting element ED into red light with a peak wavelength in the range of approximately 610 nm to 650 nm, so that red light is emitted.

[0135] For example, the first wavelength shifter 332 can be, but is not limited to, a quantum dot, a quantum rod, or a phosphor. In the following description, the first wavelength shifter 332 is a quantum dot. A quantum dot can be a particulate material that emits light of a certain color when an electron transitions from the conduction band to the valence band. A quantum dot can be a semiconductor nanocrystal material. Depending on the composition and size of the quantum dot, it has a specific band gap and can absorb light and emit light with an inherent wavelength. Examples of semiconductor nanocrystals of quantum dots can include group IV element or compound nanocrystals, group II-VI compound nanocrystals, group III-V compound nanocrystals, group IV-VI nanocrystals, or combinations thereof.

[0136] In this embodiment, the light output from the first wavelength shifter 332 may have a full width at half maximum (FWHM) of an emission wavelength spectrum of approximately 45 nm or less, approximately 40 nm or less, or approximately 30 nm or less. Accordingly, the color purity and color gamut of the colors displayed by the display device 10 can be further improved. The light output from the first wavelength shifter 332 may travel in different directions regardless of the incident direction of the incident light. Accordingly, the first wavelength shifter 332 can improve the lateral visibility of the second color displayed in the second emission region EA2.

[0137] A portion of the light emitted from the light-emitting element ED can be transmitted through the second transparent member WCL1 and emitted without being converted into red light by the first wavelength shifter 332. The component of light whose wavelength is not converted by the second transparent member WCL1 and incident on the second filtering region 322a of the second color filter 322 can be blocked by the second filtering region 322a. On the other hand, the red light converted by the second transparent member WCL1 can be transmitted through the second filtering region 322a and emitted to the outside. The third transparent member WCL2 can be disposed in the space defined by the dam BK and can overlap with the third emitting region EA3 on the third direction DR3. In an embodiment, the upper surface of the third transparent member WCL2 can be in direct contact with the first capping layer CPL1, and the side surface of the third transparent member WCL2 can be in direct contact with the dam BK.

[0138] The third transparent component WCL2 can convert or shift the peak wavelength of the incident light to another peak wavelength to output light of that other peak wavelength. For example, in an embodiment, the light emitted from the light-emitting element ED can be blue light, and this blue light can be converted into green light with a peak wavelength in the range of approximately 510 nm to 550 nm by the third transparent component WCL2 and the third filtering region 323a of the third color filter 323. Accordingly, the third light L3 emitted from the third emission region EA3 to the outside can be green light.

[0139] The third transparent component WCL2 may include a base resin 330, a light scatterer 331 dispersed in the base resin 330, and a second wavelength shifter 333 dispersed in the base resin 330.

[0140] The second wavelength shifter 333 can convert or shift the peak wavelength of the incident light to another peak wavelength. The second wavelength shifter 333 can convert blue light output from the light-emitting element ED into green light with a peak wavelength in the range of approximately 510 nm to 550 nm, causing green light to be emitted. For example, the second wavelength shifter 333 can be, but is not limited to, quantum dots, quantum rods, or phosphors. The second wavelength shifter 333 for quantum dots can have substantially the same configuration as the first wavelength shifter 332 for quantum dots described above; and therefore, for the sake of brevity, redundant descriptions can be omitted.

[0141] A portion of the light emitted from the light-emitting element (ED) can pass through the third transparent member WCL2 and exit without being converted into green light by the second wavelength shifter 333. The component of light incident on the third filtering region 323a of the third color filter 323, whose wavelength is not converted by the third transparent member WCL2, can be blocked by the third filtering region 323a. On the other hand, the green light converted by the third transparent member WCL2 can pass through the third filtering region 323a and exit to the outside.

[0142] The second sealing layer CPL2 can be disposed below the dike BK, the first transparent member TPL, the second transparent member WCL1, and the third transparent member WCL2 (e.g., directly below the dike BK, the first transparent member TPL, the second transparent member WCL1, and the third transparent member WCL2 in the direction opposite to the third direction DR3) to prevent impurities such as moisture and air from penetrating from the outside and damaging or contaminating the first transparent member TPL, the second transparent member WCL1, and the third transparent member WCL2. The second sealing layer CPL2 can cover the first transparent member TPL, the second transparent member WCL1, and the third transparent member WCL2.

[0143] The spacer layer SPC can be disposed on the lower surface of the second capping layer CPL2 (e.g., directly disposed on the lower surface of the second capping layer CPL2 in a direction opposite to the third direction DR3). The spacer layer SPC can maintain the cell gap between the substrate SUB and the opposing substrate TSUB. When viewed from above, the spacer layer SPC can surround the first transparent member TPL, the second transparent member WCL1, and the third transparent member WCL2. The spacer layer SPC can overlap with the light-blocking region BA, and can not overlap with any of the first emitting region EA1, the second emitting region EA2, and the third emitting region EA3.

[0144] In the embodiments, the spacer layer SPC may include, but is not limited to, a transparent organic material with photocurability or an organic material with photocurability and containing a light-blocking material. For example, the spacer layer SPC may be made of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, and perylene resin.

[0145] The filler layer FIL can be disposed between the opposing substrate TSUB and the substrate SUB (e.g., disposed between the opposing substrate TSUB and the substrate SUB on a third-direction DR3). The filler layer FIL can be located between the wavelength conversion layer WCL and the encapsulation layer TFEL to fill the space between the wavelength conversion layer WCL and the encapsulation layer TFEL. For example, the filler layer FIL can be in direct contact with the third encapsulation layer TFE3 of the encapsulation layer TFEL and the second capping layer CPL2 of the wavelength conversion layer WCL. However, it should be understood that the embodiments disclosed herein are not limited to this.

[0146] Figure 6 According to embodiments of this disclosure Figure 1 A magnified view of region A1.

[0147] refer to Figure 6 In this embodiment, the display area DA may include a first pixel PX1, a second pixel PX2, and a third pixel PX3, as well as a display transmissive area DTA. The first pixel PX1 can be... Figure 5 The first emission area EA1 emits the first light L1. The second pixel PX2 can... Figure 5 The second emission region EA2 emits the second light L2. The third pixel PX3 can... Figure 5 The third emission region EA3 emits the third beam L3.

[0148] The display transmissive region DTA can be located on the sides of the first pixel PX1, the second pixel PX2, and the third pixel PX3. In an embodiment, the first pixel PX1, the second pixel PX2, and the third pixel PX3 can be adjacent to each other in the second direction DR2. The display transmissive region DTA can be adjacent to the first pixel PX1, the second pixel PX2, and the third pixel PX3 in the first direction DR1. In an embodiment, the area of ​​the display transmissive region DTA (e.g., the area in a planar view) can be greater than the sum of the areas of the first pixel PX1, the second pixel PX2, and the third pixel PX3 (e.g., the sum of the areas in a planar view).

[0149] In this embodiment, the display transmissive region DTA may not include transistors, light-emitting elements (EDs), signal lines, or voltage lines. The display transmissive region DTA can transmit light incident on the surface of the display device 10 to the opposite surface of the display device 10 as is. Accordingly, since the display device 10 includes the display transmissive region DTA disposed in the display area DA, a transparent display panel can be realized.

[0150] In an embodiment, the non-display area NDA may include a first non-display area NDA1, a second non-display area NDA2, a third non-display area NDA3, and a fourth non-display area NDA4, and the third non-display area NDA3 may be located to the left of the display area DA (for example, to the left of the display area DA in a direction opposite to the first direction DR1).

[0151] In this embodiment, the third non-display area NDA3 may include a scan driver SIC, a non-display transmissive area NTA, and an anti-static element ESD. The scan driver SIC may include a scan circuit SCU and a scan line area SLU.

[0152] The scanning circuit SCU can be located to the left of the display area DA (e.g., to the left of the display area DA in a direction opposite to the first direction DR1). The scanning circuit SCU can include a buffer circuit and multiple transistors. The scanning circuit SCU can receive a clock signal, a scan input signal, and a carry signal, and output a scan signal and a sensing signal. In an embodiment, the transistors and buffer circuit of the scanning circuit SCU can be disposed in the same layer as the bottom metal layer BML, the semiconductor layer ACT, the gate layer, and the source metal layer. The gate layer may include... Figure 5 The gate electrode GE, and the source metal layer may include Figure 5 The drain electrode DE and the source electrode SE.

[0153] The second voltage line VSL can be positioned to the left of the scanning circuit SCU (e.g., to the left of the scanning circuit SCU in a direction opposite to the first direction DR1). The second voltage line VSL can be... Figure 5 The pixel electrodes ANO are disposed in the same layer, but embodiments of this disclosure are not necessarily limited thereto. In embodiments, the second voltage line VSL may include multiple vias, and Figure 5 The fourth insulating layer 160 and the pixel defining layer 170 can be in direct contact with each other through holes in the second voltage line VSL. The second voltage line VSL can be arranged along the first non-display area NDA1, the second non-display area NDA2, the third non-display area NDA3, and the fourth non-display area NDA4 to surround the display area DA (e.g., surrounding the display area DA in a plan view), such that the second voltage line VSL is spaced apart from the display area DA. The second voltage line VSL can be a low-level voltage line. The second voltage line VSL disposed in the non-display area NDA can receive a low-level voltage and can be electrically connected to the common electrode CE of the display area DA.

[0154] The bridge contact BRG can be located on the left side of the scanning circuit SCU. The bridge contact BRG can be in direct contact with the source metal layer, the second voltage line VSL, and the common electrode CE. Accordingly, in an embodiment, the common electrode CE can extend beyond the display area DA to reach the non-display area NDA, and can receive a low-level voltage from the second voltage line VSL through the bridge contact BRG.

[0155] The scan line region SLU can be located to the left of the scan circuit SCU (e.g., to the left of the scan circuit SCU in a direction opposite to the first direction DR1). In an embodiment, the scan line region SLU may include a clock line CKL, a scan input line SIL, and a carry line CRL.

[0156] The clock line CKL can be positioned to the left of the scan line region SLU (e.g., to the left of the scan line region SLU in the direction opposite to the first direction DR1). The clock line CKL can also be positioned between the non-display transmissive region NTA and the scan input line SIL (e.g., between the non-display transmissive region NTA and the scan input line SIL on the first direction DR1). The clock line CKL can comprise multiple lines extending longitudinally in the second direction DR2 and spaced apart from each other on the first direction DR1. The clock line CKL can provide (e.g., transmit) the clock signal received from the flexible film FPC to the scan circuit SCU.

[0157] The cathode edge CEG can be positioned between clock lines CKL (e.g., positioned between clock lines CKL in the first direction DR1). The common electrode CE can extend beyond the display area DA to the non-display area NDA of the cathode edge CEG. The cathode edge CEG may not overlap with any of the clock lines CKL (e.g., not overlap with any of the clock lines CKL in a plan view).

[0158] The scan input line SIL can be positioned to the right of the clock line CKL (e.g., to the right of the clock line CKL on the first direction DR1). The scan input line SIL can also be positioned between the clock line CKL and the carry line CRL (e.g., between the clock line CKL and the carry line CRL on the first direction DR1). The scan input line SIL can comprise multiple lines extending longitudinally in the second direction DR2 and spaced apart from each other on the first direction DR1. The scan input line SIL can provide the scan input signal received from the flexible film FPC to the scan circuit SCU.

[0159] The carry line CRL can be positioned to the right of the scan input line SIL (e.g., to the right of the scan input line SIL on the first direction DR1). The carry line CRL can also be positioned between the scan input line SIL and the scan circuit SCU (e.g., between the scan input line SIL and the scan circuit SCU on the first direction DR1). The carry line CRL can comprise multiple lines extending longitudinally in the second direction DR2 and spaced apart from each other in the first direction DR1. The carry line CRL can provide the carry signal received in the preceding stage of the scan circuit SCU to the following stage of the scan circuit SCU.

[0160] The non-display transmissive region NTA may be located between the anti-static element ESD and the scan line region SLU (e.g., between the anti-static element ESD and the scan line region SLU in the first direction DR1). The non-display transmissive region NTA may not include metal layers, transistors, signal lines, or voltage lines. The non-display transmissive region NTA can transmit light incident on the surface of the display device 10 to the opposite surface of the display device 10 as is. In embodiments, the area of ​​the non-display transmissive region NTA (e.g., the area in a plan view) may be larger than the area of ​​the scan circuit SCU (e.g., the area in a plan view) or the area of ​​the anti-static element ESD (e.g., the area in a plan view). For example, the width of the non-display transmissive region NTA in the first direction DR1 may be larger than the width of the scan circuit SCU in the first direction DR1 or the width of the anti-static element ESD in the first direction DR1, and the lengths of each of the non-display transmissive region NTA, the scan circuit SCU, and the anti-static element ESD in the second direction DR2 may be the same or approximately the same as each other. In this embodiment, the width of the non-display transmissive region NTA in the first direction DR1 can be greater than the width of a display transmissive region DTA corresponding to the first pixel PX1, the second pixel PX2, and the third pixel PX3 in the first direction DR1. Accordingly, since the display device 10 includes a non-display transmissive region NTA disposed in the non-display region NTA and having a predetermined area, high-density metallic patterns in the non-display region NTA can be avoided, making the non-display region NTA less noticeable. As a result, a transparent display panel can be realized.

[0161] The ESD protection element can be located at the outermost part of the non-display area NDA (e.g., at the outermost part of the non-display area NDA in a direction opposite to the first direction DR1). The ESD protection element can be combined with... Figure 4 The sealing member SEL overlaps. An anti-static element (ESD) can be disposed on the left side of the non-display transmissive region NTA (e.g., on the left side of the non-display transmissive region NTA in a direction opposite to the first direction DR1). The ESD can be arranged along the first non-display region NDA1, the second non-display region NDA2, the third non-display region NDA3, and the fourth non-display region NDA4 to surround the display region DA (e.g., surrounding the display region DA in a plan view), such that the ESD is spaced apart from the display region DA. The ESD can prevent static electricity from being introduced into the display device 10 by eliminating static electricity introduced from the outside. In an embodiment, the ESD can be disposed in the same layer as the bottom metal layer BML and the gate layer, but the embodiments of this disclosure are not limited to this.

[0162] Figure 7 This illustrates an embodiment according to the present disclosure. Figure 6A magnified view of a portion of it.

[0163] refer to Figure 7 The non-display area NDA may include a dummy pixel DPX. The dummy pixel DPX of the third non-display area NDA3 may be located to the left of the pixel PX located on the left side of the display area DA. In an embodiment, the dummy pixel DPX may include a first dummy pixel DPX1, a second dummy pixel DPX2, and a third dummy pixel DPX3. Because... Figure 5 Therefore, the first dummy pixel DPX1, the second dummy pixel DPX2, and the third dummy pixel DPX3 can have the same shape as the first pixel PX1, the second pixel PX2, and the third pixel PX3 (e.g., the same shape in a planar view). In an embodiment, similar to the first pixel PX1, the second pixel PX2, and the third pixel PX3, the first dummy pixel DPX1, the second dummy pixel DPX2, and the third dummy pixel DPX3 may include a first color filter 321, a second color filter 322, and a third color filter 323, as well as a first transparent member TPL, a second transparent member WCL1, and a third transparent member WCL2. Unlike the first pixel PX1, the second pixel PX2, and the third pixel PX3, the first dummy pixel DPX1, the second dummy pixel DPX2, and the third dummy pixel DPX3 may not include a light-emitting element ED. Accordingly, the first dummy pixel DPX1, the second dummy pixel DPX2, and the third dummy pixel DPX3 may not emit light. The first dummy pixel DPX1, the second dummy pixel DPX2, and the third dummy pixel DPX3 can overlap with the scanning circuit SCU.

[0164] The compensation layer CSL may overlap with the second voltage line VSL, the scan line region SLU, and the non-display transmissive region NTA. In some embodiments, the compensation layer CSL may extend (e.g., in a direction opposite to the first direction DR1) beyond the scan line region SLU to reach the non-display transmissive region NTA. The compensation layer CSL may surround (e.g., in a plan view) the first dummy pixel DPX1, the second dummy pixel DPX2, and the third dummy pixel DPX3. The compensation layer CSL may be disposed at the edge of the opposing substrate TSUB and surround the color filter layer CFL and the wavelength conversion layer WCL. In an embodiment, the compensation layer CSL may be disposed at the edge of the opposing substrate TSUB where the color filter layer CFL and the wavelength conversion layer WCL are not disposed to reduce the horizontal difference, thereby stabilizing the structure of the display device 10. In an embodiment, the compensation layer CSL may include at least one organic layer, but the constituent material of the compensation layer CSL is not limited to this.

[0165] Figure 8 According to embodiments of this disclosure Figure 1 A magnified view of region A2.

[0166] refer to Figure 8 The display area DA may include a first pixel PX1, a second pixel PX2, and a third pixel PX3, as well as a display transmissive area DTA. The display transmissive area DTA may be located on the sides (e.g., lateral sides) of the first pixel PX1, second pixel PX2, and third pixel PX3. In an embodiment, the first pixel PX1, second pixel PX2, and third pixel PX3 may be adjacent to each other in a second direction DR2. The display transmissive area DTA may be adjacent to the first pixel PX1, second pixel PX2, and third pixel PX3 in a first direction DR1 and in a direction opposite to the first direction DR1. The area of ​​the display transmissive area DTA (e.g., the area in a planar view) may be greater than the sum of the areas of the first pixel PX1, second pixel PX2, and third pixel PX3 (e.g., the sum of their areas in a planar view).

[0167] In this embodiment, the display transmissive region DTA may not include transistors, light-emitting elements (EDs), signal lines, or voltage lines. The display transmissive region DTA can transmit light incident on the surface of the display device 10 to the opposite surface of the display device 10 as is. Accordingly, since the display device 10 includes the display transmissive region DTA disposed in the display area DA, a transparent display panel can be realized.

[0168] In an embodiment, the non-display area NDA may include a first non-display area NDA1, a second non-display area NDA2, a third non-display area NDA3, and a fourth non-display area NDA4, and the second non-display area NDA2 may be located above the display area DA (for example, above the display area DA in the second direction DR2).

[0169] In this embodiment, the second non-display area NDA2 may include a non-display transmissive area NTA, a second voltage line VSL, a voltage connection line CVSL, and an anti-static component ESD. The non-display transmissive area NTA may include a first non-display transmissive area NTA1, a second non-display transmissive area NTA2, and a third non-display transmissive area NTA3.

[0170] The first non-display transmissive region NTA1 can be directly adjacent to the upper side of the display region DA (e.g., adjacent to the upper side of the display region DA in the second direction DR2). The first non-display transmissive region NTA1 can be disposed between the display region DA and the second voltage line VSL (e.g., disposed between the display region DA and the second voltage line VSL in the second direction DR2). The first non-display transmissive region NTA1 may not include transistors, signal lines, or voltage lines. The first non-display transmissive region NTA1 can transmit light incident on the surface of the display device 10 to the opposite surface of the display device 10 as is. The area of ​​a first non-display transmissive region NTA1 surrounded by multiple voltage connection lines CVSL, the second voltage line VSL, and the display region DA (e.g., the area in a plan view) can be larger than the area of ​​a display transmissive region DTA (e.g., the area in a plan view). Accordingly, since the display device 10 includes a first non-display transmissive region NTA1 directly adjacent to the display region DA, high-density metallic patterns in the non-display region NDA can be avoided, making the non-display region NDA less noticeable. As a result, a transparent display panel can be realized.

[0171] The second voltage line VSL or the first low-level voltage line can be disposed above the first non-display transmissive region NTA1 (e.g., disposed above the first non-display transmissive region NTA1 in the second direction DR2). In an embodiment, the second voltage line VSL can be... Figure 5 The pixel electrodes ANO are disposed in the same layer, but embodiments of this disclosure are not necessarily limited thereto. The second voltage line VSL may include multiple vias, and Figure 5 The fourth insulating layer 160 and the pixel defining layer 170 can be in direct contact with each other through the holes in the second voltage line VSL. The second voltage line VSL, which overlaps with the bridge contact BRG, can be connected to... Figure 6 The second voltage line VSL is arranged along the first non-display area NDA1, the second non-display area NDA2, the third non-display area NDA3, and the fourth non-display area NDA4 to surround the display area DA (e.g., around the display area DA in a plan view), such that the second voltage line VSL is spaced apart from the display area DA. The second voltage line VSL disposed in the non-display area NDA can receive a low-level voltage and can be electrically connected to the common electrode CE of the display area DA.

[0172] The bridge contact BRG can overlap with the second voltage line VSL. The bridge contact BRG can be disposed between the first non-display transmissive region NTA1 and the second non-display transmissive region NTA2. The bridge contact BRG can contact the source metal layer, the second voltage line VSL, and the common electrode CE. Accordingly, the common electrode CE can extend beyond the display region DA to reach the non-display region NDA, and can receive a low-level voltage from the second voltage line VSL through the bridge contact BRG.

[0173] The second non-display transmissive region NTA2 can be disposed between the first non-display transmissive region NTA1 and the third non-display transmissive region NTA3 (e.g., disposed between the first non-display transmissive region NTA1 and the third non-display transmissive region NTA3 in the second direction DR2). The second non-display transmissive region NTA2 can be disposed between the second voltage lines VSL. In an embodiment, the second voltage line VSL disposed on the lower side of the second non-display transmissive region NTA2 can extend to the first non-display transmissive region NTA1, and the second voltage line VSL disposed on the upper side of the second non-display transmissive region NTA2 can not extend to the third non-display transmissive region NTA3. The second non-display transmissive region NTA2 may not include transistors, signal lines, or voltage lines. The second non-display transmissive region NTA2 can transmit light incident on the surface of the display device 10 to the opposite surface of the display device 10 as is. The area of ​​a second non-display transmissive region NTA2 surrounded by the second voltage line VSL and multiple voltage connection lines CVSL (e.g., the area in a plan view) can be larger than the area of ​​a first non-display transmissive region NTA1 (e.g., the area in a plan view). The width of a second non-display transmissive region NTA2 in the second direction DR2 can be greater than the width of a first non-display transmissive region NTA1 in the second direction DR2, while the lengths of each of the second non-display transmissive region NTA2 and the first non-display transmissive region NTA1 in the first direction DR1 can be the same or approximately the same. Accordingly, since the display device 10 includes the second non-display transmissive region NTA2, high-density metallic patterns in the non-display region NDA can be avoided, making the non-display region NDA less noticeable. As a result, a transparent display panel can be realized.

[0174] The cathode edge CEG can overlap with the second non-display transmission region NTA2. In an embodiment, the common electrode CE can extend beyond the display region DA to the cathode edge CEG of the non-display region NDA. The common electrode CE can overlap with more than half of the second non-display transmission region NTA2.

[0175] A second voltage line VSL or a second low-level voltage line can be disposed between the second non-display transmissive region NTA2 and the third non-display transmissive region NTA3 (e.g., disposed between the second non-display transmissive region NTA2 and the third non-display transmissive region NTA3 on the second direction DR2). In an embodiment, the second voltage line VSL can be... Figure 5 The drain electrode DE and source electrode SE are disposed in the same layer, but embodiments of this disclosure are not necessarily limited thereto. The second voltage line VSL may overlap with a partition or dam defining the edge of the encapsulation layer TFEL. The second voltage line VSL overlapping with a partition or dam may not extend to the third non-display area NDA3. The second voltage line VSL may receive a low-level voltage and may be electrically connected to the common electrode CE of the display area DA via a voltage connection line CVSL.

[0176] The third non-display transmissive region NTA3 can be disposed between the second voltage line VSL and the anti-static element ESD (e.g., disposed on the second direction DR2 between the second voltage line VSL and the anti-static element ESD). The third non-display transmissive region NTA3 may not include a metal layer, transistor, signal line, or voltage line. The third non-display transmissive region NTA3 can transmit light incident on the surface of the display device 10 to the opposite surface of the display device 10 as is. In an embodiment, the width of a third non-display transmissive region NTA3 surrounded by multiple voltage connection lines CVSL, the second voltage line VSL, and the anti-static element ESD on the second direction DR2 can be greater than the width of a second non-display transmissive region NTA2 on the second direction DR2, while the lengths of each of the second non-display transmissive region NTA2 and the third non-display transmissive region NTA3 on the first direction DR1 can be the same or approximately the same. Therefore, the area of ​​the third non-display transmissive region NTA3 (e.g., the area in a plan view) can be greater than the area of ​​the second non-display transmissive region NTA2 (e.g., the area in a plan view). For example, the second non-display area NDA2 may include a plurality of non-display transmissive areas such as the first to third non-display transmissive areas NTA1 to NTA3, which may have a correspondingly increased area towards the outer portion of the second non-display area NDA2 in a plan view. Accordingly, since the display device 10 includes the third non-display transmissive area NTA3, high-density metallic patterns in the non-display area NDA can be avoided, making the non-display area NDA less noticeable. As a result, a transparent display panel can be realized.

[0177] The ESD protection element can be located at the outermost part of the non-display area NDA (e.g., at the outermost part of the non-display area NDA on the second direction DR2). The ESD protection element can be combined with... Figure 4The sealing member SEL overlaps. An anti-static element (ESD) can be disposed above the third non-display transmissive region NTA3 (e.g., disposed above the third non-display transmissive region NTA3 in the second direction DR2). The ESD element can be arranged along the first non-display region NDA1, the second non-display region NDA2, the third non-display region NDA3, and the fourth non-display region NDA4 to surround the display region DA (e.g., surrounding the display region DA in a plan view), such that the ESD element is spaced apart from the display region DA. The ESD element prevents static electricity from being introduced into the display device 10 by eliminating static electricity introduced from the outside. In an embodiment, the ESD element can be disposed in the same layer as the bottom metal layer BML and the gate layer, but the embodiments of this disclosure are not limited to this.

[0178] Figure 9 According to embodiments of this disclosure Figure 8 A magnified view of a portion of it.

[0179] refer to Figure 9 In an embodiment, the non-display area NDA may include a dummy pixel DPX. The dummy pixel DPX of the second non-display area NDA2 may be disposed above the pixel PX disposed on the upper side in the display area DA. In an embodiment, the dummy pixel DPX may include a first dummy pixel DPX1, a second dummy pixel DPX2, and a third dummy pixel DPX3. In an embodiment, since... Figure 5 Therefore, the first dummy pixel DPX1, the second dummy pixel DPX2, and the third dummy pixel DPX3 can have the same shape as the first pixel PX1, the second pixel PX2, and the third pixel PX3 (e.g., the same shape in a planar view). Similar to the first pixel PX1, the second pixel PX2, and the third pixel PX3, the first dummy pixel DPX1, the second dummy pixel DPX2, and the third dummy pixel DPX3 can include a first color filter 321, a second color filter 322, and a third color filter 323, as well as a first transparent member TPL, a second transparent member WCL1, and a third transparent member WCL2. Unlike the first pixel PX1, the second pixel PX2, and the third pixel PX3, the first dummy pixel DPX1, the second dummy pixel DPX2, and the third dummy pixel DPX3 may not include a light-emitting element ED. Accordingly, the first dummy pixel DPX1, the second dummy pixel DPX2, and the third dummy pixel DPX3 may not emit light. The first dummy pixel DPX1, the second dummy pixel DPX2, and the third dummy pixel DPX3 can overlap with the voltage connection line CVSL and the first non-display transmissive area NTA1.

[0180] The first voltage line VDL may overlap with the second voltage line VSL, which overlaps with the bridge contact BRG. The first voltage line VDL may be positioned below the second voltage line VSL (e.g., positioned below the second voltage line VSL in a direction opposite to the third direction DR3). The first voltage line VDL may be positioned between the first non-display transmissive region NTA1 and the second non-display transmissive region NTA2 (e.g., positioned between the first non-display transmissive region NTA1 and the second non-display transmissive region NTA2 in the second direction DR2). The first voltage line VDL may provide a high-level voltage to the pixel PX in the display region DA.

[0181] The compensation layer CSL may overlap with the second voltage line VSL, the voltage connection line CVSL, and the second non-display transmissive region NTA2. The compensation layer CSL may surround (e.g., in a plan view) the first dummy pixel DPX1, the second dummy pixel DPX2, and the third dummy pixel DPX3. The compensation layer CSL may be disposed at the edge of the opposing substrate TSUB and surround (e.g., in a plan view) the color filter layer CFL and the wavelength conversion layer WCL. In an embodiment, the compensation layer CSL may be disposed at the edge of the opposing substrate TSUB where the color filter layer CFL and wavelength conversion layer WCL are not disposed to reduce horizontal differences, thereby stabilizing the structure of the display device 10. In an embodiment, the compensation layer CSL may include at least one organic layer, but the constituent material of the compensation layer CSL is not limited to this.

[0182] Figure 10 According to embodiments of this disclosure Figure 1 A magnified view of region A3.

[0183] refer to Figure 10 The non-display area NDA may include a dummy pixel DPX. The dummy pixel DPX of the first non-display area NDA1 may be located below the pixel PX located on the lower side in the display area DA (e.g., in the direction opposite to the second direction DR2). In an embodiment, the dummy pixel DPX may include a first dummy pixel DPX1, a second dummy pixel DPX2, and a third dummy pixel DPX3. Because... Figure 5Therefore, the first dummy pixel DPX1, the second dummy pixel DPX2, and the third dummy pixel DPX3 can have the same shape as the first pixel PX1, the second pixel PX2, and the third pixel PX3 (e.g., the same shape in a planar view). In an embodiment, similar to the first pixel PX1, the second pixel PX2, and the third pixel PX3, the first dummy pixel DPX1, the second dummy pixel DPX2, and the third dummy pixel DPX3 may include a first color filter 321, a second color filter 322, and a third color filter 323, as well as a first transparent member TPL, a second transparent member WCL1, and a third transparent member WCL2. Unlike the first pixel PX1, the second pixel PX2, and the third pixel PX3, the first dummy pixel DPX1, the second dummy pixel DPX2, and the third dummy pixel DPX3 may not include a light-emitting element ED. Accordingly, the first dummy pixel DPX1, the second dummy pixel DPX2, and the third dummy pixel DPX3 may not emit light. The first dummy pixel DPX1 and the second dummy pixel DPX2 can overlap with the non-display transmissive area NTA, and the second dummy pixel DPX2 and the third dummy pixel DPX3 can overlap with the second voltage line VSL.

[0184] The second voltage line VSL can be disposed below the non-display transmissive region NTA (e.g., disposed below the non-display transmissive region NTA in a direction opposite to the second direction DR2). In an embodiment, the second voltage line VSL can be... Figure 5 The pixel electrodes ANO are disposed in the same layer, but embodiments of this disclosure are not necessarily limited thereto. In embodiments, the second voltage line VSL may include multiple vias, and Figure 5 The fourth insulating layer 160 and the pixel defining layer 170 can be in direct contact with each other through holes in the second voltage line VSL. The second voltage line VSL can be arranged along the first non-display area NDA1, the second non-display area NDA2, the third non-display area NDA3, and the fourth non-display area NDA4 to surround the display area DA (e.g., surrounding the display area DA in a plan view), such that the second voltage line VSL is spaced apart from the display area DA. The second voltage line VSL disposed in the non-display area NDA can receive a low-level voltage and can be electrically connected to the common electrode CE of the display area DA.

[0185] An anti-static discharge (ESD) element can be disposed between the second voltage line VSL and the non-display transmissive region NTA. The ESD element can be disposed on the underside of the non-display transmissive region NTA (e.g., on the underside of the non-display transmissive region NTA in a direction opposite to the second direction DR2). The ESD element prevents static electricity from being introduced into the display device 10 by eliminating static electricity introduced from the outside. In an embodiment, the ESD element can be disposed in the same layer as the bottom metal layer BML and the gate layer, but the embodiments of this disclosure are not limited to this.

[0186] While this disclosure has been specifically shown and described with reference to non-limiting embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made to this disclosure without departing from its scope. The embodiments described herein should be considered in a descriptive sense only and are not intended for limiting purposes.

Claims

1. A display device comprising: a display region including first, second, and third pixels respectively emitting light having colors different from each other and a display transmissive region located on sides of the first, second, and third pixels; and a first non-display region located on a first side of the display region, wherein the first non-display region includes: a scan line region including a plurality of lines extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; a scan circuit provided between the scan line region and the display region, the scan circuit receiving a signal from the plurality of lines and providing a scan signal to the display region; an electrostatic prevention element provided at an outermost portion of the first non-display region; and a non-display transmissive region located between the scan line region and the electrostatic prevention element to transmit light, and wherein an area of the non-display transmissive region in a plan view is greater than an area of the scan circuit in the plan view.

2. The display device according to claim 1, wherein the non-display transmissive region does not include a metal layer, a transistor, a signal line, or a voltage line.

3. The display device according to claim 1, wherein the plurality of lines include: a clock line provided adjacent to the non-display transmissive region, the clock line providing a clock signal to the scan circuit; a carry line provided adjacent to the scan circuit, the carry line providing a carry signal to the scan circuit; and a scan input line provided between the clock line and the carry line, the scan input line providing a scan input signal to the scan circuit.

4. The display device according to claim 1, wherein the first, second, and third pixels are adjacent to each other in the first direction; and the display transmissive region is located on a first side of the first, second, and third pixels in the second direction.

5. The display device according to claim 1, further comprising: a low-level voltage line overlapping the scan circuit; and a bridge contact overlapping the low-level voltage line, wherein each of the first, second, and third pixels includes a pixel electrode, an emission layer, and a common electrode, and wherein the common electrode extends beyond the display region to the first non-display region and directly contacts the low-level voltage line at the bridge contact.

6. The display device according to claim 5, further comprising: a substrate defining the display region and the first non-display region; a light emitting element layer provided on the substrate and including a pixel circuit and a light emitting element of each of the first, second, and third pixels; an encapsulation layer provided on the light emitting element layer; a counter substrate facing the substrate; a color filter layer provided on a surface of the counter substrate facing the substrate and including first, second, and third color filters respectively corresponding to the first, second, and third pixels; ​ a wavelength conversion layer provided on a surface of the color filter layer and including first, second, and third transparent members corresponding to the first, second, and third color filters, respectively; a filling layer provided between the encapsulation layer and the wavelength conversion layer and filling a space between the encapsulation layer and the wavelength conversion layer; and a sealing member provided along an edge of the first non-display area, the sealing member attaching the substrate to the counter substrate.

7. The display device according to claim 6, further comprising: a compensation layer provided at an edge of the surface of the counter substrate and overlapping the low-level voltage line, the scan line region, and the non-display transmissive region.

8. The display device according to claim 6, further comprising: a bank provided on the surface of the color filter layer, the bank defining the first, second, and third transparent members; and first, second, and third dummy pixels defined by the bank, the first, second, and third dummy pixels overlapping the scan circuit and having the same shape as the first, second, and third pixels in the plan view.

9. The display device according to claim 8, wherein the first, second, and third dummy pixels include the first, second, and third color filters and the first, second, and third transparent members, respectively, and do not include light emitting elements.

10. The display device according to claim 5, further comprising: a second non-display area adjacent to the first non-display area; a third non-display area located at a position opposite to the second non-display area with respect to the display area; and a fourth non-display area located at a position opposite to the first non-display area with respect to the display area, wherein the low-level voltage line and the anti-static element are provided along the first, second, third, and fourth non-display areas, surround the display area, and are spaced apart from the display area in the plan view.

11. A display device comprising: a display area including first, second, and third pixels respectively emitting light having colors different from each other and a display transmissive region located on sides of the first, second, and third pixels; a first non-display area located on a first side of the display area in a first direction and including a scan driver that supplies a scan signal to the first, second, and third pixels; and a second non-display area adjacent to the first non-display area and located on a second side of the display area in a second direction crossing the first direction, wherein the second non-display area includes: a first non-display transmissive region adjacent to the display area and transmissive to light. ​ ​ ​ a first low-level voltage line provided at an upper side of the first non-display transmissive region in the second direction and supplying a low-level voltage; a second non-display transmissive region provided at an upper side of the first low-level voltage line in the second direction and transmitting light; a second low-level voltage line provided at an upper side of the second non-display transmissive region in the second direction, in a lower layer of the first low-level voltage line, and supplying the low-level voltage; a third non-display transmissive region provided at an upper side of the second low-level voltage line in the second direction and transmitting light; and an anti-static element provided at an outermost portion of the second non-display region.

12. The display device according to claim 11, wherein an area of the second non-display transmissive region in a plan view is larger than an area of the first non-display transmissive region in the plan view; and an area of the third non-display transmissive region in the plan view is larger than the area of the second non-display transmissive region in the plan view.

13. The display device according to claim 11, further comprising: a voltage connection line extending from the display region to the first low-level voltage line and surrounding a portion of the first non-display transmissive region in a plan view.

14. The display device according to claim 11, further comprising: a bridge contact overlapping the first low-level voltage line, wherein each of the first pixel, the second pixel, and the third pixel includes a pixel electrode, an emission layer, and a common electrode, and wherein the common electrode extends beyond the display region to the second non-display region and directly contacts the first low-level voltage line at the bridge contact.

15. The display device according to claim 14, further comprising: a substrate defining the display region and the first and second non-display regions; a light-emitting element layer provided on the substrate and including a pixel circuit and a light-emitting element of each of the first, second, and third pixels; an encapsulation layer provided on the light-emitting element layer; a counter substrate facing the substrate; a color filter layer provided on a surface of the counter substrate facing the substrate and including a first color filter, a second color filter, and a third color filter corresponding to the first, second, and third pixels, respectively; a wavelength conversion layer provided on a surface of the color filter layer and including a first transparent member, a second transparent member, and a third transparent member corresponding to the first, second, and third color filters, respectively; a filling layer provided between the encapsulation layer and the wavelength conversion layer and filling a space between the encapsulation layer and the wavelength conversion layer; and a sealing member provided along an edge of the second non-display region, the sealing member attaching the substrate to the counter substrate. the pixel circuit includes:

16. The display device of claim 15, wherein, a bottom metal layer provided on the substrate; a semiconductor layer provided on the bottom metal layer; a gate layer provided on the semiconductor layer; and a top metal layer provided on the gate layer. A source metal layer is disposed on the gate layer. The first low-level voltage line is disposed in the same layer as the pixel electrode and includes multiple holes. The second low-level voltage line is disposed in the source metal layer.

17. The display device according to claim 16, further comprising: A voltage connection line extends from the second low-level voltage line to the anti-static element, and in the plan view surrounds a portion of the third non-display transmissive area. The antistatic element is disposed in the bottom metal layer and the gate layer.

18. A display device, comprising: The display area includes a first pixel, a second pixel, and a third pixel that emit light of different colors from each other, and a display transmissive area located on the sides of the first pixel, the second pixel, and the third pixel. A first non-display area is located on a first side of the display area in a first direction, and includes a scan driver that provides scan signals to the first pixel, the second pixel, and the third pixel; The second non-display area is adjacent to the first non-display area and is located on the second side of the display area in a second direction that intersects the first direction; The third non-display area is opposite to the second non-display area relative to the display area; A substrate defines the display area and the first non-display area, the second non-display area, and the third non-display area; A light-emitting element layer is disposed on the substrate and includes pixel circuits and light-emitting elements for each of the first pixel, the second pixel, and the third pixel; An encapsulation layer is disposed on the light-emitting element layer; Opposing substrate, facing the substrate; A color filter layer is disposed on the surface of the opposing substrate facing the substrate, and includes a first color filter, a second color filter, and a third color filter corresponding to the first pixel, the second pixel, and the third pixel, respectively. A wavelength conversion layer is disposed on the surface of the color filter layer and includes a first transparent member, a second transparent member, and a third transparent member corresponding to the first color filter, the second color filter, and the third color filter, respectively. as well as A dam, disposed on the surface of the color filter layer, defines the first transparent member, the second transparent member, and the third transparent member, and The third non-display area includes: The first dummy pixel, the second dummy pixel, and the third dummy pixel are defined by the embankment. The first dummy pixel, the second dummy pixel, and the third dummy pixel have the same shape as the first pixel, the second pixel, and the third pixel in the plan view. The first dummy pixel, the second dummy pixel, and the third dummy pixel are adjacent to each other in the second direction. The non-display transmissive area overlaps with the first dummy pixel and the second dummy pixel; and A low-level voltage line overlaps with the second dummy pixel and the third dummy pixel, and includes multiple holes.

19. The display device according to claim 18, wherein, The first dummy pixel, the second dummy pixel, and the third dummy pixel each include a first color filter, a second color filter, and a third color filter, as well as a first transparent component, a second transparent component, and a third transparent component. Furthermore, the first dummy pixel, the second dummy pixel, and the third dummy pixel do not include light-emitting elements. The low-level voltage line extends along the first non-display area, the second non-display area, and the third non-display area.

20. An electronic device comprising: The display device according to any one of claims 1 to 10; as well as The power supply provides power to the display device.

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