Display device and electronic device including the same

Abstract

The invention relates to a display device and an electronic device including the same. Disclosed is a display device including: a second semiconductor pattern and a first second transistor electrode connected to the second semiconductor pattern in a direction perpendicular to the second semiconductor pattern; a second conductive layer on the first and second transistor electrodes and connected to the first and second transistor electrodes; a first bridge pattern on the second conductive layer and connected to the second conductive layer; and a data line connected to the first bridge pattern to supply a data signal to the second semiconductor pattern. A first region in which the second semiconductor pattern and the first second transistor electrode are connected does not overlap a second region in which the data line and the first bridge pattern are connected.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0081232, filed on June 21, 2024, with the Korean Intellectual Property Office, and Korean Patent Application No. 10-2024-0112455, filed on August 22, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to display devices and electronic devices including display devices. Background Technology

[0004] Display devices are gaining attention due to their ability to be made lightweight and thin. Among display devices, organic light-emitting diode (OLED) displays are self-emissive devices that use organic light-emitting diodes (OLEDs) to display images and do not require a separate light source. Furthermore, OLEDs are attracting attention as the next generation of display devices due to their low power consumption, high brightness, and fast response time.

[0005] The aforementioned organic light-emitting display device includes a plurality of pixels, each of which includes an organic light-emitting diode, a plurality of transistors for driving the organic light-emitting diode, and at least one capacitor.

[0006] The above description is intended only to help understand the background of the technical ideas of this disclosure, and therefore should not be construed as corresponding to prior art known to those skilled in the art to which this disclosure pertains. Summary of the Invention

[0007] Embodiments of this disclosure may provide a display device in which short circuits between data lines and pixel transistors are prevented.

[0008] A display device according to an embodiment of the present disclosure includes: a second semiconductor pattern and a first second transistor electrode connected to the second semiconductor pattern in a direction perpendicular to the second semiconductor pattern; a second conductive layer located on and connected to the first second transistor electrode; a first bridge pattern located on and connected to the second conductive layer; and a data line connected to the first bridge pattern to supply data signals to the second semiconductor pattern, wherein a first region where the second semiconductor pattern and the first second transistor electrode are connected does not overlap with a second region where the data line and the first bridge pattern are connected.

[0009] The third region where the first and second transistor electrodes are connected to the second conductive layer and the fourth region where the first bridge pattern is connected to the second conductive layer can be spaced apart by a first length in the direction in which the second conductive layer extends.

[0010] Each of the second semiconductor pattern and the second conductive layer may extend in a first direction, the first and second transistor electrodes may extend upward in a third direction perpendicular to the first direction, and the second conductive layer may overlap with the second semiconductor pattern in a partial region.

[0011] The first and second transistor electrodes can be electrically connected to the second semiconductor pattern and the second conductive layer through contact holes located between the second semiconductor pattern and the second insulating layer.

[0012] The second conductive layer may include a first layer containing titanium and disposed on a second insulating layer, and a second layer containing molybdenum and disposed on the first layer.

[0013] The second conductive layer may include a first layer containing titanium and disposed on the second insulating layer, a second layer containing aluminum and disposed on the first layer, and a third layer containing titanium and disposed on the second layer.

[0014] The first bridge pattern can be connected to the second conductive layer through a contact hole in the first organic layer located between the first bridge pattern and the second conductive layer.

[0015] A display device according to an embodiment of the present disclosure includes: a second semiconductor pattern and a first second transistor electrode connected to the second semiconductor pattern in a direction perpendicular to the second semiconductor pattern; a first bridge pattern located on and connected to the first second transistor electrode; and a data line connected to the first bridge pattern to supply data signals to the second semiconductor pattern, wherein a first region where the second semiconductor pattern and the first second transistor electrode are connected does not overlap with a second region where the data line and the first bridge pattern are connected.

[0016] The first and second transistor electrodes are connected to the third region of the first bridge pattern, and the data line is connected to the fourth region of the first bridge pattern. They can be spaced apart by a second length in the direction in which the first bridge pattern extends.

[0017] Each of the second semiconductor pattern and the first bridge pattern may extend in a first direction, the first and second transistor electrodes may extend upward in a third direction perpendicular to the first direction, and the first bridge pattern may overlap with the second semiconductor pattern in a certain region.

[0018] The first and second transistor electrodes can be connected to the first bridge pattern through contact holes that penetrate the first insulating layer, the second insulating layer, and the first organic layer located between the first bridge pattern and the second semiconductor pattern.

[0019] The data cable can be connected to the first bridge pattern through a contact hole that penetrates the second organic layer located between the first bridge pattern and the data cable.

[0020] A display device according to an embodiment of the present disclosure includes: a second semiconductor pattern and a second conductive layer located on the second semiconductor pattern; a fifth bridge pattern located on the second semiconductor pattern and the second conductive layer to electrically connect the second semiconductor pattern and the second conductive layer; a first bridge pattern located on the second conductive layer and connected to the second conductive layer; and a data line connected to the first bridge pattern to supply data signals to the second semiconductor pattern, wherein a first region where the second semiconductor pattern and the fifth bridge pattern are connected does not overlap with a second region where the data line and the first bridge pattern are connected.

[0021] The fifth bridge pattern may include a first fifth bridge pattern and a second and a third fifth bridge pattern extending from the first fifth bridge pattern in a direction perpendicular to the second semiconductor pattern. The second fifth bridge pattern can be connected to the second conductive layer through a contact hole in the first organic layer located between the first fifth bridge pattern and the second conductive layer, and the third fifth bridge pattern can be connected to the second semiconductor pattern through a contact hole in the first insulating layer, the second insulating layer and the first organic layer located between the first fifth bridge pattern and the second conductive layer.

[0022] The second conductive layer may include a first layer containing titanium and disposed on a second insulating layer, and a second layer containing molybdenum and disposed on the first layer.

[0023] The second conductive layer may include a first layer containing titanium and disposed on the second insulating layer, a second layer containing aluminum and disposed on the first layer, and a third layer containing titanium and disposed on the second layer.

[0024] The third and fifth bridge patterns can be connected to the third region of the second semiconductor pattern and the fourth region of the first bridge pattern connected to the second conductive layer are spaced apart by a third length in the direction in which the second conductive layer extends.

[0025] The first bridge pattern can be connected to the second conductive layer through a contact hole in the first organic layer located between the first bridge pattern and the second conductive layer.

[0026] An electronic device according to an embodiment of the present disclosure includes: a processor for providing input image data; and a display device for displaying an image based on the input image data. The display device includes: a second semiconductor pattern and a first second transistor electrode connected to the second semiconductor pattern in a direction perpendicular to the second semiconductor pattern; a second conductive layer located on and connected to the first second transistor electrode; a first bridge pattern located on and connected to the second conductive layer; and a data line connected to the first bridge pattern to supply data signals to the second semiconductor pattern, wherein a first region where the second semiconductor pattern and the first second transistor electrode are connected does not overlap with a second region where the data line and the first bridge pattern are connected.

[0027] According to embodiments of the present disclosure, a display device in which short circuits between data lines and pixel transistors can be provided.

[0028] The effects of the embodiments are not limited to those exemplified above, and many more different effects are included in this specification. Attached Figure Description

[0029] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0030] Figure 2 This is a circuit diagram illustrating a pixel according to an embodiment of the present disclosure.

[0031] Figure 3 This illustrates an embodiment. Figure 2 A partial cross-sectional view of the stacked structure of the second, third, and sixth transistor regions of the pixel.

[0032] Figure 4 yes Figure 3 A magnified view of region X.

[0033] Figure 5 This illustrates an embodiment. Figure 2 A partial cross-sectional view of the stacked structure of the second, third, and sixth transistor regions of the pixel.

[0034] Figure 6 yes Figure 5 A magnified view of region Y.

[0035] Figure 7 This illustrates an embodiment. Figure 2 A partial cross-sectional view of the stacked structure of the second, third, and sixth transistor regions of the pixel.

[0036] Figure 8 yes Figure 7 A magnified view of region Z.

[0037] Figure 9 This is a block diagram of an electronic device according to an embodiment.

[0038] Figure 10 Schematic diagrams illustrating various embodiments of the electronic device are shown. Detailed Implementation

[0039] In the following, preferred embodiments will be described in detail with reference to the accompanying drawings. It should be noted that the following description only describes the parts necessary for understanding the operation according to this disclosure, and other parts will be omitted to avoid obscuring the spirit of this disclosure. Furthermore, this disclosure is not limited to the embodiments described herein, but may be implemented in other forms. However, the embodiments described herein are provided for detailed explanation to enable those skilled in the art to implement the technical ideas of this disclosure.

[0040] Throughout this specification, the term "connected" to another part includes not only cases where they are "directly connected" but also cases where other elements are inserted between them in an "indirect connection." The terminology used herein is intended to describe particular embodiments and is not intended to limit this disclosure. Throughout this specification, unless the context otherwise indicates, if a part "comprises" or "contains" a component, it means that it may also include other components, rather than excluding them. "At least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as one X, one Y, one Z, or a combination of two or more of X, Y, and Z (e.g., XYZ, XY, YZ, XZ). As used herein, the word "or" means logical "or," therefore unless the context otherwise indicates, the expression "A, B, or C" means "A and B and C," "A and B but not C," "A and C but not B," "B and C but not A," "A but not B and not C," "B but not A and not C," and "C but not A and not B."

[0041] In this document, terms such as “first” and “second” may be used to describe various components, but these components are not limited to those terms. These terms are used to distinguish one component from another. Therefore, without departing from this disclosure, a first component may be referred to as a second component.

[0042] For illustrative purposes, spatially relative terms such as “below” and “above” may be used to describe the relationship between one element or feature and other elements or features as depicted in the accompanying drawings. In addition to the orientations depicted in the drawings, spatially relative terms are intended to encompass different orientations in use, operation, or manufacture. For example, if the device shown in the drawings were flipped, an element depicted as positioned “below” other elements or features would instead be positioned “above” other elements or features. Therefore, in embodiments, the term “below” may include both upward and downward orientations. Furthermore, the device may be oriented in other directions (e.g., rotated 90 degrees or at other angles), and the spatially relative terms used herein are interpreted accordingly.

[0043] Various embodiments are described with reference to the accompanying drawings, which illustrate preferred embodiments. Therefore, it will be anticipated that the shape may vary, for example, depending on tolerances or manufacturing techniques. Consequently, the embodiments disclosed herein should not be construed as limited to the specific shapes shown, but should be interpreted as including shape changes, for example, due to manufacturing processes. Therefore, the shapes shown in the drawings may not depict the actual shape of the area of ​​the device, and the embodiments are not limited thereto.

[0044] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0045] refer to Figure 1 The display device DD may include a display panel DP, a controller 110, a data driver 120, a first scan driver 130, a second scan driver 140, a third scan driver 150, and a fourth scan driver 160, as well as a light-emitting driver 170. Furthermore, the display device DD may also include a voltage supply unit (not shown).

[0046] The display device DD can display images at various driving frequencies depending on the driving conditions. Here, the driving frequency is also called the screen scan rate or screen refresh rate, and the frequency at which the display screen is refreshed is expressed as refreshes per second.

[0047] The display panel DP can include multiple pixels PXL. The display panel DP can be connected to data lines DL1 to DLm, first scan lines SL11 to SL1n, second scan lines SL21 to SL2n, third scan lines SL31 to SL3n, fourth scan lines SL41 to SL4n, and light-emitting lines EL1 to ELn. In the display panel DP, the multiple pixels PXL can be electrically connected to the data lines DL1 to DLm, the first scan lines SL11 to SL1n, the second scan lines SL21 to SL2n, the third scan lines SL31 to SL3n, the fourth scan lines SL41 to SL4n, and the light-emitting lines EL1 to ELn. Where m and n are positive integers.

[0048] Each of the pixels PXL can receive voltage from the voltage supply unit (e.g., first power supply voltage ELVDD, second power supply voltage ELVSS, first initialization voltage VINT1, second initialization voltage VINT2, etc.).

[0049] Display panels (DPs) can be of various types, including OLED (Organic Light Emitting Diode) panels. The type of wiring arranged in a display panel DP can vary depending on the pixel structure, panel type, and other factors.

[0050] The controller 110 can control the operation of the data driver 120, the first scan driver 130, the second scan driver 140, the third scan driver 150, the fourth scan driver 160, and the light-emitting driver 170. The controller 110 can receive a control signal CTRL from an external source. Furthermore, the controller 110 can use the control signal CTRL to generate first scan control signals SCS1 to fourth scan control signals SCS4, a data control signal DCS, and a light-emitting control signal ECS.

[0051] The controller 110 may provide a first scan control signal SCS1 to the first scan driver 130 to apply scan signals to the first scan lines SL11 to SL1n according to the timing implemented in each frame. The first scan control signal SCS1 may include a first scan start pulse and a clock signal. The first scan start pulse may control the first timing of the scan signals output from the first scan driver 130. The clock signal may be used to shift the first scan start pulse.

[0052] The controller 110 can provide a second scan control signal SCS2 to the second scan driver 140 to apply scan signals to the second scan lines SL21 to SL2n according to the timing implemented in each frame. The second scan control signal SCS2 may include a second scan start pulse and a clock signal. The second scan start pulse can control the first timing of the scan signals output from the second scan driver 140. The clock signal can be used to shift the second scan start pulse.

[0053] The controller 110 can provide a third scan control signal SCS3 to the third scan driver 150 to apply scan signals to the third scan lines SL31 to SL3n according to the timing implemented in each frame. The third scan control signal SCS3 may include a third scan start pulse and a clock signal. The third scan start pulse can control the first timing of the scan signals output from the third scan driver 150. The clock signal can be used to shift the third scan start pulse.

[0054] The controller 110 can provide a fourth scan control signal SCS4 to the fourth scan driver 160 to apply scan signals to the fourth scan lines SL41 to SL4n according to the timing implemented in each frame. The fourth scan control signal SCS4 can include a fourth scan start pulse and a clock signal. The fourth scan start pulse can control the first timing of the scan signals output from the fourth scan driver 160. The clock signal can be used to shift the fourth scan start pulse.

[0055] Controller 110 can receive image signals RGB from an external source. Controller 110 can provide image data signals DATA, converted from the image signals RGB and conforming to the interface specifications of data driver 120, to data driver 120. Controller 110 can provide data control signals DCS to data driver 120 to apply data voltages to data lines DL1 to DLm. The data control signals DCS may include a source start pulse and a clock signal. The source start pulse controls the start time of data sampling. The clock signal can be used to control the sampling operation.

[0056] The controller 110 can provide a light emission control signal ECS to the light emission driver 170 to apply light emission signals to the light emission lines EL1 to ELn according to the timing implemented in each frame. The light emission control signal ECS may include a light emission control start pulse and a clock signal. The light emission control start pulse can control the first timing of the light emission control signal output from the light emission driver 170. The clock signal can be used to shift the light emission control start pulse.

[0057] The controller 110 may be a timing controller used in conventional display technology, or it may be a control device that includes a timing controller and is capable of performing other control functions.

[0058] Data driver 120 can output data signals to data lines DL1 to DLm. For example, data driver 120 can receive data control signal DCS and image data signal DATA from controller 110. Data driver 120 can convert image data signal DATA into a data signal and output the data signal to data lines DL1 to DLm. Here, the data signal can be an analog voltage corresponding to the grayscale value of image data signal DATA. That is, when a specific scan line is selected by the first scan driver 130, data driver 120 can supply analog data voltage to data lines DL1 to DLm.

[0059] The first scan driver 130 can receive a first scan control signal SCS1 from the controller 110. The first scan driver 130 can output scan signals to the first scan lines SL11 to SL1n. For example, the first scan driver 130 can sequentially supply scan signals to the first scan lines SL11 to SL1n according to the first scan control signal SCS1 from the controller 110. When scan signals are sequentially supplied from the first scan driver 130, pixels PXL can be selected in units of horizontal lines (or pixel rows). Data signals can be supplied to pixels PXL. That is, the scan signals supplied from the first scan driver 130 can be signals used for data writing.

[0060] The second scan driver 140 can receive a second scan control signal SCS2 from the controller 110. The second scan driver 140 can output scan signals to the second scan lines SL21 to SL2n. For example, the second scan driver 140 can sequentially supply scan signals to the second scan lines SL21 to SL2n according to the second scan control signal SCS2 from the controller 110. The scan signals supplied from the second scan driver 140 can be used for initialization or threshold voltage (Vth) compensation of transistors and capacitors included in the pixel PXL. When a scan signal is supplied from the second scan driver 140, the pixel PXL can perform threshold voltage compensation or initialization operations.

[0061] The third scan driver 150 can receive a third scan control signal SCS3 from the controller 110. The third scan driver 150 can output scan signals to the third scan lines SL31 to SL3n. For example, the third scan driver 150 can sequentially supply scan signals to the third scan lines SL31 to SL3n according to the third scan control signal SCS3 from the controller 110. The scan signals supplied from the third scan driver 150 can be used to initialize the driving transistors included in the pixel PXL and the capacitors included in the pixel PXL. When a scan signal is supplied from the third scan driver 150, the initialization operation of the driving transistors or the initialization operation of the capacitors can be performed.

[0062] The fourth scan driver 160 can receive a fourth scan control signal SCS4 from the controller 110. The fourth scan driver 160 can output scan signals to the fourth scan lines SL41 to SL4n. The fourth scan driver 160 can sequentially supply scan signals to the fourth scan lines SL41 to SL4n according to the fourth scan control signal SCS4 from the controller 110. The scan signals supplied from the fourth scan driver 160 can be used to initialize the light-emitting elements (LDs) included in pixel PXL (see [link]). Figure 2 The pixel PXL can perform initialization operations and bias voltage supply operations on the light-emitting element LD when a scan signal is supplied from the fourth scan driver 160.

[0063] The light-emitting driver 170 can receive a light-emitting control signal ECS from the controller 110. The light-emitting driver 170 can output light-emitting signals to the light-emitting lines EL1 to ELn. The light-emitting driver 170 can sequentially supply light-emitting signals to the light-emitting lines EL1 to ELn according to the light-emitting control signal ECS from the controller 110.

[0064] At the same time, Figure 1In this illustration, for ease of explanation, the data driver 120, the first scan driver 130, the second scan driver 140, the third scan driver 150, the fourth scan driver 160, and the light-emitting driver 170 are shown as separate components, but this disclosure is not limited thereto. That is, at least some of the data driver 120, the first scan driver 130, the second scan driver 140, the third scan driver 150, the fourth scan driver 160, and the light-emitting driver 170 can be integrated into a single drive circuit, module, etc.

[0065] The voltage supply unit can receive a voltage control signal from the controller 110. The voltage supply unit can supply voltage (e.g., a first power supply voltage ELVDD, a second power supply voltage ELVSS, a first initialization voltage VINT1, a second initialization voltage VINT2, etc.) to the display panel DP in response to the voltage control signal. In an embodiment, the first power supply voltage ELVDD may be higher than the second power supply voltage ELVSS.

[0066] The first power supply voltage ELVDD and the second power supply voltage ELVSS can be voltages used to drive the light-emitting element LD. The first initialization voltage VINT1 and the second initialization voltage VINT2 can be voltages used to initialize each of the pixels PXL. For example, the anode of the light-emitting element LD included in each of the pixels PXL can be initialized by the first initialization voltage VINT1 and the second initialization voltage VINT2. The first initialization voltage VINT1 and the second initialization voltage VINT2 can be negative voltages.

[0067] Figure 2 This is a circuit diagram illustrating pixels according to an embodiment of the present disclosure. Figure 2 For ease of explanation, pixel PXij, located on the i-th horizontal line (or the i-th pixel row) and connected to the j-th data line DLj, is shown. Here, i and j are positive integers.

[0068] refer to Figure 2 The pixel PXij may include a light-emitting element LD, a first transistor T1 to a seventh transistor T7, and a first capacitor C1.

[0069] The first electrode (or anode) of the light-emitting element LD can be connected to the second electrode (e.g., the drain electrode) (i.e., the second node N2) of the first transistor T1 via the sixth transistor T6, and the second electrode (or cathode) of the light-emitting element LD can be connected to the power line supplying the second power supply voltage ELVSS to it.

[0070] The first transistor T1 can be connected to the power line supplying it with the first power supply voltage ELVDD via the fifth transistor T5. The first transistor T1 can be connected to the first electrode of the light-emitting element LD via the sixth transistor T6. The first transistor T1 can generate a drive current and provide that drive current to the light-emitting element LD. The gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 can be used as the driving transistor for the pixel PXij. The first transistor T1 can control the amount of current flowing through the light-emitting element LD in response to the voltage applied to the first node N1.

[0071] A first capacitor C1 can be connected between a first node N1 (corresponding to the gate electrode of the first transistor T1) and the power line supplying it a first power supply voltage ELVDD. The first capacitor C1 can store the voltage corresponding to the voltage difference between the voltage of the first node N1 and the first power supply voltage ELVDD.

[0072] The second transistor T2 can be connected between the j-th data line DLj and the first node N1. The second transistor T2 may include a gate electrode for receiving a scan signal. For example, the gate electrode of the second transistor T2 can be connected to the 1i-th scan line SL1i to receive a scan signal from the first scan driver 130. When a scan signal is supplied from the first scan driver 130, the second transistor T2 can be turned on to electrically connect the j-th data line DLj and the first node N1. Therefore, a data signal (or data voltage) can be transmitted to the first node N1.

[0073] A third transistor T3 can be connected between a first node N1 corresponding to the gate electrode of the first transistor T1 and a second electrode (i.e., a second node N2) of the first transistor T1. The third transistor T3 may include a gate electrode for receiving a scan signal. For example, the gate electrode of the third transistor T3 can be connected to the 2i scan line SL2i to receive a scan signal from the second scan driver 140. When a scan signal is supplied from the second scan driver 140, the third transistor T3 can be turned on, thereby electrically connecting the first node N1 and the second node N2.

[0074] A fourth transistor T4 can be connected between the first node N1 and the power line supplying it with a first initialization voltage VINT1. The fourth transistor T4 may include a gate electrode for receiving a scan signal. For example, the gate electrode of the fourth transistor T4 can be connected to the 3i scan line SL3i and can receive a scan signal from the third scan driver 150. When a scan signal is supplied from the third scan driver 150, the fourth transistor T4 can be turned on and electrically connected to the first node N1 and the power line supplying it with the first initialization voltage VINT1. When the fourth transistor T4 is turned on, the first initialization voltage VINT1 can be supplied to the first node N1, and the voltage of the first node N1 can be initialized to the first initialization voltage VINT1.

[0075] A fifth transistor T5 can be connected between the power line supplying it with the first power supply voltage ELVDD and the first electrode (i.e., the third node N3) of the first transistor T1. The fifth transistor T5 may include a gate electrode for receiving a light-emitting signal. For example, the gate electrode of the fifth transistor T5 can be connected to the i-th light-emitting line ELi and can receive a light-emitting signal from the light-emitting driver 170. The fifth transistor T5 can be turned on when a light-emitting signal is supplied to the i-th light-emitting line ELi, and can be turned off under other conditions. When in the on state, the fifth transistor T5 can connect the first electrode of the first transistor T1 to the power line supplying it with the first power supply voltage ELVDD.

[0076] The sixth transistor T6 can be connected between the second node N2 corresponding to the second electrode of the first transistor T1 and the anode (i.e., the fourth node N4) of the light-emitting element LD. The sixth transistor T6 may include a gate electrode for receiving light-emitting signals. For example, the gate electrode of the sixth transistor T6 can be connected to the i-th light-emitting line ELi and can receive light-emitting signals from the light-emitting driver 170. When a light-emitting signal is supplied to the i-th light-emitting line ELi, the sixth transistor T6 can be turned on, and otherwise can be turned off. The sixth transistor T6 in the on state can be electrically connected between the second node N2 and the fourth node N4.

[0077] A seventh transistor T7 can be connected between the first electrode of the light-emitting element LD (i.e., the fourth node N4) and the power line supplying it with the second initialization voltage VINT2. The seventh transistor T7 may include a gate electrode for receiving scan signals. For example, the seventh transistor T7 can be connected to the 4i scan line SL4i and can receive scan signals from the fourth scan driver 160. When a scan signal is supplied from the fourth scan driver 160, the seventh transistor T7 can be turned on and electrically connected between the fourth node N4 and the power line supplying it with the second initialization voltage VINT2. When the seventh transistor T7 is turned on, the second initialization voltage VINT2 is supplied to the fourth node N4, and the voltage of the fourth node N4 can be initialized to the second initialization voltage VINT2. When the second initialization voltage VINT2 is supplied to the anode of the light-emitting element LD, the parasitic capacitor of the light-emitting element LD can discharge. As the residual voltage charged in the parasitic capacitor is discharged (eliminated), unintended micro-emission can be prevented. Therefore, the black level performance of pixel PXij can be improved. By separating the initialization operation of the gate electrode (i.e., the first node N1) of the first transistor T1 from the initialization operation of the anode (i.e., the fourth node N4) of the light-emitting element LD, it is possible to prevent the light-emitting element LD from emitting light unexpectedly during the initialization operation of the gate electrode (i.e., the first node N1) of the first transistor T1.

[0078] Figure 3 This illustrates an embodiment. Figure 2 A partial cross-sectional view of the stacked structure of the second, third, and sixth transistor regions of the pixel.

[0079] refer to Figure 3 The pixel circuit layer PCL, the display element layer DPL, and the thin film encapsulation layer TFE can be sequentially arranged on the base layer SUB (or substrate).

[0080] The pixel circuit layer PCL may include a barrier layer BRL, a buffer layer BFL, a semiconductor layer ACT, a first insulating layer GI1, a first conductive layer GAT1, a second insulating layer GI2, a first organic layer VIA1, a second organic layer VIA2, and a third organic layer VIA3.

[0081] In the pixel circuit layer PCL, the blocking layer BRL, the buffer layer BFL, the semiconductor layer ACT, the first insulating layer GI1, the first conductive layer GAT1, the second insulating layer GI2, the first organic layer VIA1, the second organic layer VIA2, and the third organic layer VIA3 can be sequentially stacked on the base layer SUB on the third-direction DR3.

[0082] The second transistor T2 may include a second semiconductor pattern ACT_T2, a gate pattern T2_GE of the second transistor T2, a first second transistor electrode ET21, and a second second transistor electrode ET22.

[0083] The third transistor T3 may include a third semiconductor pattern ACT_T3, a gate pattern T3_GE of the third transistor T3, a first third transistor electrode ET31, and a second third transistor electrode ET32.

[0084] The sixth transistor T6 may include a sixth semiconductor pattern ACT_T6, a gate pattern T6_GE of the sixth transistor T6, a first sixth transistor electrode ET61, and a second sixth transistor electrode ET62.

[0085] The base layer SUB can be made of an insulating material such as glass or resin. Furthermore, the base layer SUB can be made of a flexible material, allowing it to be bent or folded, and can have a single-layer or multi-layer structure. For example, flexible materials may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate. However, the materials forming the base layer SUB are not limited to the embodiments described above.

[0086] The barrier layer (BRL) can be disposed on the entire surface of the base layer (SUB). The barrier layer (BRL) can block unwanted components such as moisture or oxygen from entering the light-emitting element. For example, the barrier layer (BRL) can be made of silicon oxide (SiOx).

[0087] The buffer layer (BFL) can be disposed on the entire surface of the barrier layer (BRL). The buffer layer (BFL) prevents the diffusion of impurity ions and the penetration of moisture or outside air. The buffer layer (BFL) can be an inorganic insulating film containing inorganic materials. The buffer layer (BFL) can be a single film, but it can also be a multi-film consisting of at least two or more films.

[0088] A semiconductor layer ACT can be disposed on a buffer layer BFL. The semiconductor layer ACT can be disposed between the buffer layer BFL and the first insulating layer GI1. The semiconductor layer ACT can be an active layer forming the channel of the first transistor T1 to the seventh transistor T7. The semiconductor layer ACT can include a source region (or a first region) and a drain region (or a second region) in contact with a first electrode (e.g., a source electrode) and a second electrode (e.g., a drain electrode) of each of the first transistors T1 to the seventh transistor T7. The region between the source region and the drain region can be a channel region. For example, the semiconductor layer ACT can include a second semiconductor pattern ACT_T2 forming a second transistor T2. For example, the semiconductor layer ACT can include a third semiconductor pattern ACT_T3 forming a third transistor T3. For example, the semiconductor layer ACT can include a sixth semiconductor pattern ACT_T6 forming a sixth transistor T6.

[0089] The second semiconductor pattern ACT_T2 may include a first region contacting the first and second transistor electrodes ET21, a second region contacting the second transistor electrode ET22, and a channel region located between the first and second regions. The second semiconductor pattern ACT_T2 may be a semiconductor pattern made of polysilicon. The channel region of the second semiconductor pattern ACT_T2 may be an undoped semiconductor pattern and may be an intrinsic semiconductor. The first and second regions of the second semiconductor pattern ACT_T2 may be doped semiconductor patterns.

[0090] The third semiconductor pattern ACT_T3 may include a first region contacting the first and third transistor electrodes ET31, a second region contacting the second and third transistor electrodes ET32, and a channel region located between the first and second regions. The third semiconductor pattern ACT_T3 may be a semiconductor pattern made of polysilicon. The channel region of the third semiconductor pattern ACT_T3 may be an undoped semiconductor pattern and may be an intrinsic semiconductor. The first and second regions of the third semiconductor pattern ACT_T3 may be doped semiconductor patterns.

[0091] The sixth semiconductor pattern ACT_T6 may include a first region contacting the first sixth transistor electrode ET61, a second region contacting the second sixth transistor electrode ET62, and a channel region located between the first and second regions. The sixth semiconductor pattern ACT_T6 may be a semiconductor pattern made of polysilicon. The channel region of the sixth semiconductor pattern ACT_T6 may be an undoped semiconductor pattern and may be an intrinsic semiconductor. The first and second regions of the sixth semiconductor pattern ACT_T6 may be doped semiconductor patterns.

[0092] A first insulating layer GI1 may be disposed on the semiconductor layer ACT. The first insulating layer GI1 may be an inorganic insulating film comprising inorganic materials. For example, the first insulating layer GI1 may comprise the same material as the buffer layer BFL, or it may comprise one or more materials selected from those exemplified as constituent materials of the buffer layer BFL. According to an embodiment, the first insulating layer GI1 may be formed from an organic insulating film comprising organic materials. The first insulating layer GI1 may be a single film, but it may also be a multi-film consisting of at least two or more films.

[0093] The first conductive layer GAT1 may be disposed on the first insulating layer GI1. The first conductive layer GAT1 may include the gate pattern T2_GE of the second transistor T2, the gate pattern T3_GE of the third transistor T3, and the gate pattern T6_GE of the sixth transistor T6.

[0094] The first conductive layer GAT1 may contain one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The first conductive layer GAT1 may have a single-film or multi-film structure, and for example, the first conductive layer GAT1 may have a single-film structure including molybdenum (Mo).

[0095] The second insulating layer GI2 may be disposed on the first insulating layer GI1 and the first conductive layer GAT1. The second insulating layer GI2 may be disposed substantially above the entire surface of the base layer SUB. The second insulating layer GI2 may contain the same material as the first insulating layer GI1, or may contain one or more materials selected from those exemplified as constituent materials of the first insulating layer GI1.

[0096] The second conductive layer GAT2 can be disposed on the second insulating layer GI2. The second conductive layer GAT2 can be connected to and electrically connected to the first and second transistor electrodes ET21.

[0097] In embodiments, the second conductive layer GAT2 can comprise various materials. For example, the second conductive layer GAT2 can consist of a first layer comprising titanium (Ti) disposed on the second insulating layer GI2 and a second layer comprising molybdenum (Mo) disposed on the first layer. For example, the second conductive layer GAT2 can consist of a first layer comprising titanium (Ti) disposed on the second insulating layer GI2, a second layer comprising aluminum (Al) disposed on the first layer, and a third layer comprising titanium (Ti) disposed on the second layer.

[0098] The second bridge pattern BRG2 can overlap with the second region of the sixth semiconductor pattern ACT_T6. The second bridge pattern BRG2 can be connected to the second region of the sixth semiconductor pattern ACT_T6 through contact holes penetrating the first insulating layer GI1 and the second insulating layer GI2. Furthermore, the second bridge pattern BRG2 can form the second sixth transistor electrode ET62 of the sixth transistor T6.

[0099] The first organic layer VIA1 can be disposed on the second insulating layer GI2, the second conductive layer GAT2, and the second bridge pattern BRG2. The first organic layer VIA1 can be disposed substantially above the entire surface of the base layer SUB.

[0100] The first organic layer VIA1 may comprise an organic insulating material such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB).

[0101] The first bridge pattern BRG1 can overlap with the second conductive layer GAT2, and can be connected to the second conductive layer GAT2 through contact holes penetrating the first organic layer VIA1.

[0102] The third bridge pattern BRG3 can overlap with the second bridge pattern BRG2. The third bridge pattern BRG3 can be connected to the second bridge pattern BRG2 through contact holes penetrating the first organic layer VIA1.

[0103] The power line VL_ELVDD of the first power supply voltage ELVDD can be arranged on the first organic layer VIA1.

[0104] The second organic layer VIA2 may be disposed on the first organic layer VIA1, the first bridge pattern BRG1, the third bridge pattern BRG3, and the power line VL_ELVDD of the first power supply voltage ELVDD. The second organic layer VIA2 may be disposed substantially above the entire surface of the base layer SUB. The second organic layer VIA2 may contain the same material as the first organic layer VIA1, or one or more materials selected from those exemplified as constituent materials of the first organic layer VIA1.

[0105] The fourth bridge pattern BRG4 can overlap with the third bridge pattern BRG3. The fourth bridge pattern BRG4 can be connected to the third bridge pattern BRG3 through contact holes that penetrate the second organic layer VIA2.

[0106] The j-th data line DLj can be disposed on the second organic layer VIA2. The j-th data line DLj can overlap with the first bridge pattern BRG1. The j-th data line DLj can be connected to the first bridge pattern BRG1 through a contact hole penetrating the second organic layer VIA2. In other words, the j-th data line DLj can be electrically connected to the first and second transistor electrodes ET21 through the first bridge pattern BRG1 and the second conductive layer GAT2.

[0107] The third organic layer VIA3 may be disposed on the j-th data line DLj and the fourth bridge pattern BRG4. The third organic layer VIA3 may be disposed substantially above the entire surface of the base layer SUB. The third organic layer VIA3 may contain the same material as the first organic layer VIA1, or may contain one or more materials selected from those exemplified as constituent materials of the first organic layer VIA1.

[0108] The display element layer (DPL) may include an anode (AD), a pixel defining layer (PDL), an emissive layer (EML), and a cathode (CD). The anode (AD), pixel defining layer (PDL), emissive layer (EML), and cathode (CD) may be arranged sequentially or formed on a third organic layer (VIA3).

[0109] The anode (AD) can be arranged on the third organic layer (VIA3). The anode (AD) can be arranged to correspond to the light-emitting area (EA) of each pixel. The non-light-emitting area (NEA) can surround each pixel.

[0110] The anode AD can be connected to the fourth bridge pattern BRG4 through a contact hole penetrating the third organic layer VIA3. The anode AD can be connected to the second sixth transistor electrode ET62 of the sixth transistor T6 through the third bridge pattern BRG3 and the fourth bridge pattern BRG4.

[0111] The anode AD can be made of a conductive material (or material) with a constant reflectivity. The conductive material (or material) can include opaque metals. Opaque metals can include, for example, metals such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), molybdenum (Mo), and alloys thereof. According to embodiments, the anode AD can include a transparent conductive material (or material). Transparent conductive materials (or materials) can include conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), and indium tin zinc oxide (ITZO), as well as conductive polymers such as poly(3,4-ethylenedioxythiophene) (PEDOT).

[0112] The pixel-defining layer (PDL) can be disposed in the non-emitting region (NEA) or formed on the third organic layer (VIA3) and the anode (AD). The PDL can partially overlap the edge of the anode (AD) in the non-emitting region (NEA). The PDL can include an insulating material comprising inorganic or organic materials. For example, the PDL can include at least one inorganic film comprising various inorganic insulating materials known in the art, such as silicon nitride (SiNx) or silicon oxide (SiOx). Alternatively, the PDL can include at least one organic film comprising various organic insulating materials known in the art, such as photoresist films, or can consist of a single layer or multiple layers of an insulator comprising a composite of organic and inorganic materials. In other words, the constituent materials of the PDL can be varied.

[0113] In one embodiment, the pixel defining layer (PDL) may be configured to include at least one light-shielding material or a reflective material to prevent light leakage defects between pixels. According to another embodiment, the PDL may include a transparent material. Transparent materials may include, for example, polyamide resin, polyimide resin, etc., but this disclosure is not limited thereto. According to another embodiment, a reflective material layer may be separately disposed or formed on the PDL to further improve the efficiency of light emitted from each pixel.

[0114] The emissive layer (EML) can be disposed on the anode (AD) within the emissive region (EA). That is, the EML can be formed individually for each of the multiple pixels (PXL). The EML can comprise organic or inorganic materials to emit a predetermined color. For example, pixel (PXij, see...) Figure 2 This can include a first sub-pixel through a third sub-pixel. Each of the first to third sub-pixels can emit red, green, and blue light.

[0115] However, this disclosure is not limited to this, and for example, the emissive layer EML can be shared across multiple pixels PXL. In this case, the emissive layer EML can emit white light.

[0116] The cathode (CD) can be placed on the emissive layer (EML). The cathode (CD) can be shared across multiple pixels (PXL).

[0117] The thin-film encapsulation layer TFE can be disposed on the cathode CD. The thin-film encapsulation layer TFE can be shared across multiple pixels PXL. Figure 3 In the diagram, the thin-film encapsulation layer TFE is shown as directly covering the cathode CD, but a capping layer covering the cathode CD can also be arranged between the thin-film encapsulation layer TFE and the cathode CD.

[0118] Figure 4 yes Figure 3 A magnified view of region X.

[0119] refer to Figure 3 and Figure 4 The first region of the second semiconductor pattern ACT_T2 can be connected to the second conductive layer GAT2 via the first and second transistor electrodes ET21. The first and second transistor electrodes ET21 can extend in a direction perpendicular to the second semiconductor pattern ACT_T2 (i.e., on the third direction DR3).

[0120] The j-th data line DLj can be disposed on the second organic layer VIA2. The j-th data line DLj can overlap with the first bridge pattern BRG1. The j-th data line DLj can be connected to the first bridge pattern BRG1 through a contact hole penetrating the second organic layer VIA2. The first bridge pattern BRG1 can overlap with the second conductive layer GAT2 and can be connected to the second conductive layer GAT2 through a contact hole penetrating the first organic layer VIA1. The contact hole can be formed to extend in a direction perpendicular to the second semiconductor pattern ACT_T2 (i.e., in the third direction DR3).

[0121] The second conductive layer GAT2 can extend along the first direction DR1. The positions where the first bridge pattern BRG1 and the first and second transistor electrodes ET21 are connected to the second conductive layer GAT2 can be spaced apart from each other along the first direction DR1 by a first length D1. Therefore, the position where the j-th data line DLj is connected to the first bridge pattern BRG1 can not overlap with the position where the first and second transistor electrodes ET21 and the first region of the second semiconductor pattern ACT_T2 are connected.

[0122] During use of the display device DD, an unexpected physical impact may occur at or near pixel PXij on the third-party DR3 (or in the direction perpendicular to the base layer SUB). When this happens, the distance between the j-th data line DLj and the second semiconductor pattern ACT_T2 on the third-party DR3 may be shortened due to compression caused by the impact. If the j-th data line DLj and the second semiconductor pattern ACT_T2 are short-circuited to each other, data signals may fail to be input, which could cause pixel PXij to appear as a bright spot.

[0123] In embodiments of this disclosure, the connection point between the j-th data line DLj and the first bridge pattern BRG1 does not overlap with the connection point between the first and second transistor electrodes ET21 and the first region of the second semiconductor pattern ACT_T2. This prevents the j-th data line DLj from short-circuiting with the second semiconductor pattern ACT_T2 due to unexpected physical impacts. Furthermore, it prevents data signals from failing to input and appearing as bright spots due to a short circuit in the j-th data line DLj.

[0124] Figure 5 This illustrates an embodiment. Figure 2 A partial cross-sectional view of the stacked structure of the second, third, and sixth transistor regions of the pixel.

[0125] refer to Figure 5 The pixel circuit layer PCL, the display element layer DPL, and the thin film encapsulation layer TFE can be sequentially arranged on the base layer SUB (or substrate).

[0126] The pixel circuit layer PCL may include a barrier layer BRL, a buffer layer BFL, a semiconductor layer ACT, a first insulating layer GI1, a first conductive layer GAT1, a second insulating layer GI2, a first organic layer VIA1, a second organic layer VIA2, and a third organic layer VIA3.

[0127] In the pixel circuit layer PCL, the blocking layer BRL, the buffer layer BFL, the semiconductor layer ACT, the first insulating layer GI1, the first conductive layer GAT1, the second insulating layer GI2, the first organic layer VIA1, the second organic layer VIA2, and the third organic layer VIA3 can be sequentially stacked on the base layer SUB on the third-direction DR3.

[0128] The second transistor T2 may include a second semiconductor pattern ACT_T2, a gate pattern T2_GE of the second transistor T2, a first second transistor electrode ET21' and a second second transistor electrode ET22.

[0129] The third transistor T3 may include a third semiconductor pattern ACT_T3, a gate pattern T3_GE of the third transistor T3, a first third transistor electrode ET31, and a second third transistor electrode ET32.

[0130] The sixth transistor T6 may include a sixth semiconductor pattern ACT_T6, a gate pattern T6_GE of the sixth transistor T6, a first sixth transistor electrode ET61, and a second sixth transistor electrode ET62.

[0131] When comparing Figure 3 and Figure 5 When implementing the method, Figure 5 The implementation may exclude the second conductive layer GAT2. Figure 5 Implementation methods and Figure 3 The difference in the implementation may lie in the first and second transistor electrodes ET21' and the first bridge pattern BRG1'. Therefore, unnecessary descriptions can be omitted below.

[0132] The first bridge pattern BRG1' can overlap with the second semiconductor pattern ACT_T2 and can be connected to the second semiconductor pattern ACT_T2 through contact holes penetrating the first organic layer VIA1, the first insulating layer GI1, and the second insulating layer GI2. More specifically, the first bridge pattern BRG1' can be connected to a first region of the second semiconductor pattern ACT_T2. The contact holes penetrating the first organic layer VIA1, the first insulating layer GI1, and the second insulating layer GI2 can be formed to extend in a direction perpendicular to the second semiconductor pattern ACT_T2 (or, in a third direction DR3).

[0133] and Figure 3 Compared to the first bridge pattern BRG1, the first bridge pattern BRG1' can have a shape that extends further in the first direction DR1. In other words, the width of the first bridge pattern BRG1' in the first direction DR1 can be greater than the width of the first bridge pattern BRG1 in the first direction DR1.

[0134] The j-th data line DLj can be electrically connected to the second semiconductor pattern ACT_T2 through the first bridge pattern BRG1'.

[0135] Figure 6 yes Figure 5 A magnified view of region Y.

[0136] refer to Figure 6 The first region of the second semiconductor pattern ACT_T2 can be connected to the region of the first bridge pattern BRG1'.

[0137] In addition, the j-th data line DLj can be connected to another area of ​​the first bridge pattern BRG1'.

[0138] Here, the region of the first bridge pattern BRG1' can be spaced apart from another region of the first bridge pattern BRG1' by a second length D2 in the first direction DR1. Therefore, the position where the j-th data line DLj and the first bridge pattern BRG1' are connected can not overlap with the position where the second semiconductor pattern ACT_T2 and the first bridge pattern BRG1' are connected.

[0139] During use of the display device DD, an unexpected physical impact may occur at or near pixel PXij on the third-party DR3 (or in the direction perpendicular to the base layer SUB). When this happens, the distance between the j-th data line DLj and the second semiconductor pattern ACT_T2 on the third-party DR3 may be shortened due to compression caused by the impact. If the j-th data line DLj and the second semiconductor pattern ACT_T2 are short-circuited to each other, data signals may fail to be input, which could cause pixel PXij to appear as a bright spot.

[0140] In embodiments of this disclosure, the connection point between the j-th data line DLj and the first bridge pattern BRG1' can be made non-overlapping with the connection point between the second semiconductor pattern ACT_T2 and the first bridge pattern BRG1'. This prevents the j-th data line DLj from short-circuiting with the second semiconductor pattern ACT_T2 due to unexpected physical impacts. Furthermore, it prevents the appearance of bright spots caused by short circuits in the j-th data line DLj, which are resulting from data signal input failures.

[0141] Figure 7 This illustrates an embodiment. Figure 2 A partial cross-sectional view of the stacked structure of the second, third, and sixth transistor regions of the pixel.

[0142] refer to Figure 7 The pixel circuit layer PCL, the display element layer DPL, and the thin film encapsulation layer TFE can be sequentially arranged on the base layer SUB (or substrate).

[0143] The pixel circuit layer PCL may include a barrier layer BRL, a buffer layer BFL, a semiconductor layer ACT, a first insulating layer GI1, a first conductive layer GAT1, a second insulating layer GI2, a first organic layer VIA1, a second organic layer VIA2, and a third organic layer VIA3.

[0144] In the pixel circuit layer PCL, the blocking layer BRL, the buffer layer BFL, the semiconductor layer ACT, the first insulating layer GI1, the first conductive layer GAT1, the second insulating layer GI2, the first organic layer VIA1, the second organic layer VIA2, and the third organic layer VIA3 can be sequentially stacked on the base layer SUB on the third-direction DR3.

[0145] The second transistor T2 may include a second semiconductor pattern ACT_T2, a gate pattern T2_GE of the second transistor T2, and a second transistor electrode ET22.

[0146] The third transistor T3 may include a third semiconductor pattern ACT_T3, a gate pattern T3_GE of the third transistor T3, a first third transistor electrode ET31, and a second third transistor electrode ET32.

[0147] The sixth transistor T6 may include a sixth semiconductor pattern ACT_T6, a gate pattern T6_GE of the sixth transistor T6, a first sixth transistor electrode ET61, and a second sixth transistor electrode ET62.

[0148] When comparing Figure 3 and Figure 7 When implementing the method, Figure 7 Implementation methods and Figure 3 The difference in the implementation methods may be that, Figure 7 The implementation includes a fifth bridge pattern BRG5 instead of the first and second transistor electrodes ET21. Therefore, redundant descriptions can be omitted below.

[0149] The fifth bridge pattern BRG5 may include multiple patterns extending from it. Any one of these patterns can be connected to the second conductive layer GAT2 via a contact hole penetrating the first organic layer VIA1. Another of these patterns can be connected to the second semiconductor pattern ACT_T2 via contact holes penetrating the first organic layer VIA1, the first insulating layer GI1, and the second insulating layer GI2. Each of these patterns may extend on a third direction DR3 and may be parallel to each other.

[0150] The j-th data line DLj can be electrically connected to the second semiconductor pattern ACT_T2 through the first bridge pattern BRG1, the second conductive layer GAT2, and the fifth bridge pattern BRG5.

[0151] Figure 8 yes Figure 7 A magnified view of region Z.

[0152] refer to Figure 8 The fifth bridge pattern BRG5 may include a first fifth bridge pattern BRG51, a second fifth bridge pattern BRG52, and a third fifth bridge pattern BRG53.

[0153] The first and fifth bridge pattern BRG51 can be arranged on the first organic layer VIA1 and can extend in the first direction DR1.

[0154] The second fifth bridge pattern BRG52 can be connected to the second conductive layer GAT2 through a contact hole penetrating the first organic layer VIA1. The second fifth bridge pattern BRG52 can extend from the area of ​​the first fifth bridge pattern BRG51 and can extend on the third-direction DR3.

[0155] The third fifth bridge pattern BRG53 can be connected to the second semiconductor pattern ACT_T2 through contact holes penetrating the first organic layer VIA1, the first insulating layer GI1, and the second insulating layer GI2. The third fifth bridge pattern BRG53 can extend from other areas of the first fifth bridge pattern BRG51 and can extend on the third-direction DR3.

[0156] Here, the region of the first bridge pattern BRG1 can be separated from the region of the third and fifth bridge patterns BRG53 by a third length D3 in the first direction DR1. The first and fifth bridge patterns BRG51 can be spaced apart from the first bridge pattern BRG1. The second conductive layer GAT2 can connect the second and fifth bridge patterns BRG52 and the first bridge pattern BRG1 in the first direction DR1.

[0157] Therefore, the position where the j-th data line DLj is connected to the first bridge pattern BRG1 can be non-overlapping with the position where the second semiconductor pattern ACT_T2 is connected to the fifth bridge pattern BRG5.

[0158] During use of the display device DD, an unexpected impact may be applied to pixel PXij on the third-party direction DR3 (or in the direction perpendicular to the base layer SUB). At this time, the distance between the j-th data line DLj and the second semiconductor pattern ACT_T2 on the third-party direction DR3 may be shortened due to compression caused by the impact. If the j-th data line DLj and the second semiconductor pattern ACT_T2 are short-circuited, data signals may fail to input, which can manifest as a bright spot.

[0159] In embodiments of this disclosure, the connection point between the j-th data line DLj and the first bridge pattern BRG1 may not overlap with the connection point between the second semiconductor pattern ACT_T2 and the fifth bridge pattern BRG5. Therefore, it is possible to prevent the j-th data line DLj from short-circuiting with the second semiconductor pattern ACT_T2 due to unexpected impacts. Furthermore, it is possible to prevent data signals from failing to input and exhibiting a bright spot due to a short circuit in the j-th data line DLj.

[0160] The display device according to the embodiments can be applied to various types of electronic devices. In the embodiments, the electronic device includes the display device described above, and may also include other modules or devices with additional functions besides the display device.

[0161] Figure 9 This is a block diagram of an electronic device according to an embodiment. (Reference) Figure 9 The electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0162] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0163] The memory 13 can store data and / or information used to operate the processor 12 or the display module 11. When the processor 12 executes an application stored in the memory 13, image data signals and / or input control signals can be transmitted to the display module 11. The display module 11 can process the provided signals and output image information on the display screen.

[0164] The power module 14 may include a power module such as a power adapter or battery device, and a power conversion module. The power conversion module converts the power supplied by the power module and generates power to operate the electronic device 10.

[0165] At least one of the components described above for electronic device 10 may be included in the display device according to the embodiments described above. Furthermore, in terms of functionality, some of the individual modules included in a single module may be included in the display device, while other modules may be disposed separately from the display device. For example, display module 11 is included in the display device, while processor 12, memory 13, and power module 14 are not included in the display device and are instead disposed separately in electronic device 10.

[0166] Figure 10 Schematic diagrams illustrating various embodiments of the electronic device are shown.

[0167] refer to Figure 10 Various types of electronic devices that can be implemented using display devices may include: electronic devices for displaying images, such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, televisions (TVs) 10_1d, and desktop monitors 10_1e; wearable electronic devices that include display modules, such as smart glasses 10_2a, head-mounted displays (HMDs) 10_2b, and smartwatches 10_2c; and automotive electronic devices 10_3 that include display modules, such as central information displays (CIDs) and rearview mirror displays located in the vehicle's instrument cluster, center console, and dashboard.

[0168] Although this disclosure has been described with reference to embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made thereto without departing from the scope and spirit of this disclosure as set forth in the appended claims.

Claims

1. A display device, comprising: A second semiconductor pattern and a first and second transistor electrode, wherein the first and second transistor electrodes are connected to the second semiconductor pattern in a direction perpendicular to the second semiconductor pattern; A second conductive layer is located on and connected to the first second transistor electrode; The first bridge pattern is located on and connected to the second conductive layer; as well as A data line, connected to the first bridge pattern, supplies data signals to the second semiconductor pattern. Wherein, the first region where the second semiconductor pattern and the first and second transistor electrodes are connected does not overlap with the second region where the data line and the first bridge pattern are connected.

2. The display device according to claim 1, wherein, The first and second transistor electrodes are connected to a third region of the second conductive layer and the first bridge pattern is connected to a fourth region of the second conductive layer, which are spaced apart by a first length in the direction in which the second conductive layer extends.

3. The display device according to claim 1, wherein, Each of the second semiconductor pattern and the second conductive layer extends in the first direction. The first and second transistor electrodes extend upward in a third direction perpendicular to the first direction, and The second conductive layer overlaps with the second semiconductor pattern in a certain region.

4. The display device according to claim 1, wherein, The first and second transistor electrodes are electrically connected to the second semiconductor pattern and the second conductive layer through contact holes in the first and second insulating layers located between the second semiconductor pattern and the second conductive layer.

5. The display device according to claim 4, wherein, The second conductive layer includes a first layer containing titanium and disposed on the second insulating layer and a second layer containing molybdenum and disposed on the first layer.

6. The display device according to claim 4, wherein, The second conductive layer includes a first layer containing titanium and disposed on the second insulating layer, a second layer containing aluminum and disposed on the first layer, and a third layer containing titanium and disposed on the second layer.

7. The display device according to claim 1, wherein, The first bridge pattern is connected to the second conductive layer through a contact hole in the first organic layer located between the first bridge pattern and the second conductive layer.

8. A display device, comprising: A second semiconductor pattern and a first and second transistor electrode, wherein the first and second transistor electrodes are connected to the second semiconductor pattern in a direction perpendicular to the second semiconductor pattern; The first bridge pattern is located on and connected to the first and second transistor electrodes; as well as A data line, connected to the first bridge pattern, supplies data signals to the second semiconductor pattern. Wherein, the first region where the second semiconductor pattern and the first and second transistor electrodes are connected does not overlap with the second region where the data line and the first bridge pattern are connected.

9. The display device according to claim 8, wherein, The first and second transistor electrodes are connected to a third region of the first bridge pattern and the data line is connected to a fourth region of the first bridge pattern, which are spaced apart by a second length in the direction in which the first bridge pattern extends.

10. The display device according to claim 8, wherein, Each of the second semiconductor pattern and the first bridge pattern extends in a first direction. The first and second transistor electrodes extend upward in a third direction perpendicular to the first direction, and The first bridge pattern overlaps with the second semiconductor pattern in a certain area.

11. The display device according to claim 8, wherein, The first and second transistor electrodes are connected to the first bridge pattern through contact holes that penetrate the first insulating layer, the second insulating layer, and the first organic layer located between the first bridge pattern and the second semiconductor pattern.

12. The display device according to claim 8, wherein, The data line is connected to the first bridge pattern through a contact hole that penetrates a second organic layer located between the first bridge pattern and the data line.

13. Electronic devices, including: A processor used to provide input image data; as well as A display device for displaying an image based on the input image. The display device includes: A second semiconductor pattern and a second conductive layer located on the second semiconductor pattern; The fifth bridge pattern is located on the second semiconductor pattern and the second conductive layer to electrically connect the second semiconductor pattern and the second conductive layer; A first bridge pattern is located on and connected to the second conductive layer; and A data line, connected to the first bridge pattern, supplies data signals to the second semiconductor pattern. The first region where the second semiconductor pattern and the fifth bridge pattern are connected does not overlap with the second region where the data line and the first bridge pattern are connected.

14. The electronic device according to claim 13, wherein, The fifth bridge pattern includes a first fifth bridge pattern and a second and a third fifth bridge pattern extending from the first fifth bridge pattern in a direction perpendicular to the second semiconductor pattern. The second fifth bridge pattern is connected to the second conductive layer through a contact hole in the first organic layer located between the first fifth bridge pattern and the second conductive layer. The third fifth bridge pattern is connected to the second semiconductor pattern through a contact hole located between the first fifth bridge pattern and the second semiconductor pattern, through the first insulating layer, the second insulating layer, and the first organic layer.

15. The electronic device according to claim 14, wherein, The second conductive layer includes a first layer containing titanium and disposed on the second insulating layer, and a second layer containing molybdenum and disposed on the first layer.

16. The electronic device according to claim 14, wherein, The second conductive layer includes a first layer containing titanium and disposed on the second insulating layer, a second layer containing aluminum and disposed on the first layer, and a third layer containing titanium and disposed on the second layer.

17. The electronic device according to claim 14, wherein, The third and fifth bridge patterns are connected to the third region of the second semiconductor pattern and the first bridge pattern is connected to the fourth region of the second conductive layer, which are spaced apart by a third length in the direction in which the second conductive layer extends.

18. The electronic device according to claim 13, wherein, The first bridge pattern is connected to the second conductive layer through a contact hole in the first organic layer located between the first bridge pattern and the second conductive layer.

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