Display device, wearable electronic device, and method of manufacturing display device

Abstract

Provided are a display device, a wearable electronic device, and a method of manufacturing the display device, the display device including: a substrate in which a display area and a non-display area are defined, and the substrate having first and second surfaces opposing each other in a thickness direction of the substrate, and a side surface between the first and second surfaces; a display section on the first surface of the substrate in the display area and configured to display an image; a pad portion on the first surface of the substrate in the non-display area; a filling layer on the display portion and configured to cover the display portion; and a chamfered portion on at least a portion of a side surface of the substrate. The side surface of the substrate may include at least one crack extending in one direction intersecting the thickness direction.

Description

[0001] This application claims priority to and the benefit of Korean Patent Application No. 10-2024-0081269, filed on June 21, 2024, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2024-0092545, filed on July 12, 2024, in the Korean Intellectual Property Office, the entire contents of each of which are incorporated herein by reference. TECHNICAL FIELD

[0002] One or more embodiments of the present disclosure relate to a display device, a wearable electronic device, and a method of manufacturing the display device. BACKGROUND

[0003] Recently, as interest in information displays has rapidly increased, research and development of display devices have been continuously ongoing. SUMMARY

[0004] One or more aspects of embodiments of the present disclosure relate to a display device, a wearable electronic device, and a method of manufacturing the display device, which have (have) improved manufacturing efficiency and reliability.

[0005] Additional aspects will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following description, or can be learned by practice of the presented embodiments.

[0006] According to one or more embodiments of the present disclosure, a display device includes a substrate in which a display area and a non-display area are defined, and the substrate has a first surface and a second surface opposite each other in a thickness direction (e.g., in a thickness direction of the substrate), and a side surface between the first surface and the second surface; a display portion on (e.g., disposed on) the first surface of the substrate in the display area and configured to display an image; a pad portion on (e.g., disposed on) the first surface of the substrate in the non-display area; a filling layer on (e.g., disposed on) the display portion and configured to cover the display portion; and a chamfer portion on at least a portion of the side surface of the substrate. The side surface of the substrate can include at least one crack extending in a direction (e.g., one direction) intersecting the thickness direction.

[0007] The side surface of the substrate connected to the chamfer portion can have a curved surface.

[0008] The filling layer can include a transparent curable resin, and can be located on an uppermost layer (e.g., an uppermost layer of the display portion) in the display area.

[0009] The substrate can include a silicon wafer substrate.

[0010] In one or more embodiments, the display device may also include a side sealing member on the chamfer (e.g., arranged on the chamfer) to cover the chamfer.

[0011] The display unit may include: an anode on a substrate (e.g., disposed on a substrate); a pixel defining layer on a substrate (e.g., disposed on a substrate) and including an opening configured to expose a portion of the anode; an emission structure on the anode and the pixel defining layer (e.g., disposed on the anode and the pixel defining layer); and a cathode on the emission structure (e.g., disposed on the emission structure).

[0012] In one or more embodiments, the emitting structure may include: a first emitting unit on an anode and pixel defining layer (e.g., disposed on an anode and pixel defining layer) and configured to emit light; an intermediate layer on the first emitting unit (e.g., disposed on the first emitting unit); and a second emitting unit on the intermediate layer (e.g., disposed on the intermediate layer) and configured to emit light.

[0013] In one or more embodiments, the emitting structure may include: a first emitting unit on an anode and pixel defining layer (e.g., disposed on an anode and pixel defining layer) and configured to emit light; a first intermediate layer on the first emitting unit (e.g., disposed on the first emitting unit); a second emitting unit on the first intermediate layer (e.g., disposed on the first intermediate layer) and configured to emit light; a second intermediate layer on the second emitting unit (e.g., disposed on the second emitting unit); and a third emitting unit on the second intermediate layer (e.g., disposed on the second intermediate layer) and configured to emit light.

[0014] According to one or more embodiments of this disclosure, a wearable electronic device includes: a display panel; and a lens on the display panel (e.g., disposed on the display panel). The display panel may include: a substrate defining a display area and a non-display area therein, and the substrate having a first surface and a second surface opposite to each other in a thickness direction (e.g., the thickness direction of the substrate) and a side surface located between the first surface and the second surface; a display portion on the first surface of the substrate in the display area (e.g., disposed on the first surface of the substrate) and configured to display an image; a pad portion on the first surface of the substrate in the non-display area (e.g., disposed on the first surface of the substrate); a filler layer on the display portion (e.g., disposed on the display portion) and configured to cover the display portion; and a chamfer portion located on at least a portion of the side surface of the substrate. The side surface of the substrate may include at least one crack extending in a direction intersecting the thickness direction (e.g., a direction).

[0015] The filler layer may include a transparent curable resin and is located on the topmost layer in the display area (e.g., the topmost layer of the display section).

[0016] The substrate may include a silicon wafer substrate.

[0017] In one or more embodiments, the display panel may also include a side sealing member on the chamfer (e.g., arranged on the chamfer) to cover the chamfer.

[0018] The display unit may include: an anode on a substrate (e.g., disposed on a substrate); a pixel defining layer on a substrate (e.g., disposed on a substrate) and including an opening configured to expose a portion of the anode; an emission structure on the anode and the pixel defining layer (e.g., disposed on the anode and the pixel defining layer); and a cathode on the emission structure (e.g., disposed on the emission structure).

[0019] The display device according to one or more of the above embodiments can be manufactured by a method of manufacturing a display device, the method comprising the following steps: preparing a mother substrate comprising a plurality of display units; forming a fill layer on the display portion of each of the plurality of display units; irradiating a first laser beam corresponding to the boundary point between two adjacent display units among the plurality of display units onto a first surface of the mother substrate, and forming a cutting alignment mark on a second surface of the mother substrate opposite to the first surface; and flipping the mother substrate so that the second surface faces upward, irradiating the cutting alignment mark with a second laser beam to form a chamfer, and then separating each of the plurality of display units individually.

[0020] The first laser beam may be a laser with a wavelength that penetrates the mother substrate, and the second laser beam may be a laser with a wavelength that is absorbed by the mother substrate.

[0021] The parent substrate may include a silicon wafer substrate, the first laser beam may include an infrared laser, and the second laser beam may include a visible laser.

[0022] In the step of forming the cutting alignment mark, when the first laser beam is irradiated onto the first surface of the mother substrate, at least one crack can be formed inside the mother substrate.

[0023] In the step of separating each of the multiple display units individually, heat can be generated when the second laser beam is irradiated onto the cutting alignment mark, and at least one crack can propagate due to the heat, allowing the mother substrate to expand to separate individually into each of the multiple display units.

[0024] In one or more embodiments, the method may further include: after the step of individually separating each of the plurality of display units, forming a side sealing member configured to cover the chamfer.

[0025] The filler layer may include a transparent curable resin and is located on the top layer of the display portion of each of the plurality of display units. Attached Figure Description

[0026] Exemplary embodiments will now be described more fully below with reference to the accompanying drawings; however, they may be implemented in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the exemplary embodiments to those skilled in the art. Some of the above and other aspects, features, and advantages of this disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings.

[0027] Figure 1 This is a schematic plan view illustrating a mother substrate according to one or more embodiments of the present disclosure.

[0028] Figure 2 It is shown Figure 1 A schematic enlarged view of part of EA.

[0029] Figure 3 It is along Figure 2 A schematic cross-sectional view taken from line I-I'.

[0030] Figure 4 This is a schematic block diagram illustrating a display device according to one or more embodiments of the present disclosure.

[0031] Figure 5 This is a schematic plan view illustrating a display device according to one or more embodiments of the present disclosure.

[0032] Figure 6 It is shown Figure 5 An exploded perspective view of a portion of the display panel.

[0033] Figure 7 This illustrates one or more embodiments according to the present disclosure. Figure 6 A schematic planar view of one of the pixels.

[0034] Figure 8 It is according to one or more embodiments of this disclosure along Figure 7 A schematic cross-sectional view taken from line II-II'.

[0035] Figure 9 It is according to one or more embodiments of this disclosure along Figure 7 A schematic cross-sectional view taken from line II-II'.

[0036] Figure 10 This illustrates one or more embodiments according to the present disclosure, including... Figure 8 orFigure 9 A schematic cross-sectional view of the emitting structure in one of the first to third light-emitting elements.

[0037] Figure 11 This illustrates one or more embodiments according to the present disclosure, including... Figure 8 or Figure 9 A schematic cross-sectional view of a portion of the emitting structure in one of the first to third light-emitting elements.

[0038] Figure 12 This is a schematic block diagram illustrating a method of manufacturing a display device according to one or more embodiments of the present disclosure.

[0039] Figures 13 to 21 These are plan views and cross-sectional views illustrating the process operations of a method for manufacturing a display device according to one or more embodiments of the present disclosure.

[0040] Figure 22 It is shown Figure 21 The second schematic cross-sectional perspective view shows a portion of the individual unit.

[0041] Figure 23 The display shows Figure 19 A schematic diagram of the crack in the image.

[0042] Figure 24 This is a schematic block diagram illustrating a display system according to one or more embodiments of the present disclosure.

[0043] Figure 25 This illustrates one or more embodiments according to the present disclosure. Figure 24 A schematic perspective view illustrating an application example of the display system.

[0044] Figure 26 This illustrates a user wearing one or more embodiments according to this disclosure. Figure 25 A schematic diagram of the status of the head-mounted display device. Detailed Implementation

[0045] It will be apparent to those skilled in the art that one or more suitable modifications and variations may be made to this disclosure without departing from the spirit or scope of the disclosure, and specific exemplary embodiments are shown in the accompanying drawings and explained in the detailed description. However, it should be understood that this is not intended to limit the disclosure to any particular form of disclosure, and therefore includes all modifications, equivalents, and substitutions included within the scope of the disclosed technology.

[0046] In the following description, exemplary embodiments of the disclosure will be described in more detail with reference to the accompanying drawings. It should be noted in the following description that only the parts necessary for understanding operation according to this disclosure will be described, and descriptions of other parts will not be provided so as not to obscure the subject matter of the disclosure. Furthermore, this disclosure is not limited to the embodiments described below, but may be implemented in other forms. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the disclosure to those skilled in the art.

[0047] Throughout this disclosure, it will be understood that if an element is referred to as being “bonded” or “connected” to another element, then the element may be directly bonded or directly connected to said other element, or one or more intermediary elements may exist between them (e.g., when an element is referred to as being “bonded” or “connected” to another element, the element may be directly bonded or directly connected to said other element, or one or more intermediary elements may exist between them). Furthermore, the expression that an element, such as a layer, region, substrate, or plate, is placed “on” another element indicates not only an embodiment in which the element is placed “directly” on “said other element,” but also an embodiment in which another element may be placed between the element and said other element. Conversely, if an element is referred to as being “directly on” another element, then there are no intermediary elements in between (e.g., when an element is referred to as being “directly on” another element, there are no intermediary elements in between). The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting of the disclosure. Throughout this disclosure, unless explicitly stated otherwise, the words “including / comprises / have” and variations thereof will be understood to imply inclusion of the stated elements but not exclusion of any other elements. “At least one of X, Y, and Z,” “selected from at least one of X, Y, and Z,” and “selected from at least one of the group consisting of X, Y, and Z” can be interpreted as each of X, Y, and Z, or two or more of X, Y, and Z (e.g., any suitable combination, such as XYZ, XY, YZ, and XZ). As used herein, “and / or” or “or” can include one or more combinations of corresponding components.

[0048] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe one or more suitable elements, these elements are not limited by these terms. These terms are used to distinguish one element from another. Therefore, the first element described may also be referred to as the second or third element without departing from the spirit and scope of the disclosure. As utilized herein, unless the context clearly indicates otherwise, the singular forms “a” and their variations, “an,” and “the” are also intended to include the plural forms. Furthermore, when describing embodiments of this disclosure, the use of “may” refers to one or more embodiments of this disclosure.

[0049] Spatial relative terms such as “below,” “under,” “lower,” “above,” and / or “upper” may be used herein for descriptive purposes to describe the relationship of one element or feature to another (or more) elements or features as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are intended to cover different orientations of the device during use, operation, and / or manufacture. For example, if the device in the drawings is flipped (e.g., inverted), an element described as “below” or “under” other elements or features will subsequently be oriented “above” other elements or features (e.g., when the device in the drawings is flipped (e.g., inverted), an element described as “below” or “under” other elements or features will subsequently be oriented “above” other elements or features). Thus, in one or more embodiments, the example term “below” may (e.g., simultaneously) cover both the upper and lower orientations. Furthermore, the device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and thus, the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0050] One or more embodiments are described with reference to the accompanying drawings, which schematically illustrate exemplary embodiments. Therefore, it will be contemplated that the shape may vary depending on, for example, tolerances and / or manufacturing techniques. Consequently, the one or more embodiments disclosed herein should not be construed as limited to the specific shapes shown herein, but should be interpreted to include shape variations caused, for example, by manufacturing processes. Thus, the shapes shown in the drawings may not depict certain actual shapes of areas of the device, and the given embodiments are not limited thereto.

[0051] Figure 1 This is a schematic plan view illustrating a mother substrate MS according to one or more embodiments of the present disclosure.

[0052] Reference Figure 1For ease of manufacturing, the mother substrate MS can be a substrate for concurrently (e.g., simultaneously) manufacturing multiple display unit DCs. In other words, for ease of manufacturing, the mother substrate MS can be a substrate on which multiple display unit DCs are manufactured. The mother substrate MS may include one or more cell regions. A cell region may be a portion corresponding to a single display unit DC (or a single display device), and a separate display unit DC can be formed for each cell region.

[0053] In one or more embodiments, the parent substrate MS may be a silicon wafer substrate formed using semiconductor processes. In one or more embodiments, the parent substrate MS may include semiconductor materials such as group IV semiconductors, group III-V compound semiconductors, or group II-VI compound semiconductors, but the embodiments of this disclosure are not limited thereto.

[0054] Each of the display unit DCs can be individually separated for use as a display device, and multiple display unit DCs can be formed concurrently (e.g., simultaneously) on a mother substrate MS, and then separated by a cutting process, etc. In one or more embodiments, as Figure 1 As shown in part EA, multiple display units DC can be disposed on the mother substrate MS and arranged in a matrix according to rows (or display unit rows) extending in the first direction DR1 and columns (or display unit columns) extending in the second direction DR2, but the embodiments of this disclosure are not limited thereto.

[0055] Figure 2 It is shown Figure 1 A schematic enlarged view of part of EA. Figure 3 It is along Figure 2 A schematic cross-sectional view taken from line I-I'.

[0056] Reference Figures 1 to 3 The mother substrate MS may be provided with a dicing line CUL corresponding to each of the display units DC (or display devices DD). Each of the display units DC (or display devices DD) can be individually separated by a process of cutting the mother substrate MS along the dicing line CUL using a laser beam. In one or more embodiments of this disclosure, the terms "display unit" and "display device" may be used interchangeably.

[0057] Each of the display units DC can be a flat panel display device, a flexible display device, a curved display device, a foldable display device, a bendable display device, or a rollable display device. In one or more embodiments, each of the display units DC can be applied to transparent display devices, head-mounted display (HMD) devices, and / or wearable display devices, etc.

[0058] The mother substrate MS can become the substrate SUB, which serves as the base substrate of the display unit DC, after the display unit DC is separated individually.

[0059] Display unit DC may include a first display unit DC1 (or a first display device DD1) and a second display unit DC2 (or a second display device DD2). The first display unit DC1 may be arranged in an odd-numbered row of the parent substrate MS, and the second display unit DC2 may be arranged in an even-numbered row of the parent substrate MS. In one or more embodiments, the first display unit DC1 and the second display unit DC2 may be configured to be substantially identical. Hereinafter, the first display unit DC1 and the second display unit DC2 will be collectively referred to as display unit DC and / or display device DD.

[0060] Each of the display units DC may include a display portion DPP and a pad portion PDP. The display portion DPP may be located in the display area DA, and the pad portion PDP may be located in a region (e.g., a pad region) outside the display area NDA.

[0061] The display panel (DPP) may include a substrate (SUB), a pixel circuit layer (PCL), a light-emitting element layer (LDL), and an optical functional layer (OFL).

[0062] The substrate SUB can be a region of the parent substrate MS, and can be a silicon wafer substrate. The substrate SUB can include a display area DA in which an image is displayed and a non-display area NDA in which no image is displayed.

[0063] The pixel circuit layer (PCL) can be on the substrate (e.g., disposed on the substrate), and can include circuit elements.

[0064] The light-emitting element layer (LDL) can be on the pixel circuit layer (PCL) (e.g., disposed on the pixel circuit layer PCL) and can include light-emitting elements.

[0065] The optical functional layer OFL can be on the light-emitting element layer LDL (e.g., disposed on the light-emitting element layer LDL) and can include a microlens array to improve the extraction efficiency of light emitted from the light-emitting element layer LDL, but the embodiments disclosed herein are not limited thereto.

[0066] After the process of separating the mother substrate (MS) into individual display units (DCs), external connection terminals can be attached to the pad portion (PDP). The display unit DCs can be electrically connected to the outside via the external connection terminals attached to the pad portion (PDP).

[0067] The display unit (DPP) can be positioned adjacent to the cutting alignment mark (CUL) (corresponding to the cutting line CUL) located between the first display unit (DC1) and the second display unit (DC2). In this respect, if viewed from above (e.g., in a plan view), the display units (DPP) of each of the first display units (DC1) and the display units (DPP) of each of the second display units (DC2) can face each other in the second direction (DR2) (e.g., they can be adjacent to each other in the second direction (DR2)). However, the arrangement of the display units (DPP) of each of the first display units (DC1) and the second display units (DC2) is not limited to this. The cutting alignment mark (CUL) can be formed on the rear surface of the mother substrate (MS) and can correspond to the cutting line irradiated by the laser beam during the process of separating the mother substrate (MS) into each display unit (DC) in units. The cut alignment mark CUL can be formed in essentially the same process as the crack CR formed in the internal space of the mother substrate MS. (See reference...) Figure 19 The cut alignment mark CUL and crack CR will be described in detail.

[0068] Each of the display units DC may include a fill layer FIL, which is located on and covers the display unit DPP.

[0069] The filler layer FIL may comprise a curable resin having a certain level or greater viscosity. In one or more embodiments, the filler layer FIL may be made of an epoxy resin or a silicone resin. For example, in one or more embodiments, the epoxy resin may have a viscosity (cps) of about 19 to about 5400, but the disclosed embodiments are not limited thereto.

[0070] In one or more embodiments, after forming the display portion DPP on the parent substrate MS, a coating solution corresponding to the matrix material of the filler layer FIL can be applied to the display portion DPP, and then a curing process using light or heat can be performed to form the filler layer FIL in each of the display monomers DC. However, the method of forming the filler layer FIL is not limited to the embodiments described above.

[0071] The fill layer (FIL) can be located on top of the display portion (DPP) within the display area (DA) of each display unit (DC). For example, the fill layer (FIL) can be located on top of the display portion (DPP) within the display area (DA) of each display unit (DC) and can completely cover the components located below the fill layer (FIL). In one or more embodiments, the fill layer (FIL) can protect each display unit (DC) from external impacts, etc., and can provide an input surface and / or a display surface to the user. The fill layer (FIL) can be a cover member.

[0072] Figure 4 This is a schematic block diagram illustrating a display device DD according to one or more embodiments of the present disclosure.

[0073] Reference Figure 4 The display device DD may include a display panel DP, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150. The display panel DP may include a reference... Figure 2 and Figure 3 The description includes the display section (DPP) and the fill layer (FIL).

[0074] The display panel DP may include sub-pixels SP. Sub-pixels SP can be connected to gate driver 120 via first gate line GL1 to m-th gate line GLm. Sub-pixels SP can be connected to data driver 130 via first data line DL1 to n-th data line DLn, where m and n are positive integers greater than 1.

[0075] Each of the sub-pixels SP may include one or more light-emitting elements configured to generate light. Therefore, each of the sub-pixels SP can generate light having a specific color such as red, green, blue, cyan, magenta, or yellow. Two or more sub-pixels SP can constitute a pixel PXL. For example, in one or more embodiments, such as Figure 4 As shown, three sub-pixels SP can form a pixel PXL.

[0076] Gate driver 120 can be connected to sub-pixels SP arranged in the row direction via first gate lines GL1 to m-th gate lines GLm. Gate driver 120 can output gate signals to first gate lines GL1 to m-th gate lines GLm in response to gate control signal GCS. In one or more embodiments, gate control signal GCS may include a start signal indicating the start of each frame and / or a horizontal synchronization signal for timing-synchronizing the output of gate signals with applied data signals, etc.

[0077] In one or more embodiments, first emission control lines EL1 to m-th emission control lines ELm may also be provided connected in the row direction to the sub-pixel SP. In this regard, the gate driver 120 may include an emission control driver configured to control the first emission control lines EL1 to m-th emission control lines ELm. The emission control driver may operate under the control of the controller 150.

[0078] In one or more embodiments, the gate driver 120 may be arranged on one side of the display panel DP. However, the embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, the gate driver 120 may be divided into two or more physically and / or logically separate drivers, and such drivers may be arranged on one side of the display panel DP and on the opposite side of the display panel DP. Thus, according to one or more embodiments, the gate driver 120 may be arranged around the display panel DP in one or more suitable shapes.

[0079] Data driver 130 can be connected to sub-pixels SP arranged in the column direction via first data lines DL1 to nth data lines DLn. Data driver 130 can receive image data DATA and data control signal DCS from controller 150. Data driver 130 can operate in response to data control signal DCS. In one or more embodiments, data control signal DCS may include source start pulse signal, source shift clock signal and / or source output enable signal, etc.

[0080] The data driver 130 can use the voltage from the voltage generator 140 to apply a data signal having a grayscale voltage corresponding to the image data DATA to the first data lines DL1 to the nth data line DLn. When a gate signal is applied to each of the first gate lines GL1 to the mth gate line GLm, the data signal corresponding to the image data DATA can be applied to the first data lines DL1 to the nth data line DLn. Therefore, the corresponding sub-pixel SP can generate light corresponding to the data signal. Thus, an image can be displayed on the display panel DP.

[0081] In one or more embodiments, both the gate driver 120 and the data driver 130 may include complementary metal-oxide-semiconductor (CMOS) circuit elements.

[0082] Voltage generator 140 can operate in response to a voltage control signal (VCS) from controller 150. Voltage generator 140 can be configured to generate multiple voltages and provide the generated voltages to components of display device DD. For example, voltage generator 140 can be configured to receive an input voltage from outside display device DD, regulate the received voltage, and adjust the regulated voltage to generate multiple voltages.

[0083] In one or more embodiments, voltage generator 140 can generate a first power voltage VDD and a second power voltage VSS, and can provide the generated first power voltage VDD and second power voltage VSS to sub-pixel SP. The first power voltage VDD can have a relatively high voltage level, and the second power voltage VSS can have a lower voltage level than the first power voltage VDD. In one or more embodiments, the first power voltage VDD or the second power voltage VSS can be provided by an external device of display device DD.

[0084] Furthermore, voltage generator 140 can generate one or more suitable and / or designed voltages. For example, in one or more embodiments, voltage generator 140 can generate an initialization voltage applied to the sub-pixel SP. For example, in one or more embodiments, during sensing operation of sensing the electrical characteristics of the transistors and / or light-emitting elements of the sub-pixel SP, a specific reference voltage can be applied to the first data lines DL1 to the nth data lines DLn, and voltage generator 140 can generate such a reference voltage.

[0085] The controller 150 can control the overall operation of the display device DD. The controller 150 can receive input image data IMG and a control signal CTRL for controlling the display of the input image data IMG from an external source. In response to the received control signal CTRL, the controller 150 can provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS.

[0086] The controller 150 can output image data DATA by converting input image data IMG into a format suitable for a display device DD or a display panel DP. In one or more embodiments, the controller 150 can output image data DATA by aligning the input image data IMG to a format suitable for sub-pixels SP in rows.

[0087] Two or more components (e.g., two or more components selected from data driver 130, voltage generator 140, and controller 150) can be mounted on a single integrated circuit. Figure 4As shown, in one or more embodiments, the data driver 130, voltage generator 140, and controller 150 may be included in a driver integrated circuit (DIC). In these embodiments, the data driver 130, voltage generator 140, and controller 150 may be functionally separate components within a single driver integrated circuit (DIC). In one or more embodiments, at least one of the data driver 130, voltage generator 140, and controller 150 may be configured as a component separate from the driver integrated circuit (DIC).

[0088] The display device DD may include one or more temperature sensors 160. The temperature sensor 160 may be configured to detect the temperature around it and generate temperature data TEP indicating the detected temperature. In one or more embodiments, the temperature sensor 160 may be arranged adjacent to the display panel DP and / or the driver integrated circuit DIC.

[0089] The controller 150 may control one or more suitable operations of the display device DD in response to temperature data TEP. In one or more embodiments, the controller 150 may adjust the brightness of the image output from the display panel DP in response to temperature data TEP. For example, the controller 150 may adjust the data signal and the first power voltage VDD and the second power voltage VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0090] Figure 5 This is a schematic plan view illustrating a display device DD according to one or more embodiments of the present disclosure. Figure 5 For convenience, the structure of the display device DD (e.g., the structure of the display panel DP provided in the display device DD) is briefly shown with the display area DA in which the image is displayed as the center.

[0091] Reference Figure 5 The display panel (DP) can include the display area (DA) and the non-display area (NDA).

[0092] The display panel (DP) can display images through the display area (DA). The non-display area (NDA) can be arranged around the display area (DA).

[0093] The display panel (DP) can include a base (SUB), subpixels (SP), and pads (PD).

[0094] In embodiments where the display panel DP is used as a display screen for head-mounted display (HMD) devices, virtual reality (VR) devices, mixed reality (MR) devices, and / or augmented reality (AR) devices, the display panel DP can be positioned very close to the user's eyes. In these embodiments, subpixels SP with a relatively high degree of integration may be desired or required. To increase the integration of the subpixels SP, the substrate SUB can be set as a silicon substrate (or silicon wafer), but embodiments of this disclosure are not limited thereto. Subpixels SP and / or other components of the display panel DP can be formed on the silicon substrate SUB. A display device DD including a display panel DP having a substrate SUB as a silicon substrate can be referred to as an OLED-on-silicon (OLEDoS) display device.

[0095] Subpixels SP can be arranged on the substrate SUB in the display area DA. Subpixels SP can be arranged in a matrix on a first direction DR1 and a second direction DR2 intersecting the first direction DR1, but the arrangement of subpixels SP is not limited to this. For example, in one or more embodiments, subpixels SP can be arranged in a zigzag pattern on the first direction DR1 and the second direction DR2. For example, in one or more embodiments, subpixels SP can be arranged in a pentiline pattern. ® Arrangement in a specific format (e.g., RGBG matrix, RGBG structure, or RGBG matrix structure). PENTILE ® It is an officially registered trademark of Samsung Display Co., Ltd. The first direction DR1 can be the row direction, and the second direction DR2 can be the column direction.

[0096] Among multiple sub-pixels SP, two or more sub-pixels SP can form a pixel PXL.

[0097] Components for controlling sub-pixels SP can be arranged on the substrate SUB in the non-display area NDA. For example, in one or more embodiments, interconnects connected to the sub-pixels SP (such as...) Figure 4 The first gate line GL1 to the m gate line GLm and the first data line DL1 to the n data line DLn can be arranged in the non-display area NDA.

[0098] In one or more embodiments, Figure 4 At least one of the gate driver 120, data driver 130, voltage generator 140, controller 150, and temperature sensor 160 may be integrated into the non-display area NDA of the display panel DP. In one or more embodiments, Figure 4The gate driver 120 can be mounted on the display panel DP and disposed in the non-display area NDA. In one or more embodiments, the gate driver 120 can be implemented as an integrated circuit separate from the display panel DP. In one or more embodiments, the temperature sensor 160 can be disposed in the non-display area NDA to detect the temperature of the display panel DP.

[0099] The pad PD can be disposed on the substrate SUB in the non-display area NDA. The pad PD can be electrically connected to the sub-pixel SP via interconnects. For example, in one or more embodiments, the pad PD can be connected to the sub-pixel SP via first data lines DL1 to nth data lines DLn. The pad PD can be included in the reference... Figure 2 and Figure 3 The padding portion of the PDP is described.

[0100] The pad PD allows the display panel DP to connect to other components of the display device DD. In one or more embodiments, the voltages and signals necessary for operating the components included in the display panel DP can be transmitted from the display panel PD via the pad PD. Figure 4 The driver integrated circuit (DIC) is provided. For example, in one or more embodiments, the first data line DL1 to the nth data line DLn can be connected to the driver integrated circuit (DIC) via the pad PD. For example, in one or more embodiments, a first power voltage VDD and a second power voltage VSS can be received from the driver integrated circuit (DIC) via the pad PD. For example, when the gate driver 120 is mounted on the display panel DP, the gate control signal GCS can be transmitted from the driver integrated circuit (DIC) to the gate driver 120 via the pad PD.

[0101] In one or more embodiments, the circuit board may be electrically connected to the pad PD using a conductive adhesive member such as an anisotropic conductive film. In these embodiments, the circuit board may be a flexible film or a flexible printed circuit board (FPCB) made of a flexible material. The driver integrated circuit (DIC) may be mounted on the circuit board and electrically connected to the pad PD.

[0102] In one or more embodiments, the display area DA may have one or more suitable shapes. The display area DA may have a closed-loop shape including straight edges and / or curved edges. For example, in one or more embodiments, the display area DA may have a shape such as a polygonal shape, a circular shape, a semi-circular shape, and / or an elliptical shape.

[0103] In one or more embodiments, the display panel DP may have a flat display surface. In one or more embodiments, the display panel DP may have a display surface that is at least partially rounded. In one or more embodiments, the display panel DP may be flexible, foldable, or rollable. In these embodiments, the display panel DP and / or the substrate SUB may comprise a material with flexible properties.

[0104] Figure 6 It is shown Figure 5 An exploded perspective view of a portion of the display panel DP. Figure 6 For clarity and conciseness, the diagram illustrates the relationship between the display panel DP and... Figure 5 The portion corresponding to the first pixel PXL1 in two pixels PXL1 and PXL2 of the pixel PXL. Similarly, the portion corresponding to the remaining pixels PXL of the display panel DP can be set.

[0105] Reference Figure 5 and Figure 6 In one or more embodiments, each of the first pixel PXL1 and the second pixel PXL2 may include first sub-pixels SP1 to third sub-pixels SP3. However, embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels or two sub-pixels.

[0106] exist Figure 6 In the present invention, when viewed from a third direction DR3 intersecting the first direction DR1 and the second direction DR2, the first sub-pixel SP1 to the third sub-pixel SP3 are shown as having a quadrilateral shape and are shown as having the same size. However, embodiments of this disclosure are not limited thereto. According to one or more embodiments, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be modified to have one or more suitable shapes.

[0107] The display panel (DP) may include a display section (DPP) and a filler layer (FIL). The display section (DPP) may include a substrate (SUB), a pixel circuit layer (PCL), a light-emitting element layer (LDL), a packaging layer (TFE), an optical functional layer (OFL), and an outer coating layer (OC).

[0108] In one or more embodiments, the substrate SUB may include a silicon wafer substrate formed using semiconductor processes. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, in one or more embodiments, the semiconductor material may include silicon, germanium, and / or silicon-germanium. The substrate SUB may be provided by a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, or a semiconductor-on-insulator (SeOI) layer. In one or more embodiments, the substrate SUB may include a glass substrate. In one or more embodiments, the substrate SUB may include a polyimide (PI) substrate.

[0109] The pixel circuit layer (PCL) may be on a substrate SUB (e.g., disposed on the substrate SUB). The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and conductive patterns disposed between the insulating layer. The conductive patterns of the pixel circuit layer PCL may be used as at least some of circuit elements and interconnects, etc. In one or more embodiments, the conductive patterns may include copper, but embodiments of this disclosure are not limited thereto.

[0110] The circuit elements may include sub-pixel circuitry for each of the first sub-pixels SP1 to the third sub-pixels SP3. The sub-pixel circuitry may include a transistor and one or more capacitors. Each transistor may include a semiconductor portion and a gate electrode stacked with the semiconductor portion, the semiconductor portion including a source region, a drain region, and a channel region. In one or more embodiments, the substrate SUB may be a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuitry layer PCL as a conductive pattern of the pixel circuitry layer PCL. In one or more embodiments, the substrate SUB may be a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuitry layer PCL. Each capacitor may include electrodes spaced apart and / or separated from each other (e.g., spaced apart or separated). For example, in one or more embodiments, each capacitor may include electrodes spaced apart and / or separated from each other (e.g., spaced apart or separated) on a plane defined by a first direction DR1 and a second direction DR2. For example, in one or more embodiments, each capacitor may include electrodes spaced apart and / or separated from each other (e.g., spaced apart or separated) on a third direction DR3 with an insulating layer disposed therebetween.

[0111] The interconnects of the pixel circuit layer PCL may include signal lines, such as gate lines, emit control lines, and data lines, connected to each of the first sub-pixels SP1 to the third sub-pixels SP3.

[0112] The light-emitting element layer (LDL) may include an anode (AE), a pixel-defining layer (PDL), an emission structure (EMS), and a cathode (CE).

[0113] The anode AE ​​can be on the pixel circuit layer PCL (e.g., disposed on the pixel circuit layer PCL). The anode AE ​​can contact the circuit elements of the pixel circuit layer PCL. The anode AE ​​can include an opaque conductive material capable of reflecting light, but embodiments of this disclosure are not limited thereto.

[0114] The pixel-defining layer (PDL) may be on the anode AE ​​(e.g., disposed on the anode AE). The pixel-defining layer (PDL) may include an opening (OP) that exposes a portion of each anode AE. The opening (OP) of the pixel-defining layer (PDL) can be understood as an emission region corresponding to the first sub-pixel SP1 to the third sub-pixel SP3, respectively.

[0115] In one or more embodiments, the pixel-defining layer (PDL) may include an inorganic material. In these embodiments, the pixel-defining layer (PDL) may include multiple stacked inorganic layers. For example, in one or more embodiments, the pixel-defining layer (PDL) may include silicon oxide (SiO2). x ) and / or silicon nitride (SiN) x In one or more embodiments, the pixel-defining layer (PDL) may include an organic material. However, the material of the pixel-defining layer (PDL) is not limited thereto.

[0116] The emission structure EMS can be located on the anode AE ​​exposed by the opening OP of the pixel-defined layer PDL (e.g., disposed on the anode AE ​​exposed by the opening OP of the pixel-defined layer PDL). The emission structure EMS may include an emission layer configured to generate light, an electron transport layer configured to transport electrons, and a hole transport layer configured to transport holes.

[0117] In one or more embodiments, the emission structure EMS may fill the opening OP of the pixel-defining layer PDL and may be disposed integrally on the pixel-defining layer PDL. For example, in one or more embodiments, the emission structure EMS may extend across the first sub-pixel SP1 to the third sub-pixel SP3. In these embodiments, at least some of the layers in the emission structure EMS may be broken or bent at the boundary between the first sub-pixel SP1 and the third sub-pixel SP3. However, embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, the portions of the emission structure EMS corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 may be separated from each other, and each of said portions may be disposed in the opening OP of the pixel-defining layer PDL.

[0118] The cathode CE can be on the emitter structure EMS (e.g., disposed on the emitter structure EMS). The cathode CE can extend across the first sub-pixel SP1 to the third sub-pixel SP3. In this way, the cathode CE can be used as a common electrode for the first sub-pixel SP1 to the third sub-pixel SP3.

[0119] In one or more embodiments, the cathode CE may be a thin metal layer of a thin thickness to transmit light emitted from the emitting structure EMS. The cathode CE may be made of a metallic material or a transparent conductive material to have a relatively thin thickness. In one or more embodiments, the cathode CE may include at least one of one or more suitable transparent conductive materials selected from indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide. In one or more embodiments, the cathode CE may include at least one selected from silver (Ag), magnesium (Mg), and mixtures thereof (e.g., any suitable mixtures). However, the material of the cathode CE is not limited to these.

[0120] A light-emitting element can be understood to consist of an anode AE ​​(e.g., selected from anode AEs), a portion of the emission structure EMS superimposed on this anode AE, and a portion of the cathode CE superimposed on the portion of the emission structure EMS superimposed on this anode AE. For example, each of the light-emitting elements of the first sub-pixel SP1 to the third sub-pixel SP3 may include an anode AE, a portion of the emission structure EMS superimposed on this anode AE, and a cathode CE superimposed on the portion of the emission structure EMS superimposed on this anode AE. In each of the first sub-pixel SP1 to the third sub-pixel SP3, holes injected from the anode AE ​​and electrons injected from the cathode CE can be transported to the corresponding emission layer of the emission structure EMS to generate excitons, and light can be generated if the excitons transition from an excited state and decay to the ground state (e.g., light can be generated when the excitons transition from an excited state and decay to the ground state). The brightness of the light can be determined based on the amount of current flowing through the emission layer. The wavelength range of the generated light can be determined based on the structure of the emission layer.

[0121] The encapsulation layer TFE can be on the cathode CE (e.g., disposed on the cathode CE). The encapsulation layer TFE can cover the light-emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE can be configured to prevent or reduce the penetration of oxygen and / or moisture into the light-emitting element layer LDL. In one or more embodiments, the encapsulation layer TFE can include a structure in which one or more inorganic layers and one or more organic layers are stacked alternately. For example, the inorganic layers can include silicon nitride, silicon oxide, and / or silicon oxynitride (SiO2). x N y The organic layer may include organic insulating materials such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene (BCB) resin, or any suitable combination thereof. However, the materials of the organic and inorganic layers of the encapsulating TFE are not limited to these.

[0122] To improve the encapsulation efficiency of the TFE encapsulation layer, in one or more embodiments, the TFE encapsulation layer may further include aluminum oxide (Al₂O₃). x The thin film, including aluminum oxide, may be located on the upper surface of the encapsulation layer TFE adjacent to (e.g., facing) the optical functional layer OFL and / or on the lower surface of the encapsulation layer TFE adjacent to (e.g., facing) the light-emitting element layer LDL.

[0123] Thin films including alumina can be formed by atomic layer deposition (ALD). However, embodiments of this disclosure are not limited thereto. In one or more embodiments, the encapsulation layer TFE may also comprise a thin film made of at least one selected from one or more materials suitable for improving encapsulation efficiency.

[0124] The optical functional layer OFL can be on the encapsulation layer TFE (e.g., disposed on the encapsulation layer TFE). The optical functional layer OFL may include a color filter layer CFL and a lens array LA.

[0125] A color filter layer (CFL) can be disposed between the encapsulation layer (TFE) and the lens array (LA). The CFL can be configured to filter light emitted from the emission structure (EMS) to selectively output light within a wavelength range or light having a color corresponding to each sub-pixel. The CFL may include color filters (CF) corresponding to first sub-pixels SP1 through third sub-pixels SP3, and each of the color filters (CF) can transmit light within a wavelength range corresponding to the corresponding sub-pixel. For example, in one or more embodiments, the color filter (CF) corresponding to the first sub-pixel SP1 can transmit red light, the color filter (CF) corresponding to the second sub-pixel SP2 can transmit green light, and the color filter (CF) corresponding to the third sub-pixel SP3 can transmit blue light. In one or more embodiments, depending on the light emitted from the emission structure (EMS) of each sub-pixel, at least some of the color filters (CF) may not be provided.

[0126] The lens array LA can be on the color filter layer CFL (e.g., disposed on the color filter layer CFL). The lens array LA may include lenses LS corresponding to the first sub-pixels SP1 to the third sub-pixels SP3, respectively. Each of the lenses LS can improve light output efficiency by directing the light output from the emission structure EMS along a desired path. The lens array LA may have a relatively high refractive index. For example, in one or more embodiments, the lens array LA may have a higher refractive index than the outer coating OC. In one or more embodiments, the lenses LS may include organic materials. In one or more embodiments, the lenses LS may include acrylic materials. However, the materials of the lenses LS are not limited thereto.

[0127] In one or more embodiments, at least some of the color filters CF of the color filter layer CFL and at least some of the lenses LS of the lens array LA may be offset in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2, relative to the opening OP of the pixel-defining layer PDL. For example, in one or more embodiments, in the central region of the display area DA, if viewed on a third direction DR3, the center of the color filter CF and the center of the lens LS may be aligned with or superimposed on the center of the corresponding opening OP of the pixel-defining layer PDL (e.g., when viewed on a third direction DR3, the center of the color filter CF and the center of the lens LS may be aligned with or superimposed on the center of the corresponding opening OP of the pixel-defining layer PDL). For example, in the central region of the display area DA, the opening OP of the pixel-defining layer PDL may be completely superimposed on the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. In the region of the display area DA adjacent to the non-display area NDA, when viewed on the third-direction DR3, the center of the color filter CF and the center of the lens LS can be offset from the center of the opening OP of the corresponding pixel-defining layer PDL in the planar direction (e.g., when viewed on the third-direction DR3, the center of the color filter CF and the center of the lens LS can be offset from the center of the opening OP of the corresponding pixel-defining layer PDL in the planar direction). For example, in the region of the display area DA adjacent to the non-display area NDA, the opening OP of the pixel-defining layer PDL can be partially superimposed with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. Therefore, in the central region of the display area DA, light emitted from the emitting structure EMS can be effectively output in the normal direction of the display surface. In the peripheral region of the display area DA, light emitted from the emitting structure EMS can be effectively output in a direction inclined at a certain angle relative to the normal direction of the display surface.

[0128] The outer coating OC can be on the lens array LA (e.g., disposed on the lens array LA). The outer coating OC can cover the optical functional layer OFL, the encapsulation layer TFE, the emission structure EMS, and / or the pixel circuit layer PCL. The outer coating OC can include one or more suitable materials suitable for protecting the layers beneath the outer coating OC from foreign matter such as dust and moisture. For example, in one or more embodiments, the outer coating OC can include at least one of inorganic and organic insulating films. For example, in one or more embodiments, the outer coating OC can include epoxy resin, but embodiments of this disclosure are not limited thereto. The outer coating OC can have a lower refractive index than the lens array LA.

[0129] The filler layer (FIL) can be disposed on the outer coating (OC) (e.g., on the outer coating OC). The filler layer (FIL) can be disposed on the display portion (DPP) to provide the display surface and / or input surface of the display panel (DP) (or display device (DD)). The filler layer (FIL) can be a component disposed on the uppermost layer of the display portion (DPP) in the display area (DA), and can protect the display portion (DPP) from external impacts, etc. The filler layer (FIL) can have a certain or higher viscosity and can be made of a transparent, curable resin.

[0130] Figure 7 This illustrates one or more embodiments according to the present disclosure. Figure 6 A schematic planar view of one of the pixels. Figure 7 For clarity and conciseness, the diagram is shown schematically. Figure 6 The first pixel PXL1 is one of the first pixels PXL1 and the second pixel PXL2. The remaining pixels can be set similarly to the first pixel PXL1.

[0131] Reference Figure 6 and Figure 7 The first pixel PXL1 may include a first sub-pixel SP1, a second sub-pixel SP2 and a third sub-pixel SP3 arranged on the first direction DR1.

[0132] The first sub-pixel SP1 may include a first emission region EMA1 and a non-emission region NEA surrounding the first emission region EMA1. The second sub-pixel SP2 may include a second emission region EMA2 and a non-emission region NEA surrounding the second emission region EMA2. The third sub-pixel SP3 may include a third emission region EMA3 and a non-emission region NEA surrounding the third emission region EMA3.

[0133] The first emission region EMA1 can be where light is emitted from the emission structure EMS (see...). Figure 6 The second emission region EMA2 can be the region in which light is emitted from the portion of the emission structure EMS corresponding to the second sub-pixel SP1. The third emission region EMA3 can be the region in which light is emitted from the portion of the emission structure EMS corresponding to the third sub-pixel SP3. (See reference...) Figure 6 As described, each emission region can be understood as an opening OP in the pixel-defined layer PDL corresponding to each of the first sub-pixels SP1 to the third sub-pixels SP3.

[0134] In one or more embodiments, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may have substantially the same area, but the embodiments of this disclosure are not limited thereto. According to one or more embodiments, the second sub-pixel SP2 may have a larger area than the first sub-pixel SP1, and the third sub-pixel SP3 may have a larger area than the second sub-pixel SP2.

[0135] The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may have polygonal shapes. For example, in one or more embodiments, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may each independently have a quadrilateral shape or a hexagonal shape, but the embodiments of this disclosure are not limited thereto. According to one or more embodiments, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may each independently have a circular shape and / or a semi-elliptical shape, etc.

[0136] Figure 7 The arrangement of subpixels shown is illustrative, and embodiments of this disclosure are not limited thereto. Each pixel PXL may include two or more subpixels, which may be arranged in one or more suitable ways, each of the subpixels may have one or more suitable shapes, and each of the emission regions of the subpixels may also have one or more suitable shapes.

[0137] Figure 8 It is along Figure 7 A schematic cross-sectional view taken from line II-II'.

[0138] Reference Figure 7 and Figure 8 In one or more embodiments, the first pixel PXL1 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3.

[0139] Each of the first sub-pixels SP1 to the third sub-pixels SP3 may include a base SUB and a pixel circuit layer PCL disposed on the base SUB (e.g., arranged on the base SUB).

[0140] In one or more embodiments, the substrate SUB may include a silicon wafer substrate formed using semiconductor processes. For example, in one or more embodiments, the substrate SUB may include silicon, germanium, and / or silicon-germanium.

[0141] The pixel circuit layer (PCL) can be disposed on the substrate SUB. The substrate SUB and the pixel circuit layer PCL can include circuit elements for each of the first sub-pixels SP1 to the third sub-pixels SP3. For example, in one or more embodiments, the substrate SUB and the pixel circuit layer PCL can include transistor T_SP1 for the first sub-pixel SP1, transistor T_SP2 for the second sub-pixel SP2, and transistor T_SP3 for the third sub-pixel SP3. Transistor T_SP1 for the first sub-pixel SP1 can be one of the transistors included in the sub-pixel circuit of the first sub-pixel SP1, transistor T_SP2 for the second sub-pixel SP2 can be one of the transistors included in the sub-pixel circuit of the second sub-pixel SP2, and transistor T_SP3 for the third sub-pixel SP3 can be one of the transistors included in the sub-pixel circuit of the third sub-pixel SP3. Figure 8 In order to provide a clear and concise description, one transistor for each sub-pixel is shown, and the remaining circuit elements are omitted to avoid obscuring the description.

[0142] The transistor T_SP1 of the first sub-pixel SP1 may include the source region SRA, the drain region DRA, and the gate electrode GE.

[0143] The source region (SRA) and drain region (DRA) can be arranged in the substrate (SUB). The well (WL) can be arranged in the substrate (SUB) by an ion implantation process, and the source region (SRA) and drain region (DRA) can be arranged to be spaced apart and / or separated from each other in the well (WL) (e.g., spaced apart or separated). The region in the well (WL) between the source region (SRA) and the drain region (DRA) can be defined as the channel region.

[0144] The gate electrode GE is stacked between the source region SRA and the drain region DRA, and may be disposed on the gate insulating layer GI. The gate electrode GE may be spaced and / or separated from the well WL or the channel region (e.g., spaced apart or separated) by an insulating layer such as the gate insulating layer GI. The gate electrode GE may include a conductive material (e.g., an electrically conductive material or an electronic conductor).

[0145] Multiple layers included in the pixel circuit layer PCL may include insulating layers and conductive patterns disposed between the insulating layers. The conductive patterns may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 may be electrically connected to the drain region DRA via drain connections DRC passing through one or more insulating layers. The second conductive pattern CP2 may be electrically connected to the source region SRA via source connections SRC passing through one or more insulating layers.

[0146] The gate electrode GE, the first conductive pattern CP1, and the second conductive pattern CP2 can be electrically connected to other circuit elements and / or interconnects. The transistor T_SP1 of the first sub-pixel SP1 can be configured as one of the transistors constituting the sub-pixel circuit of the first sub-pixel SP1.

[0147] Each of the transistors T_SP2 of the second sub-pixel SP2 and T_SP3 of the third sub-pixel SP3 can be set to be substantially the same as the transistor T_SP1 of the first sub-pixel SP1.

[0148] As described above, the substrate SUB and the pixel circuit layer PCL may include circuit elements for each of the first sub-pixels SP1 to the third sub-pixels SP3.

[0149] The via layer VIAL can be disposed on the pixel circuit layer PCL (e.g., disposed on the pixel circuit layer PCL). The via layer VIAL can cover the pixel circuit layer PCL and can have an overall flat (or substantially uniform) surface. The via layer VIAL can comprise silicon oxide (SiO2). x Silicon nitride (SiN) x The present disclosure may contain at least one of silicon carbonitride (SiCN) and silicon carbonitride (SiCN), but the embodiments thereof are not limited thereto.

[0150] The light-emitting element layer (LDL) can be disposed on the via layer (VIAL). The LDL may include a first reflective electrode RE1 to a third reflective electrode RE3, a planarization layer PLNL, a first anode AE1 to a third anode AE3, a pixel defining layer (PDL), an emission structure (EMS), and a cathode (CE).

[0151] On the via layer VIAL, the first reflective electrode RE1 to the third reflective electrode RE3 can be respectively arranged in the first sub-pixel SP1 to the third sub-pixel SP3. For example, the first reflective electrode RE1 can be arranged on the via layer VIAL of the first sub-pixel SP1, the second reflective electrode RE2 can be arranged on the via layer VIAL of the second sub-pixel SP2, and the third reflective electrode RE3 can be arranged on the via layer VIAL of the third sub-pixel SP3. Each of the first reflective electrode RE1 to the third reflective electrode RE3 can contact a circuit element arranged on the pixel circuit layer PCL through a via passing through the via layer VIAL.

[0152] The first reflecting electrodes RE1 through RE3 can all serve as total reflection mirrors, reflecting light emitted from the emission structure EMS toward the display screen (or filler layer FIL). The first reflecting electrodes RE1 through RE3 can comprise metallic materials suitable for reflecting light (e.g., each can independently comprise a metal). For example, in one or more embodiments, the first reflecting electrodes RE1 through RE3 can each independently comprise at least one selected from aluminum, silver, magnesium, platinum, palladium, gold, nickel, neodymium, iridium, chromium, and titanium, or can each independently comprise at least one alloy selected from two or more of these materials. However, the materials of the first reflecting electrodes RE1 through RE3 are not limited to the embodiments described above.

[0153] The first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 may all have substantially the same thickness. For example, in one or more embodiments, the thickness of each of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 may be in the range of about 700 Å to about 1000 Å, but the embodiments of this disclosure are not limited thereto.

[0154] According to one or more embodiments, a connection electrode may be disposed below each of the first reflective electrodes RE1 to the third reflective electrodes RE3. The connection electrode may be configured to improve the electrical connection characteristics between the corresponding reflective electrode and the circuit elements of the pixel circuitry layer PCL. The connection electrode may comprise multiple layers. For example, in one or more embodiments, the multiple layers may comprise a stacked structure of titanium / titanium nitride (or titanium nitride) / tantalum nitride (or tantalum nitride), but embodiments of this disclosure are not limited thereto. According to one or more embodiments, the corresponding reflective electrode may be disposed between the layers constituting the connection electrode.

[0155] In one or more embodiments, the buffer pattern BFP may be disposed below at least one of the first reflective electrodes RE1 to the third reflective electrode RE3. For example, in one or more embodiments, the buffer pattern BFP may be disposed between the first reflective electrode RE1 and the via layer VIAL. The buffer pattern BFP may include inorganic materials such as silicon carbonitride, but embodiments of this disclosure are not limited thereto. The buffer pattern BFP may be disposed to adjust the height of the corresponding reflective electrode on the third-direction DR3. For example, in one or more embodiments, the buffer pattern BFP may adjust the height of the first reflective electrode RE1 between the first reflective electrode RE1 and the via layer VIAL. The first reflective electrode RE1 may cover the entire buffer pattern BFP by covering the entire upper surface and (e.g., simultaneously) both side surfaces (or (e.g., simultaneously) both ends). A region of the first reflective electrode RE1 may extend to the upper surface of the via layer VIAL by contacting (e.g., simultaneously) the two side surfaces of the buffer pattern BFP.

[0156] In one or more embodiments, in the second sub-pixel SP2, the aforementioned buffer pattern BFP may not be arranged between the second reflective electrode RE2 and the via layer VIAL, and the second reflective electrode RE2 may be directly arranged on the via layer VIAL. Furthermore, in the third sub-pixel SP3, the aforementioned buffer pattern BFP may not be arranged between the third reflective electrode RE3 and the via layer VIAL, and the third reflective electrode RE3 may be directly arranged on the via layer VIAL.

[0157] The first reflecting electrodes RE1 through RE3 can all be used as total reflection mirrors, and the cathode CE can be used as a half-reflection mirror. Light emitted from the emitting structure EMS can be amplified by at least partially reciprocating between the corresponding reflecting electrode and the cathode CE, and the amplified light can be output through the cathode CE. In this way, the distance between each reflecting electrode and the cathode CE can be understood as the resonant distance of light emitted from the emitting layer of the corresponding emitting structure EMS.

[0158] In one or more embodiments, due to the buffer pattern BFP, the first sub-pixel SP1 can have a shorter resonant distance than other sub-pixels (e.g., the second sub-pixel SP2 and the third sub-pixel SP3). This resonant distance adjustment allows light within a specific wavelength range (e.g., red) to be effectively and efficiently amplified. Therefore, the first sub-pixel SP1 can effectively and efficiently output light within the corresponding wavelength range.

[0159] exist Figure 8In the diagram, the buffer pattern BFP is shown as being disposed in the first sub-pixel SP1 and not in the second sub-pixels SP2 and SP3, but the embodiments of this disclosure are not limited thereto. According to one or more embodiments, the buffer pattern may also be disposed in at least one of the second sub-pixels SP2 and SP3 to adjust the resonant distance of at least one of the second sub-pixels SP2 and SP3. For example, in one or more embodiments, the first sub-pixel SP1 is a red sub-pixel, the second sub-pixel SP2 is a green sub-pixel, and the third sub-pixel SP3 is a blue sub-pixel; the distance between the first reflective electrode RE1 and the cathode CE may be shorter than the distance between the second reflective electrode RE2 and the cathode CE, and the distance between the second reflective electrode RE2 and the cathode CE may be shorter than the distance between the third reflective electrode RE3 and the cathode CE.

[0160] The thickness of the buffer pattern BFP (or the thickness on the third-direction DR3) can be in the range of about 400 Å to about 600 Å, but the embodiments disclosed herein are not limited thereto.

[0161] The planarization layer PLNL can be configured to planarize the step portion between the first reflective electrode RE1 and the third reflective electrode RE3. The planarization layer PLNL can be disposed on the via layer VIAL and the first reflective electrodes RE1 to RE3 (e.g., on the via layer VIAL and the first reflective electrodes RE1 to RE3). The planarization layer PLNL can integrally cover the first reflective electrodes RE1 to RE3 and the via layer VIAL and can have a flat surface. The planarization layer PLNL can include an insulating material. For example, in one or more embodiments, the planarization layer PLNL can include silicon oxide (SiO2). x ) and / or silicon nitride (SiN) x The inorganic material is used, but the embodiments of this disclosure are not limited thereto. According to one or more embodiments, the planarization layer PLNL may not be provided.

[0162] In one or more embodiments, the planarization layer PLNL may include vias that expose a region of a reflective electrode. For example, in one or more embodiments, the planarization layer PLNL may include a first via VIA1 that exposes a region of a first reflective electrode RE1, a second via VIA2 that exposes a region of a second reflective electrode RE2, and a third via VIA3 that exposes a region of a third reflective electrode RE3.

[0163] The first anode AE1, the second anode AE2, and the third anode AE3 can all be disposed on the planarization layer PLNL. For example, in one or more embodiments, the first anode AE1 can be disposed on the planarization layer PLNL to be stacked with the first reflective electrode RE1, the second anode AE2 can be disposed on the planarization layer PLNL to be stacked with the second reflective electrode RE2, and the third anode AE3 can be disposed on the planarization layer PLNL to be stacked with the third reflective electrode RE3.

[0164] If viewed from a third-party perspective DR3, the first anode AE1 to the third anode AE3 can respectively have the same characteristics as... Figure 7 The first emission region EMA1 to the third emission region EMA3 have similar shapes (for example, when viewed on a third-party DR3, the first anode AE1 to the third anode AE3 may each have the same shape as...). Figure 7 The first emission area EMA1 to the third emission area EMA3 have similar shapes.

[0165] Each of the first anodes AE1 to the third anode AE3 can be electrically connected to the corresponding reflective electrode. For example, the first anode AE1 can be electrically connected to the first reflective electrode RE1 through a first via VIA1 passing through the planarization layer PLNL. The second anode AE2 can be electrically connected to the second reflective electrode RE2 through a second via VIA2 passing through the planarization layer PLNL. The third anode AE3 can be electrically connected to the third reflective electrode RE3 through a third via VIA3 passing through the planarization layer PLNL.

[0166] The first anode AE1 to the third anode AE3 can each independently include materials selected from indium tin oxide (ITO), indium zinc oxide (IZO), and zinc oxide (ZnO). x It is at least one of the transparent conductive materials selected from indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO). However, the materials of the first anode AE1 to the third anode AE3 are not limited thereto. For example, in one or more embodiments, the first anode AE1 to the third anode AE3 may comprise titanium nitride.

[0167] In one or more embodiments, the first anode AE1 to the third anode AE3 may have substantially the same thickness. For example, the thickness of each of the first anode AE1, the second anode AE2, and the third anode AE3 may be in the range of about 700 Å to about 1000 Å, but the embodiments of this disclosure are not limited thereto.

[0168] In one or more embodiments, an insulating layer may also be provided for adjusting the height of one or more of the first anodes AE1 to the third anodes AE3. The insulating layer may be disposed between one or more of the first anodes AE1 to the third anodes AE3 and the corresponding reflective electrode. In these embodiments, the planarization layer PLNL and / or the buffer pattern BFP may not be provided.

[0169] A pixel-defining layer (PDL) may be disposed on portions of the first anodes AE1 to the third anodes AE3 and the planarization layer PLNL. The PDL may include an opening OP exposing a portion of each of the first anodes AE1 to the third anodes AE3. The opening OP of the PDL may define an emission region for each of the first sub-pixels SP1 to the third sub-pixels SP3. The PDL may be disposed in the non-emission region NEA (see [link to relevant documentation]). Figure 7 In, with reference to the limited reference. Figure 7 The first transmission area EMA1, the second transmission area EMA2, and the third transmission area EMA3 are described.

[0170] In one or more embodiments, the pixel defining layer (PDL) may include a plurality of inorganic insulating layers. Each of the plurality of inorganic insulating layers may include at least one selected from silicon oxide and silicon nitride. For example, in one or more embodiments, the pixel defining layer (PDL) may include a first inorganic insulating layer ISL1, a second inorganic insulating layer ISL2, and a third inorganic insulating layer ISL3 stacked sequentially. The first inorganic insulating layer ISL1 to the third inorganic insulating layer ISL3 may each independently include at least one selected from silicon nitride, silicon oxide, and silicon oxynitride. However, the material of the pixel defining layer (PDL) is not limited to the embodiments described above. In one or more embodiments, the first inorganic insulating layer ISL1 to the third inorganic insulating layer ISL3 may have a stepped profile in the region adjacent to the opening OP of the pixel defining layer (PDL).

[0171] The pixel-defined layer (PDL) may include separators (SPRs) in the boundary regions (BDAs) between adjacent sub-pixels. For example, the separators (SPRs) may be set in... Figure 5 In each of the boundary regions between sub-pixels SP.

[0172] The separator SPR can cause discontinuities in the boundary region BDA within the emission structure EMS. For example, in one or more embodiments, the emission structure EMS may be broken or bent in the boundary region BDA due to the separator SPR. Therefore, the segments corresponding to the first sub-pixels SP1 to the third sub-pixels SP3, respectively... Figure 7 The first emission region EMA1 to the third emission region EMA3 can be defined along the separator SPR of the pixel-defined layer PDL.

[0173] The separator SPR can be disposed in or on the pixel-defining layer PDL. In one or more embodiments, the pixel-defining layer PDL may include one or more trenches TRCH1 and TRCH2 in the boundary region BDA as the separator SPR. In one or more embodiments, as Figure 8 As shown, one or more trenches TRCH1 and TRCH2 may pass through the pixel defining layer PDL and partially through the planarization layer PLNL. In one or more embodiments, one or more trenches TRCH1 and TRCH2 may pass through the pixel defining layer PDL and the planarization layer PLNL and may partially pass through the via layer VIAL. In one or more embodiments, one or more trenches TRCH1 and TRCH2 at least partially penetrate the planarization layer PLNL and / or the via layer VIAL, and a portion of the pixel defining layer PDL may be disposed within one or more trenches TRCH1 and TRCH2.

[0174] exist Figure 8 In the diagram, two trenches TRCH1 and TRCH2 (e.g., a first trench TRCH1 and a second trench TRCH2) are shown as being disposed in the boundary region BDA, but embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, the pixel defining layer PDL may include one trench or three or more trenches in the boundary region BDA.

[0175] Due to the first trench TRCH1 and the second trench TRCH2, discontinuous portions such as the first gap VD1 and the second gap VD2 can be formed in the boundary region BDA in the emitter structure EMS. Some of the multiple layers stacked in the emitter structure EMS can be broken or bent through the first gap VD1 and the second gap VD2. For example, in one or more embodiments, at least one charge generation layer and at least one hole injection layer included in the emitter structure EMS can be broken at the first gap VD1 and the second gap VD2. Thus, portions of the emitter structure EMS included in the first sub-pixels SP1 to the third sub-pixels SP3 can be at least partially separated due to the first trench TRCH1 and the second trench TRCH2.

[0176] Depending on the shapes of the first trench TRCH1 and the second trench TRCH2, various modifications can be made to the discontinuous portions formed in the emission structure EMS.

[0177] In one or more embodiments, the emission structure EMS can be formed by processes including vacuum deposition and / or inkjet printing. In these embodiments, the same material as the emission structure EMS can be located on the bottom surface of the first trench TRCH1 and the second trench TRCH2 adjacent to the via layer VIAL.

[0178] In one or more embodiments, the pixel defining layer (PDL) may include additional spacers such that the emitter structure (EMS) also includes a discontinuous portion adjacent to the boundary region BDA. In one or more embodiments, the uppermost of the first inorganic insulating layers (ISL1) to the third inorganic insulating layers (ISL3) of the pixel defining layer (PDL) may have a width wider than the second inorganic insulating layer (ISL2) disposed immediately below the third inorganic insulating layer (ISL3). For example, the pixel defining layer (PDL) may have a "T"-shaped or "I"-shaped cross-section in the boundary region BDA. Depending on the shape of the pixel defining layer (PDL), the multiple layers included in the emitter structure (EMS) may be at least partially broken or bent in the boundary region BDA or in a region adjacent to the boundary region BDA.

[0179] The emitting structure EMS can be disposed on the anode AE ​​exposed by the opening OP of the pixel-defining layer PDL (e.g., disposed on the anode AE ​​exposed by the opening OP of the pixel-defining layer PDL). The emitting structure EMS fills the opening OP of the pixel-defining layer PDL and can be disposed integrally throughout the first sub-pixels SP1 to the third sub-pixels SP3. As previously described, the emitting structure EMS can be at least partially broken or bent in the boundary region BDA by the separator SPR. Therefore, when operating the display panel DP, the current leakage from each of the first sub-pixels SP1 to the third sub-pixels SP3 through the layer included in the emitting structure EMS to its adjacent sub-pixels can be reduced. Therefore, the first light-emitting elements LD1 to the third light-emitting elements LD3 can operate with relatively high reliability.

[0180] The cathode CE can be on the emitting structure EMS (e.g., arranged on the emitting structure EMS). The cathode CE can be commonly disposed for the first sub-pixel SP1 to the third sub-pixel SP3. The cathode CE can be used as a semi-reflective mirror that partially transmits and partially reflects light emitted from the emitting structure EMS.

[0181] The first anode AE1, the portion of the emitting structure EMS superimposed on the first anode AE1, and the portion of the cathode CE superimposed on the first anode AE1 can constitute the first light-emitting element LD1. The second anode AE2, the portion of the emitting structure EMS superimposed on the second anode AE2, and the portion of the cathode CE superimposed on the second anode AE2 can constitute the second light-emitting element LD2. The third anode AE3, the portion of the emitting structure EMS superimposed on the third anode AE3, and the portion of the cathode CE superimposed on the third anode AE3 can constitute the third light-emitting element LD3.

[0182] The encapsulation layer TFE can be on the cathode CE (e.g., disposed on the cathode CE). The encapsulation layer TFE can prevent or reduce the penetration of oxygen and / or moisture into the light-emitting element layer LDL.

[0183] The optical functional layer (OFL) can be on the encapsulation layer TFE (e.g., disposed on the encapsulation layer TFE). In one or more embodiments, the optical functional layer (OFL) can be attached to the encapsulation layer TFE via an adhesive layer (APL). For example, the optical functional layer (OFL) can be manufactured separately and attached to the encapsulation layer TFE via the adhesive layer (APL). The adhesive layer (APL) can also perform the function of protecting the underlying layer including the encapsulation layer TFE.

[0184] The optical functional layer OFL can include a color filter layer CFL and a lens array LA.

[0185] The color filter layer CFL may include first color filters CF1 to third color filters CF3, respectively, corresponding to first sub-pixels SP1 to third sub-pixels SP3. For example, in one or more embodiments, the color filter layer CFL may include a first color filter CF1 corresponding to the first sub-pixel SP1, a second color filter CF2 corresponding to the second sub-pixel SP2, and a third color filter CF3 corresponding to the third sub-pixel SP3. The first color filters CF1 to third color filters CF3 may draw (e.g., transmit) multiple beams of light within different wavelength ranges. For example, in one or more embodiments, the first color filter CF1 may transmit red light, the second color filter CF2 may transmit green light, and the third color filter CF3 may transmit blue light. In these embodiments, the first sub-pixel SP1 may be a red sub-pixel, the second sub-pixel SP2 may be a green sub-pixel, and the third sub-pixel SP3 may be a blue sub-pixel.

[0186] In one or more embodiments, the first color filter CF1 to the third color filter CF3 may be partially superimposed on each other in the boundary region BDA. In one or more embodiments, the first color filter CF1 to the third color filter CF3 may be spaced apart and / or separated from each other (e.g., spaced apart or separated), and the black matrix may be disposed between the first color filter CF1 to the third color filter CF3 that are spaced apart and / or separated from each other (e.g., spaced apart or separated).

[0187] The lens array LA can be located on the color filter layer CFL (e.g., disposed on the color filter layer CFL). The lens array LA may include first lenses LS1 to third lenses LS3, respectively corresponding to first sub-pixels SP1 to third sub-pixels SP3. For example, the lens array LA may include first lens LS1 corresponding to the first sub-pixel SP1, second lens LS2 corresponding to the second sub-pixel SP2, and third lens LS3 corresponding to the third sub-pixel SP3. First lenses LS1 to third lenses LS3 can all improve light output efficiency by outputting light emitted from first light-emitting elements LD1 to third light-emitting elements LD3 along a predetermined path.

[0188] An outer coating OC may be on the lens array LA (e.g., disposed on the lens array LA). The outer coating OC is configured to protect the underlying layer from foreign matter such as dust and moisture. A filler layer FIL may be on the outer coating OC (e.g., disposed on the outer coating OC).

[0189] Figure 9 It is according to one or more embodiments of this disclosure along Figure 7 A schematic cross-sectional view taken from line II-II'.

[0190] Reference Figure 7 and Figure 9 The pixel circuit layer PCL and the via layer VIAL are on the substrate SUB (e.g., arranged on the substrate SUB). Figure 9 The substrate SUB, pixel circuit layer PCL, and via layer VIAL can be compared with the reference. Figure 8 The substrate (SUB), pixel circuit layer (PCL), and via layer (VIAL) are similarly configured. Redundant descriptions will not be provided below.

[0191] The light-emitting element layer LDL' can be disposed on the via layer VIAL (e.g., disposed on the via layer VIAL). The light-emitting element layer LDL' may include a first reflective electrode RE1' to a third reflective electrode RE3', a first buffer pattern BFP1' and a second buffer pattern BFP2', a first cover pattern CVP1 to a third cover pattern CVP3, a first anode AE1' to a third anode AE3', a pixel defining layer PDL', an emission structure EMS', and a cathode CE.

[0192] On the via layer VIAL, the first reflective electrode RE1' to the third reflective electrode RE3' can be respectively arranged in the first sub-pixel SP1 to the third sub-pixel SP3. Each of the first reflective electrode RE1' to the third reflective electrode RE3' can contact a circuit element arranged on the pixel circuit layer PCL through a via through the via layer VIAL.

[0193] The first reflective electrode RE1' to the third reflective electrode RE3' are all configured to reflect light emitted from the emitting structure EMS' toward the display screen (or filler layer FIL). The first reflective electrode RE1' to the third reflective electrode RE3' may include a metallic material suitable for reflecting light.

[0194] In one or more embodiments, a connecting electrode may also be provided between each of the first reflective electrode RE1' to the third reflective electrode RE3' and the via layer VIAL. The connecting electrode can improve the electrical connection characteristics between the corresponding reflective electrode and the circuit elements of the pixel circuit layer PCL.

[0195] A buffer pattern can be disposed on at least one of the first reflective electrode RE1' to the third reflective electrode RE3'. In one or more embodiments, the first buffer pattern BFP1' and the second buffer pattern BFP2' can be disposed on the first reflective electrode RE1' and the third reflective electrode RE3', respectively. The heights of the first anode AE1' and the third anode AE3' on the third-direction DR3 can be adjusted by the first buffer pattern BFP1' and the second buffer pattern BFP2', respectively. The first buffer pattern BFP1' and the second buffer pattern BFP2' can each independently comprise a material selected from silicon oxide (SiO2). x ) and silicon nitride (SiN) x The present disclosure includes at least one of the inorganic materials, but the embodiments are not limited thereto.

[0196] First cover patterns CVP1 to third cover patterns CVP3 can be respectively disposed on first reflective electrodes RE1' to third reflective electrodes RE3'. In the first sub-pixel SP1, the first cover pattern CVP1 is disposed on the first reflective electrode RE1' and the first buffer pattern BFP1'. In the second sub-pixel SP2, the second cover pattern CVP2 is disposed on the second reflective electrode RE2'. In the third sub-pixel SP3, the third cover pattern CVP3 is disposed on the third reflective electrode RE3' and the second buffer pattern BFP2'. The first cover patterns CVP1 to third cover patterns CVP3 can be formed during the manufacturing process after the formation of the first buffer pattern BFP1' and the second buffer pattern BFP2'. The first cover patterns CVP1 to third cover patterns CVP3 can all comprise the same material as the first buffer pattern BFP1' and the second buffer pattern BFP2'. For example, in one or more embodiments, the first cover patterns CVP1 to third cover patterns CVP3 can all independently comprise materials selected from silicon oxide (SiO2). x ) and silicon nitride (SiN) x The present disclosure includes at least one of the inorganic materials, but the embodiments are not limited thereto.

[0197] The first anode AE1' to the third anode AE3' are respectively disposed on the first cover pattern CVP1 to the third cover pattern CVP3. In one or more embodiments, the first anode AE1' may cover the first cover pattern CVP1, the first buffer pattern BFP1', and the first reflective electrode RE1'. The second anode AE2' may cover the second cover pattern CVP2 and the second reflective electrode RE2'. The third anode AE3' may cover the third cover pattern CVP3, the second buffer pattern BFP2', and the third reflective electrode RE3'.

[0198] The first anode AE1' to the third anode AE3' can be electrically connected to the first reflective electrode RE1' to the third reflective electrode RE3', respectively. For example, in one or more embodiments, each anode can be connected to the end (or edge) of the corresponding reflective electrode. However, the embodiments of this disclosure are not limited thereto. To improve the electrical connection characteristics between the anode and the reflective electrode, the anode can be connected to the reflective electrode in one or more suitable ways.

[0199] The first anodes AE1' to the third anode AE3' and the cathode CE can partially reflect the incident light. Light emitted from the emitting layer of the emitting structure EMS' can be amplified by reciprocating between the corresponding anode and cathode CE, and can be output through the cathode CE. For example, in one or more embodiments, each anode and cathode CE can provide a resonant structure in the corresponding sub-pixel. In these embodiments, the distance between each anode and cathode CE can be understood as the resonant distance of light emitted from the emitting layer of the corresponding emitting structure EMS'.

[0200] In one or more embodiments, the first sub-pixel SP1 to the third sub-pixel SP3 may correspond to red, green, and blue, respectively. In these embodiments, the heights of the first anode AE1' and the third anode AE3' on the third-direction DR3 may be greater than the height of the second anode AE2' on the third-direction DR3, respectively, due to the first buffer pattern BFP1' and the second buffer pattern BFP2'. Therefore, the first sub-pixel SP1 and the third sub-pixel SP3 may have shorter resonant distances than the second sub-pixel SP2 due to the first buffer pattern BFP1' and the second buffer pattern BFP2'. In this way, the resonant distance of each sub-pixel can be adjusted to effectively and efficiently amplify light within the wavelength range of the corresponding color.

[0201] exist Figure 9In the diagram, the first buffer pattern BFP1' and the second buffer pattern BFP2' are shown as being disposed below the first anode AE1' and the third anode AE3', respectively; however, the embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, one of the first buffer pattern BFP1' and the second buffer pattern BFP2' may not be disposed. In one or more embodiments, both the first buffer pattern BFP1' and the second buffer pattern BFP2' may not be disposed (e.g., simultaneously). In these embodiments, the resonant distance between the anode and the cathode CE may be the same. In one or more embodiments, the buffer pattern may be disposed below each of the first anode AE1' to the third anode AE3'. In these embodiments, the buffer patterns disposed below the anodes may have different thicknesses, thus the resonant distance between the anode and the cathode CE may be different. In this way, the buffer pattern may be disposed below at least one of the first anodes AE1' to the third anode AE3' to adjust the height of the corresponding anode, thereby improving or optimizing the resonant distance in each sub-pixel.

[0202] The pixel defining layer PDL' is disposed on portions of the first anode AE1' to the third anode AE3' and the via layer VIA1' (e.g., disposed on portions of the first anode AE1' to the third anode AE3' and the via layer VIA1'). The pixel defining layer PDL' has an opening OP' that exposes a portion of each of the first anode AE1' to the third anode AE3'. The region superimposed on the pixel defining layer PDL' can be understood as the boundary region BDA between adjacent sub-pixels.

[0203] In one or more embodiments, the pixel defining layer PDL' may include a first inorganic insulating layer ISL1' to a fourth inorganic insulating layer ISL4'. The first inorganic insulating layer ISL1' may cover a portion of the first anode AE1' to the third anode AE3' and the via layer VIAL. A second inorganic insulating layer ISL2' is disposed on the first inorganic insulating layer ISL1', a third inorganic insulating layer ISL3' is disposed on the second inorganic insulating layer ISL2', and the fourth inorganic insulating layer ISL4' is disposed on the third inorganic insulating layer ISL3'. The first inorganic insulating layer ISL1' and the third inorganic insulating layer ISL3' may both comprise silicon nitride (SiN). x Furthermore, both the second inorganic insulating layer ISL2' and the fourth inorganic insulating layer ISL4' may include silicon oxide (SiO2). x However, embodiments of this disclosure are not limited thereto. In one or more embodiments, the first inorganic insulating layer ISL1' may be omitted.

[0204] The pixel-defined layer (PDL) may include separators (SPRs) in the boundary regions (BDAs) between adjacent subpixels. Separators (SPRs) may cause discontinuities such as gaps (VDs) to form in the emission structure (EMS). Due to these discontinuities, at least some of the layers included in the emission structure (EMS) may be broken or bent.

[0205] In one or more embodiments, the fourth inorganic insulating layer ISL4' may be wider than the second inorganic insulating layer ISL2' and the third inorganic insulating layer ISL3'. In these embodiments, the side surfaces of the second inorganic insulating layer ISL2' to the fourth inorganic insulating layer ISL4' adjacent to the opening OP' of the pixel defining layer PDL' may be configured as separators SPR'. A portion of the fourth inorganic insulating layer ISL4' may have an eaves shape on the second inorganic insulating layer ISL2' and the third inorganic insulating layer ISL3'.

[0206] In one or more embodiments, the second inorganic insulating layer ISL2' and the third inorganic insulating layer ISL3' may have the same width in the boundary region BDA. However, embodiments of this disclosure are not limited thereto, and the second inorganic insulating layer ISL2' and the third inorganic insulating layer ISL3' may have different widths.

[0207] In the second sub-pixel SP2, a portion of the fourth inorganic insulating layer ISL4' and the side surfaces of the second inorganic insulating layer ISL2' and the third inorganic insulating layer ISL3' can be configured as separators SPR'. Therefore, the gap VD' can be formed in the emission structure EMS' adjacent to a portion of the fourth inorganic insulating layer ISL4'.

[0208] Some of the multiple layers stacked in the emission structure EMS' may be broken or bent due to the gap VD'. For example, in one or more embodiments, at least one charge generation layer and at least one hole injection layer included in the emission structure EMS' may be broken through the gap VD'. In this way, portions of the emission structure EMS' included in the first sub-pixel SP1 to the third sub-pixel SP3 may be at least partially separated from each other due to the separator SPR'.

[0209] The pixel-defining layer PDL' may include additional spacers, such that the emitter structure EMS' also includes discontinuous portions in the boundary region BDA. In one or more embodiments, the pixel-defining layer PDL' may include one or more trenches as spacers in the boundary region BDA. The trenches may pass through one or more of the first inorganic insulating layers ISL1' to the fourth inorganic insulating layers ISL4'. Due to the trenches, some of the multiple layers stacked in the emitter structure EMS' (e.g., at least one charge generation layer and at least one hole injection layer) may be broken or bent. In one or more embodiments, the emitter structure EMS' may have a structure in which three emitter units, each including an emitter layer, are stacked and two charge generation layers may be arranged between the three emitter units. In these embodiments, the pixel-defining layer PDL' may include one or more trenches in the boundary region BDA.

[0210] The emitting structure EMS' can be located on the anodes AE1', AE2', and AE3' exposed by the opening OP' of the pixel-defining layer PDL' (e.g., arranged on the anodes AE1', AE2', and AE3' exposed by the opening OP' of the pixel-defining layer PDL'). The emitting structure EMS' can be broken or bent in the boundary region BDA or in the region adjacent to the boundary region BDA due to the separator SPR'. Therefore, when operating the display panel DP, the current leakage from each of the first sub-pixels SP1 to the third sub-pixels SP3 through the layer included in the emitting structure EMS' to the adjacent sub-pixels can be reduced. Therefore, the first light-emitting elements LD1' to the third light-emitting elements LD3' can operate with relatively high reliability.

[0211] In one or more embodiments, the emitting structure EMS' may include two emitting units stacked in sequence, and each of the emitting units may include an emitting layer configured to generate light in response to an applied current. In one or more embodiments, the emitting structure EMS' may include three emitting units stacked in sequence, and each of the emitting units may include an emitting layer configured to generate light in response to an applied current. In these embodiments, charge generation layers may be arranged between adjacent emitting units.

[0212] In one or more embodiments, the emission structure EMS' can be formed by processes including vacuum deposition and / or inkjet printing, etc.

[0213] The cathode CE can be on the emitting structure EMS' (e.g., arranged on the emitting structure EMS'). The cathode CE can be commonly set for the first sub-pixel SP1 to the third sub-pixel SP3.

[0214] The encapsulation layer TFE can be on the cathode CE (e.g., disposed on the cathode CE). The encapsulation layer TFE can prevent or reduce the penetration of oxygen and / or moisture into the light-emitting element layer LDL'.

[0215] The adhesive layer APL, optical functional layer OFL, outer coating OC, and filler layer FIL can be disposed on the encapsulation layer TFE (e.g., on the encapsulation layer TFE). The adhesive layer APL, optical functional layer OFL, outer coating OC, and filler layer FIL are respectively attached to... Figure 8 The adhesive layer APL, optical functional layer OFL, outer coating OC, and filler layer FIL are similarly configured. For the sake of simplicity, their redundant descriptions will not be provided here.

[0216] Figure 10 This illustrates one or more embodiments according to the present disclosure, including... Figure 8 or Figure 9 A schematic cross-sectional view of the emission structure EMS in one of the first to third light-emitting elements.

[0217] Reference Figure 10 The transmitting structure EMS can have a series structure in which a first transmitting unit EU1 and a second transmitting unit EU2 are stacked. The transmitting structure EMS can be configured to be connected with... Figure 8 The emission structures EMS in the first light-emitting element LD1 to the third light-emitting element LD3 are basically the same. Furthermore, the emission structure EMS can be configured to be similar to that in... Figure 9 The emission structure EMS' in the first light-emitting element LD1' to the third light-emitting element LD3' is basically the same.

[0218] Each of the first emitting unit EU1 and the second emitting unit EU2 may include at least one emitting layer that generates light according to an applied current. The first emitting unit EU1 may include a first emitting layer EML1, a first electron transport unit ETU1, and a first hole transport unit HTU1. The first emitting layer EML1 may be disposed between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second emitting unit EU2 may include a second emitting layer EML2, a second electron transport unit ETU2, and a second hole transport unit HTU2. The second emitting layer EML2 may be disposed between the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0219] Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer and / or an electron blocking layer as needed. The first hole transport unit HTU1 and the second hole transport unit HTU2 may have the same or different structures.

[0220] Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer and / or a hole blocking layer as needed. The first electron transport unit ETU1 and the second electron transport unit ETU2 may have the same or different structures.

[0221] An intermediate layer (or connecting layer), which can be configured in the form of a charge generation layer CGL, can be disposed between the first emitter unit EU1 and the second emitter unit EU2 to connect the first emitter unit EU1 and the second emitter unit EU2 to each other. Hereinafter, the charge generation layer CGL will be referred to as the intermediate layer. In one or more embodiments, the intermediate layer CGL may have a stacked structure of p-doped layers and n-doped layers. For example, the p-doped layer may include p-type (species) dopants such as 1,4,5,8,9,11-hexaazatriphenylhexacarbonitrile (HAT-CN), 7,7,8,8-tetracyanoquinone dimethyl ether (TCNQ), or 2-(7-dicyanomethylene-1,3,4,5,6,8,9,10-octafluoro-7H-pyrene-2-ylidene)-malonadionitrile (NDP-9), and the n-doped layer may include alkali metals, alkaline earth metals, lanthanides, and / or combinations thereof (e.g., any suitable combination). However, the structure (or material) of the intermediate layer CGL is not limited to the embodiments described above. In one or more embodiments, the intermediate layer CGL may have conductivity by comprising a material having a relatively high charge conductivity (or charge mobility) compared to the first emitter unit EU1 and the second emitter unit EU2.

[0222] In one or more embodiments, the first emitting layer EML1 and the second emitting layer EML2 can generate multiple beams of light with different colors. The multiple beams of light emitted from the first emitting layer EML1 and the second emitting layer EML2 can be mixed and treated as white light (e.g., combined white light). For example, in one or more embodiments, the first emitting layer EML1 can generate blue light, and the second emitting layer EML2 can include a structure in which a first sub-emitting layer configured to generate red light and a second sub-emitting layer configured to generate green light are stacked. In these embodiments, functional layers configured to perform the function of transporting holes and / or blocking the transport of electrons can be further arranged between the first and second sub-emitting layers.

[0223] In one or more embodiments, the first emission layer EML1 and the second emission layer EML2 can produce light with the same color.

[0224] Figure 11 This illustrates one or more embodiments according to the present disclosure, including... Figure 8 or Figure 9A schematic cross-sectional view of the emitting structure EMS' in one of the first to third light-emitting elements.

[0225] Reference Figure 11 The transmitting structure EMS' can have a series structure in which a first transmitting unit EU1', a second transmitting unit EU2', and a third transmitting unit EU3' are stacked. The transmitting structure EMS' can be configured to be connected with... Figure 8 The emission structure EMS in the first light-emitting element LD1 to the third light-emitting element LD3 is basically the same. Furthermore, the emission structure EMS' can be configured to be similar to that in... Figure 9 The emission structure EMS' in the first light-emitting element LD1' to the third light-emitting element LD3' is basically the same.

[0226] Each of the first emitting units EU1' to the third emitting units EU3' may include an emitting layer that generates light according to an applied current. The first emitting unit EU1' may include a first emitting layer EML1', a first electron transport unit ETU1', and a first hole transport unit HTU1'. The first emitting layer EML1' may be disposed between the first electron transport unit ETU1' and the first hole transport unit HTU1'. The second emitting unit EU2' may include a second emitting layer EML2', a second electron transport unit ETU2', and a second hole transport unit HTU2'. The second emitting layer EML2' may be disposed between the second electron transport unit ETU2' and the second hole transport unit HTU2'. The third emitting unit EU3' may include a third emitting layer EML3', a third electron transport unit ETU3', and a third hole transport unit HTU3'. The third emitting layer EML3' may be disposed between the third electron transport unit ETU3' and the third hole transport unit HTU3'.

[0227] Each of the first hole transport units HTU1' to the third hole transport units HTU3' may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer and / or an electron blocking layer as needed. The first hole transport units HTU1' to the third hole transport units HTU3' may have the same or different structures.

[0228] Each of the first electron transport units ETU1' to the third electron transport units ETU3' may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer and / or a hole blocking layer as needed. The first electron transport units ETU1' to the third electron transport units ETU3' may have the same or different structures.

[0229] The first intermediate layer CGL1' may be disposed between the first emitting unit EU1' and the second emitting unit EU2'. The second intermediate layer CGL2' may be disposed between the second emitting unit EU2' and the third emitting unit EU3'. In one or more embodiments, the first intermediate layer CGL1' and the second intermediate layer CGL2' may both have conductivity by comprising a material having a relatively high charge conductivity (or charge mobility) compared to the first emitting unit EU1', the second emitting unit EU2', and the third emitting unit EU3'.

[0230] In one or more embodiments, the first emitting layer EML1' to the third emitting layer EML3' can generate multiple beams of light with different colors. The multiple beams of light emitted from the first emitting layer EML1' to the third emitting layer EML3' can be mixed and regarded as white light (e.g., combined white light). For example, in one or more embodiments, the first emitting layer EML1' can generate blue light, the second emitting layer EML2' can generate green light, and the third emitting layer EML3' can generate red light.

[0231] In one or more embodiments, two or more emission layers selected from the first emission layer EML1' to the third emission layer EML3' can produce light of the same color.

[0232] In the following, the manufacture of a display device DD according to one or more embodiments of the present disclosure (see Figure 5 The method.

[0233] Figure 12 This is a schematic block diagram illustrating a method of manufacturing a display device according to one or more embodiments of the present disclosure. Figures 13 to 21 These are plan views and cross-sectional views illustrating the process operations of a method for manufacturing a display device according to one or more embodiments of the present disclosure. Figure 22 It is shown Figure 21 The second schematic cross-sectional perspective view shows a portion of the individual unit. Figure 23 The display shows Figure 19 A schematic diagram of the crack in the image.

[0234] For example, Figure 13 It is used to describe Figure 12 The first operation S100 view, and is the corresponding to the mother substrate MS. Figure 1 A schematic plan view of part of EA. Figure 14 It is used to describe Figure 12 The second operation S200 view, and is the corresponding to the mother substrate MS. Figure 1 A schematic plan view of part of EA. Figure 15 It is used to describe Figure 12The view of the third operation S300, and is the corresponding to the mother base MS. Figure 1 A schematic plan view of part of EA. Figure 16 It is used to describe Figure 12 The fourth operation S400 view, and is the corresponding mother base MS. Figure 1 A schematic plan view of part of EA. Figure 17 It is along Figure 13 A schematic cross-sectional view taken from line III-III'. Figure 18 It is along Figure 14 A schematic cross-sectional view taken from line III-III'. Figure 19 It is along Figure 15 A schematic cross-sectional view taken from line III-III'. Figure 20 It is along Figure 16 A schematic cross-sectional view taken from line III-III', and Figure 21 It is used to describe Figure 12 The fifth operation of S500 is a view, and is related to Figures 12 to 23 The schematic cross-sectional view corresponding to line III-III'.

[0235] Although the operation of manufacturing display devices DD is in Figures 12 to 23 In one or more embodiments, it is described as being performed sequentially; however, unless the spirit of this disclosure is altered, it will be apparent that some operations shown as being performed sequentially may be performed concurrently (e.g., simultaneously), the order of each operation may be changed, some operations may be omitted (e.g., not performed), or other operations may be included between the operations.

[0236] exist Figure 12 In order to facilitate description and for the sake of brevity, descriptions that are repeated in the above embodiments will not be provided.

[0237] Reference Figure 13 , Figure 17 and Figures 7 to 11 Multiple display units DC (or display devices DD) are formed on the first surface 10 of the mother substrate MS (S100 - first operation).

[0238] The mother substrate (MS) can be a substrate for concurrently (e.g., simultaneously) manufacturing multiple display units (DCs) for process convenience, and can be a substrate (SUB) for a display device (DD). In other words, the mother substrate (MS) can be a substrate on which multiple display units (DCs) (or display devices (DDs) are manufactured for process convenience. The mother substrate (MS) can include one or more cell regions. A cell region can be a portion corresponding to a single display unit (DC) (or a single display device (DD), and a single display unit (DC) can be formed in each cell region.

[0239] In one or more embodiments, each of the display units DC can be individually separated to be used as a display device DD, and multiple display units DC can be formed concurrently (e.g., simultaneously) on a mother substrate MS and then separated by a cutting process, etc. Multiple display units DC can be disposed on a first surface 10 (or upper surface) of the mother substrate MS and can be arranged in a matrix according to rows (or display unit rows) extending in a first direction DR1 and columns (or display unit columns) extending in a second direction DR2.

[0240] Each of the display units (DC) may include a display panel (DPP) and a pad panel (PDP).

[0241] The display unit DC may include a first display unit DC1 arranged in odd-numbered rows and a second display unit DC2 arranged in even-numbered rows on the mother substrate MS. Each of the first display unit DC1 and the second display unit DC2 may include a display portion DPP arranged in the display area DA and a pad portion PDP arranged in the non-display area NDA.

[0242] The display section DPP can be referenced. Figure 12 The description of the display section.

[0243] Reference Figure 14 , Figure 18 and Figure 12 A filler layer FIL is formed on the display portion DPP of each display unit DC (S200 - second operation).

[0244] A coating solution comprising a transparent curable resin having a viscosity of a certain degree or greater (e.g., about 2000) is applied to the display portion DPP of each display monomer DC using a spray dispenser or similar device, and then a filler layer FIL is formed by performing a curing process, in which thermal curing, UV curing, or (e.g., both thermal curing and UV curing) are performed.

[0245] In embodiments where the coating solution has a certain level or higher viscosity, the diffusion of the coating solution to the pad PDP can be limited or prevented, such that if the coating solution is applied to the display DPP, the coating solution is spaced and / or separated from the pad PDP adjacent to the display DPP (e.g., spaced apart or separated) (e.g., when the coating solution is applied to the display DPP, the coating solution is spaced and / or separated from the pad PDP adjacent to the display DPP (e.g., spaced apart or separated)).

[0246] The filler layer FIL cured by the above curing process can have a certain level or higher hardness, and due to the viscosity of the coating solution that serves as the matrix material of the filler layer FIL, the filler layer FIL can have curved or rounded corners towards the edge of the display unit DPP. The filler layer FIL with curved or rounded corners can further improve the mechanical strength of each display unit DC by dispersing external impacts in one or more suitable directions. The filler layer FIL can be positioned on the top layer of each display unit DC on the third-party DR3 and can provide a display surface and / or input surface to the user. The filler layer FIL can be a protective layer or cover member that protects each display unit DC from external impacts, etc.

[0247] Reference Figure 15 , Figure 19 and Figure 23 After positioning the laser device 100 with a wavelength that penetrates the mother substrate MS on the first surface 10 of the mother substrate MS, the first laser beam (laser 1) is irradiated onto the boundary point between two adjacent display units DC to form a cutting alignment mark CUL (S300 - third operation) on the second surface 20 (rear surface or lower surface opposite to the first surface 10) of the mother substrate MS.

[0248] For example, in one or more embodiments, the first laser beam penetrating the mother substrate MS may be an infrared laser with a wavelength of 1000 nm or greater, but the embodiments disclosed herein are not limited thereto.

[0249] The first laser beam can illuminate the first surface 10 of the mother substrate MS at a point corresponding to the bisection of the boundary region BA between two adjacent display units DC (e.g., a first display unit DC1 and a second display unit DC2 arranged adjacent to each other in the second direction DR2), thereby forming a cutting alignment mark CUL on the second surface 20 of the mother substrate MS corresponding to the aforementioned point. In one or more embodiments, the gap between two adjacent display units DC can be in the range of about 5 micrometers (μm) to about 50 μm, but the embodiments of this disclosure are not limited thereto.

[0250] In embodiments where the first laser beam irradiates a preset area (e.g., the point that bisects the boundary area BA between adjacent display units DC), a cutting alignment mark CUL can be formed on the second surface 20 of the mother substrate MS by using a focusing adjustment method that focuses the laser device 100 irradiating the first laser beam on the rear surface of the mother substrate MS or by using an irradiation method such as a dual laser device.

[0251] In embodiments where the first laser beam irradiates a predetermined area of ​​the mother substrate MS, a crack CR corresponding to a laser processing mark may be formed inside the mother substrate MS. The crack CR can be formed inside the mother substrate MS in the predetermined area irradiated by the first laser beam, and can be implemented as a cutting alignment mark CUL in the form of a line on the second surface 20 of the mother substrate MS. Figure 12 As shown, multiple cracks CR can be formed in the form of lines extending in a direction intersecting the thickness direction of the parent substrate MS on the cross section of the parent substrate MS irradiated by the first laser beam. For example, in an embodiment where the parent substrate MS has a thickness of 700 μm or greater, 3 to 15 cracks CR in the form of lines can be formed on the cross section of the parent substrate MS on which the first laser beam irradiates.

[0252] Reference Figure 16 , Figure 20 and Figure 15 After flipping the mother substrate MS so that its second surface 20 faces upward, a second laser beam (laser 2) is irradiated onto the cutting alignment mark CUL to align the mother substrate MS (see...). Figure 12 The display unit DC is separated into units (S400-Fourth Operation).

[0253] In one or more embodiments, the second laser beam may be an ultrashort pulse laser with a short wavelength (specifically, visible light, e.g., UV and green light) that is absorbed by the parent substrate MS, but embodiments of this disclosure are not limited thereto.

[0254] In embodiments where the second laser beam is concentrated on the cutting alignment mark CUL formed on the second surface 20 of the mother substrate MS, a portion of the second surface 20 of the mother substrate MS can be removed to form a recessed groove in the direction toward the first surface 10. As the mother substrate MS expands due to the heat generated when the second laser beam is irradiated, the crack CR formed inside the mother substrate MS in the third operation S300 described above propagates, causing the mother substrate MS to naturally fracture, thereby forming each display unit DC. In these embodiments, the side surface 30 of the substrate SUB of each display unit DC can be used as the cutting surface. The side surface 30 of the substrate SUB can be positioned between the first surface 10 on which the display portion DPP is formed and the second surface 20 opposite to the first surface 10 of the mother substrate MS (or substrate SUB), and can be connected to each of the first surface 10 and the second surface 20.

[0255] When the mother substrate MS breaks, the groove can be transformed into a chamfered portion CHM formed in two adjacent display units DC (e.g., a chamfered portion CHM on the side surface 30 of the substrate SUB of the first display unit DC1 and the side surface 30 of the substrate SUB of the second display unit DC2). For example, the chamfered portion CHM can be formed on at least a portion of the side surface 30 of the substrate SUB of each of the first display units DC1 and the second display units DC2. At least a portion of the side surface 30 of the substrate SUB of each display unit DC can have a certain gradient due to the chamfered portion CHM.

[0256] In one or more embodiments, in each display monomer DC fracture that is separated individually due to the parent substrate MS, at least a portion of the side surface 30 of the substrate SUB may be positioned on the same line as the edge of the filler layer FIL in the thickness direction of the substrate SUB, but embodiments of this disclosure are not limited thereto.

[0257] In one or more embodiments, a chamfered portion CHM may be formed on the entire side surface 30 of the substrate SUB of each display cell DC. The chamfered portion CHM in each display cell DC may additionally increase the edge reliability level of the substrate SUB (or its ability to withstand stress and edge impacts), thereby further improving the mechanical stability of each display cell DC.

[0258] In the third operation S300, during the irradiation of the second laser beam, the crack CR formed inside the parent substrate MS can propagate in a direction parallel to the first surface 10 (and / or the second surface 20) of the parent substrate MS, thus remaining on the cut surface of each display unit DC when the parent substrate MS fractures. Therefore, at least a portion of the cut surface of each display unit DC (or the side surface 30 of the substrate SUB) may have a curved surface due to the crack CR.

[0259] In the above embodiments, a chamfered portion CHM with a certain gradient can be formed on at least a portion of the side surface 30 of the substrate SUB of each display unit DC, and cracks CR forming a curved surface can be formed on the remaining portion of the side surface 30.

[0260] Reference Figure 21 , Figure 22 and Figure 24 A side sealing member SSM is formed to cover the cut surface of each display unit DC (S500 - fifth operation).

[0261] Before forming the side sealing component SSM, for ease of process, each display unit DC can be inverted so that the filler layer FIL of each display unit DC faces upward.

[0262] The side sealing member (SSM) may include a curable resin with a certain level or greater viscosity. The side sealing member (SSM) may be disposed on the chamfered CHM, the cut surface of each display monomer DC (or the side surface 30 of the substrate SUB), and the side surface of the filler layer FIL to cover the chamfered CHM, the cut surface of each display monomer DC, and the side surface of the filler layer FIL. The side sealing member (SSM) may include a moisture-proof and water-repellent material to prevent moisture penetration.

[0263] Following this process, a further cleaning process can be performed to remove foreign matter from the surface of the substrate SUB.

[0264] A separate display unit DC can be used in one or more suitable electronic devices, such as televisions (TVs), smartphones, wearable devices, etc. For example, in one or more embodiments, a separate display unit DC can be used in a device for implementing VR or AR.

[0265] According to the above embodiments, a first laser beam that penetrates the mother substrate MS (or substrate SUB) can be irradiated onto a predetermined area of ​​the first surface 10 of the mother substrate MS to form a cutting alignment mark CUL on the second surface 20 of the mother substrate MS, and a second laser beam that is absorbed by the mother substrate MS can be directly irradiated onto the cutting alignment mark CUL to separate the mother substrate MS into each display unit DC, thereby forming a chamfered portion CHM at the edge of each display unit DC.

[0266] As described above, in the process of separating the mother substrate MS into individual display units DC, chamfered portions CHM that improve the mechanical strength of each display unit DC can be formed concurrently (e.g., simultaneously). Therefore, a process for forming chamfered portions CHM separately can be eliminated or eliminated, thereby improving the manufacturing efficiency of the display device DD.

[0267] Furthermore, a side sealing member (SSM) can be formed on the side surface 30 of the substrate SUB of each display unit DC to cover the side surface 30 of the substrate SUB, so that the chamfered portion (CHM) and crack (CR) located on the cut surface of the substrate SUB are not exposed to the outside. In this respect, a polishing process that smooths out the cut surface (or side surface 30) of the substrate SUB due to cutting processes or the like can be eliminated or is not required, thereby further improving the manufacturing efficiency of the display device DD.

[0268] In the above embodiments, it has been described that a chamfered portion (CHM) is formed in each display unit DC during the process of separating the mother substrate MS into individual display units DC by irradiating a first laser beam that penetrates the mother substrate MS and irradiating a second laser beam that is absorbed by the mother substrate MS. However, the embodiments of this disclosure are not limited thereto. According to one or more embodiments, the mother substrate MS can be separated into individual display units DC by irradiating only a laser beam that penetrates the mother substrate MS, and a chamfered portion (CHM) can also be formed in each of the separated display units DC.

[0269] For example, the process involves using a first laser beam to penetrate the parent substrate MS and form a cutting alignment mark CUL on the second surface 20 of the substrate SUB. Then, a second laser beam, absorbed by the substrate SUB, is used to directly irradiate the cutting alignment mark CUL, separating the parent substrate MS into individual display units DC and concurrently forming chamfered edges CHM at the edges of each display unit DC. This concurrent or simultaneous formation of chamfered edges CHM enhances the mechanical strength of each display unit DC and eliminates the need for a separate chamfering process, thereby improving manufacturing efficiency.

[0270] Furthermore, a side sealing member (SSM) is applied to cover the side surface 30 of each display unit (DC), ensuring that any cracks and chamfered edges on the cut surface are not exposed. This method eliminates the need for polishing processes to smooth the cut surface, further improving the manufacturing efficiency of the display device (DD). The described method emphasizes the improved efficiency and reliability in the production of display devices (DDs) by integrating the chamfering process with the laser cutting operation.

[0271] Figure 24 This is a schematic block diagram illustrating a display system 1000 according to one or more embodiments of the present disclosure.

[0272] Reference Figure 24 The display system 1000 may include a processor 1100 and one or more display devices 1210 and 1220.

[0273] Processor 1100 can perform one or more suitable tasks and calculations. In one or more embodiments, processor 1100 may include an application processor, graphics processor, microprocessor, central processing unit (CPU), etc. Processor 1100 can be connected to other components of display system 1000 via a bus system to control those other components.

[0274] exist Figure 4In the diagram, the display system 1000 is shown to include a first display device 1210 and a second display device 1220. The processor 1100 can be connected to the first display device 1210 via a first channel CH1 and to the second display device 1220 via a second channel CH2.

[0275] Through the first channel CH1, the processor 1100 can transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1210. The first display device 1210 can display an image based on the first image data IMG1 and the first control signal CTRL1. The first display device 1210 may have a reference... Figure 4 The display device described has the same construction as DD.

[0276] Through the second channel CH2, the processor 1100 can transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1220. The second display device 1220 can display an image based on the second image data IMG2 and the second control signal CTRL2. The second display device 1220 may have a reference... Figure 25 The display device described has the same construction as DD.

[0277] Display system 1000 may include a computing system (such as a portable computer, mobile phone, smartphone, tablet PC, smartwatch, watch phone, portable multimedia player (PMP), navigation device, or ultra-mobile PC) for providing image display functionality. Additionally, display system 1000 may include at least one of an HMD device, VR device, MR device, and AR device.

[0278] Figure 24 This illustrates one or more embodiments according to the present disclosure. Figure 25 A schematic perspective view of an application example of the display system 1000.

[0279] Reference Figure 24 In one or more embodiments, Figure 24 The display system 1000 can be applied to the HMD device 2000. The HMD device 2000 can be a wearable electronic device that can be worn on the user's head.

[0280] HMD device 2000 may include a headband 2100 and a display device housing 2200. The headband 2100 may be connected to the display device housing 2200. The headband 2100 may include a horizontal and / or vertical strap for securing the HMD device 2000 to a user's head. The horizontal strap may be configured to be around the sides of the user's head (e.g., around the sides of the user's head), and the vertical strap may be configured to be above the user's head (e.g., around the top of the user's head). However, embodiments of this disclosure are not limited thereto. For example, in one or more embodiments, the headband 2100 may be implemented in the form of an eyeglass frame, a helmet, etc.

[0281] The display device housing 2200 can accommodate Figure 24 The first display device 1210 and the second display device 1220. The display device housing 2200 can also accommodate... Figure 26 The processor is 1100.

[0282] Figure 25 This illustrates a user wearing one or more embodiments according to this disclosure. Figure 26 A schematic diagram of the status of the HMD device 2000.

[0283] Reference Figure 24 In the HMD device 2000, a first display device 1210 (see...) is arranged. Figure 24 The first display panel DP1 and the second display device 1220 (see) ​ The second display panel DP2 of the HMD device 2000 may also include one or more lenses LLNS and RLNS.

[0284] Within the display device housing 2200, the right eye lens RLNS can be positioned between the first display panel DP1 and the user's right eye. Within the display device housing 2200, the left eye lens LLNS can be positioned between the second display panel DP2 and the user's left eye.

[0285] In one or more embodiments, the image output from the first display panel DP1 can be displayed to the user's right eye via a right-eye lens RLNS. The right-eye lens RLNS can refract light from the first display panel DP1 to direct the light to the user's right eye. The right-eye lens RLNS can perform an optical function to adjust the viewing distance between the first display panel DP1 and the user's right eye.

[0286] In one or more embodiments, the image output from the second display panel DP2 can be displayed to the user's left eye via a left-eye lens LLNS. The left-eye lens LLNS can refract light from the second display panel DP2 to direct the light towards the user's left eye. The left-eye lens LLNS can perform an optical function to adjust the viewing distance between the second display panel DP2 and the user's left eye.

[0287] In one or more embodiments, both the right-eye lens RLNS and the left-eye lens LLNS may include optical lenses with a pancake-shaped profile. In one or more embodiments, both the right-eye lens RLNS and the left-eye lens LLNS may include multi-channel lenses comprising sub-regions with different optical properties. In these embodiments, each display panel may output an image corresponding to a sub-region of the multi-channel lens, and the output image may pass through the sub-region and be viewed by the user.

[0288] According to one or more embodiments, in a mother substrate comprising a plurality of display units, a first laser beam penetrating the mother substrate can irradiate between the display units to form a cutting alignment mark on the rear surface of the mother substrate, and a second laser beam absorbed by the mother substrate can irradiate the cutting alignment mark to form a chamfer in each of the display units, thereby individually separating each of the display units.

[0289] Therefore, chamfers can be formed on the side surfaces of each display unit in a process that separates the display units individually, thus eliminating the need for a separate process for forming the chamfers and providing a display device with improved manufacturing efficiency.

[0290] The effects and aspects of one or more embodiments are not limited to those discussed above, and one or more suitable effects and aspects are included in this disclosure.

[0291] In the context of this application and unless otherwise defined, the term “use” and its variations may be considered synonymous with the term “utilize” and its variations, respectively.

[0292] As used herein, the terms “substantially,” “about,” or similar terms are used as approximations rather than terms of degree and are intended to account for inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. As used herein, “about” includes the stated value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0293] Any numerical range described herein is intended to include all subranges with the same numerical precision contained within the range. For example, the range “1.0 to 10.0” is intended to include all subranges between the minimum value 1.0 and the maximum value 10.0 (and including both the minimum value 1.0 and the maximum value 10.0), i.e., a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower limits of numerical values ​​contained therein, and any minimum numerical limit described in this specification is intended to include all upper limits of numerical values ​​contained therein. Therefore, the applicant reserves the right to amend this disclosure (including the claims) to expressly describe any subranges contained within the range expressly described herein.

[0294] It will be understood by those skilled in the art that, in view of the whole of this disclosure, each suitable feature of the various embodiments of this disclosure may be combined in part or in whole or in combination with one another, and may be technically interlocked and operated in a variety of suitable ways, and unless otherwise stated or implied, each embodiment may be implemented independently or in combination with one another in any suitable manner.

[0295] The display device manufacturing apparatus, display device, electronic device / equipment, or any other related device / equipment or component according to embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application-specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, various components of the device may be formed on an integrated circuit (IC) chip or on a separate IC chip. Furthermore, various components of the device may be implemented on a flexible printed circuit film, a tape-on-a-carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. Additionally, various components of the device may be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in memory, which may be implemented in a computing device using standard memory devices, such as random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer-readable media, such as CD-ROMs, flash drives, etc. Furthermore, those skilled in the art will recognize that, without departing from the scope of the embodiments of this disclosure, the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed across one or more other computing devices.

[0296] Although specific example embodiments and applications have been described herein, one or more embodiments and modifications can be derived from the above description. Therefore, the technical scope of this disclosure is not limited to such embodiments, but is limited to the broader scope of the presented claims and one or more suitable obvious modifications and equivalent arrangements.

Claims

1. A display device, the display device comprising: A substrate, in which a display area and a non-display area are defined, and the substrate has a first surface and a second surface opposite to each other in the thickness direction of the substrate, and a side surface located between the first surface and the second surface; The display unit is located on the first surface of the substrate in the display area and is configured to display an image; The pad portion is located on the first surface of the substrate in the non-display area; A filling layer is placed on the display portion and configured to cover the display portion; as well as A chamfered portion is located on at least a portion of the side surface of the substrate. The side surface of the substrate includes at least one crack extending in a direction intersecting the thickness direction.

2. The display device according to claim 1, wherein, The side surface of the base connected to the chamfer has a curved surface.

3. The display device according to claim 1, wherein, The filler layer comprises a transparent curable resin and is located on the topmost layer of the display portion in the display area.

4. The display device according to claim 1, wherein, The substrate includes a silicon wafer substrate.

5. The display device according to claim 1, further comprising a side sealing member on the chamfered portion to cover the chamfered portion.

6. The display device according to claim 1, wherein, The display unit includes: Anode, on the substrate; A pixel-defining layer on the substrate and including an opening configured to expose a portion of the anode; The emitting structure is located on the anode and the pixel defining layer; and The cathode is located on the emission structure.

7. The display device according to claim 6, wherein, The launching structure includes: A first emitting unit is located on the anode and the pixel defining layer and is configured to emit light; The intermediate layer is located on the first transmitting unit; and The second emitting unit is located on the intermediate layer and is configured to emit light.

8. The display device according to claim 6, wherein, The launching structure includes: A first emitting unit is located on the anode and the pixel defining layer and is configured to emit light; The first intermediate layer is located on the first transmitting unit; The second emitting unit is located on the first intermediate layer and is configured to emit light; A second intermediate layer, on the second transmitting unit; and The third emitting unit is located on the second intermediate layer and is configured to emit light.

9. A wearable electronic device, the wearable electronic device comprising: Display panel; as well as Lens, on the display panel, The display panel includes: a substrate defining a display area and a non-display area, the substrate having a first surface and a second surface opposite to each other in the thickness direction of the substrate, and a side surface located between the first surface and the second surface; a display portion on the first surface of the substrate in the display area and configured to display an image; a pad portion on the first surface of the substrate in the non-display area; a fill layer on the display portion and configured to cover the display portion; and a chamfered portion located on at least a portion of the side surface of the substrate. The side surface of the substrate includes at least one crack extending in a direction intersecting the thickness direction.

10. The wearable electronic device according to claim 9, wherein, The filler layer comprises a transparent curable resin and is located on the topmost layer of the display portion in the display area.

11. The wearable electronic device according to claim 9, wherein, The substrate includes a silicon wafer substrate.

12. The wearable electronic device according to claim 9, wherein, The display panel also includes a side sealing member on the chamfered portion to cover the chamfered portion.

13. The wearable electronic device according to claim 9, wherein, The display unit includes: Anode, on the substrate; A pixel-defining layer on the substrate and including an opening configured to expose a portion of the anode; The emitting structure is located on the anode and the pixel defining layer; and The cathode is located on the emission structure.

14. A method comprising the following steps: The setup includes a mother substrate comprising multiple display units; A filler layer is formed on the display portion of each of the plurality of display units; The first laser beam is directed onto the first surface of the mother substrate at the boundary point between two adjacent display units among the plurality of display units, and a cutting alignment mark is formed on the second surface of the mother substrate opposite to the first surface. as well as The mother substrate is flipped so that the second surface faces upward, and a second laser beam is directed onto the cutting alignment marks to form a chamfer. Then, each of the plurality of display units is separated individually. The method described herein is a method for manufacturing a display device.

15. The method according to claim 14, wherein, The first laser beam is a laser with a wavelength that penetrates the mother substrate, and The second laser beam is a laser with a wavelength that is absorbed by the mother substrate.

16. The method of claim 14, wherein, The parent substrate includes a silicon wafer substrate. The first laser beam includes an infrared laser, and The second laser beam includes visible light laser.

17. The method of claim 14, wherein, In the step of forming the cutting alignment mark, when the first laser beam is irradiated onto the first surface of the mother substrate, at least one crack is formed inside the mother substrate.

18. The method according to claim 17, wherein, In the step of separating each of the plurality of display units individually, heat is generated when the second laser beam is irradiated onto the cutting alignment mark, and the at least one crack propagates due to the heat, causing the mother substrate to expand to separate individually into each of the plurality of display units.

19. The method of claim 14, further comprising: After the step of separating each of the plurality of display units individually, a side sealing member configured to cover the chamfer is formed.

20. The method of claim 14, wherein, The filler layer comprises a transparent curable resin and is located on the topmost layer of the display portion of each of the plurality of display units.

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