Power management based on limited hardware enforced power control

Abstract

The invention relates to power management based on limited hardware enforced power control. Various techniques and circuit implementations for power reduction management in integrated circuits are disclosed. Specifically, a power manager circuit in an integrated circuit (e.g., a system on chip) may modify a power budget for various components in the integrated circuit to reduce an amount of power control caused by external signaling indicative of a voltage regulator overload (e.g., a voltage drop).

Description

Related application citation

[0001] This application is a divisional application of the invention patent application with international application number PCT / US2022 / 039136, international application date August 2, 2022, entry into the Chinese national phase date February 27, 2024, Chinese national application number 202280058308.4, and invention title "Power Management Based on Restricted Hardware-Forced Power Control". Technical Field

[0002] The implementation schemes described herein relate to power management in integrated circuits, and more specifically, to triggering circuits for controlling power delivery to integrated circuits. Attached Figure Description

[0003] The features and advantages of the methods and apparatus of the embodiments described in this disclosure will be more fully understood when taken in conjunction with the accompanying drawings, by referring to the following detailed description of the currently preferred, but only exemplary, embodiments according to which the present disclosure is described: Figure 1 It is a block diagram of one implementation of a system-on-a-chip (SoC) that includes a memory and a power management unit (PMU).

[0004] Figure 2 This is a block diagram of one implementation scheme of PMU.

[0005] Figure 3 This is a block diagram of another implementation scheme of PMU.

[0006] Figure 4 This is a block diagram of one implementation scheme for a global power control circuit.

[0007] Figure 5 This is a block diagram of one implementation of the memory controller pipeline.

[0008] Figure 6 This is a block diagram of one implementation of a rate limiter component.

[0009] Figure 7 This is a block diagram of another implementation of a system-on-a-chip (SOC).

[0010] Figure 8 This is a block diagram of an implementation scheme for a power management mechanism.

[0011] Figure 9 This is a timing diagram showing the power control window.

[0012] Figure 10This is a flowchart illustrating one implementation of an operating power management processor.

[0013] Figure 11 This is a flowchart illustrating a method for reducing power in an integrated circuit according to some implementation schemes.

[0014] Figure 12 This is a flowchart illustrating another method for reducing power in an integrated circuit according to some implementation schemes.

[0015] Figure 13 It is a block diagram of an implementation scheme for a power transmission system.

[0016] Figure 14 This is a block diagram illustrating one embodiment that includes a computer system, a computer-readable medium, and a fabrication system.

[0017] Figure 15 This is a block diagram of one implementation of the example system.

[0018] In the following description, numerous specific details are set forth to provide a thorough understanding of the described embodiments. However, those skilled in the art will recognize that aspects of the disclosed embodiments can be practiced without these specific details. In some instances, well-known circuits, structures, signals, computer program instructions, and techniques have not been shown in detail so as not to obscure the disclosed embodiments. Detailed Implementation

[0019] Figure 1 This is a block diagram of one embodiment of a system-on-a-chip (SOC) 110, which includes memory 120 and a power management unit (PMU) 140. The PMU 140 can be configured to power the SOC 110 and other components that may be included in the system, such as memory 120. For example, the PMU 140 can be configured to generate one or more supply voltages to power the SOC 110, and can be further configured to generate power for other components of the system (…). Figure 1The supply voltage (not shown). In addition, PMU 140 (or accompanying circuitry coupled to PMU 140) can be configured to monitor the supply voltage and detect transient undervoltage conditions, overcurrent conditions, power limiting conditions, temperature conditions, or other conditions that may cause malfunctions in SOC 110. When such a condition occurs (e.g., the electrical load of SOC 110 exceeds the capacity of PMU 140), PMU 140 can assert a trigger output signal to SOC 110. As an example, for power limiting conditions, power can be averaged over different time constants, where the power limits for different time constants are different (e.g., a shorter average time constant may have a higher limit than a longer average time constant), and triggering can be asserted based on exceeding any of the power limits for different time constants. In some implementations, the square of the current (ISql) can be used. 2 RMS constraints are used to apply power limits.

[0020] In various implementations, the trigger output signal can be transmitted to the SOC 110 via wired transmission (e.g., a hardwired interface between two components) or a serial communication interface (e.g., a bidirectional communication interface). Wired trigger signal transmission can be provided to a global power control circuitry 130 included in the SOC 110, capable of receiving trigger inputs, while serial trigger signal transmission can be provided directly to the processor engine (e.g., processor cluster 150, GPU 160, or peripheral device 180) via a serial controller 124 and / or communication structure 170. The serial controller 124 can be a System Power Management Interface (SPMI) providing bidirectional communication between the processor engine and the PMU 140. Although the illustrated serial controller 124 is transmitted via… Figure 1 The communication structure 170 communicates with the processor engine, but in various implementations, the serial controller 124 can communicate directly with one or more processor engines. The following section discusses... Figure 2 The implementation of the PMU 140 described herein discusses wired trigger signal transmission and serial trigger signal transmission in more detail. Although this document uses a SOC implementation as an example, in other implementations, a system comprising multiple integrated circuits coupled to the communication structure may be used.

[0021] As its name suggests, the components of SOC 110 can be integrated onto a single semiconductor substrate as an integrated circuit "chip". In the illustrated embodiment, the components of SOC 110 include at least one processor cluster 150, at least one graphics processing unit (GPU) 160, one or more peripheral components (e.g., peripheral component 180 (more simply, "peripheral device")), at least one memory controller 122, global power control circuitry 130, and communication structure 170. Components 150, 160, 180, 122, and 130 may all be coupled to communication structure 170. Memory controller 122 may be coupled to memory 120 during use. In some embodiments, there may be more than one memory controller coupled to a corresponding memory. In such embodiments, the memory address space may be mapped across memory controllers in any desired manner. In the illustrated embodiment, processor cluster 150 may include multiple processors (P) 152. Processors 152 may form the central processing unit (CPU) of SOC 110. Processor cluster 150 may further include one or more coprocessors (e.g., Figure 1 The coprocessor 154 in the processor 152 may be optimized for a subset of the processor's instruction set and may be used by the processor 152 to execute instructions from that subset. For example, the coprocessor 154 may be a matrix engine optimized to perform vector and matrix operations.

[0022] As described above, processor cluster 150 may include one or more processors 152 that can be used as CPUs in SOC 110. The system's CPU includes one or more processors that execute the system's main control software, such as an operating system. Typically, software executed by the CPU during use controls other components of the system to achieve the desired functionality of the system. The processor may also execute other software such as application programs. Application programs provide user functionality and may rely on the operating system for lower-level device control, scheduling, memory management, etc. Therefore, the processor may also be referred to as an application processor.

[0023] Typically, a processor may include any circuit system and / or microcode configured to execute instructions defined in the instruction set architecture implemented by the processor. A processor may encompass a processor core implemented on an integrated circuit having other components as a system-on-a-chip (SoC) or other level of integration. A processor may also include discrete microprocessors, processor cores and / or microprocessors integrated into a multi-chip module implementation, processors implemented as multiple integrated circuits, and so on.

[0024] The memory controller 122 may typically include circuitry for receiving memory operations from other components of the SOC 110 and for accessing the memory 120 to complete the memory operations. The memory controller 122 may be configured to access any type of memory 120. For example, the memory 120 may be static random access memory (SRAM), dynamic RAM (DRAM) such as synchronous DRAM (SDRAM) including double data rate (DDR, DDR2, DDR3, DDR4, etc.) DRAM. Low-power / mobile versions of DDR DRAM (e.g., LPDDR, mDDR, etc.) may be supported. The memory controller 122 may include a memory operation queue for ordering (and potentially reordering) these operations and presenting them to the memory 120. The memory controller 122 may also include data buffers for storing write data awaiting to be written to memory and read data awaiting return to the source of the memory operation. In some embodiments, the memory controller 122 may include a memory cache for storing recently accessed memory data. For example, in a specific SOC implementation, a memory cache can reduce power consumption in the SOC by preventing data from being re-accessed from the memory 120 if it is expected to be accessed again soon. In some cases, the memory cache may also be referred to as the system cache, which differs from proprietary caches such as the L2 cache or the cache within the processor, which serve only certain components. Furthermore, in some implementations, the system cache does not need to reside within the memory controller 122.

[0025] Peripheral device 180 can be any set of additional hardware functions included in SOC 110. For example, peripheral device 180 may include video peripherals such as image signal processors, video encoders / decoders, expanders, rotators, mixers, display controllers, etc., configured to process image capture data from cameras or other image sensors. Peripheral devices may include audio peripherals such as microphones, speakers, interfaces to microphones and speakers, audio processors, digital signal processors, mixers, etc. Peripheral devices may include interface controllers for various interfaces external to SOC 110, including interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect (PCI) including PCI Express (PCIe), serial and parallel ports, etc. Interconnection to external devices is provided by... Figure 1 The dashed arrow extending outwards from the SOC 110 is shown. Peripheral devices may include networked peripherals such as a Media Access Controller (MAC). Any set of hardware may be included.

[0026] Communication architecture 170 can be any communication interconnect and protocol used for communication between components of SOC 110. Communication architecture 170 can be bus-based, including shared bus configurations, crossbar configurations, and hierarchical buses with bridges. Communication architecture 170 can also be packet-based and can be hierarchical, crossbar, point-to-point, or other interconnects with bridges.

[0027] Note the number of components in the SOC 110 (and) Figure 1 The number of sub-components (such as processors 152 in each processor cluster 150) of the components shown may vary depending on the implementation. Furthermore, when multiple processor clusters are included, the number of processors 152 in one processor cluster 150 may differ from the number of processors 152 in another processor cluster 150. The number of each component / sub-component may be more or less than [the number shown in the original text]. Figure 1 The quantity shown.

[0028] As described herein, PMU 140 can be configured to assert one or more trigger signals when various conditions that may lead to malfunctions in SOC 110 are detected. Figure 2 This is a block diagram of one embodiment of PMU 140. In the illustrated embodiment, PMU 140 includes a voltage regulator 142 and a power transfer trigger circuit 144. In some embodiments, the power transfer trigger circuit 144 is configured to monitor the supply voltage in the voltage regulator 142 and provide a trigger signal when a transient undervoltage condition is detected in the voltage regulator. For example, the power transfer trigger circuit 144 can provide a trigger signal when the supply voltage provided by the voltage regulator 142 drops below a threshold (e.g., an undervoltage threshold).

[0029] Figure 3 This is a block diagram of another embodiment of the PMU 140. In the illustrated embodiment, the PMU 140 includes a voltage regulator 142, a wired power transfer trigger circuit 144, and a serial power transfer trigger circuit 146. Figure 3As shown, PMU 140 may include multiple voltage regulators 142 (e.g., voltage regulators 142A, 142B, 142C) connected to multiple sets of power delivery trigger circuits (e.g., wired power delivery trigger circuits 144A, 144B, 144C and serial power delivery trigger circuits 146A, 146B, 146C). Any number of voltage regulators 142, wired power delivery trigger circuits 144, and serial power delivery trigger circuits 146 can be envisioned in PMU 140. Voltage regulators 142A, 142B, 142C may represent different voltage regulators providing different supply voltages to different parts of SOC 110. For example, voltage regulator 142A may provide a supply voltage to processor cluster 150, while voltage regulator 142B may provide a supply voltage to GPU 160. In various embodiments, voltage regulators 142A, 142B, 142C may be a hierarchical power delivery system (e.g., Figure 9 It is part of the hierarchical power transmission system (900) described in the document.

[0030] As described above, the wired power delivery trigger circuit 144 can be directly connected to the SOC 110 (e.g., the global power control circuit 130 in the SOC 110), while the serial power delivery trigger circuit 146 can be coupled to the SOC 110 (e.g., the communication structure 170 in the SOC 110) via a serial communication interface (e.g., SPMI). In various embodiments, the serial power delivery trigger circuit 146 includes an SPMI for communicating with the SOC 110 (e.g., via a serial controller 124). Therefore, the serial power delivery trigger circuit 146 is capable of bidirectional communication with the SOC 110, while the wired power delivery trigger circuit 144 provides unidirectional communication from the wired power delivery trigger circuit 144 to the SOC 110.

[0031] In some embodiments, the wired power transfer trigger circuit 144 and the serial power transfer trigger circuit 146 are configured to monitor one or more conditions (e.g., voltage, current, or temperature) in the voltage regulator 142 and provide a trigger signal when the condition exceeds various thresholds determined by the power transfer trigger circuit. Various embodiments with fast (nanosecond) and slow (microsecond or millisecond) responses can be implemented in either the wired power transfer trigger circuit 144 or the serial power transfer trigger circuit 146. In some embodiments, a fast response is implemented in the wired power transfer trigger circuit 144 to take advantage of the high transmission speed of the wired connection. Conversely, a slow response can be implemented in the serial power transfer trigger circuit 146 because the serial connection provides a signal transmission speed at the slow response level.

[0032] In various implementations, the series connection between the series power delivery trigger circuit 146 and the SOC 110 allows the SOC 110 to query conditions. For example, when the operation of the SOC 110 changes or another event occurs, the SOC 110 can provide a request for condition information. The SOC 110 can provide the request query to the series power delivery trigger circuit 146 via a serial communication interface. The series power delivery trigger circuit 146 can then provide the condition state (e.g., a condition value higher or lower than a threshold) via a trigger signal output back to the SOC 110 through the serial communication interface.

[0033] In some embodiments, a trigger signal is provided when the electrical load experienced in the voltage regulator 142 exceeds a threshold (e.g., the voltage drops below an undervoltage threshold). For example, a voltage-sensing element, such as a voltage-based comparator circuit, can be used to implement the voltage threshold comparison. The voltage-based comparator circuit can be a fast-response circuit typically used in wired power transfer triggering circuit 144. In some embodiments, a trigger signal is provided when the current experienced in the voltage regulator 142 exceeds a current threshold (e.g., when the current exceeds a predetermined current limit). The current threshold comparison can be implemented by an output current comparator circuit (e.g., a current-sensing element), which can be a fast-response circuit used in wired power transfer triggering circuit 144. In some envisioned embodiments, current sensing capability is implemented to monitor current conditions (e.g., determining whether the current exceeds an overcurrent threshold). For example, the current sensing capability can include a filtered current sensing capability, which can be implemented in a slow-response serial power transfer triggering circuit 146. In some implementations, a trigger signal is provided when the temperature experienced in the voltage regulator 142 exceeds a predetermined temperature to prevent overheating in the PMU 140. Temperature sensing typically results in a slow response to the serial power delivery trigger circuitry 146, which can be implemented in a temperature sensing scheme.

[0034] The above description provides example implementations of various response schemes under different conditions described herein. However, it should be understood that the location and number of response schemes can vary among the voltage regulator 142, the wired power transfer trigger circuit 144, and the serial power transfer trigger circuit 146 for the desired operation of the PMU 140 and SOC 110. For example, in various implementations, both the wired power transfer trigger circuit 144 and the serial power transfer trigger circuit 146 can be implemented to monitor similar operating conditions (e.g., voltage or current) in the same voltage regulator 142. In such an implementation, the wired power transfer trigger circuit 144 provides a fast response time, while the serial power transfer trigger circuit 146 provides a slower response.

[0035] In some implementations, the wired power delivery trigger circuit 144 and the serial power delivery trigger circuit 146 can provide different power management capabilities based on different response times and the location where the trigger signal is sent in the SOC 110. As an example, such as Figure 1 and Figure 3 As shown, wired power delivery trigger circuit 144 provides a wired trigger signal to global power control circuit 130, while serial power delivery trigger circuit 146 provides a serial trigger signal to communication structure 170, and then to components such as processor cluster 150 or GPU 160. As described herein, global power control circuit 130 is capable of providing fast response and fast clock rate control to prevent functional failures in SOC 110 or PMU 140. However, the serial trigger signal provided by serial power delivery trigger circuit 146 can be implemented by components in SOC 110 (e.g., processor cluster 150 or GPU 160) to determine more precise control over the operation of SOC 110 (e.g., by using dynamic voltage and frequency control in components of SOC 110).

[0036] Therefore, in some implementations, the threshold of the wired power delivery trigger circuit 144 is closer to the point of functional failure of the SOC 110 or PMU 140 than the threshold of the serial power delivery trigger circuit 146. The threshold of the wired power delivery trigger circuit 144 can be closer to the point of functional failure of the SOC 110 or PMU 140 to provide a rapid response when operating conditions may cause a functional failure in the SOC 110 or PMU 140. Conversely, a slower response may be more suitable when the SOC 110 or PMU 140 is further from the point of functional failure. As an example, the voltage threshold of the wired power delivery trigger circuit 144 can be closer to the undervoltage that causes a functional failure in the SOC 110 or PMU 140 (e.g., the wired voltage threshold is lower than the serial voltage threshold) than the voltage threshold of the serial power delivery trigger circuit 146. Therefore, if the voltage begins to drop slowly, the serial voltage threshold may be exceeded first before the wired voltage threshold is reached, and the SOC 110 can respond to the serial trigger signal from the serial power delivery trigger circuit 146. However, if the voltage drops rapidly, even after the serial voltage threshold is reached, the fast response provided by the wired power delivery trigger circuit 144 and the global power control circuit 130 may occur before the SOC 110 has a chance to respond to the serial trigger signal. The response to the wired signal can retain functionality until a later serial trigger signal read is performed and the SOC 110 reacts to it. This tiered response scheme can provide improved performance for both the SOC 110 and PMU 140 while preventing functional failures in the device.

[0037] In some implementations, the response scheme is hierarchical based on the hierarchy within the power transmission system (e.g., the hierarchy between voltage regulators 142A, 142B, and 142C). For example, voltage regulator 142A may have a higher hierarchy than voltage regulator 142B. Therefore, a trigger signal from wired power transmission trigger circuit 144A or serial power transmission trigger circuit 146A may have a higher hierarchy (e.g., higher priority) in determining a power reduction than wired power transmission trigger circuit 144B or serial power transmission trigger circuit 146B. Furthermore, in a hierarchical power transmission system, a power reduction response (e.g., a power reduction in a component or power supply) may be triggered in one component by a trigger signal for another component. For example, a trigger signal from wired power transmission trigger circuit 144B or serial power transmission trigger circuit 146B may trigger a power reduction in voltage regulator 142A.

[0038] In various embodiments, one or more voltage regulators in voltage regulator 142 are coupled to a battery (or other power supply unit) to power SOC 110. In some embodiments, one or more of wired power transfer trigger circuit 144 or serial power transfer trigger circuit 146 are configured to monitor the voltage in the battery. Direct monitoring of the battery voltage can help prevent power loss in SOC 110 due to low battery charge state.

[0039] Return to Figure 1 In various embodiments, global power control circuitry 130 receives one or more trigger signals from PMU 140. When an event associated with the trigger signal is occurring, global power control circuitry 130 can respond by rapidly reducing the clock frequency of component operation to prevent functional failure in SOC 110 or PMU 140. According to this disclosure, an integrated circuit (e.g., SOC 110) may include multiple components (e.g., processor cluster 150, GPU 160, peripheral devices 180) and global power control circuitry 130 coupled to the multiple components (via communication structure 170).

[0040] Figure 4 This is a block diagram of one embodiment of the global power control circuit 130. In the illustrated embodiment, the global power control circuit 130 includes trigger logic circuitry 132 and rate control circuitry 134. The global power control circuit 130 receives one or more trigger signals from the PMU 140. In some embodiments, the trigger signals are asynchronous trigger signals with respect to the clock cycle of the SOC 110. For example, the trigger signals can be received by the global power control circuit 130 at any time during the clock cycle of the SOC 110.

[0041] In various implementations, trigger logic circuitry 132 receives a trigger signal from PMU 140 and determines a power reduction signal based on the received trigger signal. For example, the power reduction signal may be a synchronization signal provided at the clock rate of SOC 110 to one or more components in SOC 110. These one or more components can then implement power reduction or measurement based on the received power reduction signal. In various implementations, trigger logic circuitry 132 includes a combination of enable, hysteresis, and synchronizers to convert an asynchronous trigger signal into a synchronous power reduction signal.

[0042] Examples of techniques implemented by trigger logic circuitry 132 to provide a power reduction signal include clock jitter, clock gating, selective pulse removal, clock division, etc. These techniques can be effective for continuous operation of the SOC 110 without errors because the reduction in clock frequency offsets the effect of slower transistor evaluation at reduced voltages. For example, dividing the clock frequency by 2 (for relatively fast operation) reduces performance by approximately half. In some cases, the performance reduction may be even greater to ensure error-free operation, for example, 75% or more. Therefore, global power control circuitry 130 may be coupled to various components of the SOC 110 (e.g., processor 152 or GPU 160) or to clock resources (e.g., phase-locked loops (PLLs), delay-locked loops (DLLs), clock dividers, clock gating, clock trees, etc.) to achieve frequency reduction that helps ensure error-free (or correct) operation during undervoltage operation.

[0043] While trigger logic 132 provides a relatively fast power reduction response to trigger signals from PMU 140, various implementations of SOC 110 may require even faster response times to reduce clock frequency. For example, in implementations where SOC 110 is a multi-die SOC (e.g., SOC 110 has multiple chips operating as a single chip), a faster response time that allows for clock frequency reduction may be needed to prevent malfunctions, as a large number of parallel transactions could cause PMU 140 to exceed its limits.

[0044] In various implementations, the rate control circuit 134 within the global power control circuit 130 achieves a faster response time to trigger signals received by the global power control circuit. For example, the rate control circuit 134 may include a structure or other logic that controls the clock rate in the SOC 110 based on a received trigger signal. For instance, the rate control circuit 134 may rapidly reduce the frequency of the clock in the communication structure 170 in response to receiving a trigger signal. Figure 4 As shown, the rate control circuit 134 can receive a selected trigger signal from the PMU 140. In some embodiments, the selected power transmission trigger circuit 144 (such as...) Figure 2 and Figure 3 The wiring at the appropriate location between the selected trigger signal (shown) and the rate control circuit provides the selected trigger signal to the rate control circuit 134. For example, the wiring of the rate control circuit 134 can branch off from the wiring between the selected power transmission trigger circuit 144 and the trigger logic circuit 132. Therefore, the rate control circuit 134 can asynchronously receive the selected trigger signal from the selected power transmission circuit 144. In a contemplated embodiment, one or more voltage regulators 142 supplying power from the PMU 140 to the communication structure 170 receive the selected trigger signal.

[0045] In some implementations, the rate control circuit 134 controls the clock rate of the SOC 110 or one or more components of the SOC 110 based on receiving a selected trigger signal. For example, the rate control circuit 134 may reduce the clock rate based on receiving a selected trigger signal. Because the selected trigger signal is received asynchronously (from the clock cycle of the SOC 110), the rate control circuit 134 is able to reduce the clock rate asynchronously and without waiting for another clock cycle before reducing power in the SOC 110. Reducing the clock rate can reduce power consumption in the SOC 110, thereby preventing functional failures in the PMU 140 or the SOC 110. The rate control circuit 134 provides a fast asynchronous response time to reduce the clock rate when the trigger signal is received (e.g., within a few nanoseconds). The response time provided by the rate control circuit 134 is several orders of magnitude faster than the response time of power control using dynamic voltage and frequency control in the components of the SOC 110 (e.g., the time window for the rate control circuit 134 to respond is several orders of magnitude smaller than the time window for the components of the SOC 110 to respond). This fast response time improves protection against functional failures in power management of multi-die SOC systems.

[0046] In some implementation schemes, such as Figure 4 As shown, the rate control circuit 134 receives a power reduction signal from the trigger logic 132. For example, in a contemplated embodiment, the rate control circuit 134 may receive a power reduction signal for the CPU (processor 152) in the SOC 110. As described above, the power reduction signal is synchronized with the clock cycle of the SOC 110. Accordingly, the rate control circuit 134 may implement a slower but synchronized clock rate reduction based on the power reduction signal. However, by providing both the selected trigger signal and the power reduction signal to the rate control circuit 134, redundant power reduction response can be provided in the SOC 110 to prevent functional failures in the PMU 140 or the SOC 110.

[0047] In some implementation schemes, such as Figure 4As shown, trigger logic 132 can receive a power reduction signal from another SOC 110' (e.g., another chip or die) managed by PMU 140. Trigger logic 132 can implement the power reduction signal from SOC 110' to provide a power reduction signal to components within SOC 110. In some implementations, trigger logic 132 can provide a power reduction signal to another SOC 110'' managed by PMU 140. The other SOC 110'' can then implement a power reduction scheme (e.g., using trigger logic circuitry within SOC 110'') to reduce power based on the received power reduction signal. Specific implementations of providing / receiving power reduction signals from other SOCs allow trigger logic 132 and SOC 110 to be part of a multi-die (e.g., multi-chip) power reduction scheme.

[0048] Return to Figure 1 In various implementations, rate limiting can be provided in the SOC via the memory controller 122. For example, the memory controller 122 can monitor the transaction rate in the pipeline associated with the memory controller and slow down transactions as needed. Slowing down transactions can prevent or reduce power consumption in the PMU 140 caused by numerous transactions spanning many sources, such as multiple SOCs in a multi-die configuration.

[0049] Figure 5 This is a block diagram of one embodiment of the memory controller pipeline 500. The depiction of pipeline 500 is a simplified block diagram of one embodiment of the memory controller pipeline. It should be understood that the components of pipeline 500 and the memory controller pipeline can be... Figure 5 Variations may be made outside the scope of the description without departing from the scope of the specification and claims herein. For example, additional components or elements may be included in the memory controller pipeline and / or the location of components or elements may vary.

[0050] The memory controller pipeline 500 may include various control logic and data structures to queue memory requests, arbitrate between requests, and transfer memory requests to the memory cache, and ultimately to the memory 120 in the event of a memory cache miss. Communication interfaces 550A-550B may be part of communication structure 170 and may provide memory requests from other components of the SOC 110 to the memory controller 122. Requests may be received in request buffers 540A and 540C, which track requests as they flow through the memory controller pipeline 500 and accomplish this by returning data (for reading) or updating the memory cache or memory 120 (for writing) on ​​communication interfaces 550A-550B. Response buffers 540B and 540D may be buffers for read data to be transferred back to the requesting component for read transactions, and buffers for other responses (e.g., completion responses for certain write transactions and consistency requests for consistency transactions). Other communication interfaces 550 ( Figure 5 Further request and response buffers (not shown in the diagram) are provided. Request buffers 540A and 540C (and others) can provide input to a memory arbitrator 525, which can arbitrate requests to the memory cache 530. Requests received by the memory cache 530 can be routed through a tag and directory pipeline 520, which may include a tag memory for the memory cache (storing address tags identifying cache blocks cached in the memory cache 530). In one embodiment, the tag and directory pipeline 520 may include a consistency directory that tracks which consistency components in the SOC 110 are caching copies of cache blocks from memory. The consistency directory and associated logic can generate consistency requests that can be routed to components via response buffers 540B and 540D.

[0051] If the request is a cache hit (e.g., an address matching a tag in the tag memory), the tag and directory pipeline 520 request can be placed in the data pipeline queue 560 to access the cache data memory 595. A read arbitrator 565A can arbitrate among read requests in the data pipeline queue 560 to read from the cache data memory 595, while a write arbitrator 565B can arbitrate among write requests in the data pipeline queue 560 to write to the cache data memory 595. Read data from the cache data memory 595 can be provided to the memory output buffer 580. For those write requests that use a write response, the write response can also be placed in the memory output buffer 580.

[0052] If a request is not hit in the memory cache (e.g., the address does not match the tag in the tag memory), the tag and directory pipe 520 can place the request in the memory queue 570 for transfer to the memory 120. The memory queue 570 can be connected to a memory channel controller that accesses the memory 120. Data (for read requests) or optional write completion (for write requests) can later be returned to the memory output buffer 580 by the memory channel controller.

[0053] If data is to be loaded into the memory cache 530, the data / write response from the memory output buffer 580 can be provided to the tag and directory pipe 520, and also to the output arbitrators 590B and 590D, which can arbitrate to output the data / write response to the response buffers 540B and 540D respectively. The data / write response can then be provided to the requesting component via the communication interfaces 550A-550B.

[0054] The memory cache 530 may include multiple segments or planes that process different portions of the memory address space mapped to the memory controller 122. A plane can allow multiple memory requests to be processed in parallel. Figure 5 One plane is shown as a memory cache 530, but other planes can be configured similarly. A memory arbitrator 525 may be present for each plane.

[0055] In various implementations, multiple rate limiters 510 are placed throughout the pipeline 500. For example, the rate limiters 510 may be placed at various arbitration points within the pipeline 500. Figure 5 An example of the location of rate limiter 510 is shown. In the illustrated embodiment, rate limiter 510A is placed at the connection between read arbiter 565A or write arbiter 565B and data pipeline queue 560; rate limiter 510B is placed at the connection between tag and directory pipeline 520 and memory arbiter 525; rate limiter 510C is placed at the connection between output arbiters 590B and 590D and response buffers 540B and 540D; and rate limiter 510D is placed at the connection between response buffers 540B and 540D and communication interfaces 550A and 550B. The number and location (e.g., arbitration points) of rate limiters 510 in pipeline 500 can vary depending on the desired transaction rate control in pipeline 500.

[0056] A rate limiter 510 can be implemented to actively limit peak power levels in pipeline 500 under typically high-activity conditions. In various embodiments, the rate limiter 510 reduces command flow by inserting bubble (e.g., stall) cycles at arbitration points. In some embodiments, the rate limiter 510 is disabled by default but can be configured (e.g., tuned) by the system (e.g., SOC 110 or memory controller 122) to provide a desired power limit over pipeline 500. For example, each rate limiter 510 location may have an associated rate limiter component.

[0057] Figure 6 This is a block diagram of one embodiment of the rate limiter component 600. The rate limiter component 600 can be implemented in any rate limiter 510 described herein. The rate limiter component 600 can provide control over the operation and generation of stall control signals for the rate limiter 510. In the illustrated embodiment, the rate limiter component 600 includes a rate limiter pattern generation circuit 610, a local activity detection circuit 620, and a rate limiter control circuit 630.

[0058] The rate limiter mode generation circuit 610 may include a mode arbiter 612, a mode register 614, and a pointer 616. The rate limiter mode generation circuit 610 can be programmed using a Vmin mode input, a Vnom mode input, or a Vmax mode input. The rate limiter mode output can be determined based on the operating point input (e.g., a memory operating point) provided to the mode arbiter 612. In various embodiments, the rate limiter mode generation circuit 610 determines the rate limiter mode by cycling through the mode register 614 according to the input from the mode arbiter 612. For example, a different mode can be generated for a higher performance (higher power) operating point with more stall cycles compared to a lower performance (lower power) operating point.

[0059] In some implementations, a local activity detection circuit 620 is implemented to track local memory activity. The local activity detection circuit 620 includes: a shift register 622 that receives a history depth input and an activity indication input; an activity counter 624 that receives the activity indication input; and an activity threshold comparator 626 that compares the activity count with an activity threshold. For example, the activity indication may include local activity indications such as arbitrator verification, valid pass (e.g., tag pipeline valid pass), read enable control, write enable control, completion buffer write arbitrator grant, completion buffer bypass, and downstream interface arbitrator grant.

[0060] Shift register 622 can be a configurable register for tracking activity history. For example, the history depth can be programmed into the shift register to track history in a set number of cycles (e.g., 32 cycles, 16 cycles, or 8 cycles) before comparison with an activity threshold. Activity counter 624 can count activities during the set number of cycles programmed into shift register 622. At this time, the activity level is compared with the activity threshold in activity threshold comparator 626 to generate a raw stall signal output if the activity exceeds a predetermined activity threshold.

[0061] The initial stall signal is provided to the rate limiter control circuit 630, which can selectively block or transmit the initial stall signal according to a programmed rate limiter mode, etc. The enable arbitrator 632 is programmable with a rate limiter mode and determines the mode implemented by the rate limiter control circuit 630. One mode can be "static on," where the initial stall signal is transmitted and a stall signal is output from the rate limiter component 600, wherein the rate limiter mode is determined by the rate limiter mode generation circuit 610. Another mode can be "static off," where the initial stall signal is blocked and no rate limiting occurs. For example, the off mode can be used if the power at a given memory operating point is known to be low enough that it will not cause a drop in PMU voltage.

[0062] Additional implementations may be envisioned to have power management circuitry (PMGR) included in any of the systems described herein. Figure 7 This is a block diagram of one embodiment of a system-on-a-chip (SOC) 110, which includes memory 120 and a power management unit (PMU) 140. The PMU 140 can be configured to power the SOC 110 and other components that may be included in the system, such as memory 120. For example, the PMU 140 can be configured to generate one or more supply voltages to power the SOC 110, and can be further configured to generate power for other components of the system (…). Figure 7 The supply voltage (not shown). In addition, PMU 140 (or accompanying circuitry coupled to PMU 140) can be configured to monitor the supply voltage and detect transient undervoltage conditions or other overload conditions that could lead to malfunctions in SOC 110. When such a condition occurs (typically because the electrical load of SOC 110 exceeds the capacity of PMU 140), PMU 140 can assert a trigger input to SOC 110. In the illustrated embodiment, global power control circuitry 130 included in SOC 110 can receive the trigger input. While an SOC implementation is used herein as an example, in other implementations, a system comprising multiple integrated circuits coupled to a communication structure may be used.

[0063] As its name suggests, the components of SOC 110 can be integrated onto a single semiconductor substrate as an integrated circuit "chip". In the illustrated embodiment, the components of SOC 110 include at least one processor cluster 150, at least one graphics processing unit (GPU) 160, one or more peripheral components (e.g., peripheral component 180 (more simply, "peripheral device")), memory controller 122, power management circuitry (PMGR) 700, global power control circuitry 130, and communication structure 170. Components 150, 160, 180, 122, and 700 may all be coupled to communication structure 170. Memory controller 122 may be coupled to memory 120 during use. In some embodiments, there may be more than one memory controller coupled to a corresponding memory. In such embodiments, the memory address space may be mapped across memory controllers in any desired manner. In the illustrated embodiment, processor cluster 150 may include multiple processors (P) 152. Processors 152 may form the central processing unit (CPU) of SOC 110. Processor cluster 150 may further include one or more coprocessors (e.g., Figure 7 The coprocessor 154 in the processor 152 may be optimized for a subset of the processor's instruction set and may be used by the processor 152 to execute instructions from that subset. For example, the coprocessor 154 may be a matrix engine optimized to perform vector and matrix operations.

[0064] The PMGR 700 can be configured to manage power consumption in the SOC 110. For example... Figure 7 As shown, the PMGR 700 may include a telemetry table 702, a power management processor (PMP) 704, and power budget control code 710 that may be stored in memory within the PMGR 700 (e.g., local memory such as local static random access memory (SRAM) or read-only memory) and / or memory 120. For example, the power budget control code 710 may be stored in read-only memory or other forms of non-volatile memory and may be loaded into the PMGR 700 / memory 120 during system initialization. The telemetry table 702 may be any type of memory (e.g., static random access memory (SRAM), registers, etc.). Various components of the SOC 110 may report activity levels, performance information, power consumption data, etc., to the PMGR 700 in a somewhat regular "push" model, and thus be available for analysis within the PMGR 700 without requiring the PMGR 700 to poll various components to collect information. More specifically, in this implementation, in addition to power budget control code 710, PMP 704 can also be configured to execute code to analyze data in the telemetry table.

[0065] As previously mentioned, PMU 140 can be configured to assert a trigger signal when an undervoltage event is detected. When such an event occurs, SOC 110 (and more specifically, global power control circuitry 130) can respond by rapidly reducing the clock frequency of component operation by using techniques such as clock jitter, clock gating, selective pulse removal, clock division, and control within various components to reduce processing performance and thus power. While these techniques may be effective for continuous operation without errors (because the reduction in clock frequency offsets the effect of slower transistor evaluation at lower voltages), the performance degradation can be significant. For example, dividing the clock frequency by 2 (for relatively fast operation) reduces performance by approximately ½. In some cases, to ensure error-free operation, the performance degradation may be even greater, for example, 75% or more. Therefore, global power control circuitry 130 can be coupled to various components of SOC 110 ( Figure 7 (Not explicitly described) or clock resources (e.g., phase-locked loops (PLLs), delay-locked loops (DLLs), clock dividers, clock gates, clock trees, etc.) that may be at least coupled to various components to achieve frequency reduction that helps ensure error-free (or correct) operation during undervoltage operation. In one embodiment, global power control circuitry 130 may be configured to record the frequency (e.g., how often) of assertion trigger inputs to global power control circuitry 130 in telemetry table 702 (or the frequency at which global power control circuitry 130 participates, depending on the frequency of trigger input assertions), such as via Figure 7 As shown by the dashed arrow in the image.

[0066] In many cases, a minor performance degradation will be sufficient to reduce the load, resulting in less frequent undervoltage events. For example, if an undervoltage event occurs due to a slight overload of PMU 140, the load reduction required to prevent the event is relatively small and can be achieved by temporarily reducing the power consumption of one or more controllable components in the system, resulting in a slight performance degradation, but still within the capacity of PMU 140. PMP 704 and power budget control code 710 can be used to attempt to reduce the frequency of undervoltage events, or more specifically, to reduce the frequency at which the global power control circuitry is invoked to provide undervoltage control. For example, in one implementation, power budget control code 710 can analyze telemetry data and determine the frequency of undervoltage events or the amount of time that global power control circuitry 130 participates in reducing power consumption during a given time window. Power budget control code 710 can modify the power budget for one or more components in the next time window to attempt to reduce the occurrence of undervoltage events. For example, the power budget can be reduced, and therefore the components can consume less power in the next time window, thereby reducing the total load current on PMU 140. While the performance achievable by the component may be reduced in the next time window, the reduction in undervoltage events and the severe performance loss due to undervoltage events can be minimized, resulting in higher overall performance. For example, power budget control code 710 may attempt to reduce undervoltage triggering to a specified percentage (e.g., 1% of a given time window). Additional details will be provided further below.

[0067] At least some of the components can be configured to control power consumption based on a power budget. For example, one or more peripherals among processor cluster 150, GPU 160, and peripheral devices 180 may include power control circuitry (PwrCtl) 720A-720C, which includes corresponding power budgets 722A-722C. Power control circuitry 720A-720C can monitor the operation of the corresponding components and measure / estimate power consumption. Power control circuitry 720A-720C can compare the measured / estimated power consumption with the power budget. If the budget is exhausted or falls below a threshold, power control circuitry 720A-720C can invoke various power mitigation mechanisms. For example, power control circuitry 720A may employ mitigation mechanisms such as disabling one or more processors in processor 152 and / or disabling one or more pipelines in processor 152. Instruction release rates may be reduced, or bubbles may be inserted into the pipeline so that the corresponding circuitry does not actively evaluate each cycle. Any set of one or more mitigation mechanisms may be used. Similarly, the GPU 160 can reduce the number of active pipelines, limit the instruction release rate, and / or implement any other mitigation mechanisms. Mitigation mechanisms can be specific to a given controlled component, and different components can employ different mechanisms or a combination of similar and specific mechanisms as needed. The PMP 704 / Power Budget Control Code 710 can be independent of a specific mechanism; the details of setting the budget 722A-722C and adhering to the budget 722A-722C are implemented by the power control circuitry 720A-720C.

[0068] If power budget control code 710 reduces the power budget 722A-722C in one or more power control circuits 720A-720C, and the frequency of undervoltage events remains higher than the expected frequency in the next time window, then power budget 710 can be a further power budget in the next time window. Any algorithm for reduction can be used. For example, each budget can be reduced by a certain amount to achieve a reduction, thus distributing the performance reduction relatively evenly across the controllable components. In another algorithm, different budgets 722A-722C can be reduced in different time windows, rotating the reduction between different subsets of one or more components, and then the reduced power budget is returned to its original value in subsequent time windows.

[0069] It should be noted that while some example implementations are described as power budget control being implemented as code 710 executable by PMP 704, other implementations may implement all or part of the power budget control in hardware, for example, as a state machine and / or combinational logic.

[0070] The PMGR 700 can be configured to control the supply voltage magnitude requested by the external PMU 140. Multiple supply voltages may be generated by the PMU 140 for the SOC 110. For example, a supply voltage may be available for the processor cluster 150, and at least one supply voltage may be available for the remainder of the SOC 110 other than the processor cluster 150. In one embodiment, the same supply voltage may be used for components of the SOC 110 other than the processor cluster 150, and power gating may be used to control one or more independent power domains powered by the supply voltage. In some embodiments, multiple supply voltages may also be available for the remainder of the SOC 110. In some embodiments, memory supply voltages may also be available for the processor cluster 150 and / or the various memory arrays in the SOC 110. The memory supply voltage may be used in conjunction with the voltage supplied to the logic circuitry, and may have a lower voltage magnitude than that required to ensure robust memory operation. The PMGR 700 can be under direct software control (e.g., the software can directly request the power-on and / or power-off of components) and / or can be configured to monitor the SOC 110 and determine when to power on or off individual components. Various power states within components (e.g., the power state of processor 152) and the sequence of power state changes, different requested voltages and frequencies, etc., can be controlled via the PMGR 700.

[0071] As described above, processor cluster 150 may include one or more processors 152 that can be used as CPUs in SOC 110. The system's CPU includes one or more processors that execute the system's main control software, such as an operating system. Typically, software executed by the CPU during use controls other components of the system to achieve the desired functionality of the system. The processor may also execute other software such as application programs. Application programs provide user functionality and may rely on the operating system for lower-level device control, scheduling, memory management, etc. Therefore, the processor may also be referred to as an application processor.

[0072] Typically, a processor may include any circuit system and / or microcode configured to execute instructions defined in the instruction set architecture implemented by the processor. A processor may encompass a processor core implemented on an integrated circuit having other components as a system-on-a-chip (SoC) or other level of integration. A processor may also include discrete microprocessors, processor cores and / or microprocessors integrated into a multi-chip module implementation, processors implemented as multiple integrated circuits, and so on.

[0073] The memory controller 122 may typically include circuitry for receiving memory operations from other components of the SOC 110 and for accessing the memory 120 to complete the memory operations. The memory controller 122 may be configured to access any type of memory 120. For example, the memory 120 may be static random access memory (SRAM), dynamic RAM (DRAM) such as synchronous DRAM (SDRAM) including double data rate (DDR, DDR2, DDR3, DDR4, etc.) DRAM. Low-power / mobile versions of DDR DRAM (e.g., LPDDR, mDDR, etc.) may be supported. The memory controller 122 may include a memory operation queue for ordering (and potentially reordering) these operations and presenting them to the memory 120. The memory controller 122 may also include data buffers for storing write data awaiting to be written to memory and read data awaiting return to the source of the memory operation. In some embodiments, the memory controller 122 may include a memory cache for storing recently accessed memory data. For example, in a specific SOC implementation, a memory cache can reduce power consumption in the SOC by preventing data from being re-accessed from the memory 120 if it is expected to be accessed again soon. In some cases, the memory cache may also be referred to as the system cache, which differs from proprietary caches such as the L2 cache or the cache within the processor, which serve only certain components. Furthermore, in some implementations, the system cache does not need to reside within the memory controller 122.

[0074] Peripheral device 180 can be any set of additional hardware functions included in SOC 110. For example, peripheral device 180 may include video peripherals such as image signal processors, video encoders / decoders, expanders, rotators, mixers, display controllers, etc., configured to process image capture data from cameras or other image sensors. Peripheral devices may include audio peripherals such as microphones, speakers, interfaces to microphones and speakers, audio processors, digital signal processors, mixers, etc. Peripheral devices may include interface controllers for various interfaces external to SOC 110, including interfaces such as Universal Serial Bus (USB), Peripheral Component Interconnect (PCI) including PCI Express (PCIe), serial and parallel ports, etc. Interconnection to external devices is provided by... Figure 7 The dashed arrow extending outwards from the SOC 110 is shown. Peripheral devices may include networked peripherals such as a Media Access Controller (MAC). Any set of hardware may be included.

[0075] Communication architecture 170 can be any communication interconnect and protocol used for communication between components of SOC 110. Communication architecture 170 can be bus-based, including shared bus configurations, crossbar configurations, and hierarchical buses with bridges. Communication architecture 170 can also be packet-based and can be hierarchical, crossbar, point-to-point, or other interconnects with bridges.

[0076] Note the number of components in the SOC 110 (and) Figure 7 The number of sub-components (such as processors 152 in each processor cluster 150) of the components shown may vary depending on the implementation. Furthermore, when multiple processor clusters are included, the number of processors 152 in one processor cluster 150 may differ from the number of processors 152 in another processor cluster 150. The number of each component / sub-component may be more or less than [the number shown in the original text]. Figure 7 The quantity shown.

[0077] According to this disclosure, an integrated circuit (e.g., SOC 110) may include multiple components, a global power control circuit coupled to the multiple components, and a power management circuit. A given component among the multiple components is configured to manage power consumption based on a budget amount allocated to the given component. The global power control circuit is configured to apply power control across the multiple components in response to a trigger input to the integrated circuit. The power management circuit is configured to: detect whether the power control applied by the global power control circuit exceeds a threshold; and based on the detection that the power control applied by the global power control circuit exceeds the threshold, reduce the budget amount allocated to at least one of the multiple components. For example, the threshold may include the percentage of time during which power control is applied by the global power control circuit.

[0078] The power management circuit can be configured to measure the percentage of time within a fixed time window. For example, the power management circuit can be configured to detect the percentage during a first instance of the fixed time window and can be configured to reduce the budget amount for the next instance of the fixed time window, wherein the next instance is consecutive to the first instance. For example, the power management circuit can be configured to reduce the budget amount for a first component of a plurality of components in a given fixed time window and reduce the budget amount for a second component of a plurality of components in another given fixed time window.

[0079] Figure 8 This is a block diagram illustrating various power management mechanisms in one implementation of the SOC 110. These mechanisms... Figure 8The speed at which these mechanisms respond to managed power demands is arranged from left to right. On the left is the global power management mechanism (reference numeral 800), which operates based on a trigger input to rapidly reduce the clock frequency. The primary focus of the global power management mechanism is ensuring correctness in the event of an undervoltage event. As mentioned above, since the extent of an undervoltage event is unknown, this mechanism can be quite coarse-grained; therefore, the control can be designed to ensure correctness in the worst-case scenario.

[0080] The second fastest mechanism could be a PMP / power budget control mechanism (see figure 802). While the PMP mechanism may be slower than the global mechanism, it can offer more granular, finer-grained control. The PMP mechanism can attempt to improve efficiency and performance by taking actions that limit the involvement of the global power management mechanism. For example, as mentioned above, the PMP mechanism could include modifying the power budgets of various components that implement budget-based power management. In another embodiment, the PMP mechanism could include temporary modifications to the clock frequency and / or supply voltage to one or more components.

[0081] In addition, a third power management mechanism can be employed, which is CPU-based power control (reference numeral 804). The CPU-based power control mechanism can be implemented using software executed by processor 152, and therefore can share execution time with the operating system and various applications. The CPU-based power control mechanism can examine numerous metrics, including telemetry data in telemetry table 702, as well as various measurements of system performance. The CPU-based power control mechanism can employ dynamic voltage and frequency control, reducing voltage and frequency settings (e.g., "power state") in PMGR 700 as a mechanism to mitigate power control participation in the global power control circuit 130 and the PMP power control mechanism, and returning the power state to its original settings as needed to enhance performance. The CPU-based power control mechanism can reduce the power state, for example, if global and PMP-based mitigation will be reduced to a level where a lower power state will result in higher overall performance / efficiency, even if the system runs slower. Typically, the CPU-based mechanism can employ system-wide analysis and power management.

[0082] Global mechanisms can have timescales ranging from tens to hundreds of nanoseconds; PMP mechanisms can have time windows of approximately hundreds of microseconds; and CPU-based mechanisms can have timescales of hundreds of milliseconds. That is, PMP mechanisms can operate using time windows one or more decimal orders longer than the timescale of global mechanisms, and CPU-based mechanisms can have time windows one or more decimal orders longer than the timescale of PMP mechanisms. In one implementation, the time window of the CPU-based mechanism can be an integer multiple of the time window of the PMP mechanism.

[0083] Figure 9 An implementation scheme of a power control window using PMP-based power budget control (reference numerals 900A-900N) and a CPU power control window 902 is shown. Figure 9 In this context, time increases in arbitrary units from right to left. As previously described, a PMP-based mechanism can measure undervoltage events and / or global power control activity in a given PMP window (e.g., window 900A) and modify the power budget of one or more components in the next subsequent or immediately adjacent window (e.g., window 900B).

[0084] Figure 10 This is a flowchart illustrating the operation of one embodiment of the PMP-based power budget control 710. However, for ease of understanding, the block diagram is shown in a specific order, but other orders may be used. The blocks can be executed in parallel with combinational logic in a hardware-based embodiment. Instructions executed by the PMP 704 for a software-based embodiment can cause the PMP 704 to perform specified operations. For example, Figure 10 The operations in can be performed Figure 9 Execute at or near the end of the given PMP time window 900A-900N.

[0085] Power budget control reads global telemetry data from telemetry table 702 (box 1000). Based on this telemetry data, power budget control 710 can determine whether the occurrence of undervoltage events / triggers in a previous time window 900A-900N exceeds a desired threshold. For example, the threshold can be measured based on the number of events, the percentage of time the global power control circuit 130 participates in mitigation mechanisms, etc. The threshold can be fixed or programmable as needed.

[0086] If the occurrence of an event exceeds a desired threshold (Decision Box 1002, "Yes" branch), power budget control 710 may reduce the power budget of one or more components in the current window (Box 1004). If the occurrence of an event does not exceed the desired threshold (Decision Box 1002, "No" branch), power budget control 710 may increase the power budget in the current window (Box 1006). Increases and / or decreases may be subject to a certain hysteresis. For example, if the recent change is an increase in the power budget, a decrease in the power budget may be delayed until the decrease is indicated on two or more consecutive PMP time windows. Similarly, if the recent change is a decrease in the power budget, an increase may be delayed until the increase is indicated on two or more consecutive PMP time windows.

[0087] It's important to note that reducing and increasing the power budget can be done with different weights or magnitudes. For example, a decrease from one window to another can be greater than an increase from the same window to the next. Therefore, if frequent undervoltage events are observed, the power budget will be reduced more rapidly in an attempt to quickly reduce the coarser, correctness-based control to a lower rate. Once a lower rate is achieved, gradually increasing the power budget can allow the system to reach a stable state.

[0088] Therefore, in one embodiment, at least one component of the integrated circuit may include one or more central processing units (CPUs). The CPU may be configured to execute multiple instructions to implement power control in the integrated circuit using dynamic voltage and frequency control. The multiple instructions may implement power control over a second fixed time window, which is larger than a fixed time window used by the power management circuitry. For example, the second fixed time window may be one or more decimal orders longer than the fixed time window. In one embodiment, the second fixed time window may be an integer multiple of the fixed time window. The power management circuitry may be configured to: detect that the power control applied by the global power control circuitry is less than a threshold; and based on the detection that the power control applied by the global power control circuitry exceeds the threshold, increase the budget amount allocated to at least one of the multiple components. The increase in the budget amount may be limited to a maximum amount for at least one of the multiple components. The power management circuitry may be configured to apply hysteresis when varying between an increase and a decrease in the budget amount. As previously described, in one embodiment, the power management circuitry may include a power management processor and a memory coupled to the power management processor, the memory storing multiple instructions that, when executed by the power management processor, cause the power management processor to perform operations, including the operations described above for the power management circuitry.

[0089] Example Method Figure 11 This is a flowchart illustrating a method for reducing power in an integrated circuit according to some embodiments. Method 1100 can be implemented using any embodiment of the SOC disclosed herein, in conjunction with any circuitry or other mechanisms in the integrated circuit.

[0090] In 1102, in the illustrated embodiment, the integrated circuit receives multiple supply voltages from multiple voltage regulators, wherein the integrated circuit includes: multiple components that generate memory transactions to access memory; multiple memory controller circuits that control the memory; and a communication structure that includes multiple circuits that interconnect the multiple components and the multiple memory controller circuits.

[0091] In 1104, in the illustrated embodiment, multiple power transmission trigger circuits coupled to the integrated circuit and multiple voltage regulators generate multiple trigger signals based on the electrical load experienced by the multiple voltage regulators.

[0092] In 1106, in the illustrated embodiment, a trigger logic circuit coupled to a plurality of power transmission trigger circuits generates a power reduction signal based on a plurality of trigger signals received from the plurality of power transmission trigger circuits.

[0093] In 1108, in the illustrated embodiment, a rate control circuit coupled to at least one of the power transmission trigger circuits controls the clock rate of the multiple circuits in the communication structure, wherein the clock rate is reduced based on at least one of the multiple trigger signals from the at least one power transmission trigger circuit.

[0094] In 1110, in the illustrated embodiment, a given memory controller circuit among a plurality of memory controller circuits controls the rate at which memory transactions flow through multiple locations based on multiple rate limiter circuits at multiple locations in the pipeline within the given memory controller circuit.

[0095] Figure 12 This is a flowchart illustrating another method for power reduction in an integrated circuit according to some embodiments. Method 1200 can be implemented using any embodiment of the SOC disclosed herein, in conjunction with any circuitry or other mechanisms in the integrated circuit.

[0096] In 1202, in the illustrated embodiment, the integrated circuit receives multiple supply voltages from multiple voltage regulators, wherein multiple power transmission trigger circuits are coupled to the integrated circuit and the multiple voltage regulators.

[0097] In 1204, in the illustrated embodiment, when the electrical load experienced by the plurality of voltage regulators meets a first threshold, a trigger signal is generated by a first set of power transmission trigger circuits coupled to the integrated circuit via wiring.

[0098] In 1206, in the illustrated embodiment, when the electrical load experienced by the multiple voltage regulators meets the second threshold, a second set of power transmission trigger circuits coupled to the integrated circuit through multiple serial communication interfaces generates a trigger signal, wherein the first threshold is closer to the functional failure point of the integrated circuit than the second threshold.

[0099] Example power transmission system : Turn now Figure 13The figure illustrates a block diagram of a system with a power delivery system and computing elements. In the illustrated embodiment, system 1300 includes a hierarchical power delivery system 1310 and computing elements 1320. The hierarchical power delivery system 1310 includes a first power converter stage 1312 coupled to receive an input voltage V_in from an external source (e.g., a battery). The first power converter stage 1312 includes one or more power converters configured to generate one or more first-level regulated supply voltages. These first-level regulated supply voltages are received by one or more power converters in a second power converter stage 1314. The power converters in the power converter stage 1314 use one or more first-level regulated supply voltages to generate one or more second-level regulated supply voltages. These voltages are supplied to various loads of the computing elements 1320.

[0100] In the illustrated embodiment, computing element 1320 includes one or more integrated circuits (ICs or SOCs) 1322, typically shown herein as ICs 1322-1 to ICs 1322-N. Computing element 1320 is configurable and scalable, wherein the number of ICs varies depending on the specific implementation. For example, in a first embodiment, computing element 1320 may include a single IC die, while in a second embodiment, computing element 1320 may include two or more IC dies. Implementations that enable only a portion of the IC dies are also possible and contemplated.

[0101] While computing element 1320 is therefore scalable, the number of ICs in a particular implementation is transparent to the software executing on it. Thus, regardless of the number of ICs in a given implementation, the software executing on it can treat computing element 1320 as a single entity. Therefore, computing element 1320 in the illustrated embodiment can implement a computing architecture that can be scaled up or down as needed and is capable of executing software on various implementations regardless of such scaling.

[0102] Each of the ICs 1322-1 to 1322-N in the illustrated embodiments may include multiple different types of circuitry. For example, ICs 1322-1 to 1322-N may include various types of processor cores, graphics processing units (GPUs), neural network processors, memory controllers, input / output (I / O) circuitry, network switches for implementing various networks thereon, etc. When two or more instances of ICs 1322-1 to 1322-N are implemented to form a computing element, the various functional circuitry thereon can form a larger complex than the functional circuitry of a specific implementation using a single IC or a portion thereof. For example, ICs 1322-1 and 1322-N may both include a complex of processor cores, and thus, in a specific implementation of a computing element 1320 having two or more ICs, a larger processor core complex spanning multiple ICs is implemented. The processor core of one IC can communicate with the processor core of another IC via one or more die-to-die interfaces between the individual ICs.

[0103] Considering the varying power requirements of different types of circuits implemented on the examples of IC 1322-1 to IC 1322-N, multiple power converters can exist to generate corresponding voltages to meet the efficiency requirements of these loads. For example, the processor core may have different power requirements than the I / O circuits. Therefore, the power converter hierarchy 1314 may include one or more power converters suitable for providing a first and second level supply voltage to the processor core, and one or more power converters providing different second level supply voltages to the I / O circuits.

[0104] The hierarchical power delivery system 1310 in the illustrated embodiment is also scalable, reflecting the scalability of the computing element 1320. In various embodiments, the power converter hierarchy of the hierarchical power delivery system 1310 may include multiple power converters (e.g., switching voltage regulators, etc.) to meet the power requirements of the various loads discussed above. The number of power converters enabled for a particular embodiment can therefore correspond to the number of ICs 1322-1 to 1322-N in a particular embodiment of the computing element 1320. More generally, power converter hierarchies 1312 and 1314 can be arranged to increase power supply capacity as more computing power is implemented in the computing element 1320. In this way, the design of the hierarchical power delivery system 1310 can be reused in a variety of different embodiments of the computing element 1320. Reusing the design of the hierarchical power delivery system 1310 within the scalability of the computing element 1320 further eliminates the need to provide customized power delivery solutions for various different embodiments. This, in turn, can significantly simplify the design of various systems based on different specific implementations of computing element 1320, and reduce the amount of time required to implement any particular specific implementation of such a system.

[0105] Computer-readable media and manufacturing systems : Figure 14 This is a block diagram of one embodiment of a manufacturing system 1400. The system includes a non-transitory computer-readable medium 1420 on which instructions / descriptions 1450 of a power transmission system according to any embodiment within the scope of this disclosure are stored. The computer-readable medium 1420 can be one of a variety of different types of non-transitory media capable of providing persistent storage of information, including disk storage, solid-state drives (e.g., using flash memory), optical storage (e.g., CD-ROM), various types of random access memory (RAM), etc.

[0106] Computer system 1440 is configured to read circuit instructions / descriptions 1450 from computer-readable medium 1420. Furthermore, computer system 1440 can execute various instructions and use the circuit description to cause manufacturing system 1445 to manufacture one or more instances of the circuit represented by the circuit instructions / descriptions 1450. Manufacturing system 1445 can be any type of automated system capable of manufacturing electronic circuits.

[0107] Example System : Next, turn to Figure 15This diagram illustrates a block diagram of one embodiment of system 1500, which may utilize the methods and mechanisms described herein in combination with and / or otherwise. In the illustrated embodiment, system 1500 includes at least one instance of a system-on-a-chip (SoC) 1506, which may include various types of processing units such as a central processing unit (CPU), a graphics processing unit (GPU), or other communication architectures, as well as interfaces to memory and input / output devices. In some embodiments, one or more processors in SoC 1506 include multiple execution lanes and instruction dispatch queues. In various embodiments, SoC 1506 is coupled to external memory 1502, peripheral devices 1504, and power supply 1508.

[0108] A power supply 1508 is also provided, which supplies power voltage to the SoC 1506 and one or more power voltages to the memory 1502 and / or peripheral devices 1504. In various embodiments, the power supply 1508 represents a battery (e.g., a rechargeable battery in a smartphone, laptop, tablet, or other device). In some embodiments, more than one instance of the SoC 1506 is included (and more than one external memory 1502 is also included).

[0109] Memory 1502 can be any type of memory, such as Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Dual Data Rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM, such as mDDR3, and / or low-power versions of SDRAM, such as LPDDR2), RAMBUS DRAM (RDRAM), Static RAM (SRAM), etc. One or more memory devices are coupled onto a circuit board to form a memory module, such as a Single In-line Memory Module (SIMM), a Dual In-line Memory Module (DIMM), etc. Alternatively, the device can be mounted with a SoC or integrated circuit in a chip-on-chip, package-on-package, or multi-chip module configuration.

[0110] Depending on the type of system 1500, peripheral device 1504 may include any desired circuitry. For example, in one embodiment, peripheral device 1504 may include devices for various types of wireless communication, such as Wi-Fi, Bluetooth, cellular, GPS, etc. In some embodiments, peripheral device 1504 may also include additional memory, including RAM, solid-state memory, or disk storage. Peripheral device 1504 may include user interface devices such as displays, including touch displays or multi-touch displays, keyboards or other input devices, microphones, speakers, etc.

[0111] As shown in the figure, the illustrated system 1500 has applications in a wide range of fields. For example, system 1500 can be used as part of a chip, circuit, component, etc., in a desktop computer 1510, laptop computer 1520, tablet computer 1530, cellular or mobile phone 1540, or television 1550 (or a set-top box coupled to a television). A smartwatch and health monitoring device 1560 are also shown. In some embodiments, the smartwatch 1560 may include various general computing-related functions. For example, the smartwatch may provide access to email, mobile phone services, user calendars, etc. In various embodiments, the health monitoring device may be a dedicated medical device or otherwise include dedicated health-related functions. For example, the health monitoring device may monitor a user's vital signs, track the user's proximity to other users for epidemiological social distancing purposes, contact tracing, provide communication to emergency services in the event of a health crisis, etc. In various embodiments, the aforementioned smartwatch may or may not include some or any health monitoring-related functions. Other wearable devices are also envisioned, such as devices worn around the neck, implantable devices, glasses designed to provide augmented and / or virtual reality experiences, etc.

[0112] System 1500 can also be used as part of cloud-based service 1570. For example, the previously mentioned devices and / or other devices can access computing resources in the cloud (i.e., remotely located hardware and / or software resources). Furthermore, system 1500 can be used in one or more devices in the home in addition to those previously mentioned. For example, home appliances can monitor and detect noteworthy situations. For example, various devices in the home (e.g., refrigerators, cooling systems, etc.) can monitor the status of the devices and provide alerts to the homeowner (or, for example, a repair service) upon detecting a specific event. Alternatively, a thermostat can monitor the temperature in the home and can automatically adjust the heating / cooling system based on the homeowner's history of responses to various situations. Figure 15 The document also illustrates the application of System 1500 to various modes of transportation. For example, System 1500 can be used as a control and / or entertainment system for airplanes, trains, buses, taxis, private cars, watercraft ranging from private boats to cruise ships, and small motorcycles (for rental or private use). In various cases, System 1500 can be used to provide automated guidance (e.g., self-driving vehicles), general system control, etc. Many of these other implementations are possible and contemplated. It should be noted that... Figure 15 The devices and applications shown are merely illustrative and not intended to be limiting. Other devices are possible and envisioned.

[0113] This disclosure also envisions in Figure 15A general scalable computing architecture is used among some or all of the various devices shown. Therefore, computing elements can be scaled according to the needs of the specific system in which the computing elements are implemented. For example, a smartwatch / health monitoring device 1560 may use a first implementation of the computing elements of a scalable architecture, while a tablet computer 1530 uses a second implementation, and a desktop computer 1510 uses a third implementation. In this particular example, the implementation of the computing elements in tablet computer 1530 can be scaled relative to smartwatch / health monitoring device 1560. Similarly, the implementation of the computing elements in desktop computer 1510 can be scaled relative to the implementation of tablet computer 1530. Thus, each of these devices can utilize a general computing architecture implemented on a scale according to the needs of its respective system. In conjunction with the scalable architecture, the power transmission system according to this disclosure can be configured in each of these applications and can be scaled accordingly with the computing elements. Therefore, while each example discussed herein can utilize a power delivery system with a general design, the specific implementation of the desktop computer 1510 has a greater power delivery capability than the specific implementation of the tablet computer 1530, and the tablet computer implementation has a greater power delivery capability than the specific implementation of the smartwatch / health monitoring device 1560. However, the general design of the power delivery system used between these different devices can significantly simplify its implementation, as the power delivery system can be configured for a specific application by enabling / disabling the appropriate power converters in its power converters.

[0114] This disclosure includes references to “implementation” or groups of “implementation” (e.g., “some implementations” or “various implementations”). An implementation is a different specific implementation or instance of the disclosed concepts. References to “implementation,” “an implementation,” “a particular implementation,” etc., do not necessarily refer to the same implementation. A large number of possible implementations are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the substance or scope of this disclosure.

[0115] This disclosure may discuss potential advantages that may arise from the disclosed embodiments. Not all specific implementations of all these embodiments will necessarily exhibit any or all of the potential advantages. Whether a particular embodiment achieves an advantage depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an embodiment falling within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular embodiment may include other circuitry outside the scope of this disclosure, in conjunction with an embodiment of the disclosed embodiments, which negates or diminishes one or more of the disclosed advantages. Furthermore, suboptimal design execution of a particular embodiment (e.g., the implementing technique or tool) may also negate or diminish the disclosed advantages. Even assuming an implementation of the technique, the realization of advantages may still depend on other factors, such as the environmental circumstances in which the implementation is deployed. For example, the inputs provided to a particular embodiment may prevent one or more problems addressed in this disclosure from occurring in a particular context, and as a result, the benefits of its solution may not be realized. Given the existence of possible factors outside this disclosure, any potential advantages described herein should not be construed as a claim limitation that must be satisfied in order to prove infringement. Rather, the identification of such potential advantages is intended to show one or more types of improvements available to a designer who benefits from this disclosure. Describing such advantages permanently (e.g., stating that a particular advantage "may occur") is not intended to convey a question about whether such advantages can actually be realized, but rather to recognize that the realization of such advantages often depends on the technological reality of additional factors.

[0116] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on this disclosure, even where only a single example is described with respect to a particular feature. The embodiments disclosed in this invention are intended to be illustrative and not restrictive, without any statement to the contrary in this disclosure. Therefore, this application is intended to allow for the coverage of the claims of the disclosed embodiments, as well as such alternatives, modifications, and equivalents, which will be apparent to those skilled in the art who are aware of the effective effects of this disclosure.

[0117] For example, features in this application can be combined in any suitable manner. Therefore, new claims may be made for any such combination of features during the proceedings of this patent application (or a patent application claiming priority thereto). Specifically, referring to the appended claims, features of dependent claims may be combined with features of other dependent claims, including claims dependent on other independent claims, where appropriate. Similarly, features from the respective independent claims may be combined where appropriate.

[0118] Thus, although the appended dependent claims may be drafted such that each dependent claim depends from a single other claim, additional dependencies are contemplated. Any combination of dependent claims consistent with this disclosure is contemplated, and such combinations may be claimed in this patent application or in another patent application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0119] In appropriate cases, it is also contemplated that claims drafted in one format or statutory type (e.g., apparatus) are intended to support corresponding claims in another format or statutory type (e.g., method).

[0120] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. It is hereby announced that the following paragraphs, as well as the definitions provided throughout this disclosure, will be used to determine how claims drafted based on this disclosure are to be interpreted.

[0121] References to items in the singular form (i.e., a noun or noun phrase preceded by "a," "an," or "the") are intended to mean "one or more" unless the context clearly dictates otherwise. Thus, without accompanying context, a reference to an "item" in a claim does not exclude additional instances of that item. A "plurality" of items means a collection of two or more items.

[0122] The word "may" is used herein in an allowable sense (i.e., having the potential to, being able to), rather than in a mandatory sense (i.e., must).

[0123] The terms "comprising" and "including" and their forms are open-ended and mean "including but not limited to."

[0124] When the term "or" is used in this disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context provides otherwise. Thus, the statement "x or y" is equivalent to "x or y, or both," and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either x or y, but not both" make it clear that "or" is used in an exclusive sense.

[0125] The expressions “w, x, y, or z, or any combination thereof” or “...at least one of w, x, y, and z” are intended to cover all possibilities involving a single element up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase “...at least one of w, x, y, and z” therefore refers to at least one element in the set [w, x, y, z], thus covering all possible combinations of that list of elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0126] In this disclosure, various “labels” may precede nouns or noun phrases. Unless the context otherwise provides, different labels used for features (e.g., “first circuit”, “second circuit”, “specific circuit”, “given circuit”, etc.) refer to different instances of the feature. Furthermore, unless otherwise stated, the labels “first,” “second,” and “third” do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0127] The phrase "based on" is used to describe one or more factors that influence the determination. This term does not exclude the possibility that additional factors may influence the determination. That is, the determination may be based solely on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on another factor such as C. This phrase is also intended to cover implementations where A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on."

[0128] The phrases “responding to” and “responding” describe one or more factors that trigger an effect. This phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, whether used in conjunction with or independently of the specified factor. That is, the effect may respond solely to these factors, or it may respond to the specified factor along with other unspecified factors. Consider the phrase “responding to B to execute A.” This phrase specifies that B is a factor that triggers the execution of A or a specific result of A. This phrase does not exclude that the execution of A may also respond to certain other factors, such as C. This phrase also does not exclude that the execution of A may be performed jointly in response to B and C. This phrase is also intended to cover implementations where A is executed solely in response to B. As used herein, the phrase “responding” is synonymous with the phrase “at least partially responding to.” Similarly, the phrase “responding to” is synonymous with the phrase “at least partially responding to.”

[0129] Within this disclosure, different entities (which may be referred to differently as “units,” “circuits,” other components, etc.) may be described or claimed to be “configured” to perform one or more tasks or operations. This expression—an [entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be said to be “configured” to perform a task even if the structure is not currently being operated. Therefore, an entity described or stated as “configured” to perform a task refers to a physical thing used to perform that task, such as a device, circuit, system with processor units, and memory storing executable program instructions. This phrase is not used herein to refer to intangible things.

[0130] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured" to perform those tasks / operations, even if not specifically stated.

[0131] The term "configured as" is not intended to mean "configurable as". For example, an unprogrammed FPGA is not considered "configured as" to perform a specific function. However, the unprogrammed FPGA may be "configurable as" to perform that function. After proper programming, the FPGA can then be considered "configured as" to perform a specific function.

[0132] For the purposes of this U.S. patent application, the statement in the claims that the structure is “configured” to perform one or more tasks is expressly intended for the claim elements. No Referencing 35 USC § 112(f). If an applicant wishes to invoke part 112(f) in the course of filing a U.S. patent application based on this disclosure, it will use the phrase “means for [performing a function]” to describe the elements of the claims.

[0133] Different “circuits” may be described in this disclosure. These circuits or “circuit systems” constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom-designed or taken from standard libraries. In various specific implementations, circuit systems may include digital components, analog components, or a combination of both, as appropriate. Certain types of circuits may be commonly referred to as “cells” (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such cells also refer to circuits or circuit systems.

[0134] Therefore, the circuits / units / components and other elements disclosed in the accompanying drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the function of that circuit. For example, a particular “decoding unit” can be described as having the function of executing “the opcode of a processing instruction and routing that instruction to one or more of a plurality of functional units,” meaning that the decoding unit is “configured” to perform that function. To those skilled in the art of computers, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0135] In various implementations, as described in the preceding paragraphs, circuits, cells, and other elements can be defined by the functions or operations they are configured to perform. The arrangement of these circuits / cells / components relative to each other and the manner in which they interact form a microarchitecture definition of hardware, which is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, a microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall within the broader structure described by the microarchitecture definition. That is, those skilled in the art, with the microarchitecture definition provided according to this disclosure, can implement this structure without excessive experimentation and using the application of a person of ordinary skill in the art, by encoding the description of the circuits / cells / components in a hardware description language (HDL) such as Verilog or VHDL. The HDL description is often expressed in a way that can be revealed as functional. However, for those skilled in the art, the HDL description is a way of translating the structure of a circuit, cell, or component into the details of the next level of implementation. Such HDL descriptions can take the following forms: behavioral code (which is typically non-synthesizable), Register Transfer Language (RTL) code (which is typically synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). HDL descriptions can be sequentially synthesized against a library of cells designed for a given integrated circuit manufacturing technology and can be modified for timing, power, and other reasons to obtain the final design database that is transferred to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuitry or portions thereof can also be custom-designed in a schematic editor and captured into the integrated circuit design along with the synthesized circuitry system. The integrated circuit can include transistors and other circuit elements (e.g., passive components such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some implementations may implement multiple integrated circuits coupled together to implement the hardware circuitry, and / or discrete components may be used in some implementations. Alternatively, the HDL design can be synthesized into a programmable logic array such as a Field Programmable Gate Array (FPGA) and implemented within the FPGA. This decoupling between the design of a set of circuits and their subsequent low-level implementations often results in a situation where the circuit or logic designer never specifies a particular set of structures for the low-level implementation that goes beyond a description of what the circuit is configured to do, because that process is performed at different stages of the circuit implementation process.

[0136] The fact that a circuit of the same specifications can be implemented using many different low-level combinations of circuit elements results in a large number of equivalent circuit structures. As noted, these low-level circuit implementations can vary depending on the manufacturing technology, the foundry chosen to manufacture the integrated circuit, the cell library provided for a particular project, and so on. In many cases, the choice of different design tools or methods to produce these different implementations can be arbitrary.

[0137] Furthermore, for a given implementation, a single concrete implementation of the circuit's specific functional specifications typically involves a large number of devices (e.g., millions of transistors). Therefore, the shearing volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single implementation, let alone a large number of equivalent possible implementations. To this end, this disclosure describes the structure of a circuit using functional abbreviations commonly used in industry.

[0138] Once the above disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. This disclosure is intended to make the following claims interpretable as encompassing all such variations and modifications.

Claims

1. A system comprising: integrated circuit; Multiple voltage regulators are configured to supply multiple supply voltages to the integrated circuit; Multiple power transfer trigger circuits are coupled to the integrated circuit and the multiple voltage regulators, wherein the power transfer trigger circuits are configured to monitor the multiple voltage regulators and generate multiple trigger signals based on the electrical load experienced by the multiple voltage regulators. The integrated circuit mentioned above includes: Multiple components are configured to generate memory transactions to access memory; Multiple memory controller circuits are configured to control the memory; A communication structure includes multiple circuits, which interconnect multiple components and multiple memory controller circuits; A trigger logic circuit is coupled to the plurality of power transmission trigger circuits, wherein the trigger logic circuit is configured to generate a power reduction signal based on the plurality of trigger signals received from the plurality of power transmission trigger circuits; and A rate control circuit is configured to control the clock rate of the plurality of circuits in the communication structure, wherein the rate control circuit is coupled to at least one of the plurality of power transmission trigger circuits and is configured to reduce the clock rate based on at least one of the plurality of trigger signals from the at least one power transmission trigger circuit.

2. The system of claim 1, wherein the clock rate reduced based on at least one of the plurality of trigger signals from the at least one power transmission trigger circuit is the clock rate of the communication structure.

3. The system according to claim 1, further comprising: At least one trigger logic output circuit is configured to provide the power reduction signal to at least one additional integrated circuit.

4. The system of claim 1, wherein the power reduction signal is synchronized with the clock cycle of the integrated circuit, and wherein the rate control circuit reduces the clock rate asynchronously with the clock cycle.

5. The system of claim 1, wherein at least one of the components comprises one or more central processing units (CPUs), and wherein the rate control circuitry is configured to reduce the clock rate based on receiving the power reduction signal provided to at least one of the CPUs.

6. The system of claim 1, wherein at least one of the components comprises one or more central processing units (CPUs), and wherein the CPU is configured to execute a plurality of instructions to implement power control in the integrated circuit using dynamic voltage and frequency control.

7. The system of claim 6, wherein the rate control circuit is configured to reduce the clock rate in response to at least one of the plurality of trigger signals from the at least one power transmission trigger circuit within a time window less than the time window for the CPU to implement power control in the integrated circuit using dynamic voltage and frequency control.

8. The system according to claim 1, further comprising: Multiple rate limiter circuits at multiple locations in a pipeline within a given memory controller circuit, wherein the multiple rate limiter circuits are configured to limit the rate at which memory transactions flow through the multiple locations.

9. A system comprising: integrated circuit; Multiple voltage regulators are configured to supply multiple supply voltages to the integrated circuit; Multiple power transfer trigger circuits are coupled to the integrated circuit and the multiple voltage regulators, wherein the power transfer trigger circuits are configured to monitor the multiple voltage regulators and generate multiple trigger signals based on the electrical load experienced by the multiple voltage regulators. The integrated circuit mentioned above includes: Multiple components are configured to generate memory transactions to access memory; and Multiple memory controller circuits are configured to control the memory; and A trigger logic circuit is coupled to the plurality of power transmission trigger circuits, wherein the trigger logic circuit is configured to generate a power reduction signal based on the plurality of trigger signals received from the plurality of power transmission trigger circuits; The given memory controller circuit of the plurality of memory controller circuits includes a plurality of rate limiter circuits at a plurality of locations in the pipeline within the given memory controller circuit, and one or more of the plurality of rate limiter circuits are configured to limit the rate at which memory transactions flow through the plurality of locations.

10. The system of claim 9, wherein at least one of the rate limiters is located at an arbitration point in the pipeline.

11. The system of claim 9, wherein at least one of the rate limiters is located at a write memory arbiter in the pipeline.

12. The system of claim 9, wherein at least one of the rate limiters is located at the read memory arbiter in the pipeline.

13. The system of claim 9, wherein at least one of the rate limiters is located at a buffer in the pipeline.

14. The system of claim 9, wherein at least one of the rate limiters is located between the memory arbiter and the memory cache in the pipeline.

15. The system according to claim 9, further comprising: At least one trigger logic output circuit is configured to provide the power reduction signal to at least one additional integrated circuit.

16. The system according to claim 9, further comprising: A rate control circuit is coupled to at least one of the plurality of power transmission trigger circuits, wherein the rate control circuit is configured to control the clock rate of the plurality of circuits in the communication structure, and wherein the rate control circuit is configured to reduce the clock rate based on at least one of the plurality of trigger signals from the at least one power transmission trigger circuit.

17. A method, the method comprising: The integrated circuit receives multiple supply voltages from multiple voltage regulators, wherein the integrated circuit includes: multiple components for generating memory transactions to access memory, multiple memory controller circuits for controlling the memory, and a communication structure including multiple circuits interconnecting the multiple components and the multiple memory controller circuits; Multiple trigger signals are generated based on the electrical load experienced by the multiple voltage regulators by multiple power transmission trigger circuits coupled to the integrated circuit and the multiple voltage regulators. At the trigger logic circuit coupled to the plurality of power transmission trigger circuits, a power reduction signal is generated based on the plurality of trigger signals received from the plurality of power transmission trigger circuits; The clock rate of the plurality of circuits in the communication structure is controlled by a rate control circuit coupled to at least one of the plurality of power transmission trigger circuits, wherein the clock rate is reduced based on at least one of the plurality of trigger signals from the at least one power transmission trigger circuit; and The rate at which memory transactions flow through multiple locations is controlled by a given memory controller circuit in one of the plurality of memory controller circuits, based on multiple rate limiter circuits at multiple locations in the pipeline within the given memory controller circuit.

18. The method of claim 17, further comprising: The power reduction signal is provided to at least one additional integrated circuit.

19. The method of claim 17, wherein the rate control circuit controls the clock rate asynchronously with the clock cycle of the integrated circuit.

20. The method of claim 17, wherein at least one of the rate limiters is located at a position selected from: a memory arbiter coupled to the given memory controller circuit, a write memory arbiter in the given memory controller circuit, a read memory arbiter in the given memory controller circuit, a buffer coupled to the given memory controller circuit, and a downstream memory arbiter coupled to the given memory controller circuit.

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