Cross-chip random number generation method and apparatus

Abstract

The application provides a cross-chip random number generation method and device, applied to the technical field of computers. The method comprises the following steps: obtaining a first thread total number of a first target chip and a second thread total number of a second target chip, wherein the first thread total number is greater than the second thread total number; determining a sub-sequence total number to be generated according to the first thread total number; allocating at least one sub-sequence calculation task to each thread of the second target chip based on the sub-sequence total number and the second thread total number; sequentially processing the at least one sub-sequence calculation task according to a preset processing rule to obtain a target random number sequence consistent with a random number sequence generated by the first target chip under the same seed; wherein the preset processing rule comprises the following steps: initializing a random number generation state corresponding to a target sub-sequence, generating a random number corresponding to the target sub-sequence by using the random number generation state, and destroying the random number generation state.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a cross-chip random number generation method and device. BACKGROUND

[0002] Random number matrix is a multi-dimensional array containing random numbers, which is widely used in the fields of data science and machine learning. According to the application requirements, when the random number seed is consistent, the generated random number sequence needs to be completely consistent to ensure the reproducibility of the experiment and the stability of the model cross-platform deployment.

[0003] In the prior art, the Graphics Processing Unit (GPU) generally uses Philox pseudo-random algorithm to generate random number matrix. The algorithm realizes random number generation through four parameters: random number seed, subsequence, offset and state. When the random number seed is consistent, the same subsequence and offset combination can stably output the same random number. In the conventional implementation scheme, the GPU uses the binding mode of “one thread one subsequence”, that is, according to the number of its own threads, the corresponding number of subsequence is created, and the random number matrix generation is completed through multi-thread parallel.

[0004] However, the architectures and specifications of different GPU chips are different, and the number of stream processors and the maximum number of threads per stream processor are different, resulting in significant differences in the total number of threads of different GPUs. According to the existing scheme, the difference in the number of threads will directly cause the inconsistency of the number of subsequence, and finally make the random number matrix generated by different GPUs under the same random number seed have deviation, which further causes the problem of inconsistent calculation results when the model is deployed across platforms, seriously affecting the application reliability. SUMMARY

[0005] The present application provides a cross-chip random number generation method and device to solve the problem that different GPU chips cause inconsistency of random number matrix under the same random number seed due to the difference in the number of threads, which can realize completely consistent cross-GPU chip random number generation and guarantee the reliability of model cross-platform deployment.

[0006] The application provides a cross-chip random number generation method, comprising: obtaining a first thread total number of a first target chip and a second thread total number of a second target chip, the first thread total number being greater than the second thread total number; determining a sub-sequence total number to be generated according to the first thread total number, and allocating at least one sub-sequence calculation task to each thread of the second target chip based on the sub-sequence total number and the second thread total number; processing the at least one sub-sequence calculation task in turn according to a preset processing rule to obtain a target random number sequence consistent with a random number sequence generated by the first target chip under the same seed; wherein the preset processing rule comprises: initializing a random number generation state corresponding to a target sub-sequence, generating a random number corresponding to the target sub-sequence by using the random number generation state, and destroying the random number generation state, the target sub-sequence being any one of the at least one sub-sequence.

[0007] According to the cross-chip random number generation method provided by the application, the first thread total number is the product of the number of stream processors of the first target chip and the maximum thread number of each stream processor.

[0008] According to the cross-chip random number generation method provided by the application, the sub-sequence total number is equal to or in a preset proportion to the first thread total number.

[0009] According to the cross-chip random number generation method provided by the application, the step of allocating at least one sub-sequence calculation task to each thread of the second target chip based on the sub-sequence total number and the second thread total number comprises: calculating the quotient and the remainder of the division of the sub-sequence total number by the second thread total number; if the remainder is 0, the number of the at least one sub-sequence is the quotient; if the remainder is not 0, the number of the at least one sub-sequence is the quotient or the quotient plus 1.

[0010] According to the cross-chip random number generation method provided by the application, the step of allocating at least one sub-sequence calculation task to each thread of the second target chip based on the sub-sequence total number and the second thread total number comprises: if the remainder is not 0, sequentially allocating the remainder of the additional sub-sequence calculation tasks to the first remainder of the threads.

[0011] According to the cross-chip random number generation method provided by the application, the random number generation state comprises a random number seed, a sub-sequence identifier, an offset and an algorithm internal state.

[0012] The application further provides a cross-chip random number generation device, comprising the following modules: an acquisition module and a processing module; the acquisition module is used for acquiring a first thread total number of a first target chip and a second thread total number of a second target chip, the first thread total number being greater than the second thread total number; the processing module is used for determining a total number of sub-sequences to be generated according to the first thread total number, allocating at least one sub-sequence calculation task to each thread of the second target chip based on the total number of sub-sequences and the second thread total number, processing the at least one sub-sequence calculation task in turn according to a preset processing rule to obtain a target random number sequence consistent with a random number sequence generated by the first target chip under the same seed; wherein the preset processing rule comprises: initializing a random number generation state corresponding to a target sub-sequence, generating a random number corresponding to the target sub-sequence by using the random number generation state, and destroying the random number generation state, the target sub-sequence being any one of the at least one sub-sequence.

[0013] According to the cross-chip random number generation device provided by the application, the first thread total number is the product of the number of stream processors of the first target chip and the maximum thread number of each stream processor.

[0014] According to the cross-chip random number generation device provided by the application, the total number of sub-sequences is equal to or in a preset proportion to the first thread total number.

[0015] According to the cross-chip random number generation device provided by the application, the allocation of at least one sub-sequence calculation task to each thread of the second target chip based on the total number of sub-sequences and the second thread total number comprises: calculating the quotient and the remainder of the total number of sub-sequences and the second thread total number; if the remainder is 0, the number of the at least one sub-sequence is the quotient; if the remainder is not 0, the number of the at least one sub-sequence is the quotient or the quotient plus 1.

[0016] According to the cross-chip random number generation device provided by the application, the allocation of at least one sub-sequence calculation task to each thread of the second target chip based on the total number of sub-sequences and the second thread total number comprises: if the remainder is not 0, sequentially allocating the remainder of additional sub-sequence calculation tasks to the first remainder of threads.

[0017] According to the cross-chip random number generation device provided by the application, the random number generation state comprises a random number seed, a sub-sequence identifier, an offset and an algorithm internal state.

[0018] The application further provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the cross-chip random number generation method according to any one of the above when executing the computer program.

[0019] The application further provides a non-transitory computer readable storage medium, which stores a computer program, wherein the computer program is executed by a processor to implement the cross-chip random number generation method according to any one of the above.

[0020] The application further provides a computer program product, comprising a computer program, wherein the computer program is executed by a processor to implement the cross-chip random number generation method according to any one of the above.

[0021] The cross-chip random number generation method and device provided by the application can ensure that the target random number sequence generated by the second target chip is completely consistent with the random number sequence generated by the first target chip under the same seed, solve the random number deviation problem caused by the difference in the number of threads of different chips, and guarantee the experimental reproducibility and the stability of model cross-platform deployment. BRIEF DESCRIPTION OF DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the application or the prior art, the following will briefly introduce the drawings needed in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the application, and those skilled in the art can also obtain other drawings according to these drawings without creative effort.

[0023] Figure 1 is a flowchart of the cross-chip random number generation method provided by the application;

[0024] Figure 2 is a structural diagram of the cross-chip random number generation device provided by the application;

[0025] Figure 3 is a structural diagram of the electronic device provided by the application. DETAILED DESCRIPTION

[0026] In the following, the technical solutions of the present application will be described clearly and completely in connection with the drawings in the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all of them. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0027] It should be noted that in the embodiments of the present application, the words such as "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design presented as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being preferred or superior to other embodiments or design solutions. In fact, the use of the words such as "exemplary" or "for example" is intended to present related concepts in a specific manner.

[0028] It should be noted that in this document, the terms "comprise", "contain" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "comprises a" does not exclude the presence of additional identical elements in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the methods and devices in the embodiments of the present application is not limited to performing functions in the order shown or discussed, but can also include performing functions in a substantially simultaneous manner or in reverse order according to the functions involved, for example, the described method can be performed in an order different from that described, and various steps can also be added, omitted or combined. In addition, the features described with reference to some examples can be combined in other examples.

[0029] In order to clearly describe the technical solutions of the embodiments of the present application, in the embodiments of the present application, the same items or similar items with basically the same function and role are distinguished by using "first", "second", etc. The skilled in the art can understand that "first", "second", etc. are not limited in number and execution order.

[0030] The embodiments of the present application describe some exemplary embodiments for the purpose of illustration. It should be understood that the present application can be implemented in other ways not specifically shown in the drawings.

[0031] As Figure 1As shown, the embodiment of the present application provides a cross-chip random number generation method, which can be applied to a cross-chip random number generation device. It is suitable for scenarios such as data science and machine learning that need to rely on random number matrices, and can solve the problem of calculation result deviation caused by inconsistent random number sequences when deploying models across different GPU chips, and can guarantee experimental reproducibility and application reliability. The cross-chip random number generation method can include S101-S103:

[0032] S101, the cross-chip random number generation device obtains the first thread total number of the first target chip and the second thread total number of the second target chip.

[0033] Among them, the first thread total number is greater than the second thread total number.

[0034] Specifically, the first target chip refers to a preset reference chip, and the second target chip refers to a to-be-adapted chip currently needing to generate a random number matrix. Taking the chip with more thread total number as the reference can meet the generation demand of more subsequences and lay the foundation for subsequent unified random number sequences.

[0035] Exemplarily, the thread total number corresponding to the first target chip can be 270336, and the thread total number corresponding to the second target chip can be 8192.

[0036] Optionally, the first thread total number is the product of the number of stream processors of the first target chip and the maximum thread number of each stream processor.

[0037] Specifically, the calculation formula of the first thread total number of the first target chip is:

[0038] ;

[0039] Among them, represents the first thread total number, represents the number of stream processors, represents the maximum thread number of each stream processor.

[0040] Exemplarily, if the number of stream processors of the first target chip is 132 and the maximum thread number of each stream processor is 2048, then the first thread total number thereof is 132x2048=270336; if the number of stream processors of the first target chip is 108 and the maximum thread number of each stream processor is 2048, then the corresponding first thread total number thereof is 108x2048=221184.

[0041] It should be noted that the calculation method of the second thread total number of the second target chip can refer to the calculation process of the first thread total number described above, which will not be repeated here.

[0042] S102, the cross-chip random number generation device determines a total number of sub-sequences to be generated according to the first total number of threads, and assigns each thread of the second target chip at least one sub-sequence calculation task based on the total number of sub-sequences and the second total number of threads.

[0043] Optionally, the total number of sub-sequences is equal to or in a preset proportion to the first total number of threads.

[0044] Specifically, the total number of sub-sequences is equal to the first total number of threads is the most direct implementation, that is, one thread corresponds to one sub-sequence, which can maximize the alignment of random number sequences with the benchmark chip. The setting in a preset proportion can provide flexible adjustment space for the actual application of computing power demand.

[0045] Illustratively, the total number of sub-sequences of the first target chip is equal to the first total number of threads. If the first total number of threads of the first target chip is 270336, the corresponding total number of sub-sequences is 270336.

[0046] Optionally, the assignment of at least one sub-sequence calculation task to each thread of the second target chip based on the total number of sub-sequences and the second total number of threads includes: calculating the quotient and the remainder of the total number of sub-sequences and the second total number of threads; if the remainder is 0, the number of at least one sub-sequence is the quotient; if the remainder is not 0, the number of at least one sub-sequence is the quotient or the quotient plus one.

[0047] Illustratively, if the second total number of threads of the second target chip is 8192 and the total number of sub-sequences is 270336, the calculation can obtain a quotient of 33 and a remainder of 0, so each thread of the second target chip needs to process 33 sub-sequence calculation tasks. If the total number of sub-sequences is 270337 and the second total number of threads is 8192, the calculation can obtain a quotient of 33 and a remainder of 1, so among the 8192 threads, one thread processes 34 sub-sequences, and the remaining 8191 threads process 33 sub-sequences, ensuring that all sub-sequences can be assigned and processed.

[0048] Optionally, if the remainder is not 0, the remainder of the sub-sequence calculation tasks is sequentially assigned to the first remainder of threads.

[0049] Illustratively, still taking the total number of sub-sequences as 270337 and the second total number of threads as 8192 as an example. Since the remainder is 1, this 1 additional sub-sequence calculation task can be assigned to the first thread (thread_0). This assignment method is simple and direct, easy to execute, and can avoid task assignment confusion and ensure the consistency of the processing order.

[0050] S103、cross-chip random number generation device according to the preset processing rule in turn processing the calculation task of at least one subsequence, get with the first target chip in the same seed generated random number sequence consistent with the target random number sequence.

[0051] Wherein, the preset processing rule includes: initialization target subsequence corresponding random number generation state, using the random number generation state, generate the target subsequence corresponding random number, destroy the random number generation state, the target subsequence is in the at least one subsequence any one.

[0052] It should be noted that the technical core of the preset processing rule is just-in-time destruction, a single random number generation state is only 1.42 KB, and the thread destroys its corresponding state after processing a subsequence, and then initializes the state of the next subsequence, avoiding the problem of excessive cache occupation caused by a thread storing multiple states at the same time, and reducing performance loss. For example, when thread_0 of the second target chip processes seq_0, first initialize state_0, generate all random numbers corresponding to seq_0, then destroy state_0, and then initialize state_8192 corresponding to seq_8192 and process, and then loop until all allocated subsequence tasks are completed.

[0053] Specifically, the cross-chip random number generation device can generate a target random number sequence based on the parameters in the random number generation state using a pseudo-random number generation algorithm. The process of generating a target random number sequence can include:

[0054] Step 1, determine the total number of subsequences of the first target chip, and each thread of the second target chip needs to process the calculation task of at least one subsequence. For example, the information of the first subsequence (seq_0) of the first target chip is stored in state_0, and the first thread (thread_0) of the first target chip uses state_0 to generate the first, (subsequence total number + 1) th, (2 × subsequence total number + 1) th…… random number;

[0055] Step 2, the thread of the second target chip is completely aligned with the subsequence-thread correspondence of the first target chip, for example, the first thread (thread_0) of the second target chip also uses state_0 to generate random numbers at the same position as thread_0 of the first target chip, and the second thread (thread_1) uses state_1 to generate random numbers at the same position as thread_1 of the first target chip;

[0056] Step 3, after a round of calculation is completed by the thread of the second target chip, destroy all random number generation states at present, and generate the state corresponding to the next round of subsequence again;

[0057] Step 4, the thread of the second target chip continues to process the sub-sequence corresponding to the newly generated state, and generates random numbers completely consistent with the subsequent sub-sequence of the first target chip;

[0058] Step 5, repeat the cycle of "processing sub-sequence-destroying state-generating new state-processing new sub-sequence" until all random numbers of the sub-sequence are generated.

[0059] Exemplarily, taking the total number of threads of the first target chip as 270336 and the total number of threads of the second target chip as 8192 as an example, the process can be specifically described as:

[0060] The total number of sub-sequences of the first target chip is 270336, the information of the first sub-sequence (seq_0) is stored in state_0, and the first thread (thread_0) generates the first number (out_0), the 270337th number (out_270336), the 540673rd number (out_540672) using state_0……;

[0061] The second target chip needs to align the random number sequence of the first target chip, and the first thread (thread_0) also generates the first number (out_0), the 270337th number (out_270336), the 540673rd number (out_540672) using state_0, the second thread (thread_1) generates the second number (out_1), the 270338th number (out_270337), the 540674th number (out_540673) using state_1……;

[0062] After the 8192 threads of the second target chip complete the first round of calculation, that is, process the sub-sequences corresponding to state_0~state_8191, destroy all state_0~state_8191, and regenerate state_8192~state_16383;

[0063] The 8192 threads of the second target chip continue to process state_8192~state_16383, and generate random numbers completely consistent with thread_8192~thread_16383 of the first target chip;

[0064] Repeat the above cycle of "processing sub-sequence-destroying state-generating new state-processing new sub-sequence" until all random numbers corresponding to 270336 sub-sequences are generated, and finally realize that the random number sequence of the second target chip is completely consistent with that of the first target chip.

[0065] Optionally, the random number generation state includes a random number seed, a subsequence identifier, an offset, and an algorithm internal state. These parameters are the core components of the Philox random number generator, the random number seed is used to determine the basis value of the pseudo-random number generation, the subsequence identifier specifies the current processing subsequence number, the offset describes the position in a single subsequence, and the algorithm internal state uniformly stores the above parameter information, ensures the parameter consistency when generating a random number, and further guarantees the accuracy of the random number result.

[0066] Through the unified processing rule and sequence, the random numbers generated by the second target chip can be completely aligned with the first target chip. For example, thread_0 of the first target chip corresponds to subsequence seq_0, and uses the random number generation state (state_0) of the subsequence to generate out_0, out_270336, out_540672, and the like, and thread_0 of the second target chip will also process seq_0 first, and use state_0 to generate the same out_0, out_270336, out_540672, and the like, and finally realize the consistency of random numbers across chips.

[0067] In the embodiments of the present application, since the total number of subsequences to be generated is determined according to the first thread total number of the first target chip, and each thread of the second target chip is allocated at least one subsequence calculation task, the second target chip can be free from the limitation of its own thread number, and ensure that the target random number sequence generated by the second target chip is completely consistent with the random number sequence of the first target chip under the same seed, solve the random number deviation problem caused by the difference in thread number of different chips, and guarantee the experimental reproducibility and model cross-platform deployment stability; and since the subsequence calculation tasks are processed in turn according to the preset processing rule, and the state management mode of use and destroy is used, it is ensured that at any moment, each thread only holds the state of the subsequence being processed, so as to reduce the cache occupation and avoid the performance loss caused by state accumulation.

[0068] The above mainly introduces the scheme provided by the embodiments of the present application from the method aspect. In order to realize the above functions, it contains the hardware structure and / or software module corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of the examples described in the embodiments disclosed in the present text, the embodiments of the present application can be realized in the form of hardware or the combination of hardware and computer software. Whether a certain function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraint conditions of the technical solution. Professional technicians can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0069] It should be noted that the device in the embodiments of the present application includes a virtual device and a physical device. The virtual device can be a cross-chip random number generation device, and the physical device can include an electronic device, a computer storage medium, and a computer program product.

[0070] The cross-chip random number generation method provided in the embodiments of the present application can be executed by a cross-chip random number generation device or a control module for cross-chip random number generation in the cross-chip random number generation device. In the embodiments of the present application, the cross-chip random number generation method is executed by the cross-chip random number generation device as an example to illustrate the cross-chip random number generation device provided in the embodiments of the present application.

[0071] It should be noted that the embodiments of the present application can divide the function modules of the cross-chip random number generation device according to the above method examples. For example, each function module can be divided according to each function, or two or more functions can be integrated in one processing module. The above integrated modules can be realized in the form of hardware or in the form of software function modules. Optionally, the division of the modules in the embodiments of the present application is illustrative, and is only a logical function division. In actual implementation, another division mode can be used.

[0072] As shown in Figure 2 The cross-chip random number generation device 200 provided in the embodiments of the present application includes an acquisition module 201 and a processing module 202. The acquisition module 201 is configured to acquire a first total number of threads of a first target chip and a second total number of threads of a second target chip, and the first total number of threads is greater than the second total number of threads. The processing module 202 is configured to determine a total number of sub-sequences to be generated according to the first total number of threads, assign at least one sub-sequence calculation task to each thread of the second target chip based on the total number of sub-sequences and the second total number of threads, process the at least one sub-sequence calculation task in turn according to a preset processing rule, and obtain a target random number sequence consistent with a random number sequence generated by the first target chip under the same seed. The preset processing rule includes initializing a random number generation state corresponding to a target sub-sequence, generating a random number corresponding to the target sub-sequence by using the random number generation state, and destroying the random number generation state. The target sub-sequence is any one of the at least one sub-sequence.

[0073] Optionally, the first total number of threads is a product of a stream processor number of the first target chip and a maximum thread number of each stream processor.

[0074] Optionally, the total number of sub-sequences is equal to or in a preset proportion to the first total number of threads.

[0075] Optionally, the task of assigning at least one sub-sequence to each thread of the second target chip based on the total number of sub-sequences and the total number of threads of the second target chip comprises: calculating a quotient and a remainder of the total number of sub-sequences and the total number of threads of the second target chip; if the remainder is 0, the number of at least one sub-sequence is the quotient; if the remainder is not 0, the number of at least one sub-sequence is the quotient or the quotient plus 1.

[0076] Optionally, the task of assigning at least one sub-sequence to each thread of the second target chip based on the total number of sub-sequences and the total number of threads of the second target chip comprises: if the remainder is not 0, sequentially assigning the remainder of additional sub-sequence calculation tasks to the first remainder of threads.

[0077] Optionally, the random number generation state comprises a random number seed, a sub-sequence identifier, an offset, and an algorithm internal state.

[0078] In the embodiments of the present application, since the total number of sub-sequences to be generated is determined according to the total number of first threads of the first target chip, and at least one sub-sequence calculation task is assigned to each thread of the second target chip, the second target chip can be free from the limitation of its own thread number, and the target random number sequence generated by the second target chip is completely consistent with the random number sequence generated by the first target chip under the same seed, thus solving the problem of random number deviation caused by the difference in thread number between different chips, and ensuring the reproducibility of experiments and the stability of model cross-platform deployment. In addition, since the sub-sequence calculation tasks are processed in sequence according to the preset processing rule, and the state management mode of use and destroy is adopted, it is ensured that at any moment, each thread only holds the state of the sub-sequence being processed, so that the cache occupancy can be reduced, and the performance loss caused by state accumulation can be avoided.

[0079] Figure 3 An example of an entity structure diagram of an electronic device is shown in FIG. 1. Figure 3As shown, the electronic device can include a processor 310, a communications interface 320, a memory 330, and a communications bus 340, wherein the processor 310, the communications interface 320, and the memory 330 complete communications with each other through the communications bus 340. The processor 310 can invoke a logical instruction in the memory 330 to execute a cross-chip random number generation method, which includes: obtaining a first total number of threads of a first target chip and a second total number of threads of a second target chip, the first total number of threads being greater than the second total number of threads; determining a total number of sub-sequences to be generated according to the first total number of threads, and assigning each thread of the second target chip at least one calculation task of a sub-sequence based on the total number of sub-sequences and the second total number of threads; processing the at least one calculation task of the sub-sequence in turn according to a preset processing rule to obtain a target random number sequence consistent with a random number sequence generated by the first target chip under the same seed; wherein the preset processing rule includes: initializing a random number generation state corresponding to a target sub-sequence, generating a random number corresponding to the target sub-sequence by using the random number generation state, and destroying the random number generation state, the target sub-sequence being any one of the at least one sub-sequence.

[0080] In addition, the logical instruction in the memory 330 described above can be implemented in the form of a software functional unit and sold or used as an independent product, and can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or part of the technical solutions can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various program code storage media.

[0081] In another aspect, the present application also provides a computer program product, which comprises a computer program stored on a non-transitory computer readable storage medium, and the computer program can be executed by a processor to enable a computer to perform the cross-chip random number generation method provided by the above method, which comprises: obtaining a first thread total number of a first target chip and a second thread total number of a second target chip, the first thread total number being greater than the second thread total number; determining a total number of sub-sequences to be generated according to the first thread total number, and assigning each thread of the second target chip with a calculation task of at least one sub-sequence based on the total number of sub-sequences and the second thread total number; and processing the calculation task of the at least one sub-sequence in turn according to a preset processing rule to obtain a target random number sequence consistent with a random number sequence generated by the first target chip under the same seed; wherein the preset processing rule comprises: initializing a random number generation state corresponding to a target sub-sequence, generating a random number corresponding to the target sub-sequence by using the random number generation state, and destroying the random number generation state, the target sub-sequence being any one of the at least one sub-sequence.

[0082] In another aspect, the present application also provides a non-transitory computer readable storage medium, which stores a computer program, and the computer program can be executed by a processor to implement the cross-chip random number generation method provided by the above method, which comprises: obtaining a first thread total number of a first target chip and a second thread total number of a second target chip, the first thread total number being greater than the second thread total number; determining a total number of sub-sequences to be generated according to the first thread total number, and assigning each thread of the second target chip with a calculation task of at least one sub-sequence based on the total number of sub-sequences and the second thread total number; and processing the calculation task of the at least one sub-sequence in turn according to a preset processing rule to obtain a target random number sequence consistent with a random number sequence generated by the first target chip under the same seed; wherein the preset processing rule comprises: initializing a random number generation state corresponding to a target sub-sequence, generating a random number corresponding to the target sub-sequence by using the random number generation state, and destroying the random number generation state, the target sub-sequence being any one of the at least one sub-sequence.

[0083] The device embodiments described above are merely illustrative, wherein the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., they can be located in one place, or distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the present embodiment scheme according to actual needs. Those skilled in the art can understand and implement without creative labor.

[0084] Those skilled in the art can clearly understand the technical solutions of the various embodiments from the above description of the embodiments, and the various embodiments can be implemented by means of software with the necessary general hardware platforms, and of course, can also be implemented by hardware. Based on such understanding, the above technical solutions, essentially or in other words, the part of the prior art that makes a contribution, can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, and the like, and includes a number of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0085] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for some technical features therein; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A cross-chip random number generation method, characterized by, The method comprises the following steps: obtaining a first thread total number of a first target chip and a second thread total number of a second target chip, wherein the first thread total number is greater than the second thread total number; determining a total number of sub-sequences to be generated according to the first thread total number, and allocating at least one sub-sequence calculation task to each thread of the second target chip based on the total number of sub-sequences and the second thread total number; processing the at least one sub-sequence calculation task in sequence according to a preset processing rule to obtain a target random number sequence consistent with a random number sequence generated by the first target chip under the same seed; wherein the preset processing rule comprises: initializing a random number generation state corresponding to a target sub-sequence, generating a random number corresponding to the target sub-sequence by using the random number generation state, and destroying the random number generation state, and the target sub-sequence is any one of the at least one sub-sequence.

2. The cross-chip random number generation method of claim 1, wherein, The first thread total number is the product of the number of stream processors of the first target chip and the maximum thread number of each stream processor.

3. The cross-chip random number generation method of claim 2, wherein, The total number of sub-sequences is equal to or in a preset proportion to the first thread total number.

4. The cross-chip random number generation method of claim 1, wherein, The step of allocating at least one sub-sequence calculation task to each thread of the second target chip based on the total number of sub-sequences and the second thread total number comprises: calculating the quotient and the remainder of the total number of sub-sequences and the second thread total number; if the remainder is 0, the number of the at least one sub-sequence is the quotient; if the remainder is not 0, the number of the at least one sub-sequence is the quotient or the quotient plus 1.

5. The cross-chip random number generation method according to claim 4, characterized in that, The step of allocating at least one sub-sequence calculation task to each thread of the second target chip based on the total number of sub-sequences and the second thread total number comprises: if the remainder is not 0, sequentially allocating the remainder of the sub-sequence calculation tasks to the first remainder of the threads.

6. The cross-chip random number generation method according to any one of claims 1 to 5, characterized in that, The random number generation state comprises a random number seed, a sub-sequence identifier, an offset, and an algorithm internal state.

7. A cross-chip random number generation apparatus, comprising: The method comprises the following steps: obtaining a first thread total number of a first target chip and a second thread total number of a second target chip by using an obtaining module, wherein the first thread total number is greater than the second thread total number; determining a total number of sub-sequences to be generated according to the first thread total number by using a processing module, and allocating at least one sub-sequence calculation task to each thread of the second target chip based on the total number of sub-sequences and the second thread total number; processing the at least one sub-sequence calculation task in sequence according to a preset processing rule to obtain a target random number sequence consistent with a random number sequence generated by the first target chip under the same seed; wherein the preset processing rule comprises: initializing a random number generation state corresponding to a target sub-sequence, generating a random number corresponding to the target sub-sequence by using the random number generation state, and destroying the random number generation state, and the target sub-sequence is any one of the at least one sub-sequence. The processor executes the computer program to implement the cross-chip random number generation method according to any one of claims 1 to 6.

8. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The computer program is executed by the processor to implement the cross-chip random number generation method according to any one of claims 1 to 6. 9.A non-transitory computer-readable storage medium having stored thereon a computer program, characterized in that, ​ 10. A computer program product comprising a computer program, characterized in that, The computer program, when executed by a processor, implements the cross-chip random number generation method as claimed in any of claims 1 to 6.

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