Data transmission method and apparatus, electronic device, storage medium, and program product

Abstract

The application relates to the technical field of data transmission, and provides a data transmission method, a device, electronic equipment, a storage medium and a program product. The data transmission method comprises the following steps: acquiring the data length of to-be-transmitted data in a memory; if it is determined that the data length is aligned with a target alignment value, then based on the cacheable length of an on-chip cache, the to-be-transmitted data is fragmented and copied to the on-chip cache, and based on the storable length of a to-be-received register, the to-be-transmitted data in the on-chip cache is loaded to the to-be-received register; wherein the target alignment value is an integer multiple of the storable length, and the cacheable length is an integer multiple of the target alignment value. In the technical scheme provided by the application, for to-be-transmitted data whose data length is aligned with the target alignment value, since the data length is aligned with the storable length, the problem of whether the boundary is aligned does not need to be considered, and a mask does not need to be set, so that a large number of instructions can be saved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data transmission, and in particular to a data transmission method and device, electronic equipment, storage medium and program product. BACKGROUND

[0002] In the assembly instruction program, sometimes one-dimensional linear data needs to be transmitted from the memory to the register, although the data amount is not large, but if the transmission method is not efficient enough, it will become the performance bottleneck of the whole program.

[0003] The scheme adopted by the prior art for transmitting data from the memory to the register is to load the data of the storable length of the register into the register, and loop multiple times until all the data is loaded. However, in the last loading process, misalignment may occur at the boundary position, so in order to prevent dirty data from polluting the register, in addition to completing the basic memory-to-register address mapping calculation in each loop, it is also necessary to consider whether the current loop exceeds the boundary, and to set a mask for the exceeding part to ensure that the data of the exceeding part will not be loaded into the register, so a large number of boundary checks and mask-related instructions are needed for each data transmission. SUMMARY

[0004] The present application provides a data transmission method, device, electronic equipment, storage medium and program product to solve the defects in the prior art.

[0005] The present application provides a data transmission method, comprising:

[0006] obtaining the data length of the to-be-transmitted data in the memory;

[0007] if it is determined that the data length is aligned with a target alignment value, then based on the cacheable length of the on-chip cache, the to-be-transmitted data is fragmented and copied to the on-chip cache, and based on the storable length of the to-be-received register, the to-be-transmitted data in the on-chip cache is loaded into the to-be-received register;

[0008] wherein the target alignment value is an integer multiple of the storable length, and the cacheable length is an integer multiple of the target alignment value.

[0009] According to the data transmission method provided by the present application, based on the cacheable length of the on-chip cache, the to-be-transmitted data is fragmented and copied to the on-chip cache, and based on the storable length of the to-be-received register, the to-be-transmitted data in the on-chip cache is loaded into the to-be-received register, comprising:

[0010] copying the to-be-transmitted data corresponding to the cacheable length from the memory to the on-chip cache;

[0011] loading the to-be-transmitted data corresponding to the storable length from the on-chip cache to the to-be-received register in sequence;

[0012] copying the to-be-transmitted data corresponding to the cacheable length from the memory to the on-chip cache until the to-be-transmitted data in the memory is all transmitted to the to-be-received register.

[0013] According to the data transmission method provided by the application, copying the to-be-transmitted data corresponding to the cacheable length from the memory to the on-chip cache comprises:

[0014] copying the to-be-transmitted data corresponding to the cacheable length from the memory to the on-chip cache through a CP instruction.

[0015] According to the data transmission method provided by the application, loading the to-be-transmitted data corresponding to the storable length from the on-chip cache to the to-be-received register in sequence comprises:

[0016] calculating first position information of the to-be-transmitted data to be loaded currently in the on-chip cache based on the storable length in each loading process;

[0017] loading the to-be-transmitted data to be loaded currently into the to-be-received register based on the first position information.

[0018] According to the data transmission method provided by the application, copying the to-be-transmitted data to the on-chip cache based on the cacheable length of the on-chip cache and loading the to-be-transmitted data in the on-chip cache to the to-be-received register based on the storable length of the to-be-received register comprises:

[0019] copying the to-be-transmitted data corresponding to the cacheable length from the memory to the on-chip cache in sequence until the to-be-transmitted data in the memory is all copied to the on-chip cache;

[0020] loading the to-be-transmitted data corresponding to the storable length from the on-chip cache to the to-be-received register in sequence until the to-be-transmitted data in the on-chip cache is all loaded to the to-be-received register.

[0021] According to the data transmission method provided by the application, the method further comprises:

[0022] if it is determined that the data length is not aligned with the target alignment value, loading the to-be-transmitted data corresponding to the storable length from the memory to the to-be-received register in sequence.

[0023] According to a data transmission method provided by the present invention, the step of sequentially loading the data to be transmitted corresponding to the storable length from the memory to the register to be received includes:

[0024] During each loading process, the second location information of the data to be transferred to be loaded in the memory is calculated based on the storable length, and it is detected whether the data to be transferred to be loaded is boundary data.

[0025] If so, set a mask for the data to be transmitted to be loaded, and load the data to be transmitted to be received into the receiving register based on the second location information.

[0026] The present invention also provides a data transmission device, comprising:

[0027] The acquisition module is configured to acquire the length of the data to be transmitted in memory;

[0028] The copying module is configured to, if it is determined that the data length is aligned with the target alignment value, copy the data to be transmitted in fragments to the on-chip cache based on the cacheable length of the on-chip cache, and load the data to be transmitted from the on-chip cache into the receive register based on the storable length of the receive register.

[0029] Wherein, the target alignment value is an integer multiple of the storable length, and the cacheable length is an integer multiple of the target alignment value.

[0030] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the data transmission method as described above.

[0031] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the data transmission method as described above.

[0032] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the data transmission method as described above.

[0033] The data transmission method, device, electronic equipment, storage medium and program product provided by the application are used for copying the to-be-transmitted data from the memory to the on-chip cache, and then loading the to-be-transmitted data from the on-chip cache to the to-be-received register. In the process of copying from the memory to the on-chip cache and from the on-chip cache to the to-be-received register, the on-chip cache can copy the cacheable length at a time, and the cacheable length is an integer multiple of the storable length of the to-be-received register, which is much larger than the storable length, so that the bandwidth advantage can be fully utilized, the hardware bandwidth is higher when copying data, and the data transmission is faster. Moreover, since the data length is aligned with the storable length, the problem of whether the boundary is aligned does not need to be considered, and a mask does not need to be set, so that a large number of instructions can be saved. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions in the application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative effort.

[0035] Figure 1 is one of the flowcharts of the data transmission method provided by the application.

[0036] Figure 2 is the second flowchart of the data transmission method provided by the application.

[0037] Figure 3 is the structural schematic diagram of the data transmission device provided by the application.

[0038] Figure 4 is the structural schematic diagram of the electronic equipment provided by the application.

[0039] Reference signs:

[0040] 310: acquisition module; 320: copying module; 410: processor; 420: communication interface; 430: memory; 440: communication bus. DETAILED DESCRIPTION

[0041] In order to make the objects, technical solutions and advantages of the application clearer, the technical solutions in the application will be described clearly and completely in combination with the drawings in the application. Obviously, the described embodiments are some of the embodiments of the application, not all the embodiments. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative effort belong to the protection scope of the application.

[0042] Figure 1is a flow chart of a data transmission method according to an exemplary embodiment. As shown in Figure 1 The data transmission method comprises steps 110-120 in an exemplary embodiment, which are described in detail as follows.

[0043] In step 110, the data length of the data to be transmitted in the memory is obtained.

[0044] In the embodiment, the data length of the data to be transmitted is assumed to be L.

[0045] In step 120, if it is determined that the data length is aligned with the target alignment value, the data to be transmitted is copied to the on-chip cache based on the cacheable length of the on-chip cache, and the data to be transmitted in the on-chip cache is loaded to the receiving register based on the storable length of the receiving register.

[0046] The target alignment value is an integer multiple of the storable length, and the cacheable length is an integer multiple of the target alignment value.

[0047] In the embodiment, it is detected whether the obtained data length is aligned with the target alignment value, i.e., whether the data length is an integer multiple of the target alignment value. If the data length is aligned with the target alignment value, the data to be transmitted is copied to the on-chip cache based on the cacheable length of the on-chip cache, and the data to be transmitted in the on-chip cache is loaded to the receiving register based on the storable length of the receiving register.

[0048] In the embodiment, for the data to be transmitted whose data length is aligned with the target alignment value, the data to be transmitted is first copied from the memory to the on-chip cache, and then loaded from the on-chip cache to the receiving register. In the process from the memory to the on-chip cache and from the on-chip cache to the receiving register, the on-chip cache can copy the cacheable length at a time, and the cacheable length is an integer multiple of the storable length of the receiving register, which is much larger than the storable length. Therefore, the bandwidth advantage can be fully utilized, the hardware bandwidth is higher when copying data, and the data transmission is faster. Moreover, since the data length is aligned with the storable length, the problem of whether the boundary is aligned does not need to be considered, and a mask does not need to be set, which can save a large number of instructions.

[0049] In an exemplary embodiment of the present application, the data to be transmitted is copied to the on-chip cache based on the cacheable length of the on-chip cache, and the data to be transmitted in the on-chip cache is loaded to the receiving register based on the storable length of the receiving register, comprising:

[0050] The data to be transmitted corresponding to the cacheable length is copied from the memory to the on-chip cache;

[0051] The data to be transmitted, corresponding to the storable length, is sequentially loaded from the on-chip cache into the register to be received;

[0052] Jump to the step of copying the data to be transmitted from the memory to the on-chip cache corresponding to the cacheable length, until all the data to be transmitted in the memory is transmitted to the receiving register.

[0053] In embodiments of the present invention, such as Figure 2 As shown, when the data length L is an integer multiple of the target alignment value N, the amount of data to be transmitted corresponding to the bufferable length is copied from memory to the on-chip buffer, and large blocks of aligned data to be transmitted are moved from memory to the on-chip high-speed buffer. Then, data is loaded from an aligned, well-organized buffer into the receive register.

[0054] Specifically, the data to be transmitted, corresponding to the cacheable length, is copied from memory to the on-chip buffer. Then, the data to be transmitted, corresponding to the storable length, is read from the on-chip buffer. The read data to be transmitted is loaded into the receiving register. This process is repeated K / M times until all the data in the on-chip buffer is loaded. Then, the data to be transmitted, corresponding to the cacheable length, is copied from memory to the on-chip buffer again. The data to be transmitted in the on-chip buffer is then loaded into the receiving register in the same way. This process is repeated multiple times until all the data to be transmitted in memory is transferred to the receiving register.

[0055] The technical solution provided in this embodiment forms a two-layer loop structure, which includes an outer loop and an inner loop. In each outer loop, a block of data to be transmitted, with a size equal to the bufferable length, is copied from memory to an on-chip buffer. This outer loop can utilize data alignment characteristics to achieve high-speed data transfer cycles of L / K times. In each inner loop, a block of data to be transmitted, with a size equal to the storable length, is loaded from the on-chip buffer into the receive register. The inner loop within each outer loop can cycle K / M times.

[0056] In this embodiment of the invention, since the data to be transmitted in the on-chip cache is continuous and aligned, when loading the data to be transmitted into the receive register, the starting address of the data to be transmitted to be loaded in the on-chip cache can be quickly calculated. At the same time, each loading can ensure that the data to be transmitted is complete and of a storable length, without the need to check the boundary or set a mask.

[0057] In an exemplary embodiment of the present invention, copying the data to be transmitted, corresponding to the cacheable length, from the memory to the on-chip cache includes:

[0058] Copy the data to be transmitted corresponding to the cacheable length from the memory to the on-chip cache through a CP instruction.

[0059] In the embodiment of the present application, the CP (Copy) instruction can copy data from one location to another location, therefore, based on the CP instruction, data can be copied from the memory to the on-chip cache Buffer. Since the CP instruction has an alignment restriction requirement, the data to be transmitted must be aligned with the target alignment value N each time, and the cacheable length of the on-chip cache is an integer multiple of the target alignment value, therefore, based on the CP instruction, large blocks of aligned data to be transmitted can be efficiently and quickly moved to the on-chip cache.

[0060] In an exemplary embodiment of the present application, the sequentially loading the data to be transmitted corresponding to the storable length from the on-chip cache to the to-be-received register comprises:

[0061] In each loading process, the first position information of the data to be transmitted to be currently loaded in the on-chip cache is calculated based on the storable length;

[0062] The data to be transmitted to be currently loaded is loaded into the to-be-received register based on the first position information.

[0063] In the embodiment of the present application, the result of K / M is obtained to get the total number of cycles, according to the number i of the current cycle, the first position information of the data to be transmitted to be loaded in the on-chip cache is calculated, that is, the starting address of the data to be transmitted to be currently loaded in the on-chip cache, starting from the starting address, the data to be transmitted corresponding to the storable length is read from the on-chip cache, and the read data to be transmitted is loaded into the to-be-received register.

[0064] In the embodiment of the present application, in the process from the memory to the on-chip cache Buffer and from the on-chip cache Buffer to the to-be-received register, the on-chip cache Buffer can copy the cacheable length at a time, and the cacheable length K is an integer multiple of the storable length M of the to-be-received register, which is much larger than the storable length M, therefore, the bandwidth advantage can be more fully utilized, the hardware bandwidth is higher when copying data, and the data transmission is faster. And since the data length L is aligned with the storable length M, in addition to the address mapping calculation from the on-chip cache Buffer to the to-be-received register, there is no need to consider whether the boundary is aligned or not, and there is no need to set a mask, which can save a large number of instructions.

[0065] In an example embodiment of the present application, the copying the data to be transmitted to the on-chip cache based on the cacheable length and loading the data to be transmitted in the on-chip cache to the register to be received based on the storable length comprises:

[0066] copying the data to be transmitted corresponding to the cacheable length from the memory to the on-chip cache in sequence until all the data to be transmitted in the memory is copied to the on-chip cache;

[0067] loading the data to be transmitted corresponding to the storable length from the on-chip cache to the register to be received in sequence until all the data to be transmitted in the on-chip cache is loaded to the register to be received.

[0068] In an example embodiment of the present application, all the data to be transmitted in the memory is copied to a plurality of on-chip caches Buffer, and at the same time, an index is set for each on-chip cache Buffer based on the data to be transmitted. Then, the data to be transmitted in each on-chip cache Buffer is loaded to the register to be received in sequence based on the index.

[0069] Specifically, the data to be transmitted corresponding to the cacheable length is copied from the starting position of the data to be transmitted in the memory to the first on-chip cache Buffer, an index is set for the first on-chip cache Buffer, and then the data to be transmitted corresponding to the cacheable length is copied from the memory to the second on-chip cache Buffer, and an index is set for the second on-chip cache. The above process is repeated for a plurality of times until all the data to be transmitted in the memory is copied to the on-chip cache Buffer. Then, the data to be transmitted corresponding to the storable length is read from the first on-chip cache Buffer, and the read data to be transmitted is loaded to the register to be received. The data to be transmitted corresponding to the storable length is loaded from the second on-chip cache Buffer to the register to be received, and the above process is repeated for a plurality of times until the data in all the on-chip cache Buffer is loaded.

[0070] In an example embodiment of the present application, the data transmission method further comprises:

[0071] If it is determined that the data length is not aligned with the target alignment value, the data to be transmitted corresponding to the storable length is loaded from the memory to the register to be received in sequence.

[0072] In an example embodiment of the present application, as Figure 2As shown, if the data length of the data to be transmitted is not aligned with the target alignment value, the data to be transmitted corresponding to the storable length is sequentially loaded from the memory to the receiving register. The LD (Load) instruction can be used to load data from the memory to the register, thus, the LD instruction is executed once in each loading process until all the data to be transmitted is loaded.

[0073] In an example embodiment of the present application, the sequentially loading the data to be transmitted corresponding to the storable length from the memory to the receiving register comprises:

[0074] In each loading process, the second position information of the data to be transmitted to be currently loaded in the memory is calculated based on the storable length, and whether the data to be transmitted to be currently loaded is boundary data is detected.

[0075] If yes, a mask is set for the data to be transmitted to be currently loaded, and the data to be transmitted to be currently loaded is loaded into the receiving register based on the second position information.

[0076] In the embodiment of the present application, when the data length L is not an integer multiple of the target alignment value N, the starting address of each loading process cannot be guaranteed to be aligned, and the data amount of the last loading process can be less than the storable length M. The number of cycles required to load all the data to be transmitted is calculated. The result of L / M is calculated and rounded up to obtain the number of cycles. In each loading process, the address of the data to be transmitted to be currently loaded from the memory to the register is calculated, i.e., the starting address of the data to be loaded in the memory is calculated according to the index j of the current cycle.

[0077] Since the data length L is not an integer multiple of the storable length M, the effective data amount loaded in the last cycle will be less than M. If the complete M is still loaded, data not belonging to the data to be transmitted will be accessed, resulting in an error. Therefore, whether the data to be transmitted to be currently loaded is boundary data can be obtained based on whether the current cycle is the last cycle.

[0078] If the current cycle is the last cycle, it is determined that the data to be transmitted to be currently loaded is boundary data, and a mask is set for the data to be transmitted to be currently loaded. The mask is a bitmap, in which each bit corresponds to a data unit in the register.

[0079] If the current cycle is not the last cycle, it is determined that the data to be transmitted to be currently loaded is not boundary data, which means that the complete M units of the data to be transmitted to be loaded this time are within the effective range L, and the mask does not need to be set.

[0080] In this way, when the LD instruction is executed, the processor uses the mask to load only the valid data into the receiving register without overwriting the out-of-range portion of the register, thereby ensuring the safety and correctness of the operation. After the address and the mask are ready, the LD from Memory instruction is executed. The processor reads the data from the memory according to the calculated second position information, and applies the set mask to safely load the valid data into the receiving register.

[0081] The data transmission apparatus provided by the present application is described below, and the data transmission apparatus described below can be correspondingly referred to the data transmission method described above. It should be noted that the apparatus provided by the embodiments below belongs to the same concept as the method provided by the above embodiments, and the specific manner in which each module and unit performs operations has been described in detail in the method embodiments, which will not be described here.

[0082] In an example embodiment of the present application, refer to Figure 3 , Figure 3 The data transmission apparatus shown in FIG. 3 is a data transmission apparatus according to an example embodiment, comprising the following modules:

[0083] The obtaining module 310 is configured to obtain the data length of the to-be-transmitted data in the memory;

[0084] The copying module 320 is configured to, if it is determined that the data length is aligned with the target alignment value, copy the to-be-transmitted data to the on-chip cache based on the cacheable length of the on-chip cache, and load the to-be-transmitted data in the on-chip cache to the receiving register based on the storable length of the receiving register.

[0085] The target alignment value is an integer multiple of the storable length, and the cacheable length is an integer multiple of the target alignment value.

[0086] In an example embodiment of the present application, the copying module 320 comprises:

[0087] The first copying submodule is configured to copy the to-be-transmitted data corresponding to the cacheable length from the memory to the on-chip cache;

[0088] The first loading submodule is configured to sequentially load the to-be-transmitted data corresponding to the storable length from the on-chip cache to the receiving register;

[0089] The jumping submodule is configured to jump to the step of copying the to-be-transmitted data corresponding to the cacheable length from the memory to the on-chip cache until the to-be-transmitted data in the memory is completely transmitted to the receiving register.

[0090] In an example embodiment of the present application, the first copying submodule comprises:

[0091] The copying unit is configured to copy the to-be-transmitted data corresponding to the cacheable length from the memory to the on-chip cache through the CP instruction.

[0092] In an example embodiment of the present application, the first loading submodule comprises:

[0093] The calculating unit is configured to calculate first position information of the to-be-transmitted data currently to be loaded in the on-chip cache based on the storable length in each loading process.

[0094] The loading unit is configured to load the to-be-transmitted data currently to be loaded into the to-be-received register based on the first position information.

[0095] In an example embodiment of the present application, the copying module 320 comprises:

[0096] The second copying submodule is configured to copy the to-be-transmitted data corresponding to the cacheable length from the memory to the on-chip cache in sequence until the to-be-transmitted data in the memory is completely copied to the on-chip cache.

[0097] The second loading submodule is configured to load the to-be-transmitted data corresponding to the storable length from the on-chip cache to the to-be-received register in sequence until the to-be-transmitted data in the on-chip cache is completely loaded to the to-be-received register.

[0098] In an example embodiment of the present application, the data transmission device further comprises:

[0099] The loading module is configured to load the to-be-transmitted data corresponding to the storable length from the memory to the to-be-received register in sequence if it is determined that the data length is not aligned with the target alignment value.

[0100] In an example embodiment of the present application, the loading module comprises:

[0101] The calculating submodule is configured to calculate second position information of the to-be-transmitted data currently to be loaded in the memory based on the storable length in each loading process, and detect whether the to-be-transmitted data currently to be loaded is boundary data.

[0102] The third loading submodule is configured to set a mask for the to-be-transmitted data currently to be loaded and load the to-be-transmitted data currently to be loaded into the to-be-received register based on the second position information if the to-be-transmitted data currently to be loaded is boundary data.

[0103] Figure 4 An example of a schematic diagram of a physical structure of an electronic device is shown in Figure 4 The electronic device can include a processor 410, a communications interface 420, a memory 430, and a communications bus 440, wherein the processor 410, the communications interface 420, and the memory 430 can communicate with each other through the communications bus 440. The processor 410 can invoke a logical instruction in the memory 430 to execute a data transmission method, which includes obtaining a data length of to-be-transmitted data in a memory;

[0104] If it is determined that the data length is aligned with a target alignment value, the to-be-transmitted data is copied to an on-chip cache based on a cacheable length of the on-chip cache, and the to-be-transmitted data in the on-chip cache is loaded to a to-be-received register based on a storable length of the to-be-received register;

[0105] The target alignment value is an integer multiple of the storable length, and the cacheable length is an integer multiple of the target alignment value.

[0106] In addition, the logical instruction in the memory 430 described above can be implemented in the form of a software functional unit and sold or used as an independent product, and can be stored in a computer-readable storage medium. Based on this understanding, the technical solutions of the present application essentially or the part that contributes to the prior art or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0107] On the other hand, the present application also provides a computer program product, which includes a computer program, the computer program can be stored on a non-transitory computer readable storage medium, and the computer program can be executed by a processor to enable a computer to execute the data transmission method provided by the above-mentioned methods, which includes obtaining a data length of to-be-transmitted data in a memory;

[0108] if it is determined that the data length is aligned with the target alignment value, copying the to-be-transmitted data fragment to the on-chip cache based on a cacheable length of the on-chip cache, and loading the to-be-transmitted data in the on-chip cache to the to-be-received register based on a storable length of the to-be-received register;

[0109] The target alignment value is an integer multiple of the storable length, and the cacheable length is an integer multiple of the target alignment value.

[0110] In another aspect, the present application also provides a non-transitory computer readable storage medium having a computer program stored thereon, which, when executed by a processor, implements a data transmission method provided by the above method, and the method comprises: obtaining a data length of to-be-transmitted data in a memory;

[0111] if it is determined that the data length is aligned with the target alignment value, copying the to-be-transmitted data fragment to the on-chip cache based on a cacheable length of the on-chip cache, and loading the to-be-transmitted data in the on-chip cache to the to-be-received register based on a storable length of the to-be-received register;

[0112] The target alignment value is an integer multiple of the storable length, and the cacheable length is an integer multiple of the target alignment value.

[0113] The device embodiments described above are merely illustrative, wherein the units described as separate components can or can not be physically separate, and the components displayed as units can or can not be physical units, i.e., they can be located in one place, or distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the embodiment scheme according to actual needs. Those skilled in the art can understand and implement it without creative labor.

[0114] From the above description of the embodiments, those skilled in the art can clearly understand that the embodiments can be realized by means of software plus necessary general hardware platforms, and of course, can also be realized by hardware. Based on such understanding, the above technical solutions, essentially or in terms of the contribution to the prior art, can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as a ROM / RAM, a magnetic disk, an optical disk, etc., and includes a plurality of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments.

[0115] It should be pointed out finally that the above embodiments are only used to illustrate the technical solutions of the present application, but not to limit the same; and although the present application has been described in detail with reference to the foregoing embodiments, it should be appreciated by those skilled in the art that the technical solutions recorded in the foregoing embodiments can be modified, or some technical features thereof can be replaced equivalently; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A data transmission method, characterized in that, include: Get the length of the data to be transferred in memory; If it is determined that the data length is aligned with the target alignment value, then based on the cacheable length of the on-chip cache, the data to be transmitted is fragmented and copied to the on-chip cache, and based on the storable length of the register to be received, the data to be transmitted in the on-chip cache is loaded into the register to be received. Wherein, the target alignment value is an integer multiple of the storable length, and the cacheable length is an integer multiple of the target alignment value; The step of fragmenting and copying the data to be transmitted to the on-chip cache based on the cacheable length of the on-chip cache, and loading the data to be transmitted from the on-chip cache into the receive register based on the storable length of the receive register, includes: Copy the data to be transmitted, corresponding to the cacheable length, from the memory to the on-chip cache; The data to be transmitted, corresponding to the storable length, is sequentially loaded from the on-chip cache to the receiving register; wherein, during each loading process, the starting address of the data to be transmitted in the on-chip cache is determined according to the current inner loop count, and loading is performed based on the starting address; Jump to the step of copying the data to be transmitted from the memory to the on-chip cache corresponding to the cacheable length, until all the data to be transmitted in the memory is transmitted to the receiving register.

2. The data transmission method according to claim 1, characterized in that, Copying the data to be transmitted, corresponding to the cacheable length, from the memory to the on-chip cache includes: The data to be transmitted, corresponding to the cacheable length, is copied from the memory to the on-chip cache using the CP instruction.

3. The data transmission method according to claim 1, characterized in that, The step of sequentially loading the data to be transmitted, corresponding to the storable length, from the on-chip cache to the register to be received includes: During each loading process, the first position information of the data to be loaded and transmitted in the on-chip cache is calculated based on the storable length and the current number of inner loops. Based on the first location information, the data to be transmitted is loaded into the register to be received.

4. The data transmission method according to claim 1, characterized in that, The step of fragmenting and copying the data to be transmitted to the on-chip cache based on the cacheable length of the on-chip cache, and loading the data to be transmitted from the on-chip cache into the receive register based on the storable length of the receive register, includes: The data to be transmitted, corresponding to the cacheable length, is copied sequentially from the memory to the on-chip cache until all the data to be transmitted in the memory is copied to the on-chip cache. The data to be transmitted, corresponding to the storable length, is sequentially loaded from the on-chip cache into the receiving register until all the data to be transmitted in the on-chip cache is loaded into the receiving register.

5. The data transmission method according to any one of claims 1 to 4, characterized in that, The method further includes: If it is determined that the data length is not aligned with the target alignment value, the data to be transmitted corresponding to the storable length is sequentially loaded from the memory into the register to be received.

6. The data transmission method according to claim 5, characterized in that, The step of sequentially loading the data to be transmitted, corresponding to the storable length, from the memory to the register to be received includes: During each loading process, the second location information of the data to be transferred to be loaded in the memory is calculated based on the storable length, and it is detected whether the data to be transferred to be loaded is boundary data. If so, set a mask for the data to be transmitted to be loaded, and load the data to be transmitted to be received into the receiving register based on the second location information.

7. A data transmission device, characterized in that, include: The acquisition module is configured to acquire the length of the data to be transmitted in memory; The copying module is configured to, if it is determined that the data length is aligned with the target alignment value, copy the data to be transmitted in fragments to the on-chip cache based on the cacheable length of the on-chip cache, and load the data to be transmitted from the on-chip cache into the receive register based on the storable length of the receive register. Wherein, the target alignment value is an integer multiple of the storable length, and the cacheable length is an integer multiple of the target alignment value; The copy module includes: The first copying submodule is configured to copy the data to be transmitted, corresponding to the cacheable length, from the memory to the on-chip cache; The first loading submodule is configured to sequentially load the data to be transmitted corresponding to the storable length from the on-chip cache to the receiving register; wherein, in each loading process, the starting address of the data to be transmitted in the on-chip cache is determined according to the current inner loop count, and loading is performed based on the starting address; The jumper module is configured to jump to the step of copying the data to be transmitted from the memory, corresponding to the cacheable length, to the on-chip cache, until all the data to be transmitted in the memory is transmitted to the receiving register.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the data transmission method as described in any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the data transmission method as described in any one of claims 1 to 6.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the data transmission method as described in any one of claims 1 to 6.

Images