High-precision dead-time compensation method and system based on FPGA

Abstract

The application relates to the technical field of SPWM dead-time compensation, in particular to a high-precision dead-time compensation method and system based on FPGA, which comprises the following steps: integrating the absolute value of an actual output voltage waveform to obtain a first voltage integral value in a preset sampling window before the end of a current SPWM period; collecting a driving circuit DC bus voltage average value; calculating a predicted full-period voltage integral value and a voltage integral difference of the current SPWM period; collecting a historical rotating speed data sequence; obtaining a dead-time; predicting a target period average value of a servo motor rotating speed, which is recorded as a predicted rotating speed; calculating a first compensation amount, a second compensation amount and a third compensation amount according to the voltage integral difference, the driving circuit DC bus voltage average value, the dead-time, the average value of the historical rotating speed data sequence and the predicted rotating speed; superimposing the first compensation amount, the second compensation amount and the third compensation amount to obtain a total compensation voltage, and then generating a compensated voltage reference signal. The application realizes dead-time compensation by dynamically generating the compensated voltage reference signal.

Description

Technical Field

[0001] This invention relates to the field of SPWM dead-time compensation technology, specifically to a high-precision dead-time compensation method and system based on FPGA. Background Technology

[0002] With the rapid development of industrial automation and high-performance servo drive technology, higher requirements are placed on the control accuracy, dynamic response, and operational stability of servo systems. A servo system mainly consists of an SPWM (Sinusoidal Pulse Width Modulation) control circuit, a drive circuit, and a servo motor. The drive circuit comprises a rectifier, a DC bus, and an inverter. The SPWM control circuit receives control commands (i.e., voltage reference signals), modulates them, and outputs an SPWM drive signal to the drive circuit. This controls the switching of the inverter's power transistors, converting the DC power on the drive circuit's DC bus into AC power, which is then output to the servo motor to drive its operation. In SPWM control, a dead time must be set to prevent shoot-through between the inverter's upper and lower bridge arms. However, dead time can cause output voltage waveform distortion and harmonic generation, leading to torque pulsation, speed fluctuations, and positioning errors in the servo motor, severely impacting system performance. Currently, common dead-time compensation methods rely on software algorithms, which can be embedded in FPGAs (Field-Programmable Gate Arrays). These dead-time compensation methods compensate for the dead time, thereby offsetting its effects.

[0003] While there are some FPGA-based dead-time compensation schemes in the existing technology, the following problems still exist: First, the existing technology only relies on a single variable (such as voltage or current) for compensation, without comprehensively considering the influence of multiple factors such as load changes and speed fluctuations, resulting in limited compensation effect; Second, the existing technology uses complex methods such as analog integrator circuits, resulting in slow calculation speed and insufficient calculation time reserved for FPGA processing, making it difficult to meet the requirements of fast real-time response.

[0004] Therefore, in order to solve the above problems, there is an urgent need for a dead zone compensation method and system based on FPGA that can integrate multi-source information and achieve fast and high-precision dynamic compensation, so as to improve the control performance and operating efficiency of servo drive. Summary of the Invention

[0005] (1) Technical problems to be solved

[0006] The purpose of this invention is to provide a high-precision dead-time compensation method and system based on FPGA to achieve dead-time compensation for SPWM control.

[0007] (2) Technical solution

[0008] To achieve the above objectives, the present invention provides a high-precision dead-zone compensation method based on FPGA, the method comprising the following steps:

[0009] S1. Obtain the preset SPWM cycle length; divide the running time into SPWM cycles according to the SPWM cycle length; within the preset sampling window before the end of the current SPWM cycle, collect the actual output voltage waveform and integrate the absolute value of the actual output voltage waveform to obtain the first voltage integral value; collect the average value of the DC bus voltage of the drive circuit; based on the first voltage integral value, calculate the predicted full-cycle voltage integral value of the current SPWM cycle through a prediction algorithm, and record it as the second voltage integral value; subtract the second voltage integral value from the integral value of the preset ideal voltage absolute value to obtain the voltage integral difference; collect the servo motor speed data sequence within the preset speed sampling interval, and record it as the historical speed data sequence; obtain the dead time.

[0010] S2, the next SPWM cycle immediately following the current SPWM cycle is denoted as the target cycle; the average servo motor speed within the target cycle is predicted using an extrapolation algorithm based on the historical speed data sequence, and is denoted as the predicted speed.

[0011] S3. The first compensation amount is calculated using a feedback algorithm based on the voltage integral difference. The second compensation amount is calculated based on the average value of the DC bus voltage of the drive circuit and the dead time. The third compensation amount is calculated based on the average value of the historical speed data sequence and the predicted speed. The first compensation amount, the second compensation amount and the third compensation amount are added together to obtain the total compensation voltage.

[0012] S4. The total compensation voltage is superimposed with the preset ideal reference voltage to generate a compensated voltage reference signal. The compensated voltage reference signal is then input into the SPWM control circuit to control the on and off of the inverter power switch.

[0013] Further, the method of calculating the predicted full-cycle voltage integral value of the current SPWM cycle based on the first voltage integral value using a prediction algorithm, and denoting it as the second voltage integral value, includes:

[0014] The actual output voltage waveforms of the two SPWM cycles preceding the current SPWM cycle are acquired and sequentially denoted as the first historical output voltage waveform and the second historical output voltage waveform, respectively. The SPWM cycles corresponding to the first and second historical output voltage waveforms are denoted as the first historical cycle and the second historical cycle, respectively, where the second historical cycle is the SPWM cycle preceding the current SPWM cycle. The absolute value of the second historical output voltage waveform is integrated from the start point of the second historical cycle to a pre-set interruption point to obtain the interrupt integral. The time interval between the start point of the second historical cycle and the pre-set interruption point is equal to the length of the sampling window. The absolute value of the second historical output voltage waveform is integrated from the start point of the second historical cycle to the end point of the second historical cycle to obtain the full-wave integral. The ratio of the full-wave integral to the interrupt integral is calculated and denoted as the voltage proportionality coefficient. The length of the sampling window is less than the length of the SPWM cycle. The length of the SPWM cycle is an integer multiple of the 50 Hz fundamental wave cycle. The difference between the length of the SPWM cycle and the length of the sampling window is greater than the pre-set upper limit of the FPGA operation time.

[0015] Multiply the first voltage integral value by the voltage proportionality coefficient to obtain the second voltage integral value.

[0016] Furthermore, the method for predicting the average servo motor speed within the target period using an extrapolation algorithm based on historical speed data sequences, denoted as the predicted speed, includes:

[0017] Based on the historical speed data sequence, the average speed of the servo motor within the target period is obtained by fitting the data using the exponential smoothing method, and is denoted as the predicted speed.

[0018] Further, the method for calculating the first compensation amount using a feedback algorithm based on the voltage integral difference, calculating the second compensation amount based on the average DC bus voltage of the drive circuit and the dead time, calculating the third compensation amount based on the average value of the historical speed data sequence and the predicted speed, and adding the first compensation amount, the second compensation amount, and the third compensation amount to obtain the total compensation voltage includes:

[0019] The absolute values ​​of the first and second historical output voltage waveforms are integrated to obtain the first historical voltage integral value and the second historical voltage integral value. The integral values ​​of the first and second historical voltages are then subtracted from the integral values ​​of the first and second historical voltages and the absolute value of the ideal voltage to obtain the first historical integral difference and the second historical integral difference.

[0020] The reference compensation amount is calculated based on the first historical integral difference, the second historical integral difference, and the voltage integral difference; the formula for calculating the reference compensation amount is: ;

[0021] in, Indicates the baseline compensation amount. Indicates the first historical integral difference. Indicates the second historical integral difference. Represents the voltage integral difference. Indicates the SPWM period length; , , These represent the pre-set proportional coefficient, integral coefficient, and differential coefficient, respectively.

[0022] examine Is it at the pre-set first lower limit? Up to the first upper limit Within the interval; if If it falls within the range of the first lower limit to the first upper limit, then the first compensation amount will be... The value is set to ,like If it is less than the first lower limit, then the first compensation amount will be... The value is set to ,like If it exceeds the first upper limit, then the first compensation amount will be... The value is set to .

[0023] The second compensation amount is calculated based on the average DC bus voltage of the drive circuit and the dead time; the calculation formula for the second compensation amount is: ;

[0024] in, This indicates the second compensation amount. Indicates dead time. This represents the average value of the DC bus voltage of the drive circuit.

[0025] The average value of the historical speed data sequence is calculated; based on the average value of the historical speed data sequence and the predicted speed, a third compensation amount is calculated; the formula for calculating the third compensation amount is:

[0026] in, Indicates the third compensation amount; This represents the pre-set load voltage compensation coefficient; Indicates the predicted rotational speed; This represents the average value of a historical speed data series.

[0027] Add the first compensation amount, the second compensation amount, and the third compensation amount to obtain the total compensation voltage. .

[0028] Furthermore, the method of superimposing the total compensation voltage with a pre-set ideal reference voltage to generate a compensated voltage reference signal, and inputting the compensated voltage reference signal into the SPWM control circuit to control the on and off of the inverter power switching transistor includes:

[0029] Read the preset ideal reference voltage The total compensation voltage With the ideal reference voltage Perform algebraic addition to generate the first compensated voltage. ; for the first compensated voltage The voltage after the second compensation is obtained by performing amplitude limiting processing. ; the second compensated voltage The compensated voltage reference signal is used as the modulation wave input to the SPWM control circuit. It is compared with the pre-set triangular carrier signal to generate the compensated SPWM drive signal, which in turn controls the turn-on and turn-off of the inverter power switch.

[0030] Based on the same inventive concept, this invention also provides a high-precision dead-zone compensation system based on FPGA, the system comprising:

[0031] The data reading module is used to acquire the preset SPWM cycle length; divide the running time into SPWM cycles according to the SPWM cycle length; within the preset sampling window before the end of the current SPWM cycle, acquire the actual output voltage waveform and integrate the absolute value of the actual output voltage waveform to obtain the first voltage integral value; acquire the average value of the DC bus voltage of the drive circuit; based on the first voltage integral value, calculate the predicted full-cycle voltage integral value of the current SPWM cycle through a prediction algorithm, and record it as the second voltage integral value; subtract the second voltage integral value from the integral value of the preset ideal voltage absolute value to obtain the voltage integral difference; acquire the servo motor speed data sequence within the preset speed sampling interval, and record it as the historical speed data sequence; and acquire the dead time.

[0032] The speed prediction module, connected to the data reading module, is used to define the next SPWM cycle immediately following the current SPWM cycle as the target cycle; and to predict the average servo motor speed within the target cycle using an extrapolation algorithm based on historical speed data sequences, which is denoted as the predicted speed.

[0033] The voltage compensation module, connected to the speed prediction module, is used to calculate the first compensation amount based on the voltage integral difference using a feedback algorithm, calculate the second compensation amount based on the average value of the DC bus voltage of the drive circuit and the dead time, calculate the third compensation amount based on the average value of the historical speed data sequence and the predicted speed, and add the first compensation amount, the second compensation amount and the third compensation amount to obtain the total compensation voltage.

[0034] The modulation module, connected to the voltage compensation module, is used to superimpose the total compensation voltage with the preset ideal reference voltage to generate a compensated voltage reference signal. The compensated voltage reference signal is then input into the SPWM control circuit to control the on and off of the inverter power switching transistors.

[0035] Furthermore, the data reading module includes:

[0036] The integration module is used to acquire the actual output voltage waveforms of the two SPWM cycles preceding the current SPWM cycle, and chronologically record them as the first historical output voltage waveform and the second historical output voltage waveform, respectively. The SPWM cycles corresponding to the first and second historical output voltage waveforms are recorded as the first historical cycle and the second historical cycle, respectively; the second historical cycle is the SPWM cycle preceding the current SPWM cycle. The absolute value of the second historical output voltage waveform is integrated from the start point of the second historical cycle to a pre-set interruption point to obtain the interrupt integral. The time interval between the start point of the second historical cycle and the pre-set interruption point is equal to the length of the sampling window. The absolute value of the second historical output voltage waveform is integrated from the start point of the second historical cycle to the end point to obtain the full-wave integral. The ratio of the full-wave integral to the interrupt integral is calculated and recorded as the voltage proportionality coefficient. The length of the sampling window is less than the length of the SPWM cycle. The length of the SPWM cycle is an integer multiple of the 50 Hz fundamental wave cycle. The difference between the length of the SPWM cycle and the length of the sampling window is greater than the pre-set upper limit of the FPGA operation time.

[0037] The voltage prediction module, connected to the integration module, is used to multiply the first voltage integral value by the voltage proportionality coefficient to obtain the second voltage integral value.

[0038] Furthermore, the speed prediction module includes:

[0039] The exponential smoothing module is used to fit the historical speed data sequence using the exponential smoothing method to obtain the average speed of the servo motor within the target period, which is denoted as the predicted speed.

[0040] Furthermore, the voltage compensation module includes:

[0041] The integral difference calculation module is used to perform integral calculations on the absolute values ​​of the first historical output voltage waveform and the second historical output voltage waveform to obtain the first historical voltage integral value and the second historical voltage integral value; and to obtain the first historical integral difference and the second historical integral difference by subtracting the integral values ​​of the first historical voltage integral value and the second historical voltage integral value from the integral value of the absolute value of the ideal voltage.

[0042] The first compensation calculation module, connected to the integral difference calculation module, is used to calculate the reference compensation amount based on the first historical integral difference, the second historical integral difference, and the voltage integral difference; the calculation formula for the reference compensation amount is:

[0043] ;

[0044] in, Indicates the baseline compensation amount. Indicates the first historical integral difference. Indicates the second historical integral difference. Represents the voltage integral difference. Indicates the SPWM period length; , , These represent the pre-set proportional coefficient, integral coefficient, and differential coefficient, respectively.

[0045] examine Is it at the pre-set first lower limit? Up to the first upper limit Within the interval; if If it falls within the range of the first lower limit to the first upper limit, then the first compensation amount will be... The value is set to ,like If it is less than the first lower limit, then the first compensation amount will be... The value is set to ,like If it exceeds the first upper limit, then the first compensation amount will be... The value is set to .

[0046] The second compensation calculation module, connected to the first compensation calculation module, is used to calculate the second compensation amount based on the average value of the DC bus voltage of the drive circuit and the dead time; the calculation formula for the second compensation amount is:

[0047] ;

[0048] in, This indicates the second compensation amount. Indicates dead time. This represents the average value of the DC bus voltage of the drive circuit.

[0049] The third compensation calculation module, connected to the second compensation calculation module, is used to calculate the average value of the historical speed data sequence; and to calculate the third compensation amount based on the average value of the historical speed data sequence and the predicted speed; the calculation formula for the third compensation amount is as follows:

[0050] ;

[0051] in, Indicates the third compensation amount; This represents the pre-set load voltage compensation coefficient; Indicates the predicted rotational speed; This represents the average value of a historical speed data series.

[0052] The total compensation voltage calculation module, connected to the third compensation amount calculation module, is used to add the first compensation amount, the second compensation amount, and the third compensation amount to obtain the total compensation voltage. .

[0053] Furthermore, the modulation module includes:

[0054] The drive signal calculation module is used to read the preset ideal reference voltage. The total compensation voltage With the ideal reference voltage Perform algebraic addition to generate the first compensated voltage. ; for the first compensated voltage The voltage after the second compensation is obtained by performing amplitude limiting processing. ; the second compensated voltage The compensated voltage reference signal is used as the modulation wave input to the SPWM control circuit. It is compared with the pre-set triangular carrier signal to generate the compensated SPWM drive signal, which in turn controls the turn-on and turn-off of the inverter power switch.

[0055] (3) Beneficial effects

[0056] Compared with the prior art, the beneficial effects of the present invention are:

[0057] 1. Based on multi-source information such as voltage error, DC bus voltage fluctuation and load change, a composite compensation method combining feedback algorithm and multi-feedforward calculation is adopted to obtain the total compensation voltage that can dynamically and accurately offset nonlinear distortion, thereby improving the accuracy of dead zone compensation.

[0058] 2. Based on the integration result of the voltage waveform of the part that has not ended in the current SPWM cycle, the voltage proportional coefficient prediction method based on historical cycle data is adopted to obtain the full cycle voltage integral prediction value of the current cycle. This allows sufficient computing time for the FPGA, enabling all calculations to be completed in one cycle and then applied to the next cycle, thus improving the real-time response capability of the system. Attached Figure Description

[0059] Figure 1 This is a flowchart of the high-precision dead-zone compensation method based on FPGA according to Embodiment 1 of the present invention;

[0060] Figure 2 This is a schematic diagram of the module composition of the FPGA-based high-precision dead-zone compensation system in Embodiment 2 of the present invention. Detailed Implementation

[0061] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0062] Before giving examples, it is necessary to explain the application scenarios of the present invention. The present invention is applied to dynamically generating a compensated voltage reference signal, inputting the compensated voltage reference signal into the SPWM control circuit, and then controlling the on and off of the inverter power switch transistor, thereby realizing dead zone compensation.

[0063] Example 1: As Figure 1 As shown, this embodiment provides a high-precision dead-zone compensation method based on FPGA, the method including the following steps:

[0064] S1. Obtain the preset SPWM cycle length; divide the running time into SPWM cycles according to the SPWM cycle length; within the preset sampling window before the end of the current SPWM cycle, collect the actual output voltage waveform and integrate the absolute value of the actual output voltage waveform to obtain the first voltage integral value; collect the average value of the DC bus voltage of the drive circuit; based on the first voltage integral value, calculate the predicted full-cycle voltage integral value of the current SPWM cycle through a prediction algorithm, and record it as the second voltage integral value; subtract the second voltage integral value from the integral value of the preset ideal voltage absolute value to obtain the voltage integral difference; collect the servo motor speed data sequence within the preset speed sampling interval, and record it as the historical speed data sequence; obtain the dead time.

[0065] S2, the next SPWM cycle immediately following the current SPWM cycle is denoted as the target cycle; the average servo motor speed within the target cycle is predicted using an extrapolation algorithm based on the historical speed data sequence, and is denoted as the predicted speed.

[0066] S3. The first compensation amount is calculated using a feedback algorithm based on the voltage integral difference. The second compensation amount is calculated based on the average value of the DC bus voltage of the drive circuit and the dead time. The third compensation amount is calculated based on the average value of the historical speed data sequence and the predicted speed. The first compensation amount, the second compensation amount and the third compensation amount are added together to obtain the total compensation voltage.

[0067] S4. The total compensation voltage is superimposed with the preset ideal reference voltage to generate a compensated voltage reference signal. The compensated voltage reference signal is then input into the SPWM control circuit to control the on and off of the inverter power switch.

[0068] For example, the servo system mainly consists of an SPWM control circuit, a drive circuit, and a servo motor. The drive circuit comprises a rectifier, a DC bus of the drive circuit, and an inverter. A compensated voltage reference signal is calculated by the FPGA and transmitted to the SPWM control circuit. After modulation, the SPWM drive signal is output to the drive circuit, controlling the switching of the inverter's power switching transistors. This converts the DC power on the drive circuit's DC bus into AC power, which is then output to the servo motor to drive its operation. To prevent shoot-through of the inverter's upper and lower bridge arms, a dead time is set in the SPWM drive signal. However, the dead time causes distortion of the output voltage waveform and generates harmonics, leading to torque pulsation, speed fluctuations, and positioning errors in the servo motor, severely affecting system performance. Therefore, this embodiment generates a compensated voltage reference signal using the FPGA. The SPWM drive signal generated after modulation of the compensated voltage reference signal by the SPWM control circuit can dynamically compensate for the dead time, thereby reducing its impact. It is worth noting that the effect of dead-time compensation is related to the operating state of the servo motor, which is complex and variable. Therefore, this method cannot completely compensate for the impact of dead time, but it can minimize its influence to a certain extent. First, based on pre-set system parameters, a timer and logic control unit are used to obtain and divide a fixed SPWM period. This embodiment calculates a compensated voltage reference signal for each SPWM period to offset the impact of dead time as much as possible. A sampling window is pre-opened before the end of the current SPWM period. The starting point of the sampling window is the starting point of the current SPWM period, and the length of the sampling window is set to 80% of the SPWM period length. The remaining 20% ​​of the current SPWM period is used to meet the FPGA's computation time requirements. During the remaining 20% ​​of the current SPWM period, the FPGA needs to calculate the compensated voltage reference signal for the next SPWM period. Within the sampling window, a voltage sensor deployed at the inverter output is used to take the absolute value of the acquired actual output voltage waveform and perform integration to obtain the first voltage integral value. Simultaneously, a voltage sampling circuit is used to obtain the average voltage of the DC bus of the drive circuit. Then, based on the first voltage integral value, a prediction is made using historical data to obtain the predicted voltage integral value for the entire current SPWM cycle, which is denoted as the second voltage integral value. Finally, based on the integral value of the second voltage integral value and the integral value of the pre-set ideal voltage absolute value, a difference comparison method is used to obtain the final voltage integral difference. The voltage integral difference is caused by multiple factors. On the one hand, it is due to the dead-zone compensation error caused by changes in the servo motor's operating state. On the other hand, servo motor performance, SPWM control performance, and inverter performance also affect the voltage integral difference. A sensor is used to collect the servo motor speed data sequence within a pre-set speed sampling interval, which is denoted as the historical speed data sequence.The speed sampling range is determined based on the rate of change of the servo motor's operating state. If the servo motor operates relatively stably, the speed sampling range and sampling interval can be larger. However, if the servo motor's operating conditions change rapidly, the speed sampling range should be smaller, and the sampling interval should also be smaller. The preset dead time parameter is obtained from the system register.

[0069] Based on historical speed data sequences, an extrapolation algorithm is used for fitting calculations to obtain a predicted value of the average speed of the servo motor in the next SPWM cycle (i.e., the target cycle) immediately following the current cycle. This predicted speed is denoted as the predicted speed. The predicted speed is used to predict the dynamic change trend of the load in advance.

[0070] Using the FPGA's built-in modules, a feedback control algorithm is employed based on the voltage integral difference to obtain the first compensation amount for closed-loop error correction. Based on the average DC bus voltage of the drive circuit and the dead time, a formulaic calculation method based on the average voltage error model is used to obtain the second compensation amount to directly offset the voltage loss caused by the dead time. Based on the average value of historical speed data sequences and the predicted speed, a method is used to calculate the difference and multiply it by a coefficient to obtain the third compensation amount to compensate for voltage distortion effects caused by load changes. Finally, an algebraic summation method is used to add the first, second, and third compensation amounts to obtain the total compensation voltage used for final compensation.

[0071] Based on the total compensation voltage and the ideal reference voltage provided by the main controller, an algebraic summation and limiting method is used to obtain the compensated voltage reference signal. Finally, the compensated voltage reference signal is input to the SPWM control circuit, where it is compared with a triangular carrier wave as a modulation wave to obtain and generate the compensated SPWM drive signal. The compensated SPWM drive signal is then output to the drive circuit, thereby precisely controlling the on / off state of the power switches in the inverter and achieving high-precision dead-time compensation.

[0072] Further, the method of calculating the predicted full-cycle voltage integral value of the current SPWM cycle based on the first voltage integral value using a prediction algorithm, and denoting it as the second voltage integral value, includes:

[0073] The actual output voltage waveforms of the two SPWM cycles preceding the current SPWM cycle are acquired and sequentially denoted as the first historical output voltage waveform and the second historical output voltage waveform, respectively. The SPWM cycles corresponding to the first and second historical output voltage waveforms are denoted as the first historical cycle and the second historical cycle, respectively, where the second historical cycle is the SPWM cycle preceding the current SPWM cycle. The absolute value of the second historical output voltage waveform is integrated from the start point of the second historical cycle to a pre-set interruption point to obtain the interrupt integral. The time interval between the start point of the second historical cycle and the pre-set interruption point is equal to the length of the sampling window. The absolute value of the second historical output voltage waveform is integrated from the start point of the second historical cycle to the end point of the second historical cycle to obtain the full-wave integral. The ratio of the full-wave integral to the interrupt integral is calculated and denoted as the voltage proportionality coefficient. The length of the sampling window is less than the length of the SPWM cycle. The length of the SPWM cycle is an integer multiple of the 50 Hz fundamental wave cycle. The difference between the length of the SPWM cycle and the length of the sampling window is greater than the pre-set upper limit of the FPGA operation time.

[0074] Multiply the first voltage integral value by the voltage proportionality coefficient to obtain the second voltage integral value.

[0075] For example, firstly, the actual output voltage waveforms of the two consecutive cycles preceding the current SPWM cycle (i.e., the first historical cycle and the second historical cycle) are acquired. These two waveforms are then chronologically labeled as the first historical output voltage waveform and the second historical output voltage waveform, respectively. Starting from the beginning of the second historical cycle and ending at a specific interruption point, the absolute value of the second historical output voltage waveform is integrated; the resulting integral value is called the interruption integral. The time interval between the interruption point and the beginning is set to be exactly equal to the length of the sampling window. Then, starting from the beginning of the second historical cycle and ending at its end, the absolute value of the waveform is integrated to obtain the full-wave integral. A voltage scaling factor is calculated. This voltage scaling factor is the ratio of the full-wave integral to the interruption integral. Multiplying the obtained first voltage integral value by the voltage scaling factor yields the second voltage integral value. The second voltage integral value represents the predicted full-cycle voltage integral value of the current SPWM cycle.

[0076] Furthermore, the method for predicting the average servo motor speed within the target period using an extrapolation algorithm based on historical speed data sequences, denoted as the predicted speed, includes:

[0077] Based on the historical speed data sequence, the average speed of the servo motor within the target period is obtained by fitting the data using the exponential smoothing method, and is denoted as the predicted speed.

[0078] For example, the exponential smoothing method uses the historical speed data sequence as input and assigns different weights to data points at different times in the historical speed data sequence. Historical data points closer to the target period are assigned greater weights and have a greater impact on the prediction results. Conversely, data points farther away have their weights decay exponentially and have less influence. The exponential smoothing method can extract the mainstream trend of speed changes from the historical data sequence while filtering out short-term fluctuations and glitches caused by instantaneous load disturbances or measurement noise. This ensures that the final calculated average servo motor speed within the target period, i.e., the predicted speed, reflects the true operating trend of the system and has good anti-interference capabilities.

[0079] Further, the method for calculating the first compensation amount using a feedback algorithm based on the voltage integral difference, calculating the second compensation amount based on the average DC bus voltage of the drive circuit and the dead time, calculating the third compensation amount based on the average value of the historical speed data sequence and the predicted speed, and adding the first compensation amount, the second compensation amount, and the third compensation amount to obtain the total compensation voltage includes:

[0080] The absolute values ​​of the first and second historical output voltage waveforms are integrated to obtain the first historical voltage integral value and the second historical voltage integral value. The integral values ​​of the first and second historical voltages are then subtracted from the integral values ​​of the first and second historical voltages and the absolute value of the ideal voltage to obtain the first historical integral difference and the second historical integral difference.

[0081] The reference compensation amount is calculated based on the first historical integral difference, the second historical integral difference, and the voltage integral difference; the formula for calculating the reference compensation amount is:

[0082] ;

[0083] in, Indicates the baseline compensation amount. Indicates the first historical integral difference. Indicates the second historical integral difference. Represents the voltage integral difference. Indicates the SPWM period length; , , These represent the pre-set proportional coefficient, integral coefficient, and differential coefficient, respectively.

[0084] examine Is it at the pre-set first lower limit? Up to the first upper limit Within the interval; if If it falls within the range of the first lower limit to the first upper limit, then the first compensation amount will be... The value is set to ,like If it is less than the first lower limit, then the first compensation amount will be... The value is set to ,like If it exceeds the first upper limit, then the first compensation amount will be... The value is set to .

[0085] The second compensation amount is calculated based on the average DC bus voltage of the drive circuit and the dead time; the calculation formula for the second compensation amount is:

[0086] ;

[0087] in, This indicates the second compensation amount. Indicates dead time. This represents the average value of the DC bus voltage of the drive circuit.

[0088] The average value of the historical speed data sequence is calculated; based on the average value of the historical speed data sequence and the predicted speed, a third compensation amount is calculated; the formula for calculating the third compensation amount is:

[0089] ;

[0090] in, Indicates the third compensation amount; This represents the pre-set load voltage compensation coefficient; Indicates the predicted rotational speed; This represents the average value of a historical speed data series.

[0091] Add the first compensation amount, the second compensation amount, and the third compensation amount to obtain the total compensation voltage. .

[0092] For example, an error benchmark for feedback control is first established through integration and difference calculation. The absolute values ​​of the first and second historical output voltage waveforms are integrated respectively to obtain the first and second historical voltage integral values. These are then subtracted from the integral value of the ideal voltage absolute value to obtain the first historical integral difference and the second historical integral difference. The first historical integral difference, the second historical integral difference, and the voltage integral difference of the current period together constitute a data sequence characterizing the voltage error change trend. The first historical integral difference, the second historical integral difference, and the voltage integral difference of the current period not only reflect the change in the fundamental voltage but also take into account the harmonic voltages.

[0093] Then, a feedback control algorithm is used to calculate the reference compensation amount based on the first historical integral difference, the second historical integral difference, and the voltage integral difference. This feedback control algorithm comprehensively considers the current value of the error (proportional term), the cumulative effect of the error (integral term), and the trend of error change (differential term), aiming to quickly eliminate steady-state error and suppress overshoot. To ensure the stability of the calculation, the reference compensation amount is limited to obtain the first compensation amount. Based on the feedback compensation, the method also introduces two feedforward compensations: a second compensation amount and a third compensation amount. The second compensation amount is a direct feedforward amount, calculated using a formula based on the average DC bus voltage of the drive circuit and the dead time. This second compensation amount aims to quickly and directly offset the average voltage loss caused by the dead time itself. The third compensation amount is an adaptive feedforward amount, calculated based on the difference between the average value of the historical speed data sequence and the predicted speed. The third compensation amount is essentially a load observer, which indirectly infers the change in load torque by the trend of speed change, and compensates in advance for the dead zone effect and other distortions caused by load changes, thereby improving the compensation accuracy of the algorithm under dynamic conditions such as acceleration and deceleration.

[0094] Finally, the first, second, and third compensation values ​​are added together to obtain the total compensation voltage. This total compensation voltage combines the precision of feedback control with the speed of feedforward control, thus achieving a balance between high precision and fast response.

[0095] Furthermore, the method of superimposing the total compensation voltage with a pre-set ideal reference voltage to generate a compensated voltage reference signal, and inputting the compensated voltage reference signal into the SPWM control circuit to control the on and off of the inverter power switching transistor includes:

[0096] Read the preset ideal reference voltage The total compensation voltage With the ideal reference voltage Perform algebraic addition to generate the first compensated voltage. ; for the first compensated voltage The voltage after the second compensation is obtained by performing amplitude limiting processing. ; the second compensated voltage The compensated voltage reference signal is used as the modulation wave input to the SPWM control circuit. It is compared with the pre-set triangular carrier signal to generate the compensated SPWM drive signal, which in turn controls the turn-on and turn-off of the inverter power switch.

[0097] For example, the ideal reference voltage is expected to be a pure sine wave command.

[0098] Example 2: Based on the same inventive concept, such as Figure 2 As shown, this embodiment also provides a high-precision dead-time compensation system based on FPGA, the system comprising:

[0099] The data reading module is used to acquire the preset SPWM cycle length; divide the running time into SPWM cycles according to the SPWM cycle length; within the preset sampling window before the end of the current SPWM cycle, acquire the actual output voltage waveform and integrate the absolute value of the actual output voltage waveform to obtain the first voltage integral value; acquire the average value of the DC bus voltage of the drive circuit; based on the first voltage integral value, calculate the predicted full-cycle voltage integral value of the current SPWM cycle through a prediction algorithm, and record it as the second voltage integral value; subtract the second voltage integral value from the integral value of the preset ideal voltage absolute value to obtain the voltage integral difference; acquire the servo motor speed data sequence within the preset speed sampling interval, and record it as the historical speed data sequence; and acquire the dead time.

[0100] The speed prediction module, connected to the data reading module, is used to define the next SPWM cycle immediately following the current SPWM cycle as the target cycle; and to predict the average servo motor speed within the target cycle using an extrapolation algorithm based on historical speed data sequences, which is denoted as the predicted speed.

[0101] The voltage compensation module, connected to the speed prediction module, is used to calculate the first compensation amount based on the voltage integral difference using a feedback algorithm, calculate the second compensation amount based on the average value of the DC bus voltage of the drive circuit and the dead time, calculate the third compensation amount based on the average value of the historical speed data sequence and the predicted speed, and add the first compensation amount, the second compensation amount and the third compensation amount to obtain the total compensation voltage.

[0102] The modulation module, connected to the voltage compensation module, is used to superimpose the total compensation voltage with the preset ideal reference voltage to generate a compensated voltage reference signal. The compensated voltage reference signal is then input into the SPWM control circuit to control the on and off of the inverter power switching transistors.

[0103] Furthermore, the data reading module includes:

[0104] The integration module is used to acquire the actual output voltage waveforms of the two SPWM cycles preceding the current SPWM cycle, and chronologically record them as the first historical output voltage waveform and the second historical output voltage waveform, respectively. The SPWM cycles corresponding to the first and second historical output voltage waveforms are recorded as the first historical cycle and the second historical cycle, respectively; the second historical cycle is the SPWM cycle preceding the current SPWM cycle. The absolute value of the second historical output voltage waveform is integrated from the start point of the second historical cycle to a pre-set interruption point to obtain the interrupt integral. The time interval between the start point of the second historical cycle and the pre-set interruption point is equal to the length of the sampling window. The absolute value of the second historical output voltage waveform is integrated from the start point of the second historical cycle to the end point to obtain the full-wave integral. The ratio of the full-wave integral to the interrupt integral is calculated and recorded as the voltage proportionality coefficient. The length of the sampling window is less than the length of the SPWM cycle. The length of the SPWM cycle is an integer multiple of the 50 Hz fundamental wave cycle. The difference between the length of the SPWM cycle and the length of the sampling window is greater than the pre-set upper limit of the FPGA operation time.

[0105] The voltage prediction module, connected to the integration module, is used to multiply the first voltage integral value by the voltage proportionality coefficient to obtain the second voltage integral value.

[0106] Furthermore, the speed prediction module includes:

[0107] The exponential smoothing module is used to fit the historical speed data sequence using the exponential smoothing method to obtain the average speed of the servo motor within the target period, which is denoted as the predicted speed.

[0108] Furthermore, the voltage compensation module includes:

[0109] The integral difference calculation module is used to perform integral calculations on the absolute values ​​of the first historical output voltage waveform and the second historical output voltage waveform to obtain the first historical voltage integral value and the second historical voltage integral value; and to obtain the first historical integral difference and the second historical integral difference by subtracting the integral values ​​of the first historical voltage integral value and the second historical voltage integral value from the integral value of the absolute value of the ideal voltage.

[0110] The first compensation calculation module, connected to the integral difference calculation module, is used to calculate the reference compensation amount based on the first historical integral difference, the second historical integral difference, and the voltage integral difference; the calculation formula for the reference compensation amount is:

[0111] ;

[0112] in, Indicates the baseline compensation amount. Indicates the first historical integral difference. Indicates the second historical integral difference. Represents the voltage integral difference. Indicates the SPWM period length; , , These represent the pre-set proportional coefficient, integral coefficient, and differential coefficient, respectively.

[0113] examine Is it at the pre-set first lower limit? Up to the first upper limit Within the interval; if If it falls within the range of the first lower limit to the first upper limit, then the first compensation amount will be... The value is set to ,like If it is less than the first lower limit, then the first compensation amount will be... The value is set to ,like If it exceeds the first upper limit, then the first compensation amount will be... The value is set to .

[0114] The second compensation calculation module, connected to the first compensation calculation module, is used to calculate the second compensation amount based on the average value of the DC bus voltage of the drive circuit and the dead time; the calculation formula for the second compensation amount is:

[0115] ;

[0116] in, This indicates the second compensation amount. Indicates dead time. This represents the average value of the DC bus voltage of the drive circuit.

[0117] The third compensation calculation module, connected to the second compensation calculation module, is used to calculate the average value of the historical speed data sequence; and to calculate the third compensation amount based on the average value of the historical speed data sequence and the predicted speed; the calculation formula for the third compensation amount is as follows:

[0118] ;

[0119] in, Indicates the third compensation amount; This represents the pre-set load voltage compensation coefficient; Indicates the predicted rotational speed; This represents the average value of a historical speed data series.

[0120] The total compensation voltage calculation module, connected to the third compensation amount calculation module, is used to add the first compensation amount, the second compensation amount, and the third compensation amount to obtain the total compensation voltage. .

[0121] Furthermore, the modulation module includes:

[0122] The drive signal calculation module is used to read the preset ideal reference voltage. The total compensation voltage With the ideal reference voltage Perform algebraic addition to generate the first compensated voltage. ; for the first compensated voltage The voltage after the second compensation is obtained by performing amplitude limiting processing. ; the second compensated voltage The compensated voltage reference signal is used as the modulation wave input to the SPWM control circuit. It is compared with the pre-set triangular carrier signal to generate the compensated SPWM drive signal, which in turn controls the turn-on and turn-off of the inverter power switch.

[0123] It should be noted that the specific methods by which each module performs operations in the system described in the above embodiments have been described in detail in the embodiments related to the method, and will not be elaborated here.

[0124] Finally, it should be noted that although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high-precision dead-time compensation method based on FPGA, characterized in that, The method comprises the following steps: S1, obtaining a pre-set SPWM cycle length; dividing a running time into SPWM cycles according to the SPWM cycle length; collecting an actual output voltage waveform and integrating an absolute value of the actual output voltage waveform in a pre-set sampling window before the end of a current SPWM cycle to obtain a first voltage integral value; collecting a driving circuit DC bus voltage average value; calculating a predicted full-cycle voltage integral value of the current SPWM cycle by a prediction algorithm according to the first voltage integral value, and recording the value as a second voltage integral value; obtaining a voltage integral difference by subtracting an integral value of a pre-set ideal voltage absolute value from the second voltage integral value; collecting a servo motor speed data sequence in a pre-set speed sampling interval, and recording the sequence as a historical speed data sequence; and obtaining a dead time; S2, recording a next SPWM cycle following the current SPWM cycle as a target cycle; predicting a servo motor speed average value in the target cycle by an extrapolation algorithm according to the historical speed data sequence, and recording the value as a predicted speed; S3, calculating a first compensation amount by a feedback algorithm according to the voltage integral difference, calculating a second compensation amount according to the driving circuit DC bus voltage average value and the dead time, calculating a third compensation amount according to an average value of the historical speed data sequence and the predicted speed, and adding the first compensation amount, the second compensation amount and the third compensation amount to obtain a total compensation voltage; S4, superimposing the total compensation voltage on a pre-set ideal reference voltage to generate a compensated voltage reference signal, inputting the compensated voltage reference signal into an SPWM control circuit, and then controlling the turn-on and turn-off of an inverter power switch tube.

2. The FPGA-based high-precision dead-time compensation method of claim 1, wherein, The method of calculating a predicted full-cycle voltage integral value of the current SPWM cycle by a prediction algorithm according to the first voltage integral value, and recording the value as a second voltage integral value comprises: obtaining actual output voltage waveforms in the first two SPWM cycles of the current SPWM cycle, and recording the waveforms in the order of time as a first historical output voltage waveform and a second historical output voltage waveform respectively; recording the SPWM cycles corresponding to the first historical output voltage waveform and the second historical output voltage waveform as a first historical cycle and a second historical cycle respectively; wherein the second historical cycle is the SPWM cycle preceding the current SPWM cycle; integrating the absolute value of the second historical output voltage waveform from the start of the second historical cycle to a pre-set breaking point to obtain a breaking integral; the time interval between the start of the second historical cycle and the pre-set breaking point is equal to the length of the sampling window; integrating the absolute value of the second historical output voltage waveform from the start of the second historical cycle to the end of the second historical cycle to obtain a full-wave integral; calculating a ratio of the full-wave integral to the breaking integral, and recording the ratio as a voltage proportionality coefficient; the length of the sampling window is less than the length of the SPWM cycle; the length of the SPWM cycle is an integer multiple of a 50 Hz fundamental wave cycle; the difference between the length of the SPWM cycle and the length of the sampling window is greater than a pre-set upper limit of FPGA operation time; multiplying the first voltage integral value by the voltage proportionality coefficient to obtain the second voltage integral value.

3. The FPGA-based high-precision dead-time compensation method of claim 2, wherein, The method for predicting the average speed of the servo motor in the target period according to the historical speed data sequence by using an extrapolation algorithm comprises the following steps: The average speed of the servo motor in the target period is fitted by using an exponential smoothing method according to the historical speed data sequence, and is recorded as the predicted speed.

4. The FPGA-based high-precision dead-time compensation method of claim 3, wherein, The method for calculating the total compensation voltage comprises the following steps: The absolute values of the first historical output voltage waveform and the second historical output voltage waveform are integrated to obtain the first historical voltage integral value and the second historical voltage integral value, respectively; and the first historical voltage integral value and the second historical voltage integral value are subtracted from the integral value of the absolute value of the ideal voltage to obtain the first historical integral difference and the second historical integral difference, respectively. The reference compensation amount is calculated according to the first historical integral difference, the second historical integral difference and the voltage integral difference; and the calculation formula of the reference compensation amount is as follows: ； wherein, represents a reference compensation amount, represents a first historical integral difference, represents a second historical integral difference, represents a voltage integral difference, represents an SPWM cycle length; , , respectively represent a pre-set proportional coefficient, an integral coefficient, and a differential coefficient. checking whether the value is within a preset first lower limit to a first upper limit interval; if the value is within the first lower limit to the first upper limit interval, the value of the first compensation amount is set to , if the value is less than the first lower limit, the value of the first compensation amount is set to , if the value is greater than the first upper limit, the value of the first compensation amount is set to ; The second compensation amount is calculated according to the average value of the DC bus voltage of the driving circuit and the dead time; and the calculation formula of the second compensation amount is as follows: ； wherein represents a second compensation quantity, represents a dead time, represents a drive circuit DC bus voltage average value; The average value of the historical speed data sequence is calculated; the third compensation amount is calculated according to the average value of the historical speed data sequence and the predicted speed; and the calculation formula of the third compensation amount is as follows: ； wherein, represents a third compensation amount; represents a pre-set load voltage compensation coefficient; represents a predicted rotational speed; represents an average value of a historical rotational speed data sequence; adding the first compensation amount, the second compensation amount, and the third compensation amount to obtain a total compensation voltage .

5. The FPGA-based high-precision dead-time compensation method of claim 4, wherein, The method for generating the compensated voltage reference signal by superimposing the total compensation voltage on the ideal reference voltage and inputting the compensated voltage reference signal into the SPWM control circuit to control the conduction and turn-off of the power switch tube of the inverter comprises the following steps: reading a pre-set ideal reference voltage ; algebraically adding the total compensation voltage to the ideal reference voltage to generate a first compensated voltage ; limiting the first compensated voltage to obtain a second compensated voltage ; recording the second compensated voltage as a compensated voltage reference signal; inputting the compensated voltage reference signal as a modulation wave into an SPWM control circuit, comparing the compensated voltage reference signal with a pre-set triangular carrier signal to generate a compensated SPWM driving signal, and further controlling the turn-on and turn-off of the power switch tubes of the inverter.

6. A high-precision dead-time compensation system based on FPGA, characterized in that, The system comprises: The data reading module is configured to obtain the pre-set SPWM period length; divide the running time into SPWM periods according to the SPWM period length; collect the actual output voltage waveform and integrate the absolute value of the actual output voltage waveform to obtain the first voltage integral value in a pre-set sampling window before the end of the current SPWM period; collect the average value of the DC bus voltage of the driving circuit; calculate the predicted full-period voltage integral value of the current SPWM period by using a prediction algorithm according to the first voltage integral value, and record the second voltage integral value; subtract the integral value of the pre-set ideal voltage absolute value from the second voltage integral value to obtain the voltage integral difference; collect the speed data sequence of the servo motor in a pre-set speed sampling interval, and record the historical speed data sequence; and obtain the dead time. The speed prediction module is connected with the data reading module and is configured to record the next SPWM period as the target period after the current SPWM period; and predict the average speed of the servo motor in the target period according to the historical speed data sequence by using an extrapolation algorithm, and record the predicted speed. The voltage compensation module is connected with the rotation speed prediction module, and is configured to calculate a first compensation amount by using a feedback algorithm according to the voltage integral difference, calculate a second compensation amount according to the average value of the DC bus voltage of the driving circuit and the dead time, calculate a third compensation amount according to the average value of the historical rotation speed data sequence and the predicted rotation speed, and add the first compensation amount, the second compensation amount and the third compensation amount to obtain a total compensation voltage; The modulation module is connected with the voltage compensation module, and is configured to superimpose the total compensation voltage and a pre-set ideal reference voltage to generate a compensated voltage reference signal, and input the compensated voltage reference signal into an SPWM control circuit to control the turn-on and turn-off of the power switch tube of the inverter.

7. The FPGA-based high-precision dead-time compensation system of claim 6, wherein, The data reading module comprises: The integral module is configured to obtain actual output voltage waveforms in the first two SPWM periods of a current SPWM period, and sequentially record the actual output voltage waveforms as a first historical output voltage waveform and a second historical output voltage waveform in chronological order; record the SPWM periods corresponding to the first historical output voltage waveform and the second historical output voltage waveform as a first historical period and a second historical period respectively; the second historical period is a SPWM period preceding the current SPWM period; integrate the absolute value of the second historical output voltage waveform from the start point of the second historical period to a pre-set interruption point to obtain an interruption integral; the time interval between the start point of the second historical period and the pre-set interruption point is equal to the length of a sampling window; integrate the absolute value of the second historical output voltage waveform from the start point of the second historical period to the end point of the second historical period to obtain a full-wave integral; calculate the ratio of the full-wave integral to the interruption integral, and record the ratio as a voltage proportionality coefficient; the length of the sampling window is less than the length of the SPWM period; the length of the SPWM period is an integer multiple of the fundamental wave period of 50 Hz; the difference between the length of the SPWM period and the length of the sampling window is greater than a pre-set upper limit of FPGA operation time; The voltage prediction module is connected with the integral module, and is configured to multiply the first voltage integral value by the voltage proportionality coefficient to obtain a second voltage integral value.

8. The FPGA-based high-precision dead-time compensation system of claim 7, wherein, The rotation speed prediction module comprises: The exponential smoothing module is configured to fit the average value of the rotation speed of a target period according to the historical rotation speed data sequence by using an exponential smoothing method, and record the average value as a predicted rotation speed.

9. The FPGA-based high-precision dead-time compensation system of claim 8, wherein, The voltage compensation module comprises: The integral difference calculation module is configured to integrate the absolute value of the first historical output voltage waveform and the absolute value of the second historical output voltage waveform respectively to obtain a first historical voltage integral value and a second historical voltage integral value; and subtract the first historical voltage integral value and the second historical voltage integral value from the integral value of the absolute value of the ideal voltage respectively to obtain a first historical integral difference and a second historical integral difference; The first compensation amount calculation module is connected with the integral difference calculation module, and is configured to calculate a reference compensation amount according to the first historical integral difference, the second historical integral difference and the voltage integral difference; and the calculation formula of the reference compensation amount is: ； wherein, represents a reference compensation amount, represents a first historical integral difference, represents a second historical integral difference, represents a voltage integral difference, represents an SPWM cycle length; , , respectively represent a pre-set proportional coefficient, an integral coefficient, and a differential coefficient. checking whether the value is within a preset first lower limit to a first upper limit interval; if the value is within the first lower limit to the first upper limit interval, the value of the first compensation amount is set to , if the value is less than the first lower limit, the value of the first compensation amount is set to , if the value is greater than the first upper limit, the value of the first compensation amount is set to ; The second compensation quantity calculation module is connected with the first compensation quantity calculation module and is configured to calculate a second compensation quantity according to the average value of the DC bus voltage of the drive circuit and the dead time. ； wherein represents a second compensation quantity, represents a dead time, represents a drive circuit DC bus voltage average value; The third compensation quantity calculation module is connected with the second compensation quantity calculation module and is configured to calculate an average value of the historical speed data sequence, and calculate a third compensation quantity according to the average value of the historical speed data sequence and the predicted speed. The calculation formula of the third compensation quantity is as follows: ； wherein, represents a third compensation amount; represents a preset load voltage compensation coefficient; represents a predicted rotation speed; represents an average value of a historical rotation speed data sequence; The total compensation voltage calculation module is connected with the third compensation amount calculation module, and is configured to add the first compensation amount, the second compensation amount and the third compensation amount to obtain a total compensation voltage .

10. The FPGA-based high-precision dead-time compensation system of claim 9, wherein, The modulation module comprises: The drive signal calculation module is configured to read an ideal reference voltage set in advance ; perform algebraic addition on the total compensation voltage and the ideal reference voltage to generate a first compensated voltage ; perform amplitude limiting processing on the first compensated voltage to obtain a second compensated voltage ; take the second compensated voltage as a compensated voltage reference signal; and input the compensated voltage reference signal as a modulation wave into an SPWM control circuit, compare the compensated voltage reference signal with a triangular carrier signal set in advance, and generate a compensated SPWM drive signal to control the turn-on and turn-off of the power switch tube of the inverter.

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