Key expansion system and encryption / decryption system

Abstract

The application relates to the technical field of data security, in particular to a key expansion system and an encryption and decryption system. The key expansion system at least comprises: at least eight registers, the eight registers at least comprising sequentially configured: a zeroth register, a first register, a second register, a third register, a fourth register, a fifth register, a sixth register and a seventh register; at least six selectors, the selectors being used for selecting from two registers to read and write a key; a logic processor being signal-connected with each selector and each register, the logic processor being used for performing a round key addition operation iteration according to a previous round key output by the selector and a subkey output by a previous-stage logic processor, and storing a result round key output in iteration in a corresponding register in sequence. The key expansion system has higher compatibility, better timing, higher round key expansion efficiency and lower cost.

Description

Technical Field

[0001] This application relates to the field of data security technology, specifically to a key expansion system and an encryption / decryption system. Background Technology

[0002] AES is an advanced encryption method in cryptography, also known as Rijndael encryption. It was released by the National Institute of Standards and Technology (NIST) on November 26, 2001, in FIPS PUB 197, and became an effective standard on May 26, 2002. It was mainly used to replace the original DES (Data Encryption Standard). By 2006, the algorithm had become one of the most popular algorithms in modern symmetric cryptography.

[0003] AES is an iterative block cipher that supports 128-bit plaintext blocks. The number of encryption rounds varies with the key length. Common key lengths include 128, 192, and 256 bits, corresponding to 10, 12, and 14 encryption rounds respectively. Based on the key length characteristics, this algorithm is also known as AES-128, AES-192, and AES-256. Except for the final round, each round of the AES encryption algorithm contains four steps: byte substitution, row shifting, column mixing, and round key addition (AddRoundKey). Round key addition is one of the core components of the AES encryption algorithm, making its security crucial. The AddRoundKey step is required in the AES encryption and decryption process, performing an XOR operation with the round key (roundkey). The round key is obtained through the keyexpansion algorithm. However, in the current encryption and decryption process, the key expansion calculation path is long, the timing is poor, and it consumes a lot of registers, resulting in wasted resources.

[0004] Therefore, the current AES encryption method has a long path, poor timing, and consumes a lot of registers. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a key expansion system and an encryption / decryption system.

[0006] A first aspect of the embodiments of this application provides a key expansion system, comprising at least:

[0007] At least eight registers, which include at least the following sequentially configured registers: register zero, register one, register two, register three, register four, register five, register six, and register seven.

[0008] At least six two-to-one selectors, wherein each selector is connected to two registers, and the selector is used to select from the two registers to read or write the key;

[0009] A logic processor is connected to each of the selectors and each of the register signals respectively. The logic processor is used to perform a round key addition operation iteratively based on the previous round key output by the selector and the subkey output by the previous level logic processor, and store the round key output by the iteration in the corresponding register in sequence.

[0010] In one optional embodiment of this application, the at least six two-to-one selectors include at least: a zeroth selector, a first selector, a second selector, a third selector, a fourth selector, and a fifth selector, wherein,

[0011] The zeroth selector is connected to the zeroth register, the fourth register, and the logic processor signal, respectively;

[0012] The first selector is connected to the first register, the fifth register, and the logic processor signal, respectively;

[0013] The second selector is connected to the zeroth register, the second register, and the logic processor signal, respectively;

[0014] The third selector is connected to the first register, the third register, and the logic processor signal, respectively;

[0015] The fourth selector is connected to the second register, the sixth register, and the logic processor signals, respectively;

[0016] The fifth selector is connected to the third register, the seventh register, and the logic processor signal, respectively.

[0017] In one optional embodiment of this application, the logic processor includes at least six XOR logic processors, each corresponding to one of the selectors. Each XOR logic processor is signal-connected to the corresponding selector and the two registers connected to the selector. Each XOR logic processor is used to perform XOR processing on the previous round key selected and output by the selector and the subkey output by the previous level logic processor, and output the result round key. The iteratively output result round key is then stored sequentially in the corresponding register.

[0018] In an optional embodiment of this application, the logic processor further includes:

[0019] An encryption port and a decryption port; wherein, during encryption, the encryption port is connected to each register and the XOR logic processor signal, and the decryption port is disconnected; during decryption, the decryption port is connected to each register and the XOR logic processor signal, and the encryption port is disconnected.

[0020] In an optional embodiment of this application, the above-described key expansion system further includes:

[0021] A module selector is connected to a first XOR logic processor and a fourth XOR logic processor respectively. The module selector is used to short-circuit with the second XOR logic processor and the third XOR logic processor when the key length of the round key is 128 bits or 256 bits. The second XOR logic processor is the XOR logic processor connected to the second selector, and the third XOR logic processor is the XOR logic processor connected to the third selector.

[0022] In an optional embodiment of this application, if the key length of the round key is 128 bits, then each round key addition operation iteration includes:

[0023] The initial key is configured in the zeroth register, the first register, the second register, and the third register to obtain the zeroth round key;

[0024] The zeroth XOR logic processor performs a byte transformation on the subkey output from the third register and then performs an XOR operation with the subkey stored in the zeroth register to obtain the zeroth subkey of the current round key, and stores the zeroth subkey in the zeroth register.

[0025] The first XOR logic processor performs an XOR operation between the subkey output by the zeroth XOR logic processor and the subkey stored in the first register to obtain the first subkey of the current round key, and stores the first subkey in the first register;

[0026] The fourth XOR logic processor performs an XOR operation between the subkey output by the first XOR logic processor and the subkey stored in the second register to obtain the second subkey of the current round key, and stores the second subkey in the second register;

[0027] The fifth XOR logic processor performs an XOR operation between the subkey output by the fourth XOR logic processor and the subkey stored in the third register to obtain the third subkey of the current round key, and stores the third subkey in the third register.

[0028] In an optional embodiment of this application, if the key length of the round key is 256 bits, then each round key addition operation iteration includes:

[0029] The initial key is configured in the zeroth register, the first register, the second register, the third register, the fourth register, the fifth register, the sixth register, and the seventh register to obtain the zeroth round key;

[0030] The zeroth XOR logic processor performs a byte transformation on the subkey output from the seventh register and then performs an XOR operation with the subkey stored in the zeroth register to obtain the zeroth subkey of the current round key, and stores the zeroth subkey in the zeroth register;

[0031] The first XOR logic processor performs an XOR operation between the subkey output by the zeroth XOR logic processor and the subkey stored in the first register to obtain the first subkey of the current round key, and stores the first subkey in the first register;

[0032] The fourth XOR logic processor performs an XOR operation between the subkey output by the first XOR logic processor and the subkey stored in the second register to obtain the second subkey of the current round key, and stores the second subkey in the second register.

[0033] The fifth XOR logic processor performs an XOR operation between the subkey output by the fourth XOR logic processor and the subkey stored in the third register to obtain the third subkey of the current round key, and stores the third subkey in the third register.

[0034] The zeroth XOR logic processor performs a byte transformation on the subkey output from the third register and an XOR operation with the subkey stored in the fourth register to obtain the fourth subkey of the current round key, and stores the fourth subkey in the fourth register.

[0035] The first XOR logic processor performs an XOR operation on the subkey output by the zeroth XOR logic processor and the subkey stored in the fifth register to obtain the fifth subkey of the current round key, and stores the fifth subkey in the fifth register;

[0036] The fourth XOR logic processor performs an XOR operation on the subkey output by the first XOR logic processor and the subkey stored in the sixth register to obtain the sixth subkey of the current round key, and stores the sixth subkey in the sixth register;

[0037] The fifth XOR logic processor performs an XOR operation between the subkey output by the fourth XOR logic processor and the subkey stored in the seventh register to obtain the seventh subkey of the current round key, and stores the seventh subkey in the seventh register.

[0038] In an optional embodiment of this application, if the key length of the round key is 192 bits, then the iteration of the round key addition operation between every two consecutive rounds includes:

[0039] The initial key is configured in the zeroth register, the first register, the second register, the third register, the sixth register, and the seventh register to obtain the zeroth round key;

[0040] The zeroth XOR logic processor performs a byte transformation on the subkey output from the seventh register in the zeroth round key and an XOR operation with the subkey stored in the zeroth register to obtain the zeroth subkey of the current round key, and stores the zeroth subkey in the fourth register;

[0041] The first XOR logic processor performs an XOR operation on the subkey output by the zeroth XOR logic processor and the subkey stored in the first register to obtain the first subkey of the current round key, and stores the first subkey in the fifth register;

[0042] The second XOR logic processor performs an XOR operation on the subkey output by the first XOR logic processor and the subkey stored in the second register to obtain the second subkey of the current round key, and stores the second subkey in the zeroth register;

[0043] The third XOR logic processor performs an XOR operation on the subkey output by the second XOR logic processor and the subkey stored in the third register to obtain the third subkey of the current round key, and stores the third subkey in the first register;

[0044] The fourth XOR logic processor performs an XOR operation between the subkey output by the third XOR logic processor and the subkey stored in the sixth register to obtain the fourth subkey of the current round key, and stores the fourth subkey in the second register;

[0045] The fifth XOR logic processor performs an XOR operation between the subkey output by the fourth XOR logic processor and the subkey stored in the seventh register to obtain the fifth subkey of the current round key, and stores the fifth subkey in the third register;

[0046] The zeroth XOR logic processor performs a byte transformation on the subkey output from the third register in the first round key and an XOR operation with the subkey stored in the fourth register to obtain the zeroth subkey of the next round key, and stores the zeroth subkey in the zeroth register.

[0047] The first XOR logic processor performs an XOR operation between the subkey output by the zeroth XOR logic processor and the subkey stored in the fifth register to obtain the first subkey of the next round key, and stores the first subkey in the first register;

[0048] The second XOR logic processor performs an XOR operation between the subkey output by the first XOR logic processor and the subkey stored in the zero register to obtain the second subkey of the next round key, and stores the second subkey in the second register;

[0049] The third XOR logic processor performs an XOR operation between the subkey output by the second XOR logic processor and the subkey stored in the first register to obtain the third subkey for the next round of keys, and stores the third subkey in the third register.

[0050] The fourth XOR logic processor performs an XOR operation between the subkey output by the third XOR logic processor and the subkey stored in the second register to obtain the fourth subkey of the next round key, and stores the fourth subkey in the sixth register;

[0051] The fifth XOR logic processor performs an XOR operation between the subkey output by the fourth XOR logic processor and the subkey stored in the third register to obtain the fifth subkey for the next round of keys, and stores the fifth subkey in the seventh register.

[0052] In one optional embodiment of this application, each register is a word register.

[0053] A second aspect of this application provides an encryption / decryption system, including the key expansion system as described in any of the preceding claims.

[0054] The key expansion system provided in this application includes at least eight registers, at least six 2-to-1 selectors, and a logic processor. The selectors select from the two registers to read and write keys. The logic processor is connected to each selector and each register. The logic processor performs iterative round key addition operations based on the previous round key output by the selector and the sub-key output by the previous stage logic processor, and stores the resulting round keys sequentially in the corresponding registers. Key expansion for round keys of different lengths (128-bit, 192-bit, and 256-bit) can be implemented in a single integrated circuit without requiring different circuits for different key lengths (keysize), resulting in higher compatibility. Furthermore, this application embodiment only requires at least six 2-to-1 selectors to schedule at least eight registers, resulting in better timing performance, significantly reducing the unit cost and quantity cost of selectors, and decreasing the interaction frequency of round key scheduling, thus shortening the key expansion path. In summary, this application embodiment provides a key expansion system with higher compatibility, better timing performance, higher round key expansion efficiency, and lower cost. Attached Figure Description

[0055] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0056] Figure 1 A simplified schematic diagram of the module structure of the key expansion system provided in the embodiments of this application;

[0057] Figure 2 A circuit and logic diagram of the key expansion system provided in the embodiments of this application;

[0058] Figure 3 A schematic diagram of key storage in each register during the encryption process in the key extension system provided in this application embodiment when the key length is 192;

[0059] Figure 4 This is a schematic diagram of key storage in each register during the decryption process when the key length is 192 in the key extension system provided in this application embodiment. Detailed Implementation

[0060] In the process of implementing this application, the applicant discovered that the current AES encryption method has a long path, poor timing, and consumes a lot of registers.

[0061] To address the aforementioned problems, this application provides a key expansion system and an encryption / decryption system. To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description, through embodiments and in conjunction with the accompanying drawings, further illustrates a key expansion system and an encryption / decryption system of this application. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit this application.

[0062] The serial numbers assigned to components in this document, such as "first" and "second," are used solely to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages). It should be understood that the terms "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are used solely for the convenience of describing this application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0063] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0064] Please see Figure 1 , Figure 1 This is a logical block diagram of a key expansion system provided in an embodiment of this application. Figure 2 This is a circuit diagram of a key expansion system provided in an embodiment of this application. Figure 2 Solid boxes containing numbers represent registers, including register a[0], register a[1], register a[2], register a[3], register a[4], register a[5], register a[6], and register a[7]; dashed boxes represent registers containing the last subkey in the previous round of key addition operations. Figure 2 This includes: the third register a[3] and the seventh register a[7]; the selector Figure 2 Not shown in the image; Figure 2In the text, “⊕” represents an XOR logic processor or the corresponding XOR operation, such as… Figure 2 In the diagram, the X / OR logic processors, from left to right, include: the zeroth X / OR logic processor ⊕0, the first X / OR logic processor ⊕1, the second X / OR logic processor ⊕2, the third X / OR logic processor ⊕3, the fourth X / OR logic processor ⊕4, and the fifth X / OR logic processor ⊕5. The zeroth X / OR logic processor ⊕0 is used to perform round key addition operations iteratively by replacing the bytes of the zeroth register a[0] or the fourth register a[4] of the previous round key with the bytes of the third register a[3] or the seventh register a[7] of the previous round key.

[0065] In one optional embodiment of this application, the key expansion system includes at least: at least eight registers, at least six 2-to-1 selectors, and a logic processor, wherein:

[0066] The eight registers include, in order: register a[0], register a[1], register a[2], register a[3], register a[4], register a[5], register a[6], and register a[7]; each register can be a word register. A word register is generally a register that can store one machine word of data. The size of a machine word depends on the computer architecture and is usually 16-bit, 32-bit, or 64-bit. For example, in a 32-bit system, a word register can store 32 bits of data.

[0067] At least six two-to-one selectors, that is, each selector is connected to two registers, and the selector is used to select from the two registers to read or write the key; for example, one of the selectors is connected to the zero register a[0] and the fourth register a[4], then the zero register a[0] and the fourth register a[4] are selected to read or write the key data therein.

[0068] The logic processor is connected to each of the selectors and registers respectively. The logic processor performs iterative round key addition operations based on the previous round key output by the selector and the subkey output by the previous-stage logic processor, and stores the resulting round keys in the corresponding registers in sequence. The round key addition operation refers to an XOR operation on the round key. In this embodiment, three types of round keys are involved: the previous round key refers to the round key output during the previous operation before the current round key addition operation, or the initial round key; the registered round key refers to the round key obtained from the current register when performing the round key addition operation; and the resulting round key refers to the new round key output after performing the round key addition operation on the current register. A round key is a series of subkeys derived from the initial master key through a key expansion algorithm in a block cipher algorithm. These subkeys are used in each "round" of encryption or decryption. In this embodiment, each round key consists of multiple subkeys, and each subkey is distributed in different registers. Round key addition is a core operation in modern block cipher algorithms (especially AES). Essentially, it involves performing a bitwise XOR operation between the current data block (called the "state") and the corresponding round key. Symbolically, this is represented as: New state = Current state ⊕ Round key, where "⊕" indicates the XOR operation.

[0069] The key expansion system provided in this application includes at least eight registers, at least six 2-to-1 selectors, and a logic processor. The selectors select from the two registers to read and write keys. The logic processor is connected to each selector and each register. The logic processor performs iterative round key addition operations based on the previous round key output by the selector and the sub-key output by the previous stage logic processor, and stores the resulting round keys sequentially in the corresponding registers. Key expansion for round keys of different lengths (128-bit, 192-bit, and 256-bit) can be implemented in a single integrated circuit without requiring different circuits for different key lengths (keysize), resulting in higher compatibility. Furthermore, this application embodiment only requires at least six 2-to-1 selectors to schedule at least eight registers, resulting in better timing performance, significantly reducing the unit cost and quantity cost of selectors, and decreasing the interaction frequency of round key scheduling, thus shortening the key expansion path. In summary, this application embodiment provides a key expansion system with higher compatibility, better timing performance, higher round key expansion efficiency, and lower cost.

[0070] In one optional embodiment of this application, the at least six two-to-one selectors include at least: a zeroth selector S0, a first selector S1, a second selector S2, a third selector S3, a fourth selector S4, and a fifth selector S5 (not shown in the figure), wherein,

[0071] The zeroth selector S0 is connected to the zeroth register a[0], the fourth register a[4], and the logic processor signal, thereby enabling a two-to-one selection operation between the zeroth register a[0] and the fourth register a[4]. The first selector S1 is connected to the first register a[1], the fifth register a[5], and the logic processor signal, thereby enabling a two-to-one selection operation between the first register a[1] and the fifth register a[5]. The second selector S2 is connected to the zeroth register a[0], the second register a[2], and the logic processor signal, thereby enabling a two-to-one selection operation between the zeroth register a[0] and the second register a[2]. The third selector S3 is connected to the first register a[1], the third register a[3], and the logic processor signal, thereby enabling a two-to-one selection operation between the first register a[1] and the third register a[3]. The fourth selector S4 is connected to the second register a[2], the sixth register a[6], and the logic processor signal, respectively, thereby enabling a two-to-one selection operation between the second register a[2] and the sixth register a[6]. The fifth selector S5 is connected to the third register a[3], the seventh register a[7], and the logic processor signal, respectively, thereby enabling a two-to-one selection operation between the third register a[3] and the seventh register a[7].

[0072] Of course, in an optional embodiment of this application, in order to improve the scheduling efficiency of each register and facilitate bidirectional encryption and decryption operations, the number of selectors can be expanded. For example, it may also include: a sixth selector S6, a seventh selector S7, an eighth selector S8, a ninth selector S9, and a tenth selector S10, wherein:

[0073] The sixth selector S6 is connected to the third register a[3], the seventh register a[7], and the byte transformation logic signal, respectively. This enables a two-to-one selection operation between the third register a[3] and the seventh register a[7].

[0074] The seventh selector S7 is connected to the zeroth logic processor output out0, the second logic processor output out2, and the zeroth register a[0] input signal, respectively. This enables a two-to-one selection operation between the zeroth logic processor output out0 and the second logic processor output out2.

[0075] The eighth selector S8 is connected to the first logic processor output out1, the third logic processor output out3, and the first register a[1] input signal, respectively. This enables a two-to-one selection operation between the first logic processor output out1 and the third logic processor output out3.

[0076] The ninth selector S9 is connected to the output out2 of the second logic processor, the output out4 of the fourth logic processor, and the input signal of the second register a[2], respectively. This enables a two-to-one selection operation between the output out2 of the second logic processor and the output out4 of the fourth logic processor.

[0077] The tenth selector S10 is connected to the output out3 of the third logic processor, the output out5 of the fifth logic processor, and the input signal of the third register a[3]. This enables a two-to-one selection operation between the output out3 of the third logic processor and the output out5 of the fifth logic processor.

[0078] In this embodiment, each selector connects to two registers. Only six selectors are needed to perform two-to-one scheduling of eight registers, which greatly reduces the unit cost and quantity cost of selectors. At the same time, it reduces the interaction frequency of round key scheduling, shortens the key expansion path, and improves the key expansion efficiency.

[0079] In traditional round key addition operations: when the round key length (keysize) is 128 bits, 4 registers are updated each time; when the round key length (keysize) is 256 bits, 8 registers are updated each time; and when the round key length (keysize) is 192 bits, 6 registers are updated each time. In an optional embodiment of this application, the logic processor in the key expansion system provided in this application includes at least six X / OR logic processors. Each X / OR logic processor corresponds one-to-one with each selector. Each X / OR logic processor is signal-connected to the corresponding selector and the two registers connected to the selector. Each X / OR logic processor is used to perform XOR processing on the previous round key selected and output by the selector and the subkey output by the previous stage logic processor, and output the result round key. The iteratively output result round key is stored sequentially in the corresponding register to facilitate the next round key addition operation, thereby improving the overall key expansion efficiency. At the same time, the number of X / OR logic processors used is greatly reduced, thereby reducing the cost of the key expansion system.

[0080] Please continue reading Figure 2In an optional embodiment of this application, the logic processor further includes an encryption port enc and a decryption port dec. During encryption, the encryption port enc is connected to each register and the XOR logic processor signal, while the decryption port dec is disconnected; during decryption, the decryption port dec is connected to each register and the XOR logic processor signal, while the encryption port enc is disconnected. This achieves encryption and decryption functions within the same circuit, resulting in better integration.

[0081] Please continue reading Figure 2 In an optional embodiment of this application, the above-described key expansion system further includes a module selector K. The module selector K is connected to the first XOR logic processor ⊕1 and the fourth XOR logic processor ⊕4, respectively. The module selector K is used to short-circuit with the second XOR logic processor ⊕2 and the third XOR logic processor ⊕3 when the key length (keysize) of the round key is 128 bits or 256 bits. The second XOR logic processor ⊕2 refers to the XOR logic processor connected to the second selector S2, and the third XOR logic processor ⊕3 refers to the XOR logic processor connected to the third selector S3. When the round key length keysize is 128 bits, 4 registers are updated each time; when the round key length keysize is 256 bits, 8 registers are updated each time, both being multiples of 4. Therefore, when the round key length keysize is 128 bits or 256 bits, only 4 or 8 registers need to be used, and 4 selectors need to be configured. This greatly reduces the number of selectors and XOR logic processors used, thereby reducing the cost of the key expansion system and reducing the key expansion path.

[0082] Please see Figure 2 In an optional embodiment of this application, if the key length keysize of the round key is 128 bits, then each round key increment operation iteration includes:

[0083] The initial key is configured in the zeroth register a[0], the first register a[1], the second register a[2], and the third register a[3] to obtain the zeroth round key;

[0084] The zeroth XOR logic processor ⊕0 performs XOR processing on the subkey output by the third register a[3] after byte transformation and the subkey stored in the zeroth register a[0] to obtain the zeroth subkey of the current round key, and stores the zeroth subkey in the zeroth register a[0].

[0085] The first XOR logic processor ⊕1 performs an XOR operation on the subkey output by the zeroth XOR logic processor ⊕0 and the subkey stored in the first register a[1] to obtain the first subkey of the current round key, and stores the first subkey in the first register a[1].

[0086] The fourth XOR logic processor ⊕4 performs an XOR operation on the subkey output by the first XOR logic processor ⊕1 and the subkey stored in the second register a[2] to obtain the second subkey of the current round key, and stores the second subkey in the second register a[2].

[0087] The fifth XOR logic processor ⊕5 performs an XOR operation on the subkey output by the fourth XOR logic processor ⊕4 and the subkey stored in the third register a[3] to obtain the third subkey of the current round key, and stores the third subkey in the third register a[3].

[0088] Please continue reading Figure 2 In an optional embodiment of this application, if the key length keysize of the round key is 256 bits, then each round key increment operation iteration includes:

[0089] The initial key is configured in the zeroth register a[0], the first register a[1], the second register a[2], the third register a[3], the fourth register a[4], the fifth register a[5], the sixth register a[6], and the seventh register a[7] to obtain the zeroth round key;

[0090] The zeroth XOR logic processor ⊕0 performs a byte transformation on the subkey output by the seventh register a[7] and an XOR operation on the subkey stored in the zeroth register a[0] to obtain the zeroth subkey of the current round key, and stores the zeroth subkey in the zeroth register a[0].

[0091] The first XOR logic processor ⊕1 performs an XOR operation on the subkey output by the zeroth XOR logic processor ⊕0 and the subkey stored in the first register a[1] to obtain the first subkey of the current round key, and stores the first subkey in the first register a[1].

[0092] The fourth XOR logic processor ⊕4 performs an XOR operation on the subkey output by the first XOR logic processor ⊕1 and the subkey stored in the second register a[2] to obtain the second subkey of the current round key, and stores the second subkey in the second register a[2].

[0093] The fifth XOR logic processor ⊕5 performs an XOR operation on the subkey output by the fourth XOR logic processor ⊕4 and the subkey stored in the third register a[3] to obtain the third subkey of the current round key, and stores the third subkey in the third register a[3].

[0094] The zeroth XOR logic processor ⊕0 performs XOR processing on the subkey output by the third register a[3] after byte transformation and the subkey stored in the fourth register a[4] to obtain the fourth subkey of the current round key, and stores the fourth subkey in the fourth register a[4].

[0095] The first XOR logic processor ⊕1 performs an XOR operation on the subkey output by the zeroth XOR logic processor ⊕0 and the subkey stored in the fifth register a[5] to obtain the fifth subkey of the current round key, and stores the fifth subkey in the fifth register a[5].

[0096] The fourth XOR logic processor ⊕4 performs an XOR operation on the subkey output by the first XOR logic processor ⊕1 and the subkey stored in the sixth register a[6] to obtain the sixth subkey of the current round key, and stores the sixth subkey in the sixth register a[6].

[0097] The fifth XOR logic processor ⊕5 performs an XOR operation on the subkey output by the fourth XOR logic processor ⊕4 and the subkey stored in the seventh register a[7] to obtain the seventh subkey of the current round key, and stores the seventh subkey in the seventh register a[7].

[0098] Please continue reading Figure 2 and Figure 3 , Figure 3 In this application, "Round" represents the number of iteration rounds. In one optional embodiment, if the key length (keysize) of the round key is 192 bits, then 12 iterations are performed.

[0099] The key addition operation iterations for every two consecutive rounds include:

[0100] Round 1:

[0101] The initial key is configured in the zeroth register a[0], the first register a[1], the second register a[2], the third register a[3], the sixth register a[6], and the seventh register a[7] to obtain the zeroth round key;

[0102] The zeroth XOR logic processor ⊕0 performs a byte transformation on the subkey output by the seventh register a[7] in the zeroth round key and performs an XOR operation with the subkey stored in the zeroth register a[0] to obtain the zeroth subkey of the current round key, and stores the zeroth subkey in the fourth register a[4].

[0103] The first XOR logic processor ⊕1 performs an XOR operation on the subkey output by the zeroth XOR logic processor ⊕0 and the subkey stored in the first register a[1] to obtain the first subkey of the current round key, and stores the first subkey in the fifth register a[5].

[0104] The second XOR logic processor ⊕2 performs an XOR operation on the subkey output by the first XOR logic processor ⊕1 and the subkey stored in the second register a[2] to obtain the second subkey of the current round key, and stores the second subkey in the zero register a[0].

[0105] The third XOR logic processor ⊕3 performs an XOR operation on the subkey output by the second XOR logic processor ⊕2 and the subkey stored in the third register a[3] to obtain the third subkey of the current round key, and stores the third subkey in the first register a[1].

[0106] The fourth XOR logic processor ⊕4 performs an XOR operation on the subkey output by the third XOR logic processor ⊕3 and the subkey stored in the sixth register a[6] to obtain the fourth subkey of the current round key, and stores the fourth subkey in the second register a[2].

[0107] The fifth XOR logic processor ⊕5 performs an XOR operation on the subkey output by the fourth XOR logic processor ⊕4 and the subkey stored in the seventh register a[7] to obtain the fifth subkey of the current round key, and stores the fifth subkey in the third register a[3].

[0108] Round Two:

[0109] The zeroth XOR logic processor ⊕0 performs a byte transformation on the subkey output by the third register a[3] in the first round key and an XOR operation on the subkey stored in the fourth register a[4] to obtain the zeroth subkey of the next round key, and stores the zeroth subkey in the zeroth register a[0].

[0110] The first XOR logic processor ⊕1 performs an XOR operation on the subkey output by the zeroth XOR logic processor ⊕0 and the subkey stored in the fifth register a[5] to obtain the first subkey of the next round key, and stores the first subkey in the first register a[1].

[0111] The second XOR logic processor ⊕2 performs an XOR operation on the subkey output by the first XOR logic processor ⊕1 and the subkey stored in the zero register a[0] to obtain the second subkey of the next round key, and stores the second subkey in the second register a[2].

[0112] The third XOR logic processor ⊕3 performs an XOR operation between the subkey output by the second XOR logic processor ⊕2 and the subkey stored in the first register a[1] to obtain the third subkey of the next round key, and stores the third subkey in the third register a[3].

[0113] The fourth XOR logic processor ⊕4 performs an XOR operation between the subkey output by the third XOR logic processor ⊕3 and the subkey stored in the second register a[2] to obtain the fourth subkey of the next round key, and stores the fourth subkey in the sixth register a[6].

[0114] The fifth XOR logic processor ⊕5 performs an XOR operation on the subkey output by the fourth XOR logic processor ⊕4 and the subkey stored in the third register a[3] to obtain the fifth subkey of the next round key, and stores the fifth subkey in the seventh register a[7].

[0115] This process continues until all round keys have been iterated or the iteration goal has been reached.

[0116] In traditional round key addition operations: when the round key length (keysize) is 128 bits, 4 registers are updated each time; when the round key length (keysize) is 256 bits, 8 registers are updated each time; and when the round key length (keysize) is 192 bits, 6 registers are updated each time. The key expansion system provided in this application, through 8 registers and 6 selectors, can simultaneously implement key expansion for 128-bit, 192-bit, and 256-bit key lengths in a single circuit. It has higher integration, fewer registers and selectors, and can select a two-to-one selector, which requires less data processing compared to other multiple-to-one selectors, resulting in higher overall efficiency.

[0117] Please see Figure 4When the key length (keysize) of the round key is 192 bits, the iterative process of the decryption operation is also 12 rounds. The decryption operation is the reverse process of the above encryption operation. Please refer to the above encryption process, which will not be repeated here.

[0118] In one optional embodiment of this application, the logic processor in the key expansion system provided in this application includes at least six XOR logic processors. Each XOR logic processor corresponds one-to-one with each selector. Each XOR logic processor is signal-connected to the corresponding selector and two registers connected to the selector. Each XOR logic processor is used to perform XOR processing on the previous round key selected and output by the selector and the subkey output by the previous stage logic processor, and output the result round key. The iteratively output result round key is stored sequentially in the corresponding register to facilitate the next round key addition operation, thereby improving the overall key expansion efficiency. At the same time, the number of XOR logic processors used is greatly reduced, thereby reducing the cost of the key expansion system.

[0119] One embodiment of this application provides an encryption / decryption system, including the key expansion system as described in any of the preceding claims.

[0120] The beneficial effects of this key expansion system have been described in detail in the above embodiments and will not be repeated here.

[0121] It should be understood that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order constraint on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the diagram may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0122] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0123] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A key expansion system, characterized by, At least includes: At least eight registers, eight registers at least includes in turn configuration: the zero register, the first register, the second register, the third register, the fourth register, the fifth register, the sixth register, the seventh register; At least six two-alternative selectors, wherein each selector connects two registers, the selector is used to select from the two registers to read and write keys; Logic processor, signal connection with each selector and each register respectively, the logic processor is used to carry out round key addition operation iteration according to the last round key output by the selector and the subkey output by the previous stage logic processor, and the result round key output by iteration is stored in the corresponding register in order.

2. The key expansion system of claim 1, wherein, At least six two-alternative selectors at least include: the zero selector, the first selector, the second selector, the third selector, the fourth selector and the fifth selector, wherein, The zero selector is signal connected with the zero register and the fourth register respectively, and the logic processor; The first selector is signal connected with the first register, the fifth register and the logic processor respectively; The second selector is signal connected with the zero register, the second register and the logic processor respectively; The third selector is signal connected with the first register, the third register and the logic processor respectively; The fourth selector is signal connected with the second register, the sixth register and the logic processor respectively; The fifth selector is signal connected with the third register, the seventh register and the logic processor respectively.

3. The key expansion system of claim 2, wherein, The logic processor at least includes six exclusive or logic processors, the exclusive or logic processor corresponds to each selector, each exclusive or logic processor is signal connected with the corresponding selector, the two registers connected by the selector respectively, each exclusive or logic processor is used to output the result round key after exclusive or processing according to the last round key output by the selector selection and the subkey output by the previous stage logic processor, and the result round key output by iteration is stored in the corresponding register in order.

4. The key expansion system of claim 3, wherein, The logic processor further includes: Encryption port and decryption port; wherein, in encryption, the encryption port is signal connected with each register and the exclusive or logic processor, and the decryption port is disconnected; in decryption, the decryption port is signal connected with each register and the exclusive or logic processor, and the encryption port is disconnected.

5. The key expansion system of claim 3, wherein, Further includes: Module selector, the module selector is signal connected with the first exclusive or logic processor and the fourth exclusive or logic processor respectively, the module selector is used to short circuit the second exclusive or logic processor and the third exclusive or logic processor in the case that the key length of round key is 128 bits or 256 bits; wherein, the second exclusive or logic processor refers to the exclusive or logic processor signal connected with the second selector, and the third exclusive or logic processor refers to the exclusive or logic processor signal connected with the third selector.

6. The key expansion system of claim 4, wherein, If the key length of the round key is 128 bits, each round of the round key addition operation iteration includes: configuring the initial key in the zeroth register, the first register, the second register and the third register to obtain a zeroth round key; the zeroth XOR logic processor XOR processes the sub-key output by the third register after byte transformation with the sub-key stored in the zeroth register to obtain a zeroth sub-key of the current round key, and stores the zeroth sub-key to the zeroth register; the first XOR logic processor XOR processes the sub-key output by the zeroth XOR logic processor with the sub-key stored in the first register to obtain a first sub-key of the current round key, and stores the first sub-key to the first register; the fourth XOR logic processor XOR processes the sub-key output by the first XOR logic processor with the sub-key stored in the second register to obtain a second sub-key of the current round key, and stores the second sub-key to the second register; the fifth XOR logic processor XOR processes the sub-key output by the fourth XOR logic processor with the sub-key stored in the third register to obtain a third sub-key of the current round key, and stores the third sub-key to the third register.

7. The key expansion system of claim 4, wherein, If the key length of the round key is 256 bits, each round of the round key addition operation iteration includes: configuring the initial key in the zeroth register, the first register, the second register, the third register, the fourth register, the fifth register, the sixth register and the seventh register to obtain a zeroth round key; the zeroth XOR logic processor XOR processes the sub-key output by the seventh register after byte transformation with the sub-key stored in the zeroth register to obtain a zeroth sub-key of the current round key, and stores the zeroth sub-key to the zeroth register; the first XOR logic processor XOR processes the sub-key output by the zeroth XOR logic processor with the sub-key stored in the first register to obtain a first sub-key of the current round key, and stores the first sub-key to the first register; the fourth XOR logic processor XOR processes the sub-key output by the first XOR logic processor with the sub-key stored in the second register to obtain a second sub-key of the current round key, and stores the second sub-key to the second register; the fifth XOR logic processor XOR processes the sub-key output by the fourth XOR logic processor with the sub-key stored in the third register to obtain a third sub-key of the current round key, and stores the third sub-key to the third register; the zeroth XOR logic processor XOR processes the sub-key output by the third register after byte transformation with the sub-key stored in the fourth register to obtain a fourth sub-key of the current round key, and stores the fourth sub-key to the fourth register; The first exclusive OR logic processor XORs the sub-key output by the zeroth exclusive OR logic processor with the sub-key stored in the fifth register to obtain a fifth sub-key of the current round key, and stores the fifth sub-key into the fifth register; The fourth exclusive OR logic processor XORs the sub-key output by the first exclusive OR logic processor with the sub-key stored in the sixth register to obtain a sixth sub-key of the current round key, and stores the sixth sub-key into the sixth register; The fifth exclusive OR logic processor XORs the sub-key output by the fourth exclusive OR logic processor with the sub-key stored in the seventh register to obtain a seventh sub-key of the current round key, and stores the seventh sub-key into the seventh register.

8. The key expansion system of claim 5, wherein, If the key length of the round key is 192 bits, each iteration of the round key addition operation includes: configuring the initial key into the zeroth register, the first register, the second register, the third register, the sixth register, and the seventh register to obtain a zeroth round key; The zeroth exclusive OR logic processor XORs the sub-key output by the seventh register in the zeroth round key after byte transformation with the sub-key stored in the zeroth register to obtain a zeroth sub-key of the current round key, and stores the zeroth sub-key into the fourth register; The first exclusive OR logic processor XORs the sub-key output by the zeroth exclusive OR logic processor with the sub-key stored in the first register to obtain a first sub-key of the current round key, and stores the first sub-key into the fifth register; The second exclusive OR logic processor XORs the sub-key output by the first exclusive OR logic processor with the sub-key stored in the second register to obtain a second sub-key of the current round key, and stores the second sub-key into the zeroth register; The third exclusive OR logic processor XORs the sub-key output by the second exclusive OR logic processor with the sub-key stored in the third register to obtain a third sub-key of the current round key, and stores the third sub-key into the first register; The fourth exclusive OR logic processor XORs the sub-key output by the third exclusive OR logic processor with the sub-key stored in the sixth register to obtain a fourth sub-key of the current round key, and stores the fourth sub-key into the second register; The fifth exclusive OR logic processor XORs the sub-key output by the fourth exclusive OR logic processor with the sub-key stored in the seventh register to obtain a fifth sub-key of the current round key, and stores the fifth sub-key into the third register; The zeroth exclusive OR logic processor XORs the sub-key output by the third register in the first round key after byte transformation with the sub-key stored in the fourth register to obtain a zeroth sub-key of the next round key, and stores the zeroth sub-key into the zeroth register; The first XOR logic processor XORs the sub-key output by the zeroth XOR logic processor with the sub-key stored in the fifth register to obtain a first sub-key of the next round key, and stores the first sub-key into the first register; The second XOR logic processor XORs the sub-key output by the first XOR logic processor with the sub-key stored in the zeroth register to obtain a second sub-key of the next round key, and stores the second sub-key into the second register; The third XOR logic processor XORs the sub-key output by the second XOR logic processor with the sub-key stored in the first register to obtain a third sub-key of the next round key, and stores the third sub-key into the third register; The fourth XOR logic processor XORs the sub-key output by the third XOR logic processor with the sub-key stored in the second register to obtain a fourth sub-key of the next round key, and stores the fourth sub-key into the sixth register; The fifth XOR logic processor XORs the sub-key output by the fourth XOR logic processor with the sub-key stored in the third register to obtain a fifth sub-key of the next round key, and stores the fifth sub-key into the seventh register.

9. The key expansion system of claim 1, wherein, Each register is a word register.

10. An encryption and decryption system characterized by comprising: A key expansion system as claimed in any one of claims 1 to 9. A key expansion system as claimed in any one of claims 1 to 9.

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