Method for measuring chip delay, electronic device and storage medium

Abstract

The application provides a method for measuring chip delay, an electronic device and a storage medium. The method comprises the following steps: sequentially connecting at least two same to-be-tested chips in communication to form a serial path for signal transmission through each complete chip in sequence, each to-be-tested chip comprising a plurality of functional modules connected in communication in sequence; inputting a test signal to the to-be-tested chip located at the head of the serial path, so that the test signal is transmitted through each to-be-tested chip in sequence along the serial path; monitoring the signal transmission state inside each to-be-tested chip to identify the position of each to-be-tested chip outputting an identifiable signal and record the corresponding time point; calculating the time difference Δt between the time points of any two to-be-tested chips corresponding to the same identifiable signal, and calculating the delay of the test signal in a single to-be-tested chip as Δt / (M-1) according to the time difference Δt and the number M of to-be-tested chips through which the test signal passes within the time difference Δt.

Description

Technical Field

[0001] This application relates primarily to the field of chips, and more particularly to a method for measuring chip delay, an electronic device, and a storage medium. Background Technology

[0002] In electronic devices, chip latency performance is a key indicator of efficiency and response speed. With technological advancements, chip designs are becoming increasingly complex and integrated, making the measurement of chip latency performance particularly crucial. Accurate latency measurement not only helps optimize chip design but also ensures the stability and reliability of chips in practical applications. Currently, methods for measuring chip latency mainly include: simulation, Built-In Self-Test (BIST), and testing with added compensation modules. However, these methods either have low accuracy, require integrated test modules within the chip, or necessitate the introduction of additional compensation modules. Furthermore, these methods cannot measure chip latency based on garbled test data. Summary of the Invention

[0003] The technical problem to be solved by this application is to provide a method, electronic device and storage medium for measuring chip delay. The method, electronic device and storage medium for measuring chip delay simplify the measurement method, reduce the measurement cost, and can measure the delay of garbled test signals in the chip under test.

[0004] This application proposes a method for measuring chip delay, comprising: sequentially communicating at least two identical chips under test (DUTs) to form a serial path for sequential transmission of signals through each complete chip, each DUT including multiple functional modules sequentially communicated; inputting a test signal to the DUT located at the beginning of the serial path, causing the test signal to be transmitted sequentially through each DUT along the serial path; monitoring the signal transmission state inside each DUT to identify the position where each DUT outputs a recognizable signal and recording the corresponding time point; and calculating the time difference Δt between the time points corresponding to the same recognizable signal of any two DUTs, and calculating the delay of the test signal in a single DUT as Δt / (M-1) based on the time difference Δt and the number M of DUTs through which the test signal passes within the time difference Δt.

[0005] In another aspect, this application also proposes an electronic device including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform a method for measuring chip delay as described above.

[0006] In another aspect, this application also proposes a storage medium storing a computer program, wherein the computer program is configured to execute, at runtime, the method for measuring chip delay as described above.

[0007] The technical solution of this application has the following technical effects: it monitors the signal transmission status inside at least two communication-connected chips under test, avoids garbled data at the entry and exit points of the chips under test, identifies the position of the output identifiable signal in each chip under test, and records the corresponding time point. Based on the time difference between the time points and the number of chips under test through which the test signal passes within the time difference, the delay of the test signal in a single chip under test is calculated. Thus, on the one hand, no additional auxiliary modules are needed, simplifying the measurement method and reducing the measurement cost; on the other hand, it is possible to measure the delay of garbled test signals in the chip under test. Attached Figure Description

[0008] The accompanying drawings are included to provide a further understanding of this application. They are incorporated into and constitute a part of this application. The drawings illustrate embodiments of this application and, together with this specification, serve to explain the principles of this application. In the drawings:

[0009] Figure 1 This is a schematic diagram of the structure of the chip under test;

[0010] Figure 2 This is a flowchart illustrating a method for measuring chip delay according to one embodiment of this application;

[0011] Figure 3 This is a schematic diagram of the structure of a test module for measuring delay in one embodiment of this application;

[0012] Figure 4 This is a schematic diagram of the structure of a test module for measuring delay in another embodiment of this application;

[0013] Figure 5 This is a line graph of the delay used to compare multiple test signals in one embodiment of this application. Detailed Implementation

[0014] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some examples or embodiments of this application. For those skilled in the art, these drawings can be applied to other similar scenarios without creative effort. Unless obvious from the context or otherwise specified, the same reference numerals in the drawings represent the same structures or operations.

[0015] As indicated in this application, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0016] Unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps described in these embodiments do not limit the scope of this application. It should also be understood that, for ease of description, the dimensions of the various parts shown in the drawings are not drawn to actual scale. Techniques, methods, and devices known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and devices should be considered part of the specification. In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limitations. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0017] In the description of this application, it should be understood that the orientation or positional relationship indicated by directional terms such as "front, back, up, down, left, right", "horizontal, vertical, horizontal" and "top, bottom" is usually based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing this application and simplifying the description. Unless otherwise stated, these directional terms do not indicate or imply that the device or element referred to must have a specific orientation or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the scope of protection of this application; the directional terms "inner" and "outer" refer to the inner and outer contours relative to the outline of each component itself.

[0018] For ease of description, spatial relative terms such as "above," "on top of," "on the upper surface of," "above," etc., are used herein to describe the spatial positional relationship of a device or feature as shown in the figures to other devices or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation of the device as described in the figures. For example, if the device in the figures were inverted, a device described as "above" or "on top of" other devices or structures would subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein will be interpreted accordingly.

[0019] Furthermore, it should be noted that the use of terms such as "first" and "second" to define components is merely for the purpose of distinguishing the corresponding components. Unless otherwise stated, these terms have no special meaning and therefore should not be construed as limiting the scope of protection of this application. In addition, although the terminology used in this application is selected from commonly known and used terms, some terms mentioned in this application's specification may have been chosen by the applicant according to his or her judgment, and their detailed meanings are explained in the relevant sections of this description. Moreover, this application should be understood not only through the actual terms used, but also through the meaning implied by each term.

[0020] This application uses flowcharts to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed precisely in sequence. Instead, various steps can be processed in reverse order or simultaneously. Furthermore, other operations may be added to these processes, or one or more steps may be removed from these processes.

[0021] refer to Figure 1 The schematic diagram of the chip under test 110 shown illustrates that the chip under test 110 has n functional modules, including a first functional module 111, a second functional module 112, and an nth functional module 113, which are sequentially connected in communication. A test signal is input to the chip under test 110, transmitted from the first functional module 111 to the nth functional module 113, and after processing by each functional module, the signal is output from the chip under test 110 (i.e.,...). Figure 1 The delay of the test signal in the chip under test (DUT) 110 is the time difference between the time when the DUT 110 outputs the output signal and the time when the test signal is input to the DUT 110. The test signal is a garbled signal encoded according to certain rules, and the output signal of the DUT 110 is also a garbled signal encoded according to certain rules. This makes it impossible to correlate the test signal with the corresponding output signal, and therefore impossible to calculate the time difference.

[0022] The chip delay measurement method of this application can measure the delay of garbled signals within the chip under test. The method will now be described through specific implementation details.

[0023] refer to Figure 2 The flowchart shown illustrates the method for measuring chip delay. Figure 2 The implementation method includes steps S110 to S140.

[0024] In step S110, refer to Figure 3The test module for delay testing includes n chips under test (DUTs), such as a first DUT 121, a second DUT 122, and an nth DUT 123. These n DUTs are identical and are sequentially connected to form a serial path for signal transmission through each complete chip. The test module includes at least two DUTs, meaning n is equal to or greater than 2. For ease of explanation, this will be referred to as... Figure 4 The test module with n=2 is shown below for illustration.

[0025] In step S120, refer to Figure 4 A test signal is input to the first chip under test 121 located at the beginning of the serial path, so that the test signal is transmitted sequentially through each chip under test along the serial path. After being processed by the first chip under test 121, the test signal is output to the second chip under test 122 and is finally output by the second chip under test 122.

[0026] In one embodiment, the test signal is a garbled message and / or garbled cells. The garbled message and garbled cells are data encoded according to certain rules. Using a garbled test signal can more realistically reflect the actual application scenario of the chip under test. The garbled message includes a recognizable signal that can be identified by at least one functional module in each chip under test (first chip under test 121 and second chip under test 122); similarly, the garbled cells include a recognizable signal that can be identified by at least one functional module in each chip under test. The first chip under test 121 is the same as the second chip under test 122; therefore, the functional module in the first chip under test 121 that can identify the recognizable signal is the same as the functional module in the second chip under test 122 that can identify the same recognizable signal. Further details can be found by referring to… Figure 4 Position 1 is located between the first functional module 111 and the second functional module 112 in the first chip under test 121, and position 2 is located between the first functional module 111 and the second functional module 112 in the second chip under test 122. If the first functional module 111 can identify the identifiable signal in the test signal, since each chip under test is the same, the first functional module 111 in each chip under test can identify the same identifiable signal in the test signal.

[0027] In step S130, the signal transmission status inside the first chip under test 121 and the signal transmission status inside the second chip under test 122 are monitored. The monitored content includes whether the signal output by each functional module in each chip under test is identifiable, so as to identify the location of the identifiable signal output in each chip under test and record the time point of the identifiable signal output.

[0028] To elaborate, assume the signal output by the first functional module 111 is identifiable, meaning the signals at positions 1 and 2 are identifiable. Record the time point t1 when an identifiable signal is detected at position 1, and the time point t2 when an identifiable signal is detected at position 2. It should be noted that other functional modules may also output identifiable signals, not limited to the first functional module 111. The signals output by each functional module in each chip under test can be monitored to determine whether the signal output by each module is identifiable. If identifiable, the corresponding time point is recorded.

[0029] In step S140, the identifiable signal output by the first functional module 111 in the first chip under test 121 and the identifiable signal output by the first functional module 111 in the second chip under test 122 may be the same or different, but they contain the same identification code (ID). Therefore, the identifiable signals output by the first functional modules 111 of different chips under test can be matched together by the identification code and marked as the same identifiable signal. Figure 4 In the above, the identifiable signal at position 1 and the identifiable signal at position 2 are the same identifiable signal.

[0030] Calculate the time difference Δt between the time points of the same identifiable signal corresponding to the first chip under test 121 and the second chip under test 122. The identifiable signal at position 1 and the identifiable signal at position 2 are the same identifiable signal. The time point of the identifiable signal at position 1 is t1, and the time point of the identifiable signal at position 2 is t2. The time difference Δt is t2-t1.

[0031] Based on the time difference Δt and the number M of chips under test (DUTs) that the test signal passes through within the time difference Δt, the delay of the test signal in a single DUT is calculated as Δt / (M-1). Specifically, in... Figure 4 In the first chip under test 121, the test signal passes through functional modules from the second functional module 112 to the nth functional module 113, and in the second chip under test 122, it passes through the first functional module 111. Therefore, from position 1 to position 2, the functional modules through which the test signal passes are the same as those in a complete chip under test. Figure 4 In this context, M is 2, and the delay of the test signal in the chip under test is Δt / (2-1). It can be understood that when... Figure 3 When there are 3 chips under test, M is 3, and the delay of the test signal in the chip under test is Δt / (3-1).

[0032] Steps S110 to S140 can be performed using Electronic Design Automation (EDS) software.

[0033] This application monitors the signal transmission status within at least two communication-connected chips under test (DUTs), avoiding garbled data at the DUT's input and output points. It identifies the location of identifiable signals output from each DUT and records the corresponding time points. Based on the time difference between these time points and the number of DUTs the test signal passes through within that time difference, the delay of the test signal within a single DUT is calculated. Thus, on the one hand, no additional auxiliary modules are needed, simplifying the measurement method and reducing measurement costs; on the other hand, it can measure the delay of garbled test signals within the DUT.

[0034] In one embodiment, multiple test signals are input to the first chip under test 121 located at the beginning of the serial path according to a first preset timing sequence. At least two time intervals with different durations exist between adjacent test signals. For example, referring to Table 1 below, test signals data 1, data 2, data 3, data 4, and data 5 are sequentially input to the first chip under test 121 according to the first preset timing sequence. The content and length of these test signals can be the same or different; the time intervals between adjacent test signals are Δ1, Δ2, Δ3, and Δ4, respectively. The first preset timing sequence is adjusted to make at least two time intervals different in duration, for example, making Δ2 and Δ3 different, or making Δ1, Δ2, Δ3, and Δ4 all different. Inputting test signals according to the first preset timing sequence allows measurement of the delay of the chip under test under different input signal densities, thereby reflecting the true delay performance of the chip under test under different loads.

[0035] Table 1 Delay of multiple test signals

[0036] Test data Time points in the first chip under test The time point in the second chip under test Delay data 1 a1 a2 a2-a1 data 2 b1 b2 b2-b1 data 3 c1 c2 c2-c1 data 4 d1 d2 d2-d1 data 5 e1 e2 e2-e1

[0037] Referring to Table 1, for test signal data 1, record two time points a1 and a2 corresponding to the same identifiable signal and calculate the delay. Similarly, for test signals data 2, data 3, data 4, and data 5, record two time points corresponding to the same identifiable signal and calculate the delay. Based on the data in Table 1, compare the delay of each test signal to obtain the maximum and minimum delay, and calculate the average delay. The transmission characteristics of multiple test signals input according to a first preset timing sequence and having at least two different time intervals can be analyzed in the chip under test based on the maximum, minimum, and average delays, thus providing a basis for subsequent optimization of the design code of the chip under test.

[0038] In one embodiment, multiple test signals are input to the first test chip 121 located at the beginning of the serial path according to a first preset timing sequence, and the delay of the first input test signal is compared with the delay of the subsequent input test signals to determine the congestion status of the test signals. Specifically, refer to... Figure 5The line graph showing the delays of data 1, data 2, data 3, data 4, and data 5 indicates that data 1 has the shortest delay, while data 4 has the longest delay. This can be seen from... Figure 5 Analyzing the signal congestion in the chip under test provides a basis for subsequent optimization of the chip design code.

[0039] refer to Figure 4 In another implementation, multiple test signals are input to the first chip under test (DUT) 121 located at the beginning of the serial path according to a second preset timing sequence. At least two test signals have different contents, and the lengths of the multiple test signals can be the same or different. The second preset timing sequence can be the same as or different from the first preset timing sequence. Furthermore, the delay of each test signal can be recorded, and the delays of each test signal can be compared to obtain the maximum delay and minimum delay, as well as calculate the average delay. Based on the maximum delay, minimum delay, and average delay, the transmission characteristics of multiple test signals input according to the second preset timing sequence and with different contents in the DUT can be analyzed, thereby providing a basis for subsequent optimization of the DUT's design code. Furthermore, the delay of the first input test signal can be compared with the delay of subsequent input test signals to determine the congestion status of the multiple test signals.

[0040] In another aspect, this application also proposes an electronic device comprising a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the method for measuring chip delay as described above.

[0041] In another aspect, this application also proposes a storage medium storing a computer program, wherein the computer program is configured to execute, at runtime, the method for measuring chip delay as described above.

[0042] Some aspects of this application can be executed entirely by hardware, entirely by software (including firmware, resident software, microcode, etc.), or by a combination of hardware and software. The aforementioned hardware or software may be referred to as a "data block," "module," "engine," "unit," "component," or "system." The processor may be one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DAPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), processors, controllers, microcontrollers, microprocessors, or combinations thereof. Furthermore, aspects of this application may manifest as computer products residing in one or more computer-readable media, including computer-readable program code. For example, computer-readable media may include, but are not limited to, magnetic storage devices (e.g., hard disks, floppy disks, magnetic tapes, etc.), optical discs (e.g., compressed CDs, digital multifunction DVDs, etc.), smart cards, and flash memory devices (e.g., cards, sticks, key drives, etc.).

[0043] A computer-readable medium may contain a propagated data signal containing computer program code, for example, on baseband or as part of a carrier wave. This propagated signal may take various forms, including electromagnetic, optical, and so on, or suitable combinations thereof. A computer-readable medium can be any computer-readable medium other than a computer-readable storage medium, which can be connected to an instruction execution system, apparatus, or device to enable communication, propagation, or transmission of a program for use. The program code located on the computer-readable medium can be propagated through any suitable medium, including radio, cable, fiber optic cable, radio frequency signals, or similar media, or any combination of the above media.

[0044] This application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic associated with at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. Furthermore, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0045] It should be noted that, in order to simplify the description of the embodiments disclosed in this application and thus aid in the understanding of one or more embodiments of the invention, the foregoing description of the embodiments of this application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of this application requires more features than those mentioned. In fact, the embodiments have fewer features than all the features of the single embodiments disclosed above.

[0046] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used to describe embodiments are sometimes modified by the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in this application are approximate values, which may be changed depending on the characteristics required by individual embodiments. In some embodiments, numerical parameters should take into account specified significant digits and employ a general method of digit preservation. Although the numerical ranges and parameters used to confirm their breadth of range in some embodiments of this application are approximate values, in specific embodiments, such values ​​are set as accurately as feasible.

Claims

1. A method for measuring chip delay, characterized in that, include: At least two identical chips under test are sequentially connected in communication to form a serial path through which signals are transmitted sequentially through each complete chip. Each chip under test includes multiple functional modules that are sequentially connected in communication. A test signal is input to the chip under test located at the beginning of the serial path, so that the test signal is transmitted sequentially through each chip under test along the serial path; Monitor the signal transmission status inside each of the chips under test to identify the location where each chip under test outputs a identifiable signal and record the corresponding time point; as well as Calculate the time difference Δt between any two chips under test corresponding to the same identifiable signal. Based on the time difference Δt and the number of chips under test M that the test signal passes through within the time difference Δt, calculate the delay of the test signal in a single chip under test as Δt / (M-1).

2. The method for measuring chip delay as described in claim 1, characterized in that, The test signal is a garbled message and / or garbled information element, wherein the garbled message includes the identifiable signal that can be recognized by at least one functional module in the chip under test, and the garbled information element includes the identifiable signal that can be recognized by at least one functional module in the chip under test.

3. The method for measuring chip delay as described in claim 1, characterized in that, Multiple test signals are input to the chip under test located at the beginning of the serial path according to a first preset timing sequence, wherein at least two time intervals with different durations exist between adjacent test signals.

4. The method for measuring chip delay as described in claim 3, characterized in that, The delay of each test signal is compared to obtain the maximum delay and the minimum delay, and the average delay is calculated.

5. The method for measuring chip delay as described in claim 3, characterized in that, The delay of the first input test signal is compared with the delay of subsequent input test signals to determine the congestion status of the multiple test signals.

6. The method for measuring chip delay as described in claim 1, characterized in that, Multiple test signals are input to the chip under test located at the beginning of the serial path according to the second preset timing sequence, wherein at least two of the test signals have different contents.

7. The method for measuring chip delay as described in claim 6, characterized in that, The delay of each test signal is compared to obtain the maximum delay and the minimum delay, and the average delay is calculated.

8. The method for measuring chip delay as described in claim 6, characterized in that, The delay of the first input test signal is compared with the delay of subsequent input test signals to determine the congestion status of the multiple test signals.

9. The method for measuring chip delay as described in claim 1, characterized in that, Monitor the signals output by each functional module in each chip under test to determine whether the signal output by each module is identifiable. If it is identifiable, record the corresponding time point.

10. An electronic device comprising a memory and a processor, characterized in that, The memory stores a computer program, and the processor is configured to run the computer program to perform the method for measuring chip delay as described in any one of claims 1 to 9.

11. A storage medium, characterized in that, The storage medium stores a computer program, wherein the computer program is configured to execute the method for measuring chip delay as described in any one of claims 1 to 9 when running.

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