Method and system for monitoring energy consumption of multi-core heterogeneous ASIC (Application Specific Integrated Circuit) computing mainboard

Abstract

The embodiment of the invention can be applied to the technical field of mainboards, and particularly provides an energy consumption monitoring method and system for a multi-core heterogeneous ASIC computing mainboard, and the method comprises the steps: obtaining a structured feature set of each core in the operation process of the multi-core heterogeneous ASIC computing mainboard; aligning the instruction system structure of each core of the multi-core heterogeneous ASIC computing mainboard with the structured feature set to generate a coding vector; after collecting a hardware energy consumption data set of each core of the multi-core heterogeneous ASIC computing mainboard, generating a predicted power consumption value with the coding vector; and performing aggregation processing of a core dimension, a time dimension and a task dimension on the predicted power consumption value, and identifying an abnormal power consumption position based on an aggregation result. According to the technical scheme of the embodiment of the invention, the whole-process and hierarchical monitoring of the energy consumption of the multi-core heterogeneous platform under the software and hardware collaborative perspective is realized, the power consumption analysis capability and the abnormal response efficiency are improved, and the problem that the abnormal power consumption recognition capability is weak in a traditional multi-core system energy consumption monitoring method is solved.

Description

Technical Field

[0001] This application relates to the technical field of motherboards, and more specifically, to a method and system for monitoring the power consumption of multi-core heterogeneous ASIC computing motherboards. Background Technology

[0002] With the increasing complexity of information processing tasks and the growing demand for dedicated computing, multi-core heterogeneous ASIC computing motherboards have been widely used in embedded systems, high-performance computing, and edge intelligence. Compared with traditional homogeneous processing architectures, multi-core heterogeneous systems have higher computational parallelism and energy efficiency. However, they also bring a series of management challenges, such as complex operating states, diverse scheduling structures, and frequent task switching. Among these challenges, energy consumption monitoring and energy efficiency analysis have become one of the key technical bottlenecks restricting their performance optimization and safe and stable operation.

[0003] Traditional power consumption monitoring methods for multi-core systems involve deploying voltage and current sensors on the motherboard and synchronously sending the sampled values ​​to a power consumption monitoring module, combined with a static threshold judgment mechanism to analyze power consumption trends. These methods can achieve real-time power management for single-core or small-scale multi-core processors to a certain extent. However, they suffer from weak abnormal power consumption identification capabilities when faced with complex task scheduling, high-frequency context switching, and multi-dimensional load coupling in multi-core heterogeneous systems. Summary of the Invention

[0004] To overcome the problem of weak abnormal power consumption identification capability in traditional multi-core system power consumption monitoring methods, embodiments of this application provide a power consumption monitoring method and system for multi-core heterogeneous ASIC computing motherboards. This method can integrate task execution behavior characteristics, core structure information and timing power consumption change patterns to achieve structured modeling of multi-dimensional power consumption data and high-precision abnormal power consumption identification, effectively improving the operational stability and energy efficiency management capabilities of complex systems.

[0005] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0006] According to one aspect of the embodiments of this application, a method for monitoring the power consumption of a multi-core heterogeneous ASIC computing motherboard is provided, comprising: acquiring execution data of each core during the operation of the multi-core heterogeneous ASIC computing motherboard, and constructing a structured feature set based on the execution data; aligning the instruction architecture of each core of the multi-core heterogeneous ASIC computing motherboard with the structured feature set to extract power-sensitive paths and key execution segments under multi-core collaboration, and generating encoding vectors using the power-sensitive paths and key execution segments; collecting hardware power consumption datasets of each core of the multi-core heterogeneous ASIC computing motherboard, inputting the hardware power consumption datasets and the encoding vectors into a preset structured power consumption inference model, and outputting predicted power consumption values ​​of each core in different time-series segments; performing aggregation processing on the predicted power consumption values ​​in core dimension, time dimension and task dimension to obtain aggregation results, and identifying abnormal power consumption locations based on the aggregation results.

[0007] In some embodiments of this application, based on the foregoing scheme, the step of acquiring the execution data of each core during the operation of a multi-core heterogeneous ASIC computing motherboard and constructing a structured feature set based on the execution data includes: periodically collecting the instruction sequence, task scheduling time, and load status of each core and the general-purpose processor core within a preset operating cycle of the multi-core heterogeneous ASIC computing motherboard; generating execution data based on the instruction sequence, the task scheduling time, and the load status; performing time-series analysis on the execution data, extracting the operation type frequency, memory access density, and scheduling switching count in the time period, and generating a structured feature set based on the operation type frequency, the memory access density, and the scheduling switching count.

[0008] In some embodiments of this application, based on the foregoing scheme, the step of performing time-series analysis on the execution data, extracting the operation type frequency, memory access density, and scheduling switching count within a time period, and generating a structured feature set based on the operation type frequency, memory access density, and scheduling switching count includes: performing time-series analysis on the execution data, extracting the operation type frequency, memory access density, and scheduling switching count within a time period, and generating a task execution feature set based on the operation type frequency, memory access density, and scheduling switching count; classifying and integrating the task execution feature set according to a preset task identifier to obtain an integration result; performing feature vector standardization processing on the integration result combined with the structural attributes of various cores of a multi-core heterogeneous ASIC computing motherboard to obtain a task vector group; constructing a task time slice feature structure using the task vector group and the task scheduling time; and mapping the task time slice feature structure to a preset multi-dimensional task feature space to generate a structured feature set.

[0009] In some embodiments of this application, based on the foregoing scheme, the step of aligning the instruction architecture of each core of the multi-core heterogeneous ASIC computing motherboard with the structured feature set to extract energy-sensitive paths and key execution segments under multi-core collaboration, and generating encoding vectors using the energy-sensitive paths and key execution segments, includes: pre-constructing a core structure feature index based on the instruction architecture of each core of the multi-core heterogeneous ASIC computing motherboard; mapping each type of task in the structured feature set to the core structure feature index; and generating instruction adaptation parameters based on the corresponding task index; and identifying multi-core... The scheduling process involves high-frequency instruction segments and cross-core collaborative segments with concentrated power consumption fluctuations. An energy-sensitive path set is constructed based on these high-frequency instruction segments and cross-core collaborative segments. The task jump characteristics include the number of core migrations, task switching latency, and context reconstruction frequency within the scheduling cycle. The energy-sensitive path set is sorted and clustered to obtain a sorted clustering result. This result is combined with scheduling information to extract key execution segments. The energy-sensitive path set and the key execution segments are then encoded to obtain an encoding vector. The scheduling information includes scheduling priority, time slice utilization, and inter-core migration ratio.

[0010] In some embodiments of this application, based on the aforementioned scheme, the step of collecting hardware power consumption datasets of each core of a multi-core heterogeneous ASIC computing motherboard, inputting the hardware power consumption datasets and the encoded vectors into a preset structured power inference model, and outputting the predicted power consumption values ​​of each core in different timing segments includes: synchronously acquiring current, voltage, and power sampling values ​​of the corresponding timing segments from the local power monitoring interface of each core of the multi-core heterogeneous ASIC computing motherboard; generating a hardware power consumption dataset based on the current, voltage, and power sampling values; performing noise filtering and timing alignment processing on the hardware power consumption dataset to construct timing power consumption features; inputting the encoded vectors and the timing power consumption features into a preset structured power inference model; and performing multivariate power estimation on the encoded vectors and the timing power consumption features through the structured power inference model to output the predicted power consumption values ​​of each core in different timing segments.

[0011] In some embodiments of this application, based on the aforementioned scheme, the step of aggregating the predicted power consumption value in terms of core dimension, time dimension, and task dimension to obtain the aggregation result, and identifying the abnormal power consumption location based on the aggregation result, includes: analyzing the fluctuation confidence interval based on the predicted power consumption value, constructing a power consumption time set based on the fluctuation confidence interval; using the power consumption time set to calculate the average power consumption, maximum fluctuation amplitude, and load overlap ratio of each processing core in all time periods to construct a core energy consumption feature set; extracting scheduling identifiers for each task in different time segments from the task scheduling logs of the multi-core heterogeneous ASIC calculation motherboard; performing a dual association mapping of timestamp and core number on the execution data and the task scheduling time to generate task mapping information; and fusing the core energy consumption feature set, scheduling identifiers, and task mapping information to obtain the abnormal power consumption location.

[0012] In some embodiments of this application, based on the aforementioned scheme, the step of fusing the core energy consumption feature set, scheduling identifier, and task mapping information to obtain the abnormal power consumption location includes: fusing the core energy consumption feature set, scheduling identifier, and task mapping information to generate a power consumption representation structure; constructing a power consumption tensor dataset based on the power consumption representation structure; performing attribution aggregation analysis on the power consumption tensor dataset to obtain the transient fluctuation value and energy consumption index corresponding to each task; and identifying the transient fluctuation value and the energy consumption index through a preset abnormal threshold strategy to obtain the abnormal power consumption location.

[0013] According to another aspect of the embodiments of this application, a power consumption monitoring system for a multi-core heterogeneous ASIC computing motherboard is provided, comprising: a data acquisition module, used to acquire execution data of each core during the operation of the multi-core heterogeneous ASIC computing motherboard, and construct a structured feature set based on the execution data; an alignment analysis module, used to align the instruction architecture of each core of the multi-core heterogeneous ASIC computing motherboard with the structured feature set to extract power consumption sensitive paths and key execution segments under multi-core collaboration, and generate encoding vectors using the power consumption sensitive paths and key execution segments; a data acquisition module, used to acquire hardware power consumption datasets of each core of the multi-core heterogeneous ASIC computing motherboard, input the hardware power consumption datasets and the encoding vectors into a preset structured power consumption inference model, and output predicted power consumption values ​​of each core in different time periods; and an aggregation processing module, used to perform aggregation processing on the predicted power consumption values ​​in core dimension, time dimension and task dimension to obtain aggregation results, and identify abnormal power consumption locations based on the aggregation results.

[0014] Compared with existing technologies, this application has the following advantages: strong identification capability. By acquiring the execution data of each core during the operation of a multi-core heterogeneous ASIC computing motherboard, a structured feature set is constructed to reflect the execution structure and scheduling relationship of tasks at a micro level. Then, by aligning with the core instruction architecture, energy-sensitive paths and key execution segments in a multi-core collaborative environment are extracted, thereby generating an encoding vector, enhancing the expressive ability of the energy consumption relationship between tasks and structures. Subsequently, this encoding vector is jointly input with the energy consumption datasets of each core hardware into a structured power consumption inference model, achieving high-precision predictive power consumption modeling without relying on instruction replay. Finally, through aggregated analysis of core, time, and task dimensions, a multi-level energy consumption attribution structure is constructed. Combined with a three-dimensional power consumption tensor dataset and anomaly identification mechanism, the location of abnormal power consumption is accurately located. This achieves full-process, hierarchical, and refined modeling and monitoring of energy consumption on a multi-core heterogeneous platform from a hardware-software collaborative perspective, improving power consumption analysis capabilities and anomaly response efficiency, and addressing the problem of weak abnormal power consumption identification capability in traditional multi-core system energy consumption monitoring methods. Attached Figure Description

[0015] Figure 1 This is a flowchart illustrating the power consumption monitoring method for a multi-core heterogeneous ASIC computing motherboard provided in an embodiment of the present invention. Figure 2 This is a schematic block diagram of the power consumption monitoring system for a multi-core heterogeneous ASIC computing motherboard provided in an embodiment of the present invention. Detailed Implementation

[0016] Exemplary embodiments will now be described in a more comprehensive manner with reference to the accompanying drawings. However, the exemplary embodiments can be implemented in various forms and should not be construed as limited to these examples; rather, these embodiments are provided so that this application will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art.

[0017] Furthermore, the features, structures, or characteristics described in this application can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to provide a full understanding of the embodiments of this application. However, those skilled in the art will recognize that when implementing the technical solutions of this application, not all the detailed features in the embodiments may be used, one or more specific details may be omitted, or other methods, elements, devices, steps, etc., may be employed.

[0018] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0019] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0020] It should be noted that "multiple" in this article refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0021] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0022] like Figure 1 As shown, this embodiment provides a power consumption monitoring method for a multi-core heterogeneous ASIC computing motherboard, enabling dynamic modeling, attribution analysis, and anomaly identification of power consumption behavior in a multi-core heterogeneous environment. It can finely reflect the power consumption distribution characteristics of different cores under different task scenarios. The power consumption monitoring method specifically includes the following steps: Step S1: Obtain the execution data of each core during the operation of the multi-core heterogeneous ASIC computing motherboard, and construct a structured feature set based on the execution data.

[0023] Specifically, a lightweight tracing probe is embedded in the operating system scheduling layer of a multi-core heterogeneous ASIC computing motherboard to collect execution data generated by each processing core during runtime in real time. This execution data includes, but is not limited to, instruction opcodes, target registers, source operands, memory access behavior, control transfer identifiers, and execution time stamps, and is bound to the scheduling time slice and unique task identifier during data acquisition. Based on this execution data, a structured feature set with a three-layer structure of task-core-instruction is constructed. Nodes represent specific instruction events, edges represent adjacent execution order dependencies, node attributes include instruction semantics, context structure, and resource requirements, and edge attributes represent multi-dimensional features such as scheduling transfers, shared memory access, or computational dependency paths, forming a structured task description graph that supports heterogeneous semantic fusion.

[0024] In one example, open-source tracing components such as perf+LTTng are used to collect execution data for both ARM and RISC-V cores. The instruction sample size is sampled at a granularity of no less than 100,000 instructions per core per second. Context attribution mapping is established using task identifiers (such as PID and TID in Linux). Then, a graph building library (such as NetworkX) is used to generate a structured feature set containing instruction nodes, time-sequence edges, and shared data interaction edges.

[0025] Step S2: Align the instruction architecture and structured feature set of each core of the multi-core heterogeneous ASIC computing motherboard to extract the energy-sensitive paths and key execution segments under multi-core collaboration, and use the energy-sensitive paths and key execution segments to generate encoding vectors.

[0026] Specifically, by aligning the instruction semantic nodes in the structured feature set with the instruction architecture of each core, and based on the instruction execution cost model and microarchitecture resource mapping rules, the instruction path of each task is quantified for execution overhead and classified for energy consumption characteristics. High-cost, high-concurrency, frequent memory access, or cross-core scheduling path segments are identified and defined as energy-sensitive paths. Furthermore, key execution segments within the paths are extracted, such as those frequently triggering L1 / L2 cache misses, high SIMD unit occupancy segments, and DMA collaborative transfer segments. Encoding vectors are constructed by combining their execution frequency, resource consumption, and timing position. The vector dimensions must at least include instruction load density, execution switching frequency, data locality strength, and instruction resource mapping ratio.

[0027] In one example, five instruction groups are defined for the RISC-V core: arithmetic logic, control flow, memory access, special coprocessing, and no-operation. By establishing an instruction feature table, the frequency of each type of instruction within the graph path segment is statistically analyzed. Combined with power sensitivity weights, principal component analysis (PCA) is used to compress the instruction into a 128-dimensional encoded vector, which is then used to input the power inference model.

[0028] Step S3: Collect the hardware power consumption dataset of each core of the multi-core heterogeneous ASIC computing motherboard, input the hardware power consumption dataset and the encoding vector into the preset structured power inference model, and output the predicted power consumption value of each core in different time segments.

[0029] Specifically, a multi-channel power monitoring chip embedded in the motherboard (such as the TI INA3221) or a customized on-chip sensing module is used to periodically sample the current, voltage, and corresponding execution cycle information of each processing core, forming a timestamp-aligned hardware power consumption dataset. The sampling period is controlled at the 10ms level. The structured power inference model is based on a graph neural network (GNN) or a multilayer perceptron (MLP+Attention) with an attention mechanism. The structural design supports the input encoding vector and the hardware power consumption dataset as joint inputs, and outputs the core-level predicted power consumption value for each time segment (such as 10ms~100ms).

[0030] In one example, the power meter built into the NVIDIA Jetson platform was used to collect the current and voltage fluctuations of the four-core heterogeneous units within a 100ms time window, with the sampling frequency set to 1kHz. The time-aligned 128-dimensional encoded vector and the power signal sequence were input into the improved Bi-LSTM model, and the predicted power consumption value of each core in each window segment was output, with the error rate controlled within ±4%.

[0031] Step S4: Aggregate the predicted power consumption values ​​according to the core dimension, time dimension and task dimension to obtain the aggregation result, and identify the abnormal power consumption location based on the aggregation result.

[0032] Specifically, based on the predicted power consumption sequence of each core, the average power consumption and variance change rate within the sliding window are calculated, and a fluctuation confidence interval is formed by combining the upper and lower boundaries. On this basis, each prediction time period is labeled with a time series identifier, and a power consumption time set divided by processing core is constructed. Next, based on this matrix, the average power consumption, maximum fluctuation amplitude, and load overlap ratio of each processing core across all time periods are extracted to construct a core energy consumption feature set. Further, by combining task scheduling information with the constructed task mapping information, task-level energy consumption aggregation vectors, core-level power consumption stability indicators, and time-series energy consumption distribution structures are generated, ultimately constructing a three-dimensional power consumption tensor dataset with a task-core-time series structure. Attribution aggregation analysis is performed on this power consumption tensor dataset, outputting the transient fluctuation value and energy consumption index for each task, and identifying abnormal power consumption locations through a preset anomaly threshold strategy.

[0033] In one example, the fluctuation confidence interval is set to mean ± 2σ. An abnormal mutation point is defined as the fluctuation value exceeding the upper limit of the interval within three consecutive time periods, and the energy consumption index is greater than 0.85. If this condition is met, the time point is determined to be an abnormal power consumption location, and the corresponding task and core are recorded.

[0034] This embodiment acquires the execution data of each core during the operation of a multi-core heterogeneous ASIC computing motherboard and constructs a structured feature set based on the execution data. Next, the instruction architecture of each core of the multi-core heterogeneous ASIC computing motherboard is aligned with the structured feature set to extract energy-sensitive paths and key execution segments under multi-core collaboration. Then, the energy-sensitive paths and key execution segments are used to generate encoding vectors. Subsequently, hardware energy consumption datasets of each core of the multi-core heterogeneous ASIC computing motherboard are collected. The hardware energy consumption datasets and the encoding vectors are input into a preset structured power consumption inference model, which outputs the predicted power consumption values ​​of each core in different time-series segments. Finally, the predicted power consumption values ​​are aggregated in terms of core dimension, time dimension, and task dimension to obtain the aggregation result, and the abnormal power consumption locations are identified based on the aggregation result. It enables multi-dimensional modeling, collaborative perception, and anomaly identification, accurately capturing power consumption fluctuations caused by unbalanced task scheduling, structural mismatch, or operational coupling in multi-core heterogeneous architectures. It achieves end-to-end feature fusion and power consumption inference from execution data to hardware power consumption data, significantly improving the accuracy of power consumption modeling and the reliability of anomaly diagnosis in complex heterogeneous systems. It provides effective support for dynamic scheduling optimization and power consumption anomaly prevention and control of multi-core heterogeneous ASIC computing motherboards, and improves the problem of weak abnormal power consumption identification capability in traditional multi-core system power consumption monitoring methods.

[0035] Step S1 can preferably be one of the following steps S11 to S13, specifically as follows: Step S11: Periodically collect the instruction sequence, task scheduling time and load status of each core and general processor core within the preset operating cycle of the multi-core heterogeneous ASIC computing motherboard.

[0036] In this example step, a periodic triggering module embedded in the scheduler of a multi-core heterogeneous ASIC computing motherboard performs a status scan on each core and general-purpose processor core within each set time window (e.g., 10ms). The collected data includes the instruction sequence of each core in the current time period (i.e., a binary or assembly-level representation arranged in the order of instruction execution), the corresponding task scheduling time (including task start time, end time, and bound core number), and the load status in the current period (e.g., CPU utilization, memory access rate, instruction cache hit rate, etc.). All types of data are collected at the hardware level using high-precision timers and performance monitoring registers (such as PMU), and are timestamped and cached in a local intermediate result buffer for subsequent processing modules to retrieve.

[0037] In one example, taking a heterogeneous ASIC computing motherboard with 4 DSP cores and 2 general-purpose ARM cores as an example, during the execution of a specified algorithm task on the motherboard, the acquisition module triggers a scheduling query every 10ms, sequentially reading the instruction sequence (e.g., instruction format ADD R1, R2, R3), current task scheduling information (e.g., task T1 is assigned to DSP core 1, from timestamp 1032ms to 1045ms), and the load status during that time period (e.g., the average instruction execution rate of the DSP core during that time period is 85%, and the cache hit rate is 92%) from each core. All sampled data is written to a structured buffer named CoreTraceBuffer, and the data lifespan is set to 60 seconds for subsequent timing analysis processing.

[0038] Step S12: Generate execution data based on instruction sequence, task scheduling time, and load status.

[0039] In this example step, the instruction sequence, task scheduling time, and load status collected in step S11 are semantically fused, and the execution context information of each instruction is constructed through context association logic. This context information includes at least the following dimensions: the task number to which the instruction belongs, the start and end timestamps, the bound execution core number, the average load status of that core within the time slice, and scheduling switching information before and after the current task execution (such as the inbound / outbound task ID). The entire processing is implemented through a context parser, which, based on a multi-threaded mapping table, performs keyword comparison and time-series concatenation of different data sources within the same time period to generate structured execution data. The generated data is in the form of a five-tuple: <Instruction ID, Execution Time, Belonging Task ID, Core Number, Load Information>, and is sorted according to execution time.

[0040] In one example, taking the execution segment of task T1 collected in step S11 as an example, the parser identifies that the execution time slice of T1 is from 1032ms to 1045ms, belonging to DSP core 1, and the instruction sequence executed during this period consists of 10 basic instructions. The system associates these instructions with task scheduling information, marks each instruction as belonging to task T1, and supplements the load status data of DSP core 1 during this time period (e.g., ALU utilization of 78%, memory access count of 210 times), finally generating the following execution data:<ADDR1, R2, R3, 1032.4ms, T1, DSP1, ALU=78%, MEM_ACCESS=210> , <mul r4, r1, r2,1032.6ms, t1, dsp1, alu="83%," mem_access="230">Continue in this manner to complete the annotation of all instructions.

[0041] Step S13: Perform time-series analysis on the execution data, extract the operation type frequency, memory access density and scheduling switching count in the time period, and generate a structured feature set based on the operation type frequency, memory access density and scheduling switching count.

[0042] Wherein, step S13 can preferably be steps S131 to S133 as follows: Step S131: Perform time-series analysis on the execution data, extract the operation type frequency, memory access density and scheduling switching count in the time period, and generate a task running feature set based on the operation type frequency, memory access density and scheduling switching count.

[0043] In this example step, the system uses a sliding window mechanism (e.g., a window width of 1ms and a step size of 0.5ms) to segment the execution data along the timeline. Within each window, the system collects three key metrics: 1) Operation type frequency—the frequency and proportion of each type of instruction, categorized by arithmetic, logical, jump, and memory access; 2) Memory access density—the proportion of memory access instructions within the window and the actual memory bandwidth usage; 3) Scheduling switching count—the number of task inbound and outbound operations within the window. After the statistics are completed, the system aggregates these three metrics into a set of task execution feature data and creates a record for each time window. The task execution feature set for all time windows is stored in TaskFeatureSet, providing a foundation for the subsequent generation of task vector groups.

[0044] In one example, the system analyzes the execution data of task T1 during the period from 1032ms to 1045ms, using a 1ms sliding window for segmentation. For the window from 1033ms to 1034ms, the system counts 22 instructions: 12 arithmetic instructions, 3 memory access instructions, 4 logic instructions, and 3 control jump instructions; the memory access bandwidth usage is 5MB / s; and a task switch is detected within this window (T1 is temporarily suspended by DSP core 1). This information is encoded as the following runtime characteristics:<WindowID:1033,ADD:12, MEM:3, LOGIC:4, BRANCH:3, MEM_DENSITY:5MB / s, SWITCH_COUNT:1> .

[0045] Step S132: Classify and integrate the task running feature set according to the preset task identifier to obtain the integration result. Combine the integration result with the structural attributes of various cores of the multi-core heterogeneous ASIC computing motherboard to perform feature vector standardization processing to obtain the task vector group.

[0046] In this example step, the task runtime feature set generated in step S131 is clustered and integrated according to the task number to generate a task-level feature summary. Subsequently, the system standardizes the aggregated feature vector by combining the structural attributes of various cores in the current motherboard (such as instruction throughput, memory access bandwidth limit, and supported operation types). The standardization process uses Z-score normalization or Min-Max normalization, allowing the load features of different tasks on different cores to be compared under a unified dimension, thereby generating task vector groups. This process is implemented by the feature normalization engine, and the output is a standardized vector matrix, recording the unit load features of each type of task under each core structure.

[0047] In one example, tasks T1 and T2 are executed on a DSP core and an ARM core, respectively. The average operation type frequency vector of task T1 is [ADD=15, MEM=5, LOGIC=4]. The processing power of the ARM core and the DSP core for ADD is 100 MIPS and 150 MIPS, respectively. After Z-score normalization, the alignment vectors of T1 on the ARM core and the DSP core are [0.67, 0.45, 0.30] and [0.78, 0.38, 0.26], respectively, and finally combined into the following task vector group: [{Task: T1, Core: ARM, Vector: [0.67, 0.45, 0.30]}, {Task: T1, Core: DSP, Vector: [0.78, 0.38, 0.26]}, ... ].

[0048] Step S133: Construct a task time slice feature structure with multi-dimensional attribute labels using task vector groups and task scheduling time, and map the task time slice feature structure to a preset multi-dimensional task feature space to generate a structured feature set.

[0049] In this example step, each task vector group is matched with its corresponding task scheduling time to form a time-slice-level task load structure. Each structure contains multi-dimensional attribute labels such as task number, assigned core, time range, standardized load characteristics, and historical scheduling trajectory. The system uses these multi-dimensional attribute labels as keys to map unique coordinates to each time slice in a pre-defined multi-dimensional task feature space (e.g., three-dimensional space: task-time-core), realizing the mapping operation from time slice data to graph nodes. The graph structure is constructed in the form of a graph database (such as Neo4j), where nodes represent task time slices and edges represent scheduling trajectories or core migration trajectories, ultimately generating a complete structured feature set.

[0050] In one example, task T1 has an alignment vector of [0.78, 0.38, 0.26], a scheduling time slice of 1032ms–1045ms, belongs to DSP core 1, and has a scheduling trajectory of T3→T1→T4. The task time slice feature structure constructed by the system is as follows: { TaskID: T1, CoreID: DSP1, TimeWindow: [1032, 1045], LoadVector: [0.78, 0.38, 0.26], Trace: [T3→T1→T4] }

[0051] This structure is mapped to a node in the multidimensional task feature space and connected to other task nodes in the graph, forming a structured representation of the heterogeneous scheduling execution process.

[0052] Step S2 can preferably be one of the following steps S21 to S23, specifically as follows: Step S21: Based on the instruction architecture of each core of the multi-core heterogeneous ASIC computing motherboard, a core structure feature index is pre-constructed, including the supported instruction set types, arithmetic unit configuration and memory access path features; the load coupling features of each type of task in the structured feature set are mapped to the core structure feature index to analyze the degree of adaptation between each type of task and the core structure, and to obtain instruction adaptation parameters.

[0053] In this example step, static analysis is performed on the ISA (Instruction Set Architecture) of each core to extract the supported instruction set types, including but not limited to arithmetic and logic operations, branch jumps, memory access instructions, vector processing, and custom operation instructions. Combining the definition of the core microarchitecture in a hardware description language (such as Verilog or VHDL), the parallelism of its arithmetic units (e.g., scalar ALU, FPU, SIMD units) and memory access path topology (e.g., L1 cache, bandwidth, latency) are extracted. A core structure feature index table is then constructed, with the core number as the key, linking the aforementioned feature items.

[0054] Subsequently, the load coupling features of each task type in the structured feature set generated in step S13 are structurally matched with the aforementioned index. The load coupling features refer to the execution path utilization, resource consumption, and conflict probability of various operation types (such as floating-point multiplication, branching, and bitwise operations) in the target core structure. Instruction adaptation parameters are generated through the matching relationship, where each item in the matrix represents the execution coupling strength score of a certain type of operation of the task on a certain core. The scoring criteria include execution latency, instruction issuance success rate, and structural hazard probability.

[0055] In one example, suppose task A involves a large number of floating-point multiplication and division instructions, branch jumps, and cache-intensive access behaviors. Its load coupling characteristics are: floating-point operation frequency accounts for 70%, L1 cache hit rate is 65%, and average scheduling switching interval is 30µs. For a core that supports IEEE-754 floating-point operations, has an FPU but no branch prediction mechanism, its FPU operation unit bandwidth is 2 instructions / cycle, and its memory access bandwidth is 64 bits / cycle. After analysis, it is found that this core has a high coupling strength to task A, with a fit score of 0.81.

[0056] This scoring mechanism ultimately yields an instruction adaptation parameter of size (number of task types × number of cores), laying the foundation for subsequent path identification and energy consumption analysis.

[0057] Step S22: Identify high-frequency instruction segments and cross-core collaborative segments with concentrated power consumption fluctuations during multi-core scheduling based on instruction adaptation parameters and task jump features, and construct a set of energy-sensitive paths based on high-frequency instruction segments and cross-core collaborative segments; among them, task jump features are the number of core migrations, task switching latency and context reconstruction frequency of tasks within the scheduling cycle.

[0058] In this example step, the task scheduling log and instruction execution trajectory are analyzed to extract the multi-core migration behavior of the task during its runtime cycle, including the timestamp of the core switching event, the core number before and after the switch, the change in task scheduling priority, and the time cost of context reconstruction, in order to constitute the task jump characteristics.

[0059] Based on instruction adaptation parameters, extract high-energy-consuming instruction segments that frequently occur during core switching (such as high-frequency floating-point operations, branch failure re-execution segments, shared cache contention segments, etc.) and mark them as high-frequency instruction segments; if it is detected that a task frequently alternates between two or more cores (such as data prefetching is completed on core A and computation tasks are completed on core B), and this process is accompanied by power consumption spikes, it is marked as a cross-core collaborative segment.

[0060] Subsequently, based on the timing range, power consumption fluctuation intensity, and jump context characteristics of the instruction segments, the aforementioned high-frequency instruction segments and cross-core collaborative segments are integrated to form a set of energy-sensitive paths. This set records the execution segments that have the greatest impact on system power consumption under a multi-core scheduling environment, providing key input for subsequent behavior coding.

[0061] In one example, suppose a task T undergoes three core migrations within 10ms, from Core0 → Core2 → Core3, with each migration preceded and followed by the execution of an FPU-intensive subtask. Analysis of its jump characteristics reveals a context reconstruction latency of up to 6µs and significant scheduling response time jitter. The corresponding execution data shows that the frequently invoked instruction segments are combinations of three instructions: FMUL.D (floating-point multiplication double precision), LOAD.D, and STORE.D, which are re-issued after each migration. Matching with the adaptation matrix reveals that these instruction segments have the shortest execution path and the largest power consumption fluctuation on Core3. Therefore, this is identified as a critical path in the energy-sensitive path set.

[0062] Step S23: Sort and cluster the energy-sensitive path set to obtain the sorting and clustering results. Combine the sorting and clustering results with the scheduling information to extract the key execution segments that have the most significant impact on power consumption. Encode the energy-sensitive path set and the key execution segments to obtain the encoding vector. The scheduling information includes scheduling priority, time slice utilization rate and inter-core migration ratio.

[0063] In this example step, density clustering (such as DBSCAN) and ranking algorithms (such as weighted ranking based on path fluctuation amplitude and power consumption area) are used to cluster and rank the energy-sensitive path set. Each path is quantified based on its average power consumption, duration, cross-core execution frequency, and task occupancy ratio to generate a cluster label.

[0064] Subsequently, the clustering results are fused with scheduling information. The scheduling information includes the task's scheduling priority (e.g., real-time priority level), the task's time slice occupancy in the target core (e.g., 40%), and the frequency and proportion of migration behavior (e.g., 3 core switches during the entire task execution cycle, with a total migration time occupancy of 10%). These parameters are used as weights to further filter the paths in the clustering results.

[0065] Finally, the key execution segments most sensitive to power consumption fluctuations under scheduling semantics were selected, and they were vectorized using encoding logic, including fields such as path number, operation mode features, scheduling attribute labels, and core instruction mapping features, to construct an encoding vector, providing an efficient semantic representation for subsequent power consumption model input.

[0066] In one example, a certain type of task, after cluster analysis, forms three energy-sensitive path clusters. Among them, the sub-paths in path cluster C2 have an average power consumption of 260mW, an execution time of 15ms, and account for 65% of the scheduling time slice. Its corresponding scheduling information is priority 5 (the highest being 0) and migration ratio of 12%. Based on the ranking and scheduling attribute analysis, cluster C2 is identified as the most critical path. The execution segment LOAD → FMUL → FADD → STORE, its running cycle, corresponding core number, scheduling status, etc., are extracted and encoded according to the predefined field order to generate a 64-bit encoded vector for subsequent power consumption prediction model input.

[0067] Step S3 can preferably be any of the following steps S31 to S33, specifically as follows: Step S31: Synchronously obtain the current, voltage and power sampling values ​​of the corresponding timing segment from the local power monitoring interface of each core of the multi-core heterogeneous ASIC computing motherboard, and generate a hardware power consumption dataset based on the current, voltage and power sampling values.

[0068] In this example step, the local power monitoring module integrated in the multi-core heterogeneous ASIC computing motherboard is used to synchronously sample the power consumption parameters of each core. Each core is sampled in real time through a voltage sensing module and current detection circuit (such as shunt resistor detection and current transformer) provided by the on-chip power management unit. Triggered by the system global scheduling clock, the control logic collects the power consumption parameters of each core at equal intervals (e.g., 1ms).

[0069] The collected raw data includes: voltage (V), current (A), and power (W) values ​​for each core. Each sample is associated with a corresponding time stamp. After collection, the data is transferred to the central monitoring module via DMA and indexed by time sequence and core number to construct the initial hardware energy consumption dataset.

[0070] In one example, a multi-core heterogeneous ASIC computing motherboard has four cores, numbered Core0 to Core3. Each core samples current, voltage, and power values ​​every 1ms during operation. For example: Core0 collected a current of 320mA and a voltage of 1.0V at 1ms, and calculated the power to be 0.32W. Core1 collected data at the same time, showing a current of 270mA, a voltage of 0.9V, and a power of 0.243W. The rest of the cores follow the same pattern.

[0071] Each record, along with its timestamp and core number, constitutes an energy consumption sampling item. All sampling items form a complete hardware energy consumption dataset, providing a real physical measurement basis for subsequent power consumption modeling.

[0072] Step S32: Perform noise filtering and timing alignment processing on the hardware power consumption dataset to construct the timing power consumption features of the encoding vector, and input the encoding vector and timing power consumption features into the preset structured power inference model.

[0073] In this example step, the hardware power consumption dataset generated in step S31 is filtered and normalized to eliminate high-frequency noise caused by power supply disturbances, electromagnetic interference, or ADC sampling errors. Commonly used filtering algorithms are moving average filtering and wavelet denoising. The moving average filtering uses a local smoothing strategy with a window width of 3 to remove abrupt transition points, while wavelet denoising uses the Daubechies-4 wavelet function to decompose the signal and performs threshold pruning on high-frequency coefficients.

[0074] Next, based on the system global clock and task scheduling timestamps, the power consumption sampling data of each core is time-aligned. The alignment strategy is to use the time slice boundary of the encoding vector as a reference benchmark, and re-divide the power consumption data into time segments that correspond one-to-one with the encoding vector, ensuring that the behavior representation and power consumption record are highly consistent in the time dimension.

[0075] The final result is a time-series power consumption feature, with each sequence corresponding to an encoding vector, including time-series statistical features such as average power consumption value, power consumption fluctuation amplitude, fluctuation frequency, and peak position, which serve as the model input.

[0076] In one example, a key execution segment represented by a certain encoding vector spans a 3ms time interval, and the corresponding Core2 sampling power value for this segment is: 1ms: 0.30W, 2ms: 0.35W, 3ms: 0.28W.

[0077] After applying a moving average filter, the smoothed power consumption sequence is obtained as [0.315W, 0.31W, 0.31W]. After extracting the statistical features of this sequence, the following features are obtained: average power consumption: 0.312W; fluctuation range: ±0.02W; peak position: 2ms. This power consumption feature sequence will be merged with the encoded vector and input into the structured power consumption inference model.

[0078] Step S33: Perform multivariate power estimation on the encoding vector and timing power characteristics using a structured power inference model, and output the predicted power consumption value of each core in different timing segments.

[0079] In this example step, a pre-trained structured power inference model is used to fuse and infer the input encoded vector and temporal power consumption features. This model is a multi-input feature-aware structure that can use existing ensemble learning algorithms (such as XGBoost) or lightweight neural networks (such as BiLSTM-FFN structures) to capture the differences in nonlinear behavior and power consumption trends between cores.

[0080] The model jointly models the structural information in the encoded vector (such as task type, core number, scheduling status, etc.) with the temporal correlation in the power consumption feature sequence, and outputs the corresponding predicted power consumption value for each time segment. The accuracy of this prediction is higher than that of traditional regression models, and it can adapt to different combinations of instruction-level contexts and hardware behaviors.

[0081] The prediction results are output in the format of a triplet sequence of timestamp-core number-predicted power consumption value, which can be used for further aggregation and attribution analysis.

[0082] In one example, the input encoded vector represents a high-frequency floating-point execution segment of a task on Core 1, and the power consumption feature sequence shows frequent power fluctuations. This is input into a structured power inference model built on a BiLSTM network, which predicts power consumption based on task context and time-series features: The predicted power consumption is 0.26W in the 1ms, 0.29W in the 2ms, and 0.31W in the 3ms.

[0083] The error between the result and the actual sampled value is less than ±4%, which meets the accuracy requirements. All predicted power consumption values ​​are composed of a time-series output sequence, which serves as the basis for energy consumption attribution and anomaly identification in the subsequent step S4.

[0084] Step S4 can preferably be one of the following steps S41 to S45, specifically as follows: Step S41: Analyze the fluctuation confidence interval based on the predicted power consumption value, map and calibrate the fluctuation confidence interval with the corresponding encoding vector, extract the corresponding clock cycle stamp and task execution identifier to obtain the timing identifier, and construct a power consumption time set divided by processing core based on the predicted power consumption value, fluctuation confidence interval and timing identifier.

[0085] In this example step, the predicted power consumption sequence obtained in step S3 is used to calculate the confidence interval of power consumption within each time slice using deterministic statistical methods. For example, at a 95% confidence level, a sliding window statistical method is used to derive the upper and lower limits of the fluctuation range. In practice, for each time slice, the average and standard deviation of all power consumption values ​​within that time slice are calculated to construct the confidence interval.

[0086] Subsequently, based on the core number, task number, and execution status fields carried in the encoding vector, each power consumption sample point is calibrated, and its corresponding clock cycle stamp and task execution identifier are extracted to form a complete time identifier (i.e., time sequence identifier). Based on this, all predicted power consumption samples are aggregated under the corresponding processing core to construct a two-dimensional power consumption time set.

[0087] Each row of the matrix corresponds to a core, and each column corresponds to a time slice. The value in each cell is the predicted power consumption range and its center value within that time slice, forming the basic data structure for aggregation analysis.

[0088] In one example, the predicted power consumption of Core2 during the period from 15ms to 20ms is [0.28W, 0.29W, 0.35W, 0.27W, 0.30W, 0.33W]. After statistical analysis using a 95% confidence interval, the fluctuation range for this time period is [0.27W, 0.35W], with a mean of 0.303W. According to the encoding vector, this segment of predicted power consumption corresponds to task T104 during the Core2 execution phase, with a timestamp of [15ms–20ms] and the task execution identifier being T104@Core2.

[0089] Through mapping, this data segment is filled into columns 15-20 of the Core2 row in the power consumption time set, and subsequent steps use this matrix as input to perform power consumption attribution processing.

[0090] Step S42: Calculate the average power consumption, maximum fluctuation range, and load overlap ratio of each processing core in all time periods using the power consumption time set, and construct a core energy consumption feature set based on the average power consumption, maximum fluctuation range, and load overlap ratio.

[0091] In this example step, each row of the power consumption time set is iterated through sequentially to extract the power consumption sequence for each core. Statistical calculations are then performed on this sequence to extract the following three core energy consumption metrics: Average power consumption: The arithmetic mean of the power consumption values ​​at the center of all time slices; Maximum fluctuation range: The maximum span of the confidence interval (upper limit minus lower limit) across all time slices. Load overlap ratio: This is a statistical measure of the proportion of overlapping multi-task scheduling within each time slice, indicating the degree of parallel processing of that core.

[0092] These metrics together constitute the core's energy consumption feature vector, which is used to subsequently determine whether there are abnormal power consumption behaviors or imbalances in scheduling strategies.

[0093] In one example, Core1's power consumption time frame behavior is: [0.21W, 0.23W, 0.25W, 0.24W, 0.29W, 0.26W], with a maximum fluctuation range of 0.06W. The system scheduling log shows that this core had 4 time slices with overlapping tasks, accounting for 66.7% of the total time period. Ultimately, the core's energy consumption feature vector is: average power consumption: 0.246W; maximum fluctuation range: 0.06W; load overlap ratio: 66.7%.

[0094] This result is stored as one of the core energy consumption features for use in the next step of attribution processing.

[0095] Step S43: Based on the task scheduling log of the multi-core heterogeneous ASIC computing motherboard, extract the allocation core, migration trajectory and scheduling priority information of each task in different time segments, and generate a scheduling identifier based on the allocation core, migration trajectory and scheduling priority information.

[0096] In this example step, the scheduling path of each task throughout its entire runtime is extracted by reading the motherboard system scheduling log. This path includes the cores allocated to the task in different time slices, the specific timing trajectory of migration from one core to another, and the priority level at each scheduling.

[0097] All scheduling path entries are standardized into structured scheduling identifiers. Each identifier record includes the following fields: task number, scheduling time period, allocation core number, migration direction (source core and target core), scheduling priority level, etc.

[0098] In one example, task T210 experiences the following scheduling trajectory between 10ms and 30ms: 10ms–15ms allocation to Core0 (priority 6); Migrate to Core2 (priority 5) in 16ms–25ms; Migrate to Core 3 (priority 4) in 26ms–30ms.

[0099] This scheduling path generates the following scheduling identifier structure: { "task_id": "T210", "segments": [ {"start": 10, "end": 15, "core": "Core0", "priority": 6}, {"start": 16, "end": 25, "core": "Core2", "priority": 5}, {"start": 26, "end": 30, "core": "Core3", "priority": 4} ] }

[0100] Step S44: Perform a dual association mapping between the execution data and the task scheduling time using timestamps and core numbers, extract the scheduling relationship between the task and the corresponding core for each instruction, and generate task mapping information.

[0101] In this example step, the execution timestamp, program counter (PC) value, and thread number of each instruction are extracted from the collected execution data. Combined with the scheduling identifier generated in step S43, a dual mapping strategy of timestamp alignment and core number alignment is used to accurately associate each instruction with its actual task and scheduling core.

[0102] After the association is completed, task mapping information is generated, and the record format is: instruction number – belonging task number – execution core number – scheduling time segment.

[0103] In one example, instruction ID#9834 is executed at 17ms, its program counter points to a floating-point calculation module, and the thread number corresponds to task T210. The scheduling flag confirms that T210 is scheduled to Core2 during the 17ms period. Therefore, the instruction mapping information is: Instruction ID: 9834; Task: T210; Execution Core: Core2; Time Segment: 16ms–25ms.

[0104] This information is stored in the task mapping table, providing a basic basis for power consumption attribution and abnormal mutation detection.

[0105] Step S45: Fuse the core energy consumption feature set, scheduling identifier and task mapping information to obtain the location of abnormal power consumption.

[0106] In this example step, the structured data from steps S42 to S44 are combined with conditional clustering analysis and a sliding window power consumption comparison algorithm to identify time periods in which significant anomalies occur between task scheduling, instruction context, and power consumption trends.

[0107] Key identification logic includes: The core energy consumption characteristics show an uneven distribution (e.g., the power consumption of a certain core is consistently high). After a certain task was migrated, the power consumption suddenly increased, exceeding the historical average of +3σ; The instruction mapping revealed that similar operations produce different power consumption levels on different cores.

[0108] If these conditions are met, the current time slice or instruction point is determined to be an abnormal power consumption location, and its corresponding timestamp, core number, task number and impact index are recorded to form an abnormal power consumption list.

[0109] In one example, after task T105 migrated to Core1, its power consumption suddenly increased from 0.25W to 0.35W, more than doubling. Combined with instruction mapping information, this segment was confirmed to be a high-concurrency I / O processing segment, and such high fluctuations were not observed in historical data. The system marked this time slice (e.g., 22ms@Core1) as an abnormal power consumption location and recorded the following information: Timestamp: 22ms; Core ID: Core1; Task: T105; Anomaly Type: Power Consumption Surge After Migration; Triggering Indicator: Fluctuation Amplitude > Historical Average + 3σ; This mutation point is for further analysis and processing by the system operation and maintenance or power consumption optimization scheduling strategy module.

[0110] Step S45 can preferably be one of the following steps S451 to S454, specifically as follows: Step S451: Integrate the core energy consumption feature set, scheduling identifier and task mapping information to generate a task-level energy consumption aggregation vector, a core-level power consumption stability index and a time period energy consumption distribution structure.

[0111] In this example step, based on task mapping information, all power consumption data involved in each task throughout its lifecycle are aggregated to calculate its corresponding average power consumption, power consumption standard deviation, peak power consumption, number of cores involved, etc., forming a task-level energy consumption aggregation vector. This vector fields include: task number, task duration, average power consumption, peak power consumption, power consumption variance, core distribution density, etc.

[0112] Next, based on the core power consumption feature set, the power consumption stability indicators of each core are statistically analyzed, including: root mean square error of power consumption (RMSE), confidence interval volatility, cross-task power consumption offset, etc., to generate a core-level power consumption stability indicator set.

[0113] Finally, the system uses a sliding time window as a unit to statistically analyze the power consumption data of each core in each time period, forming a time period power consumption distribution structure. This structure uses timestamps as indexes and records data such as the core distribution power consumption ratio, abnormal power consumption slope, and task coverage within that time period.

[0114] In one example, task T301 has a lifecycle of 10ms–40ms, involving Core1 and Core3. The average power consumption is 0.28W, the peak power consumption is 0.39W, and the standard deviation of power consumption is 0.034W, resulting in the following task energy consumption aggregation vector: { "task_id": "T301", "duration": 30ms, "mean_power": 0.28W, "peak_power": 0.39W, "std_dev": 0.034W, "core_span": 2 } Core1's power consumption RMSE was 0.015W throughout the entire analysis period, the variance across tasks was 0.026, and the average confidence interval span was 0.045W, which serve as its power consumption stability indicators.

[0115] The energy consumption distribution structure within the time period of 20ms–30ms shows that Core1 accounts for 62%, Core2 accounts for 28%, and Core3 accounts for 10%. There were two abnormal gradient changes during this period, and the task coverage reached 87%.

[0116] Step S452: Generate a power consumption representation structure using the task-level energy consumption aggregation vector, the core-level power consumption stability index, and the time-period energy consumption distribution structure.

[0117] In this example step, a three-dimensional representation structure is constructed with the task dimension, core dimension, and temporal dimension as its axes. Specifically, this is achieved by: The energy consumption aggregation vector for each task is expanded along the task dimension; The power consumption stability metrics for each core are expanded on the core dimension; The power consumption distribution data within each sliding time window is expanded in the time dimension.

[0118] After normalization, the three sets of data are organized into a unified data cube structure using a tensor combination function (such as Tensor.mergeStack), which facilitates subsequent input into the analysis model in the form of structured tensors.

[0119] In one example, task T301 is mapped to Core1 and Core3, with a time period of 10ms–40ms. The values ​​of all its metrics in the task dimension (T301), core dimension (Core1, Core3), and time-series dimension (30 time points) are combined to generate a portion of the following tensor structure: PowerTensor[T301][Core1][10ms] = 0.29W; PowerTensor[T301][Core1][11ms] = 0.31W; ... PowerTensor[T301][Core3][25ms] = 0.27W; ...

[0120] Step S453: Construct a power tensor dataset with a three-dimensional structure of task-core-time sequence based on the power consumption representation structure, and perform attribution aggregation analysis on the power tensor dataset to obtain the transient fluctuation value and energy consumption index corresponding to each task.

[0121] In this example step, the constructed power consumption tensor dataset is fed into a statistical framework based on attribution clustering analysis. This framework uses a multidimensional sliding window clustering algorithm (such as K-shape clustering or Spectral Clustering) to perform subspace clustering analysis on the power consumption tensor, thereby identifying anomalous clustering regions of power consumption.

[0122] Transient fluctuation value: Calculate the maximum power consumption change magnitude and the steepest power consumption gradient for each task in the time dimension.

[0123] Energy consumption metrics: The variance ratio of power consumption distribution on different cores for the same task is statistically analyzed to measure the degree to which the task's power consumption is concentrated on a few cores.

[0124] The analysis process explicitly sets a fixed sliding window size (e.g., 5ms) and performs attribution mapping on tensor slices within each window to ensure that the output results have a clear spatiotemporal reference.

[0125] In one example, the power consumption of task T402 suddenly increased from 0.23W to 0.37W between 20ms and 25ms, with a sudden change gradient of +0.028W / ms, and its transient fluctuation value was calculated to be 0.14W.

[0126] The task's power consumption was as high as 78% on Core 2, while Core 1 and Core 3 accounted for only 12% and 10% respectively, with a power consumption variance ratio of 0.76, indicating a significant concentration of core power consumption.

[0127] Step S454: Identify transient fluctuation values ​​and energy consumption indicators through a preset abnormal threshold strategy to obtain the location of abnormal power consumption.

[0128] In this example step, predefined threshold rules are used to determine anomalies in the aforementioned analysis results. The anomaly threshold strategy employed includes: The transient fluctuation value is greater than the historical task mean plus 3 standard deviations; The concentration of core energy consumption is greater than the set upper limit of concentration (e.g., 0.7). When multiple tasks cluster on the same core within the same time period, the power consumption overlap rate is greater than 80%.

[0129] Once any of the above conditions are met, the behavior of the task in the corresponding time period is determined to be an abnormal power consumption location, and its identification information (task number, core number, timestamp, trigger indicator type) is output.

[0130] In one example, the transient fluctuation of task T510 was 0.16W, exceeding three standard deviations of the historical average fluctuation of 0.05W (with a threshold of 0.14W). Simultaneously, the power consumption of this task during the 25ms–30ms period was almost entirely concentrated in Core0, with a concentration of 0.84, exceeding the set upper limit. Based on this, the system identified this time period as an abnormal power consumption location and generated the following structured identifier: { "task_id": "T510", "core": "Core0", "timestamp": "25ms–30ms", "abnormal_type": "transient mutation + concentrated energy consumption", "wave_magnitude": 0.16W, "concentration_index": 0.84 }

[0131] Example 3: like Figure 2 As shown, this embodiment provides an energy consumption monitoring system 10 for a multi-core heterogeneous ASIC computing motherboard. The energy consumption monitoring system includes the following modules: The data acquisition module 11 is mainly used to acquire the execution data of each core during the operation of the multi-core heterogeneous ASIC computing motherboard, and to construct a structured feature set based on the execution data.

[0132] The data acquisition module 11 obtains execution data in real time, including program counter, operation type, register read / write status and cache hit rate, by accessing the low-level execution monitoring interface of each core in the motherboard. It also constructs a structured feature set based on task dimension, operation category dimension and time sequence dimension to provide accurate behavioral description vectors for subsequent energy consumption behavior modeling.

[0133] Alignment analysis module 12 is mainly used to align the instruction architecture and structured feature set of each core of the multi-core heterogeneous ASIC computing motherboard in order to extract the energy-sensitive path and key execution segment under multi-core collaboration, and generate encoding vector using the energy-sensitive path and key execution segment.

[0134] The alignment analysis module 12, based on a pre-defined heterogeneous instruction architecture index table, compares the structural characteristics (such as pipeline depth, memory access path length, and instruction decoding complexity) of different cores when processing various instructions. It maps load coupling characteristics to the structure index table and calculates instruction adaptation parameters between tasks and cores. Furthermore, by combining task jump characteristics (such as migration frequency and switching latency), it identifies high-frequency instruction segments and cross-core collaborative segments with concentrated power consumption fluctuations. The resulting set of energy-sensitive paths is sorted and clustered, and combined with scheduling priority and other information, key high-energy-consuming contribution segments are extracted and finally encoded into representative coding vectors.

[0135] The data acquisition module 13 is mainly used to collect the hardware power consumption dataset of each core of the multi-core heterogeneous ASIC computing motherboard, input the hardware power consumption dataset and the encoding vector into the preset structured power inference model, and output the predicted power consumption value of each core in different time segments.

[0136] The data acquisition module 13 connects to the local power monitoring path of each core, accurately recording current, voltage, and instantaneous power according to the sampling period, generating a standardized hardware energy consumption dataset. After noise filtering and time alignment, the data is synchronously input into a structured power inference model (such as a Transformer-MLP fusion structure or an LSTM regression network) along with the encoded vector, enabling the output of predicted power consumption values ​​for each core under different time windows, ensuring the time accuracy control and prediction reliability of the dynamic energy consumption evolution process.

[0137] The aggregation processing module 14 is mainly used to aggregate the predicted power consumption value in terms of core dimension, time dimension and task dimension to obtain the aggregation result, and to identify the location of abnormal power consumption based on the aggregation result.

[0138] The aggregation processing module 14 performs multi-dimensional attribution analysis on the prediction results, constructing a comprehensive aggregation result matrix from the core dimension (such as stability fluctuation RMSE), time dimension (such as fluctuation confidence interval), and task dimension (such as mapping energy consumption contribution). It also combines scheduling identifiers and instruction mapping relationships to construct a three-dimensional structure representation of task-core-time series. This module further integrates task energy consumption aggregation vectors, core fluctuation stability indicators, and time-series energy consumption distribution structures to construct a power consumption tensor dataset. Through anomaly identification strategies (such as power consumption mutations exceeding thresholds, abnormal energy consumption concentration, etc.), it identifies and labels mutation features, ultimately locating abnormal power consumption locations with engineering value to assist in system scheduling optimization or fault early warning decisions.

[0139] This embodiment constructs a four-level module system consisting of data acquisition, alignment, energy consumption modeling, and aggregation attribution. It establishes precise correlations in three dimensions: task behavior semantics, core structure adaptation, and power consumption timing analysis. This breaks through the limitations of existing energy consumption monitoring technologies that rely on simple power average statistics. It enables the modeling, prediction, and diagnostic identification of fine-grained energy consumption behavior in multi-core heterogeneous environments, significantly improving the intelligence level and system adaptability of energy consumption analysis.

[0140] It should be noted that although several modules or units of the system for executing actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to the embodiments of this application, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0141] Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause an electronic device (such as a personal computer, server, touch terminal, or network device, etc.) to execute the methods according to the embodiments of this application.

[0142] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the embodiments disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein.

[0143] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.< / mul>

Claims

1. A method for monitoring energy consumption of a multi-core heterogeneous ASIC computing motherboard, the method comprising: The method comprises the following steps: ​ acquiring execution data of each core in the running process of a multi-core heterogeneous ASIC computing mainboard, and constructing a structured feature set based on the execution data; aligning the instruction architecture of each core of the multi-core heterogeneous ASIC computing mainboard with the structured feature set to extract an energy consumption sensitive path and a key execution segment under multi-core collaboration, and generating a code vector by using the energy consumption sensitive path and the key execution segment; collecting a hardware energy consumption data set of each core of the multi-core heterogeneous ASIC computing mainboard, inputting the hardware energy consumption data set and the code vector into a preset power consumption inference model, and outputting a predicted power consumption value of each core in different time sequence segments; performing aggregation processing on the predicted power consumption value in the core dimension, time dimension and task dimension to obtain an aggregation result, and identifying an abnormal power consumption position based on the aggregation result. 2.The energy consumption monitoring method of the multi-core heterogeneous ASIC computing mainboard according to claim 1, wherein, The step of acquiring execution data of each core in the running process of a multi-core heterogeneous ASIC computing mainboard, and constructing a structured feature set based on the execution data, comprises the following steps: periodically collecting instruction sequences, task scheduling times and load states of each core and a general processor core within a preset running period of the multi-core heterogeneous ASIC computing mainboard; generating execution data based on the instruction sequences, the task scheduling times and the load states; performing time sequence analysis on the execution data, extracting operation type frequency, memory access density and scheduling switching times in a time period, and generating a structured feature set based on the operation type frequency, the memory access density and the scheduling switching times. 3.The energy consumption monitoring method of the multi-core heterogeneous ASIC computing mainboard according to claim 2, characterized in that, The step of performing time sequence analysis on the execution data, extracting operation type frequency, memory access density and scheduling switching times in a time period, and generating a structured feature set based on the operation type frequency, the memory access density and the scheduling switching times, comprises the following steps: performing time sequence analysis on the execution data, extracting operation type frequency, memory access density and scheduling switching times in a time period, and generating a task running feature set based on the operation type frequency, the memory access density and the scheduling switching times; classifying and integrating the task running feature set according to a preset task identifier to obtain an integration result, and performing feature vector standardization processing on the integration result in combination with the structural properties of each type of core of the multi-core heterogeneous ASIC computing mainboard to obtain a task vector group; generating a structured feature set based on the task vector group and the task scheduling times. 4.The method of claim 1, wherein, The step of aligning the instruction architecture of each core of the multi-core heterogeneous ASIC computing mainboard with the structured feature set to extract an energy consumption sensitive path and a key execution segment under multi-core collaboration, and generating a code vector by using the energy consumption sensitive path and the key execution segment, comprises the following steps: previously constructing a core structure feature index based on the instruction architecture of each core of the multi-core heterogeneous ASIC computing mainboard, mapping each type of task in the structured feature set to the core structure feature index, and generating instruction adaptation parameters based on the corresponding task index; The instruction adaptation parameter and the task jump feature are used to identify a high-frequency instruction segment and a cross-core collaboration segment with concentrated power consumption fluctuations in a multi-core scheduling process, and an energy consumption sensitive path is determined based on the high-frequency instruction segment and the cross-core collaboration segment; wherein the task jump feature is the number of core migrations, task switching delay and context reconstruction frequency of the task in a scheduling period; The energy consumption sensitive path set is sorted and clustered to obtain a sorting and clustering result, the sorting and clustering result is combined with scheduling information to extract a key execution segment, and the energy consumption sensitive path set and the key execution segment are encoded to obtain an encoding vector; wherein the scheduling information is scheduling priority, time slice usage rate and migration proportion between processing cores. 5.The method of claim 1, wherein, The steps of collecting a hardware energy consumption dataset of each core of a multi-core heterogeneous ASIC computing mainboard, inputting the hardware energy consumption dataset and the encoding vector into a preset structured power consumption inference model, and outputting predicted power consumption values of each core in different timing segments, include: Synchronously obtaining current, voltage and power sampling values of the corresponding timing segment from the local power monitoring interface of each core of the multi-core heterogeneous ASIC computing mainboard, and generating a hardware energy consumption dataset based on the current, voltage and power sampling values; Noise filtering and timing alignment processing are performed on the hardware energy consumption dataset to construct a timing power consumption feature, and the encoding vector and the timing power consumption feature are input into a preset structured power consumption inference model; The encoding vector and the timing power consumption feature are subjected to multivariate power consumption estimation through the structured power consumption inference model, and predicted power consumption values of each core in different timing segments are output. 6.The energy consumption monitoring method of the multi-core heterogeneous ASIC computing mainboard according to claim 2, wherein, The steps of performing core dimension, time dimension and task dimension aggregation processing on the predicted power consumption values to obtain an aggregation result, and identifying an abnormal power consumption position based on the aggregation result, include: A fluctuation confidence interval is analyzed based on the predicted power consumption values, and a power consumption time set is constructed based on the fluctuation confidence interval; The average power consumption, maximum fluctuation amplitude and load overlap ratio of each processing core in all time segments are calculated using the power consumption time set to construct a core energy consumption feature set; Task scheduling logs of the multi-core heterogeneous ASIC computing mainboard are used to extract scheduling identifiers generated by each task in different timing segments; The execution data and the task scheduling time are doubly associated and mapped with timestamps and core numbers to generate task mapping information; The core energy consumption feature set, scheduling identifier and task mapping information are fused to obtain an abnormal power consumption position.

7. The method of claim 6, wherein the method further comprises: The steps of fusing the core energy consumption feature set, scheduling identifier and task mapping information to obtain an abnormal power consumption position include: The core energy consumption feature set, scheduling identifier and task mapping information are fused to generate a power consumption representation structure; A power consumption tensor dataset is constructed based on the power consumption representation structure, and attribution aggregation analysis is performed on the power consumption tensor dataset to obtain transient fluctuation values and energy consumption indicators corresponding to each task; An abnormal power consumption position is obtained by identifying the transient fluctuation values and the energy consumption indicators through a preset abnormal threshold strategy.

8. An energy consumption monitoring system of a multi-core heterogeneous ASIC computing motherboard, characterized by, ​ The data acquisition module is configured to acquire execution data of each core in a running process of the multi-core heterogeneous ASIC computing mainboard, and construct a structured feature set based on the execution data. The alignment analysis module is configured to align instruction system structures of each core of the multi-core heterogeneous ASIC computing mainboard with the structured feature set, so as to extract an energy consumption sensitive path and a key execution segment under multi-core cooperation, and generate a code vector by using the energy consumption sensitive path and the key execution segment. The data acquisition module is configured to acquire hardware energy consumption data sets of each core of the multi-core heterogeneous ASIC computing mainboard, input the hardware energy consumption data sets and the code vector into a preset structured power consumption inference model, and output predicted power consumption values of each core in different timing sections. The aggregation processing module is configured to perform aggregation processing on the predicted power consumption values in a core dimension, a time dimension and a task dimension, obtain an aggregation result, and identify an abnormal power consumption position based on the aggregation result.

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