Maintenance, recording and transmission method, device and equipment for cache consistency

Abstract

The invention discloses a maintenance, recording and transmission method, device and equipment for cache consistency, and the recording method comprises the steps: responding to a first processing unit in a processing unit array to cache a first data block, and obtaining a first position coordinate of the first processing unit in the processing unit array, the first coordinate comprises a plurality of values respectively corresponding to a plurality of dimensions of the processing unit array; according to the first coordinate data, a first directory entry corresponding to the first data block in the cache consistency directory is updated, the first directory entry comprises a plurality of arrays corresponding to a plurality of dimensions, and in the first directory entry, the first data block corresponds to the first directory entry; the array corresponding to each dimension is used for marking dimension coordinates of the processing unit which caches the first data block on the dimension. The recording method can reduce the directory capacity.

Description

Technical Field

[0001] The embodiments of this disclosure relate to a method for recording a cache consistency catalog, a method for maintaining cache consistency, a method for transmitting cache consistency requests, a device for recording a cache consistency catalog, a cache consistency node, a processor chip, an electronic device, and a storage medium. Background Technology

[0002] In multi-core processors (such as multi-core CPUs), each processor core has its own cache. A processor core can read data from main memory (such as Double Data Rate, DDR) and store it in its local cache for computation. After performing a computation, the processor core can update the data in its cache and write the updated data back to main memory. If multiple processor cores use the same data simultaneously, that data will have multiple copies stored in multiple caches. Because multiple processor cores operate in parallel, modifications to data in one cache may not promptly notify other caches, potentially leading to inconsistencies and errors. Therefore, maintaining cache consistency across multiple cores is crucial. There are two main strategies for multi-core CPU cache consistency: bus-sniffing-based consistency strategies and directory-based consistency strategies.

[0003] The bus snooping-based consistency strategy, also known as bus snooping, works as follows: when a CPU core modifies a value in its cache, it can broadcast this event to all other cores via the bus; each CPU core can listen to the data broadcast on the bus and check if there is a copy of the same data in its local cache; if there is a copy, it performs the corresponding operation to ensure cache consistency across multiple cores.

[0004] Directory-based consistency strategies can maintain a data structure called a directory, which stores information such as which caches different data copies are written to and their corresponding states. When the CPU performs a write operation, it no longer broadcasts to the caches of all cores, but instead uses this directory to track the state of data copies in all caches and only sends them to the specified data copies. This saves a lot of bus bandwidth compared to bus sniffing and is more scalable. Summary of the Invention

[0005] When recording shared information in a cache coherence directory, the directory's storage width increases linearly with the number of cores, leading to a corresponding increase in directory capacity and severely limiting multi-core scalability. To address these issues, at least one embodiment of this disclosure provides a method for recording a cache coherence directory, a method for maintaining cache coherence, a method for transmitting cache coherence requests, a cache coherence directory recording device, a cache coherence node, a processor chip, an electronic device, and a storage medium. Each entry in the cache coherence directory only needs to record shared information in each dimension of the processing unit array to indicate the position of the corresponding data block's shared processing unit in each dimension. This significantly reduces the number of bits of data that need to be recorded in each directory entry, thereby reducing directory capacity and mitigating the limitations on multi-core scalability.

[0006] At least one embodiment of this disclosure provides a method for recording a cache consistency directory, comprising: in response to a first processing unit in a processing unit array caching a first data block, obtaining a first position coordinate of the first processing unit in the processing unit array, wherein the first position coordinate includes multiple values ​​corresponding to multiple dimensions of the processing unit array; updating a first directory entry in the cache consistency directory corresponding to the first data block according to the first position coordinate, wherein the first directory entry includes multiple arrays corresponding to the multiple dimensions, wherein in the first directory entry, the array corresponding to each dimension is used to mark the dimension coordinate of the processing unit caching the first data block in the dimension.

[0007] At least one embodiment of this disclosure provides a method for maintaining cache consistency, comprising: responding to an access operation of a first processing unit in a processing unit array to a first data block, searching for a first directory entry corresponding to the first data block from a cache consistency directory, wherein the first directory entry includes a plurality of arrays corresponding to a plurality of dimensions of the processing unit array, wherein in the first directory entry, the array corresponding to each dimension is used to mark the dimension coordinates of the processing unit that caches the first data block in the dimension; determining the target dimension coordinates of the first data block in each dimension based on the plurality of arrays in the first directory entry; and sending a consistency request based on the target dimension coordinates in the plurality of dimensions.

[0008] At least one embodiment of this disclosure provides a method for transmitting a cache consistency request, comprising: a cache consistency node determining, based on a first directory entry in a cache consistency directory, the target dimension coordinates of a first data block cached on each dimension of a processing unit array, wherein the first directory entry includes multiple arrays corresponding to multiple dimensions of the processing unit array, and in the first directory entry, the array corresponding to each dimension is used to mark the dimension coordinates of the processing unit that caches the first data block on the dimension; the cache consistency node sending a consistency fusion request to an interconnection network based on the target dimension coordinates on the multiple dimensions of the processing unit array, wherein the consistency fusion request includes marking information of the target dimension coordinates of each of the multiple dimensions; the interconnection network decomposing the consistency fusion request into multiple consistency requests based on the marking information of the target dimension coordinates of each of the multiple dimensions, and sending the multiple consistency requests to the corresponding multiple processing units respectively.

[0009] At least one embodiment of this disclosure also provides a recording device for a cache consistency directory, including an acquisition unit and an update unit. The acquisition unit is configured to acquire a first position coordinate of the first processing unit in the processing unit array in response to a first processing unit caching a first data block in the processing unit array, wherein the first position coordinate includes multiple values ​​corresponding to multiple dimensions of the processing unit array. The update unit is configured to update a first directory entry in the cache consistency directory corresponding to the first data block according to the first position coordinate, wherein the first directory entry includes multiple arrays corresponding to the multiple dimensions, and in the first directory entry, the array corresponding to each dimension is used to mark the dimension coordinate of the processing unit caching the first data block in the dimension.

[0010] At least one embodiment of this disclosure also provides a cache consistency node, including a lookup unit, a determination unit, and a sending unit. The lookup unit is configured to, in response to an access operation of a first processing unit in a processing unit array to a first data block, look up a first directory entry corresponding to the first data block from a cache consistency directory. The first directory entry includes multiple arrays corresponding to multiple dimensions of the processing unit array. In the first directory entry, the array corresponding to each dimension is used to mark the dimension coordinates of the processing unit that caches the first data block in the dimension. The determination unit is configured to, based on the multiple arrays in the first directory entry, determine the target dimension coordinates of the first data block cached in each dimension. The sending unit is configured to, based on the target dimension coordinates in the multiple dimensions, send a consistency request.

[0011] At least one embodiment of this disclosure also provides a processor chip, including a processing unit array and a plurality of cache coherence nodes. The processing unit array includes a plurality of processing units arranged in an array. Each cache coherence node is configured to store a directory. Each cache coherence node is further configured to: in response to an access operation of a first processing unit in the processing unit array to a first data block, search for a first directory entry corresponding to the first data block from the stored cache coherence directory. The first directory entry includes a plurality of arrays corresponding to a plurality of dimensions of the processing unit array. In the first directory entry, the array corresponding to each dimension is used to mark the dimension coordinates of the processing unit that caches the first data block in the dimension. Based on the plurality of arrays in the first directory entry, determine the target dimension coordinates of the first data block cached in each dimension. Based on the target dimension coordinates in the plurality of dimensions, send a coherence request.

[0012] At least one embodiment of this disclosure also provides an electronic device, including: a processor; a memory including one or more computer program modules; wherein the one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules include instructions for implementing at least one of a method for recording a cache consistency catalog, a method for maintaining cache consistency, and a method for transmitting cache consistency requests as described in any embodiment of this disclosure.

[0013] At least one embodiment of this disclosure also provides a storage medium for storing non-transitory computer-readable instructions, which, when executed by a computer, can implement at least one of the methods for recording a cache consistency catalog, maintaining cache consistency, and transmitting cache consistency requests as described in any embodiment of this disclosure. Attached Figure Description

[0014] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same reference numerals denote the same elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0015] Figure 1 A flowchart illustrating a method for recording a cache consistency catalog according to some embodiments of this disclosure;

[0016] Figure 2 A schematic diagram of a distributed directory provided for some embodiments of this disclosure;

[0017] Figure 3 A schematic diagram of a catalog provided for some embodiments of this disclosure;

[0018] Figure 4 This is a schematic diagram of a processing unit array provided for some embodiments of this disclosure;

[0019] Figure 5 A schematic diagram illustrating the connection between the processing unit and the cache consistency node provided in some embodiments of this disclosure;

[0020] Figure 6 A flowchart illustrating a method for maintaining cache consistency provided in some embodiments of this disclosure;

[0021] Figure 7 This is a schematic diagram illustrating a request transmission provided for some embodiments of this disclosure;

[0022] Figure 8 A schematic diagram illustrating the processor unit distribution of a directory tagging shared cache block provided for some embodiments of this disclosure;

[0023] Figure 9 A schematic block diagram of a recording device for a cache consistency catalog provided for some embodiments of this disclosure;

[0024] Figure 10 A schematic block diagram of a cache consistency node provided for some embodiments of this disclosure;

[0025] Figure 11 A schematic block diagram of an electronic device provided for some embodiments of this disclosure;

[0026] Figure 12 A schematic block diagram of another electronic device provided for some embodiments of this disclosure; and

[0027] Figure 13 This is a schematic diagram of a storage medium provided for some embodiments of this disclosure. Detailed Implementation

[0028] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0029] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0030] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0031] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0032] It should be noted that the terms "one" and "more" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless explicitly stated otherwise in the context, they should be understood as "one or more". "More" should be understood as two or more.

[0033] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0034] Hardware cache coherence is a design consideration in large-scale, high-performance multi-core processors. To reduce on-chip network bandwidth waste and power consumption caused by broadcasting listener requests, a distributed directory approach can be used to reduce invalid listener requests. However, a distributed directory needs to track the consistency status of each cache block within a limited capacity. The directory vector table records which upstream cores cache each data block (e.g., cache line). As the number of cores scales to hundreds, the directory vector table corresponding to each data block struggles to expand accordingly. For example, each entry in the directory can record information about the sharer of the corresponding data block, and each entry can have multiple bits corresponding to all cores to indicate whether each core caches the data block corresponding to the entry. With this recording method, the directory's storage width increases linearly with the number of cores, thus increasing the capacity of all distributed directories. This directory structure severely limits the scalability of multi-core processors.

[0035] At least one embodiment of this disclosure provides a method for recording a cache consistency directory, a method for maintaining cache consistency, a method for transmitting cache consistency requests, a recording device for a cache consistency directory, a cache consistency node, a processor chip, an electronic device, and a storage medium. This allows each entry in the directory to record only the shared information of the processing unit array in each dimension to indicate the position of the shared processing unit of the corresponding data block in each dimension. This can significantly reduce the number of bits of data that need to be recorded in each directory entry, thereby reducing the directory capacity and reducing the limitation on the scalability of multi-core processors.

[0036] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0037] At least one embodiment of this disclosure provides a method for recording a cache consistency catalog, comprising: in response to a first processing unit in a processing unit array caching a first data block, obtaining a first position coordinate of the first processing unit in the processing unit array, wherein the first position coordinate includes multiple values ​​corresponding to multiple dimensions of the processing unit array; and updating a first catalog entry in the cache consistency catalog corresponding to the first data block according to the first position coordinate, wherein the first catalog entry includes multiple arrays corresponding to multiple dimensions, and in the first catalog entry, the array corresponding to each dimension is used to mark the dimension coordinate of the processing unit caching the first data block in the dimension.

[0038] At least one embodiment of this disclosure also provides a method for maintaining cache consistency, comprising: responding to an access operation of a first processing unit in a processing unit array to a first data block, searching for a first directory entry corresponding to the first data block from a cache consistency directory, wherein the first directory entry includes multiple arrays corresponding to multiple dimensions of the processing unit array, and in the first directory entry, the array corresponding to each dimension is used to mark the dimension coordinates of the processing unit that caches the first data block in the dimension; determining the target dimension coordinates of the first data block in each dimension based on the multiple arrays in the first directory entry; and sending a consistency request based on the target dimension coordinates in the multiple dimensions.

[0039] Figure 1 This is a flowchart illustrating a method for recording a cache consistency directory, provided for some embodiments of this disclosure.

[0040] like Figure 1 As shown, in at least one embodiment, the recording method includes the following operations.

[0041] Step S110: In response to the first processing unit in the processing unit array caching the first data block, obtain the first position coordinates of the first processing unit in the processing unit array, each first position coordinate including multiple values ​​corresponding to multiple dimensions of the processing unit array.

[0042] Step S120: Update the first directory entry in the cache consistency directory corresponding to the first data block according to the first location coordinates. The first directory entry includes multiple arrays corresponding to multiple dimensions. In the first directory entry, the array corresponding to each dimension is used to mark the dimension coordinates of the processing unit that caches the first data block.

[0043] For example, the first directory entry is an entry in a directory used to maintain cache consistency.

[0044] For example, the recording method could be a recording method for a directory used to maintain cache consistency, and the directory used to maintain cache consistency could be a distributed directory.

[0045] Figure 2 This is a schematic diagram of a distributed directory provided for some embodiments of this disclosure.

[0046] like Figure 2 As shown, the processor can use distributed cache coherence nodes. Multiple cache coherence nodes 200 can be used to manage multiple storage spaces respectively. Each cache coherence node 200 stores a directory 210. The directories 210 in multiple cache coherence nodes 200 can form a distributed directory. Different directories 201 can be used to record shared information corresponding to different storage spaces.

[0047] Figure 3 This is a schematic diagram of a catalog provided for some embodiments of this disclosure.

[0048] like Figure 3 As shown, directory 310 includes multiple entries 311. Each entry records shared information corresponding to a data block in the corresponding storage space. The data block can be, for example, a cache line. Each entry can record shared information about a cache line, such as the cache line's identifier (TAG), status information, and whether all coherent processor cores cache the cache line. Based on the MESI protocol, the status information can include four states: M, E, S, and I. M indicates modified, meaning the cache line's value differs from the main memory value; E indicates exclusive, meaning the cache line exists only in the current cache and is inconsistent with the main memory data; S indicates shared, meaning the cache line also exists in other caches and is clean; and I indicates invalid, meaning the cache line is invalid.

[0049] For example, a processing unit can be a processor core, also known as a consistent processor core. Multiple processor cores can be arranged in an array. The array can be a one-dimensional array, a two-dimensional array, a three-dimensional array, or a more multi-dimensional array. It can also be a multi-dimensional structure formed by dividing and combining local regions.

[0050] Figure 4 This is a schematic diagram of a processing unit array provided for some embodiments of this disclosure.

[0051] like Figure 4 As shown, (a) shows a three-dimensional array in a 3D stacked form, including three dimensions: X, Y, and Z. (b) shows a two-dimensional array, in the form of multiple dies encapsulated in two dimensions.

[0052] A processor may include multiple dies, and each die may include multiple cores. These dies are then expanded in two dimensions to form a two-dimensional core array. In some of the following embodiments, a two-dimensional array is used as an example for illustration.

[0053] Figure 5 This is a schematic diagram showing the connection between the processing unit and the cache consistency node provided in some embodiments of this disclosure.

[0054] like Figure 5 As shown, multiple processing units 510 can be interconnected with multiple cache consistency nodes 520 through an interconnection network. The interconnection network may include multiple routing nodes, and data communication is achieved through the forwarding operations of the routing nodes. Each processing unit can access data cached by other processing units through a cache consistency node. For example, after a processing unit modifies cached data, in order to maintain cache consistency, the processing unit can broadcast the modification information to other processing units that have cached the data through a cache consistency node. As another example, because the processing unit is far from the main memory, the speed at which the processing unit retrieves data from the main memory is slow. To improve processing efficiency, the processing unit can retrieve the data from other processing units that have already cached the data through a cache consistency node. When a processing unit accesses the cache of another processing unit through a cache consistency node, the processing unit can first send the request to the cache consistency node that manages the storage space where the data block is located. The cache consistency node can find other processing units that have cached the data block by querying the directory and routes the request to the processing unit that has cached the data block.

[0055] For example, the recording method of this disclosure embodiment can be executed by a cache consistency node.

[0056] For example, in step S110, the first data block can be any data block, such as any cache line.

[0057] For example, the first processing unit can be any processing unit in the processing unit array, such as processing unit P(1,1) or processing unit P(2,2). If the cache consistency node N1 is used to manage the storage space where the first data block a1 is located, when it detects that processing units P(1,1) and P(2,2) are caching the first data block a1, the cache consistency node N1 can obtain the position coordinates of processing units P(1,1) and P(2,2) in the processing unit array. Taking a two-dimensional array as an example, the position coordinates of the processing unit include the coordinate values ​​of two dimensions (X and Y). For example, the coordinate value of the X dimension of processing unit P(1,1) is 1, and the coordinate value of the Y dimension is 1.

[0058] For example, in step S120, the cache consistency node N1 can update the directory in the cache consistency node N1 according to the coordinates of processing units P(1,1) and P(2,2). Specifically, it can update the first directory entry corresponding to the first data block a1 in the directory. Taking a two-dimensional array as an example, the first directory entry includes an X array corresponding to the X dimension and a Y array corresponding to the Y dimension. The X array is used to characterize whether the processing unit at each coordinate in the X dimension caches the first data block a1. The X dimension includes, for example, three coordinate dimensions X = 1 to 3. Then, the X array is used to mark the dimension coordinates of the processing unit that caches the first data block a1 in the X dimension. For example, if the processing unit P(3,3) caches the first data block a1, the dimension coordinate of the processing unit P(3,3) in the X dimension is X = 3. Then, in the X array, the dimension coordinate X = 3 can be marked to distinguish it from the X dimension coordinates that do not cache the first data block a1. After processing units P(1,1) and P(2,2) cache the first data block a1, the X array can be updated to mark the coordinates of the two dimensions X=1 and X=2. Therefore, the X array can be used to indicate whether the processing units corresponding to each coordinate in the X dimension have cached the first data block a1. If each coordinate in the X dimension represents a row of the processing unit array, then X=1 to X=3 represent the first to third rows of the processing unit array, and the X array can be used to characterize whether the processing units in each row of the first to third rows have cached the first data block a1.

[0059] Similarly, the Y array is used to mark the Y-dimensional coordinates of the processing unit that caches the first data block. For example, if processing unit P(3,3) caches the first data block a1, and the Y-dimensional coordinate of processing unit P(3,3) is Y=3, then the Y-dimensional coordinate Y=3 can be marked in the Y array to distinguish it from the Y-dimensional coordinates of those that do not cache the first data block a1. After processing units P(1,1) and P(2,2) cache the first data block a1, the Y array can be updated to mark the Y=1 and Y=2 dimensions. Therefore, the Y array can be used to indicate whether the first data block a1 is cached in a group of processing units corresponding to each dimension coordinate of the Y dimension (such as the six dimensions Y=1 to 6). If each dimension coordinate of the Y dimension corresponds to a column of the processing unit array, then the Y array can be used to characterize whether the first data block a1 is cached in each column of processing units.

[0060] Based on the above approach, only the shared information of each dimension needs to be recorded in the catalog entries, instead of the shared information of each processing unit, which can significantly reduce the number of bits of data that each catalog entry needs to record.

[0061] For example, the array corresponding to each dimension includes multiple elements that correspond one-to-one with multiple dimensional coordinates on the corresponding dimension. Among them, the multiple coordinates include the first dimension coordinates, and the multiple elements include the first element corresponding to the first dimension coordinates. When the value of the first element is the first value, it means that the first data block is cached in the group of processing units corresponding to the first dimension coordinates. When the value of the first element is the second value, it means that the first data block is not cached in any of the group of processing units corresponding to the first dimension coordinates.

[0062] For example, taking a two-dimensional array as an example, the X dimension includes three coordinate dimensions X=1 to 3, and the Y dimension includes six coordinate dimensions Y=1 to 6. Correspondingly, the X array can include three elements [x1,x2,x3] corresponding to X=1, X=2, and X=3 respectively, and the Y array can include six elements [y1,y2,y3,y4,y5,y6] corresponding to Y=1, Y=2, ..., Y=6 respectively.

[0063] For example, the first value can be 1, meaning that the value 1 indicates that the first data block a1 is stored in the corresponding group of processing units; the second value can be 0, meaning that the value 0 indicates that the first data block a1 is not stored in the corresponding group of processing units. See also Figure 5 If processing units P(1,1) and P(2,2) store the first data block a1, while the other processing units do not, then the X array can be 110, indicating that the first data block a1 is stored in the two rows of processing units corresponding to the coordinates X=1 and X=2 in the X dimension. Correspondingly, the Y array can be 1100000, indicating that the first data block a1 is stored in the two columns of processing units corresponding to the coordinates Y=1 and Y=2 in the Y dimension. The above is just an example; the first and second values ​​can be set according to actual needs.

[0064] For example, multiple arrays in the first directory entry can be used to determine whether the processing unit at each coordinate combination position obtained from multiple dimension coordinate combinations has cached the first data block. The processing unit at each coordinate combination position obtained from the marked dimension coordinate combinations of multiple dimensions can be determined to have cached the first data block, while the processing unit at the other coordinate combination positions can be considered not to have cached the first data block. For example, the coordinates X=1 and X=2 in the X dimension are marked as having cached the first data block, while other X dimension coordinates are not marked; the coordinate Y=1 in the Y dimension is marked as having cached the first data block, while other Y dimension coordinates are not marked. Then, the position (1,1) obtained by combining X=1 and Y=1, and the position (2,1) obtained by combining X=2 and Y=1, can be determined to have cached the first data block.

[0065] For example, in some embodiments, the method for recording the cache consistency directory may further include: in response to a second processing unit in the processing unit array deleting a cached first data block, obtaining the second position coordinates corresponding to the second processing unit respectively; and updating the first directory entry according to the second position coordinates.

[0066] For example, the second processing unit can be any processing unit in the processing unit array that caches the first data block, such as processing unit P(3,3). When it is detected that processing unit P(3,3) performs the operation of deleting the cached first data block, the first directory entry can be updated according to the position coordinates of processing unit P(3,3). For example, after processing unit P(3,3) deletes the first data block, none of the processing units corresponding to the X=3 dimension coordinate have cached the first data block, so the mark for the X=3 dimension coordinate can be deleted from the X array, and the same applies to the Y dimension.

[0067] According to the cache consistency directory recording method of this disclosure, each entry in the directory only needs to record the shared information of each dimension of the processing unit array to indicate the position of the shared processing unit of the corresponding data block in each dimension. This can significantly reduce the number of bits of data that need to be recorded in each directory entry, thereby reducing the directory capacity and reducing the limitation on the scalability of multi-core systems. The cache consistency directory recording method of this disclosure is a novel directory implementation method suitable for large-scale multi-core systems. It combines routing nodes to complete the merging and distributing of listening requests, reducing listening bandwidth consumption, and uses dimension bitmaps to mark shared information to effectively reduce the directory capacity. For example, when the number of cores increases to 128 and the L2 cache is 1MB, the tag size and directory shared information overhead before the improvement are: (54+128)*16*4096=1.4MB, where 54 is the tag size and 128 is the tag size, which uses 128 bits to mark the shared information of 128 cores respectively. The improved tag size overhead is (54+8+1+8+1)*16*4096=0.56MB, and the improved directory size is reduced by more than half compared to the original.

[0068] At least one embodiment of this disclosure also provides a method for maintaining cache consistency. Figure 6 This is a flowchart illustrating a method for maintaining cache consistency provided in some embodiments of this disclosure.

[0069] like Figure 6 As shown, the method for maintaining cache consistency includes the following operations.

[0070] Step S610: In response to the access operation of the first processing unit in the processing unit array to the first data block, search for the first directory entry corresponding to the first data block in the cache consistency directory. The first directory entry includes multiple arrays corresponding to multiple dimensions of the processing unit array. In the first directory entry, the array corresponding to each dimension is used to mark the dimension coordinates of the processing unit that caches the first data block in the dimension.

[0071] Step S620: Determine the target dimension coordinates where the first data block is cached in each dimension based on the multiple arrays in the first directory entry.

[0072] Step S630: Send a consistency request based on the target dimension coordinates on multiple dimensions.

[0073] For example, the access operation of the first processing unit to the first data block may include modification operation or read operation of the first data block. Taking the modification operation as an example, after the first processing unit modifies the local first data block, it needs to send the modification information to other sharers (other processing units that cache the first data block) so that the other sharers can invalidate the cached first data block or update the cached first data block.

[0074] For example, after the first processing unit modifies the first data block a1 in the local cache, it can notify the cache consistency node that manages the shared information of the first data block through the interconnection network. After receiving the notification, the cache consistency node searches for the first directory entry corresponding to the first data block a1 in the local directory to find other processing unit nodes that have cached the first data block a1.

[0075] For example, a first directory entry includes multiple arrays corresponding to multiple dimensions of the processing unit array. In the first directory entry, each dimension's array is used to indicate whether a group of processing units corresponding to each dimension's coordinates has cached the first data block. For example, each dimension's array includes multiple elements that correspond one-to-one with multiple dimension coordinates, where the multiple dimension coordinates include the first dimension coordinate, and the multiple elements include the first element corresponding to the first dimension coordinate. When the value of the first element is a first value (e.g., value 1), it indicates that the group of processing units corresponding to the first dimension coordinate has cached the first data block; when the value of the first element is a second value (e.g., value 0), it indicates that none of the processing units corresponding to the first dimension coordinate have cached the first data block.

[0076] For example, with Figure 5Taking the illustrated two-dimensional array as an example, the first processing unit is, for example, processing unit P(2,6), and the cache consistency node managing the shared information of the first data block is, for example, cache consistency node N1. The X array in the first directory entry represents, for example, two groups of processing units corresponding to the coordinates X=1 and X=2 in the X dimension that cache the first data block a1. The Y array in the first directory entry represents, for example, two groups of processing units corresponding to the coordinates Y=1 and Y=2 in the Y dimension that cache the first data block a1. In step S610, in response to the access operation of processing unit P(2,6) on the first data block a1, cache consistency node N1 finds the first directory entry corresponding to the first data block a1. In step S620, by checking the first directory entry, the target dimension coordinates in the X dimension are determined to be X=1 and X=2, and the target dimension coordinates in the Y dimension are Y=1 and Y=2. In step S630, a consistency request (also known as a listening request) is sent to the corresponding processing unit based on the target dimension coordinates in the X and Y dimensions, so that these processing units can update or invalidate the first data block in the cache based on the consistency request, thereby achieving data consistency across multiple caches.

[0077] For example, the catalog may include multiple entries corresponding to multiple data blocks. Each entry includes multiple arrays corresponding to multiple dimensions. For each entry, each array can be used to indicate whether a set of processing units corresponding to the coordinates of each dimension have cached the corresponding data block.

[0078] According to the method for maintaining cache consistency in the embodiments of this disclosure, each entry in the directory only needs to record the shared information of each dimension of the processing unit array to indicate the position of the shared processing unit of the corresponding data block in each dimension. This can significantly reduce the number of bits of data that need to be recorded in each directory entry, thereby reducing the directory capacity and reducing the limitation on the scalability of multi-core processors.

[0079] For example, sending a consistency request based on target dimension coordinates in multiple dimensions may include: determining at least one coordinate combination position obtained by combining target dimension coordinates in multiple dimensions; and sending a consistency request to at least one processing unit located at the at least one coordinate combination position.

[0080] For example, the coordinate combination position can also be called the intersection position. The processing unit at the intersection position of the target dimension coordinates can be used as the target processing unit. See [link to relevant documentation]. Figure 5If the target dimension coordinates in the X dimension are X=1 and X=2, and the target dimension coordinates in the Y dimension are Y=1 and Y=2, then the intersection positions include the intersection position of the first row and the first column (1,1), the intersection position of the first row and the second column (1,2), the intersection position of the second row and the first column (2,1), and the intersection position of the second row and the second column (2,2). Therefore, a consistency request can be sent to the processing units P(1,1), P(1,2), P(2,1) and P(2,2).

[0081] For example, in the above embodiments, the directory uses a dimensional bitmap to record the processing units of shared data, which has a certain degree of ambiguity and may locate processing units without sharing relationships, thereby increasing the number of located processing units. For example, if P(1,1) and P(2,2) cache the first data block, the directory will record that the first data block is cached at the coordinates X=1 and X=2 in the X dimension, and at the coordinates Y=1 and Y=2 in the Y dimension. According to the records in the directory, four processing units, P(1,1), P(1,2), P(2,1), and P(2,2), will be located, introducing the irrelevant processing units P(1,2) and P(2,1). In some embodiments, when the cache consistency node sends a consistency request, one request can be sent for each target processing unit. However, since the above ambiguous directory may locate a large number of target processing units, more requests may need to be sent, consuming more bandwidth resources. To reduce the consumption of bandwidth resources, the following embodiments provide a method for sending and transmitting requests.

[0082] For example, sending a consistency request to at least one processing unit located at the at least one coordinate combination location may include: when there are multiple coordinate combination locations, generating a consistency fusion request based on the multiple coordinate combination locations, and sending the consistency fusion request to the interconnection network; wherein the consistency fusion request includes labeling information of the target dimension coordinates of each of the multiple dimensions, and the consistency fusion request is decomposed into multiple consistency requests in the interconnection network according to the labeling information of the target dimension coordinates of each of the multiple dimensions.

[0083] For example, if multiple target processing units P(1,1), P(1,2), P(2,1), and P(2,2) are identified based on the catalog, a consensus fusion request (a single request) can be generated and sent to these four processing units. The interconnect network (e.g., network-on-chip (NoC)) can decompose the single consensus request into four consensus requests during transmission and send them to the four processing units respectively. Based on this approach, multiple requests are merged into a single request, and the single request can be transmitted at least a distance on the interconnect network before being decomposed into multiple requests. Only a single request needs to be transmitted in the initial transmission phase, reducing bandwidth consumption.

[0084] For example, a consistency fusion request is decomposed into multiple consistency requests in the following way: the consistency fusion request is transmitted along the first dimension of multiple dimensions; in response to the consistency fusion request being transmitted to the routing node corresponding to the target dimension coordinates in the first dimension, a first request and a second request are obtained based on the consistency fusion request decomposition, wherein the first request includes the labeling information of the target dimension coordinates of each of the multiple dimensions, and the second request includes the labeling information of the target dimension coordinates of the other dimensions in the multiple dimensions besides the first dimension; the first request is continued to be transmitted along the first dimension, and the second request is transmitted along the second dimension of multiple dimensions.

[0085] For example, if the array also includes a third dimension and there is a processing unit in the third dimension that caches the first data block, then it can continue to decompose based on the first request or the second request to obtain the request transmitted in the third dimension, or it can decompose based on the consistent fusion request to obtain the request transmitted in the third dimension.

[0086] For example, the first, second, and third dimensions can be set according to actual needs, meaning the priority of transmission dimensions can be set based on actual requirements. For a two-dimensional array structure, an XY transmission method can be used, that is, transmission is first along the X direction, and then the decomposed requests are transmitted along the Y direction, or a YX transmission method can also be used. For a three-dimensional array structure, routing rules such as XYZ or ZXY can be used. For example, if the target processing units are concentrated in a certain dimension, the fusion request can be routed to that dimension first, and then the fusion request can be decomposed, which can reduce the transmission paths of multiple decomposed requests, thereby reducing the overall bandwidth of consistency requests. For example, if the target processing units are concentrated on a plane in the Z direction, priority can be given to Z-direction routing, followed by XY or YX, which can reduce the pressure on the multiplexing channel.

[0087] For example, the fusion request may include the marking information of the target dimension coordinates of each of the three dimensions. The marking information of the target dimension coordinates in each dimension can indicate which coordinates in each dimension have the first data block cached.

[0088] Figure 7 This is a schematic diagram illustrating a request transmission provided for some embodiments of this disclosure.

[0089] like Figure 7 As shown, taking a three-dimensional array as an example, routing can be prioritized in the X direction, then the Y direction, and finally the Z direction. The multi-monitor fusion request in the diagram is the consistency fusion request described above. For example, Figure 5 The structure shown is a distribution structure in a vertical plane (e.g., Z=1) along the Z direction. In the fusion request, the marker information in the Z dimension is, for example, 11; the marker information in the X dimension is, for example, 110; and the marker information in the Y dimension is, for example, 110000. See also... Figure 5 and Figure 7 If the transmission origin of the fusion request is in the plane Z=1 (i.e. Figure 5 If the routing node corresponding to N1 in the plane shown is to first transmit the fusion request along the X direction, when it reaches the routing node corresponding to processing unit P(2,2), this routing node can decompose the fusion request into a first request and a second request. The first request continues to be transmitted along the X direction, and the second request is transmitted along the Y direction. The second request may not contain coordinate marking information in the X dimension. The original fusion request can be transmitted to processing unit P(2,2). When the first request transmitted in the X direction reaches the routing node corresponding to processing unit P(2,1), this routing node can decompose the first request into a third request and transmit the third request along the Y direction. The original first request can be transmitted to processing unit P(2,1). Since there are also target processing units in the Z=2 plane, the first request transmitted in the Y direction can be decomposed into a request that continues to be transmitted along the Y direction and a request that is transmitted along the Z direction at the routing node corresponding to processing unit P(2,2). This process continues until the request is transmitted to all target processing units.

[0090] The multi-listening fusion and decomposition broadcast method for dimension-marked data provided in this disclosure reduces listening bandwidth consumption. When a single address data request detects shared data at multiple coordinate locations in the detection directory, the consistency maintenance node only needs to send a single listening request, i.e., a multi-listening fusion request, which carries dimension-marked shared information (i.e., marking information). The routing node decomposes the listening request by parsing the dimension marks. When encountering dimension switching or multi-directional distribution, the routing node copies the multi-listening fusion request and modifies the dimension-shared marking information. The decomposed requests only need to retain their respective listening ranges. A single multi-listening fusion request can be decomposed into a single listening request or a multi-listening fusion request with a smaller marking range. The decomposed marking ranges are mutually exclusive. This method has a higher relative bandwidth utilization when the listening area is more concentrated.

[0091] For example, if multiple listening areas are concentrated in one dimension, then other dimensions will have no listening requests, or only single-converged listening requests, thus greatly saving bandwidth in those other dimensions. Therefore, other dimensions can handle more other services, such as DDR read / write operations.

[0092] For example, multiple processing units in a processing unit array that cache the same data block are arranged in consecutive positions in the same dimension; or multiple processing units in a processing unit array that cache the same data block are arranged within a rectangular area.

[0093] Figure 8 This is a schematic diagram of the processor unit distribution for a directory tagging shared cache block provided for some embodiments of this disclosure.

[0094] like Figure 8 As shown, if multiple processing units of shared data are concentrated in the one-dimensional region shown in area B, then during the listening process, the cache consistency node will not locate irrelevant processing units. Similarly, if multiple processing units of shared data are concentrated in the rectangular regions shown in areas C or D, then during the listening process, the cache consistency node will also not locate irrelevant processing units, and the target location can be precisely locked. Alternatively, the shared scope can be reduced to a single processing unit. In these scenarios, using dimensional labeling methods results in precise recording and listening, with the shared scope concentrated in a single node, arbitrarily dispersed within a single dimension, or in a rectangular region. Reasonable mapping of resources can better leverage the advantages of dimensional labeling, for example, concentrating the processing units of shared data within a square in one dimension, or within a two-dimensional square plane, or within a three-dimensional cube.

[0095] At least one embodiment of this disclosure also provides a method for transmitting a cache consistency request. The method includes: a cache consistency node determining the target dimension coordinates of a first data block cached in each dimension of a processing unit array based on a first directory entry in a cache consistency directory, wherein the first directory entry includes multiple arrays corresponding to multiple dimensions of the processing unit array, and in the first directory entry, the array corresponding to each dimension is used to mark the dimension coordinates of the processing unit that caches the first data block in that dimension; the cache consistency node sending a consistency fusion request to an interconnection network based on the target dimension coordinates of each of the multiple dimensions of the processing unit array, wherein the consistency fusion request includes marking information of the target dimension coordinates of each of the multiple dimensions; and the interconnection network decomposing the consistency fusion request into multiple consistency requests based on the marking information of the target dimension coordinates of each of the multiple dimensions, and sending the multiple consistency requests to the corresponding multiple processing units respectively.

[0096] For details regarding this transmission method, please refer to the relevant descriptions in the above embodiments, which will not be repeated here.

[0097] According to at least one embodiment of this disclosure, a recording method for a cached consistent directory table is provided. In a directory with a multidimensional network structure, shared information is marked using a dimensional bitmap, which can reduce the overhead of directory resources.

[0098] According to at least one embodiment of this disclosure, multiple requests are merged or integrated into a single fused request, which is issued by the consistency node and then parsed, replicated, and redistributed by the routing node. The fused request reduces the size of the listening requests issued by the consistency node, effectively reducing listening bandwidth requirements and preventing large-scale listening requests from consuming on-chip network and cross-die bandwidth resources, thereby avoiding power waste and network congestion.

[0099] It should be noted that, in the embodiments of this disclosure, the execution order of each step in each method of the cache consistency recording method, the cache consistency maintenance method, and the cache consistency request transmission method is not limited. Although the execution process of each step has been described in a specific order above, this does not constitute a limitation on the embodiments of this disclosure. The steps can be executed sequentially or in parallel, depending on actual needs. The method may also include more or fewer steps.

[0100] At least one embodiment of this disclosure also provides a recording device for a cache-consistent directory, which can significantly reduce the number of bits of data that need to be recorded for each directory entry, thereby reducing the directory capacity and reducing the limitation on multi-core scalability.

[0101] Figure 9 This is a schematic block diagram of a recording device for a cache consistency directory provided for some embodiments of this disclosure. Figure 9 As shown, the recording device 900 includes an acquisition unit 910 and an update unit 920. For example, the recording device 900 can be applied to a server or terminal, or to any device or system that needs to record directory information; the embodiments disclosed herein do not limit this application.

[0102] The acquisition unit 910 is configured to acquire the first position coordinates of the first processing unit in the processing unit array in response to a first processing unit caching a first data block in the processing unit array. The first position coordinates include multiple values ​​corresponding to multiple dimensions of the processing unit array. For example, the acquisition unit 910 can perform actions such as... Figure 1 Step S110 of the recording method for the cache consistency catalog shown.

[0103] The update unit 920 is configured to update the first directory entry in the cache consistency directory corresponding to the first data block according to the first location coordinates. The first directory entry includes multiple arrays corresponding to the multiple dimensions. In the first directory entry, the array corresponding to each dimension is used to mark the dimension coordinates of the processing unit that caches the first data block in that dimension. For example, the update unit 920 can perform the following... Figure 1 Step S120 of the recording method for the cache consistency catalog shown.

[0104] For example, the acquisition unit 910 and the update unit 920 can be hardware, software, firmware, or any feasible combination thereof. For example, the acquisition unit 910 and the update unit 920 can be dedicated or general-purpose circuits, chips, or devices, or a combination of a processor and memory. The embodiments of this disclosure do not limit the specific implementation of the acquisition unit 910 and the update unit 920.

[0105] It should be noted that in the embodiments of this disclosure, each unit of the recording device 900 corresponds to each step of the aforementioned recording method of the cache consistency directory. For the specific functions of the recording device 900, please refer to the relevant description of the recording method above, which will not be repeated here. Figure 9 The components and structure of the recording device 900 shown are merely exemplary and not limiting. The recording device 900 may also include other components and structures as needed.

[0106] At least one embodiment of this disclosure also provides a cache consistency node. Figure 10 This is a schematic block diagram illustrating a cache consistency node provided for some embodiments of this disclosure. Figure 10 As shown, the cache consistency node 1000 includes a lookup unit 1010, a determination unit 1020, and a sending unit 1030.

[0107] The lookup unit 1010 is configured to, in response to an access operation of a first processing unit in the processing unit array to a first data block, search for a first directory entry corresponding to the first data block in a cache consistency directory. The first directory entry includes multiple arrays corresponding to multiple dimensions of the processing unit array. In the first directory entry, each dimension-corresponding array is used to mark the dimension coordinates of the processing unit that caches the first data block in that dimension. For example, the lookup unit 1010 can perform actions such as... Figure 6 Step S610 of the method for maintaining cache consistency is shown.

[0108] The determining unit 1020 is configured to determine the target dimension coordinates where the first data block is cached in each dimension based on multiple arrays in the first directory entry. For example, the determining unit 1020 can perform actions such as... Figure 6 Step S620 of the method for maintaining cache consistency is shown.

[0109] The sending unit 1030 is configured to send a consistency request based on the target dimension coordinates of each of the multiple dimensions. For example, the sending unit 1030 can perform the following: Figure 6 Step S630 of the method for maintaining cache consistency is shown.

[0110] For example, the search unit 1010, the determination unit 1020, and the sending unit 1030 can be hardware, software, firmware, or any feasible combination thereof. For example, the search unit 1010, the determination unit 1020, and the sending unit 1030 can be dedicated or general-purpose circuits, chips, or devices, or a combination of a processor and memory. The embodiments of this disclosure do not limit the specific implementation of the search unit 1010, the determination unit 1020, and the sending unit 1030.

[0111] It should be noted that in the embodiments of this disclosure, each unit of the cache consistency node 1000 corresponds to each step of the aforementioned method for maintaining cache consistency. For the specific functions of the cache consistency node 1000, please refer to the relevant description of the method for maintaining cache consistency above, which will not be repeated here. Figure 10 The components and structure of the cache consistency node 1000 shown are merely exemplary and not restrictive. The cache consistency node 1000 may also include other components and structures as needed.

[0112] At least one embodiment of this disclosure also provides a processor chip, which includes a processing unit array and a plurality of cache coherence nodes. The processing unit array includes a plurality of processing units arranged in an array. Each cache coherence node is configured to store a directory. Each cache coherence node is further configured to: in response to an access operation of a first processing unit in the processing unit array to a first data block, search for a first directory entry corresponding to the first data block from the stored cache coherence directory. The first directory entry includes a plurality of arrays corresponding to a plurality of dimensions of the processing unit array. In the first directory entry, the array corresponding to each dimension is used to mark the dimension coordinates of the processing unit that caches the first data block in the dimension. Based on the plurality of arrays in the first directory entry, determine the target dimension coordinates of the first data block cached in each dimension. Based on the target dimension coordinates of each of the plurality of dimensions, send a coherence request.

[0113] For example, the processor chip may further include an interconnect network; wherein each of the cache consistency nodes is further configured to send a consistency fusion request to the interconnect network, wherein the consistency fusion request includes labeling information of the target dimension coordinates of each of the multiple dimensions; the interconnect network is configured to decompose the consistency fusion request into multiple consistency requests according to the labeling information of the target dimension coordinates of each of the multiple dimensions, and send the multiple consistency requests to the corresponding multiple processing units respectively.

[0114] For example, the processor chip can be a CPU chip. For details about the processor chip, please refer to the relevant description in the above embodiments, which will not be repeated here.

[0115] Figure 11 This is a schematic block diagram of an electronic device provided for some embodiments of this disclosure. For example... Figure 11 As shown, the electronic device 1100 includes a processor 1110 and a memory 1120. The processor 1110 may include, for example, a processor core. The memory 1120 is used to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 1110 is used to execute the non-transitory computer-readable instructions, which, when executed by the processor 1110, can perform one or more steps of any of the methods described above: the cache coherence catalog recording method, the cache coherence maintenance method, and the cache coherence request transmission method. The memory 1120 and the processor 1110 can be interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0116] For example, processor 1110 may be a central processing unit (CPU), a digital signal processor (DSP), or other processing unit with data processing and / or program execution capabilities, such as a field-programmable gate array (FPGA); for example, the central processing unit (CPU) may be an x86 or ARM architecture. Processor 1110 may be a general-purpose processor or a special-purpose processor, and may control other components in electronic device 1100 to perform desired functions.

[0117] For example, memory 1120 may include any combination of one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disc read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and processor 1110 may run one or more computer program modules to implement various functions of electronic device 1100. Various application programs and various data, as well as various data used and / or generated by the application programs, may also be stored in the computer-readable storage medium.

[0118] It should be noted that, in the embodiments of this disclosure, the specific functions and technical effects of the electronic device 1100 can be referred to the description above of the recording method of the cache consistency catalog, the method of maintaining cache consistency, and the transmission method of cache consistency requests, and will not be repeated here.

[0119] Figure 12 This is a schematic block diagram of another electronic device provided in some embodiments of this disclosure. The electronic device 1200 is, for example, suitable for implementing at least one of the following methods: a method for recording a cache consistency catalog, a method for maintaining cache consistency, and a method for transmitting cache consistency requests, as provided in embodiments of this disclosure. The electronic device 1200 may be a user terminal, etc. It should be noted that... Figure 12 The illustrated electronic device 1200 is merely an example and does not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0120] like Figure 12 As shown, electronic device 1200 may include a processing device (e.g., a central processing unit, a graphics processor, etc.) 1210, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 1220 or a program loaded from storage device 1280 into random access memory (RAM) 1230. The processing device 1210 may include, for example, a processor core. Various programs and data required for the operation of electronic device 1200 are also stored in RAM 1230. The processing device 1210, ROM 1220, and RAM 1230 are interconnected via bus 1240. Input / output (I / O) interface 1250 is also connected to bus 1240.

[0121] Typically, the following devices can be connected to I / O interface 1250: input devices 1260 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 1270 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 1280 including, for example, magnetic tapes, hard disks, etc.; and communication devices 1290. Communication device 1290 allows electronic device 1200 to communicate wirelessly or wiredly with other electronic devices to exchange data. Although... Figure 12 An electronic device 1200 with various devices is shown, but it should be understood that it is not required to implement or have all of the devices shown, and the electronic device 1200 may alternatively implement or have more or fewer devices.

[0122] For example, according to embodiments of this disclosure, at least one of the methods for recording a cache consistency catalog, maintaining cache consistency, and transmitting a cache consistency request can be implemented as a computer software program. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program including program code for performing any of the methods described above: the method for recording a cache consistency catalog, the method for maintaining cache consistency, and the method for transmitting a cache consistency request. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 1290, or installed from a storage device 1280, or installed from a ROM 1220. When the computer program is executed by the processing device 1210, it can perform the functions defined in the methods for recording a cache consistency catalog, maintaining cache consistency, and transmitting a cache consistency request provided in embodiments of this disclosure.

[0123] At least one embodiment of this disclosure also provides a storage medium for storing non-transitory computer-readable instructions, which, when executed by a computer, can implement any of the methods described in any embodiment of this disclosure: the method for recording a cache-coherent directory, the method for maintaining cache coherence, and the method for transmitting cache coherence requests. Using this storage medium, the number of bits of data required to be recorded for each directory entry can be significantly reduced, thereby reducing the directory capacity and mitigating limitations on multi-core scalability.

[0124] Figure 13 This is a schematic diagram of a storage medium provided for some embodiments of this disclosure. For example... Figure 13 As shown, storage medium 1300 is used to store non-transitory computer-readable instructions 1310. For example, when the non-transitory computer-readable instructions 1310 are executed by a computer, one or more steps of any of the methods described above—the method of recording a cache consistency catalog, the method of maintaining cache consistency, and the method of transmitting a cache consistency request—can be performed.

[0125] For example, the storage medium 1300 can be used in the aforementioned electronic device 1100. For example, the storage medium 1300 can be... Figure 11 The memory 1120 in the illustrated electronic device 1100. For example, a description of the storage medium 1300 can be found here. Figure 11 The corresponding description of the memory 1120 in the illustrated electronic device 1100 will not be repeated here.

[0126] It should be noted that the storage medium (computer-readable medium) described above in this disclosure can be a computer-readable signal medium or a non-transitory computer-readable storage medium, or any combination of the two. A non-transitory computer-readable storage medium can be, for example,, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a non-transitory computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a non-transitory computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such transmitted data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The computer-readable signal medium can also be any computer-readable medium other than a non-transitory computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0127] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol, such as Hypertext Transfer Protocol (HTTP), and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (LANs), wide area networks (WANs), the Internet (e.g., the Internet), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks.

[0128] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0129] The aforementioned computer-readable medium carries one or more programs that, when executed by the electronic device, cause the electronic device to: acquire at least two Internet Protocol (IP) addresses; send a node evaluation request including the at least two IP addresses to a node evaluation device, wherein the node evaluation device selects an IP address from the at least two IP addresses and returns it; and receive the IP address returned by the node evaluation device; wherein the acquired IP address indicates an edge node in a content delivery network.

[0130] Alternatively, the aforementioned computer-readable medium carries one or more programs that, when executed by the electronic device, cause the electronic device to: receive a node evaluation request including at least two Internet Protocol (IP) addresses; select an IP address from the at least two IP addresses; and return the selected IP address; wherein the received IP address indicates an edge node in the content delivery network.

[0131] Computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof, including but not limited to object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, such as a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0132] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0133] The units described in the embodiments of this disclosure can be implemented in software or hardware. The names of the units are not, in some cases, intended to limit the specific unit.

[0134] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), System-on-Chip (SoCs), Complex Programmable Logic Devices (CPLDs), etc.

[0135] In this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0136] The above description is merely a partial embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0137] Furthermore, while the operations are described in a specific order, this should not be construed as requiring these operations to be performed in the specific order shown or in sequential order. Multitasking and parallel processing may be advantageous in certain environments. Similarly, while several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments.

[0138] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A method for recording a cache coherence directory, comprising: in response to a first processing unit in a processing unit array caching a first data block, obtaining a first location coordinate of the first processing unit in the processing unit array, wherein the first location coordinate comprises a plurality of values corresponding to a plurality of dimensions of the processing unit array respectively; updating, according to the first location coordinate, a first directory entry corresponding to the first data block in the cache coherence directory, wherein the first directory entry comprises a plurality of arrays corresponding to the plurality of dimensions respectively, and each array corresponding to a dimension in the first directory entry is used to mark a dimension coordinate of a processing unit caching the first data block on the dimension. 2.The method of claim 1, further comprising: in response to a second processing unit in the processing unit array deleting the cached first data block, obtaining a second location coordinate corresponding to the second processing unit respectively; updating the first directory entry according to the second location coordinate. 3.The method of claim 1 or 2, wherein the plurality of arrays in the first directory entry are used to determine whether a processing unit at a coordinate combination location obtained by combining dimension coordinates of the plurality of dimensions caches the first data block. 4.The method of claim 1 or 2, wherein the array corresponding to each dimension comprises a plurality of elements corresponding to a plurality of dimension coordinates on the dimension one by one, wherein the plurality of coordinates comprises a first dimension coordinate, and the plurality of elements comprises a first element corresponding to the first dimension coordinate; in a case where a value of the first element is a first value, it indicates that the first data block is cached in a group of processing units corresponding to the first dimension coordinate; in a case where the value of the first element is a second value, it indicates that none of the group of processing units corresponding to the first dimension coordinate caches the first data block. 5.A method for maintaining cache coherence, comprising: in response to a first processing unit in a processing unit array accessing a first data block, searching for a first directory entry corresponding to the first data block in a cache coherence directory, wherein the first directory entry comprises a plurality of arrays corresponding to a plurality of dimensions of the processing unit array respectively, and each array corresponding to a dimension in the first directory entry is used to mark a dimension coordinate of a processing unit caching the first data block on the dimension; determining, according to the plurality of arrays in the first directory entry, a target dimension coordinate on each dimension on which the first data block is cached; sending a coherence request according to the target dimension coordinates on the plurality of dimensions.

6. The method of maintaining cache coherency according to claim 5, wherein, sending a coherence request according to the target dimension coordinates on the plurality of dimensions, comprising: determining at least one coordinate combination location obtained by combining the target dimension coordinates on the plurality of dimensions; sending a coherence request to at least one processing unit located at the at least one coordinate combination location. 7.The method of claim 5, wherein The array corresponding to each dimension includes a plurality of elements corresponding to a plurality of dimension coordinates on the dimension, wherein the plurality of dimension coordinates include a first dimension coordinate, and the plurality of elements include a first element corresponding to the first dimension coordinate; In a case where a value of the first element is a first value, it is indicated that the first data block is cached in a group of processing units corresponding to the first dimension coordinate; In a case where the value of the first element is a second value, it is indicated that none of the processing units in the group of processing units corresponding to the first dimension coordinate caches the first data block.

8. The method of claim 5-7, wherein, The directory includes a plurality of entries corresponding to a plurality of data blocks, respectively, and each of the plurality of entries includes a plurality of arrays corresponding to a plurality of dimensions, respectively.

9. The method of maintaining cache coherency according to claim 6 or 7, wherein, The method further includes: sending a consistency request to at least one processing unit located at the at least one coordinate combination position, including: In a case where the number of the at least one coordinate combination position is a plurality, generating a consistency fusion request based on the plurality of coordinate combination positions, and sending the consistency fusion request to the interconnection network; The consistency fusion request includes marker information of target dimension coordinates of the plurality of dimensions, respectively, and the consistency fusion request is decomposed into a plurality of consistency requests in the interconnection network according to the marker information of the target dimension coordinates of the plurality of dimensions, respectively.

10. The method of maintaining cache coherency according to claim 9, wherein, The consistency fusion request is decomposed into a plurality of consistency requests by: transmitting the consistency fusion request along a first dimension of the plurality of dimensions, and in response to the consistency fusion request being transmitted to a routing node corresponding to a target dimension coordinate on the first dimension, decomposing the consistency fusion request to obtain a first request and a second request, wherein the first request includes the marker information of the target dimension coordinates of the plurality of dimensions, respectively, and the second request includes the marker information of the target dimension coordinates of the dimensions other than the first dimension of the plurality of dimensions; continuing to transmit the first request along the first dimension, and transmitting the second request along a second dimension of the plurality of dimensions.

11. The method of claim 5-7, wherein, The plurality of processing units caching the same data block in the processing unit array are arranged at consecutive positions in the same dimension; or The plurality of processing units caching the same data block in the processing unit array are arranged in a rectangular region.

12. A method of transmitting a cache consistency request, including: determining, by a cache consistency node, target dimension coordinates on each dimension of a processing unit array at which a first data block is cached according to a first directory entry in a cache consistency directory, wherein the first directory entry includes a plurality of arrays corresponding to a plurality of dimensions of the processing unit array, respectively, and in the first directory entry, an array corresponding to each dimension is used to mark a dimension coordinate on the dimension of a processing unit caching the first data block. The cache coherence node sends a coherence fusion request to the interconnection network according to target dimension coordinates on multiple dimensions of the processing unit array, wherein the coherence fusion request comprises tag information of the target dimension coordinates on the multiple dimensions respectively; The interconnection network decomposes the coherence fusion request into multiple coherence requests according to the tag information of the target dimension coordinates on the multiple dimensions respectively, and sends the multiple coherence requests to corresponding multiple processing units respectively.

13. A recording device of a cache coherence directory, comprising: an obtaining unit configured to obtain a first position coordinate of a first processing unit in the processing unit array in response to the first processing unit caching a first data block, wherein the first position coordinate comprises multiple values corresponding to multiple dimensions of the processing unit array respectively; an updating unit configured to update a first directory entry corresponding to the first data block in the cache coherence directory according to the first position coordinate, wherein the first directory entry comprises multiple arrays corresponding to the multiple dimensions respectively, and in the first directory entry, each array corresponding to a dimension is used to mark a dimension coordinate of a processing unit caching the first data block on the dimension.

14. A cache coherence node, comprising: a searching unit configured to search for a first directory entry corresponding to a first data block in a cache coherence directory in response to an access operation of the first data block by a first processing unit in a processing unit array, wherein the first directory entry comprises multiple arrays corresponding to multiple dimensions of the processing unit array respectively, and in the first directory entry, each array corresponding to a dimension is used to mark a dimension coordinate of a processing unit caching the first data block on the dimension; a determining unit configured to determine target dimension coordinates on each dimension of the processing unit caching the first data block according to the multiple arrays in the first directory entry; a sending unit configured to send a coherence request according to the target dimension coordinates on the multiple dimensions.

15. A processor chip, comprising: a processing unit array comprising multiple processing units arranged in an array; multiple cache coherence nodes, wherein each cache coherence node is configured to store a directory; wherein each cache coherence node is further configured to: search for a first directory entry corresponding to a first data block in a stored cache coherence directory in response to an access operation of the first data block by a first processing unit in a processing unit array, wherein the first directory entry comprises multiple arrays corresponding to multiple dimensions of the processing unit array respectively, and in the first directory entry, each array corresponding to a dimension is used to mark a dimension coordinate of a processing unit caching the first data block on the dimension; determine target dimension coordinates on each dimension of the processing unit caching the first data block according to the multiple arrays in the first directory entry; send a coherence request according to the target dimension coordinates on the multiple dimensions.

16. The processor chip of claim 15, further comprising an interconnection network. wherein, Each of the cache coherence nodes is further configured to send a coherence merge request to the interconnection network, wherein the coherence merge request comprises the tag information of the target dimension coordinates of the plurality of dimensions respectively. The interconnection network is configured to decompose the coherence merge request into a plurality of coherence requests according to the tag information of the target dimension coordinates of the plurality of dimensions respectively, and send the plurality of coherence requests to the corresponding plurality of processing units respectively. 17.An electronic device comprising: a processor; a memory including one or more computer program modules; wherein the one or more computer program modules are stored in the memory and configured to be executed by the processor, and the one or more computer program modules comprise instructions for implementing at least one of the record method of the cache coherence directory of any one of claims 1-4, the method of maintaining cache coherence of any one of claims 5-11, or the transmission method of the cache coherence request of claim 12. 18.A storage medium for storing non-transitory computer-readable instructions that, when executed by a computer, can implement at least one of the record method of the cache coherence directory of any one of claims 1-4, the method of maintaining cache coherence of any one of claims 5-11, or the transmission method of the cache coherence request of claim 12.

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