Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises a pixel circuit. The pixel circuit includes a driving transistor and a variable capacitor. The driving transistor is used for generating light-emitting driving current, and the variable capacitor is electrically connected with the control end of the driving transistor. Wherein when the display frequency of the display panel is greater than or equal to a preset value, the capacitance value of the variable capacitor is c1; when the display frequency of the display panel is smaller than a preset value, the capacitance value of the variable capacitor is c2, and c1 is smaller than c2. According to the display panel, the variable capacitor with the controllable capacitance value is arranged, so that the capacitance value corresponding to the control end is adjusted according to the display frequency of the display panel. For example, the capacitance value of the variable capacitor is adjusted to be small, so that the risk that data signals at the control end are not completely written due to the fact that the capacitance is too large is reduced. For example, the capacitance value of the variable capacitor is adjusted to be large, so that the influence of the leakage current on the potential stability of the control end is weakened, and the phenomenon of flicker of a display picture is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] In existing technologies, the gate potential of the driving transistor in a pixel circuit can affect the transistor's on / off state. However, the gate potential of the driving transistor is easily affected by leakage current and is difficult to achieve the expected value. To improve gate potential stability, a common approach is to connect the gate of the driving transistor to a voltage-stabilizing capacitor, thereby reducing the impact of leakage current on the gate potential.

[0003] It should be noted that while the aforementioned voltage-stabilizing capacitor enhances the stability of the gate potential of the driving transistor, it also reduces the rate of change of the gate potential of the driving transistor in certain stages (such as the data writing stage), affecting the working state of the pixel circuit. Summary of the Invention

[0004] This application provides a display panel and display device to solve the problem that the setting of the voltage regulator capacitor reduces the speed of gate potential change of the driving transistor.

[0005] In view of this, this application provides a display panel including pixel circuitry.

[0006] The pixel circuit includes a driving transistor and a variable capacitor. The driving transistor generates the light-emitting driving current, and the variable capacitor is electrically connected to the control terminal of the driving transistor.

[0007] When the display frequency of the display panel is greater than or equal to the preset value, the capacitance value of the variable capacitor is c1; when the display frequency of the display panel is less than the preset value, the capacitance value of the variable capacitor is c2, and c1 < c2.

[0008] Based on the same inventive concept, this application also provides a display device, including the above-mentioned display panel.

[0009] Compared with the prior art, the display module and display device provided by the present invention achieve at least the following beneficial effects: When the display panel has a high display frequency, it means that the corresponding refresh rate during the display process is high, and the number of image frames displayed per unit time is high. Therefore, the blanking phase duration between adjacent display stages is short. Considering that the data writing phase corresponding to the pixel circuit can occur during the aforementioned blanking phase, the limited blanking phase duration corresponding to a high display frequency determines that the data writing phase duration corresponding to the pixel circuit is also limited. In this case, if the capacitance value corresponding to the control terminal of the driving transistor is too large, the limited data writing phase duration can easily lead to insufficient data signal writing at the control terminal. Therefore, this embodiment sets a variable capacitor with a controllable capacitance value, and then adjusts the capacitance value at the control terminal according to the display frequency of the display panel. When the display frequency is greater than or equal to a preset value (at which point the display panel can be considered to be in high-frequency display mode), the capacitance value of the variable capacitor can be adjusted to a smaller value to reduce the risk of incomplete data signal writing at the control terminal due to excessive capacitance. In addition, when the display frequency of the display panel is less than the preset value (at which time the display panel can be regarded as being in low frequency display mode), the data writing stage can be relatively longer. In this case, the capacitance value of the variable capacitor can be adjusted to a larger value to reduce the impact of leakage current on the potential stability at the control terminal, thereby improving the phenomenon of screen flickering. Attached Figure Description

[0010] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0011] Figure 1 This is an equivalent circuit diagram of a pixel circuit in a related technology; Figure 2 An equivalent circuit diagram of a pixel circuit in a display panel provided in this application; Figure 3 An equivalent circuit diagram of a partial structure of a pixel circuit provided in this application; Figure 4 A schematic diagram showing how the capacitance of the regulating transistor provided in this application changes with the regulating voltage; Figure 5 A schematic diagram showing the relationship between the adjustment voltage transmitted by the adjustment signal line and the display frequency; Figure 6 A schematic diagram showing the relationship between the adjustment voltage transmitted by the adjustment signal line and the display frequency; Figure 7 An equivalent circuit diagram of a partial structure of a pixel circuit provided in this application; Figure 8 An equivalent circuit diagram of a partial structure of a pixel circuit provided in this application; Figure 9 This is a schematic diagram of a display device provided in this application. Detailed Implementation

[0012] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0013] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0014] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0015] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0016] Figure 1 This is an equivalent circuit diagram of a pixel circuit in a related technology.

[0017] In existing technologies, such as Figure 1 As shown, the gate c of the driving transistor T1 is electrically connected to the first reset transistor T2 and the first transistor T3. Normally, leakage current easily occurs between the gate c and the first reset transistor T2, and between the gate c and the first transistor T3, leading to poor potential stability at the gate c and affecting the on / off state of the driving transistor T1. To solve the problem of the gate c potential of the driving transistor T1 being affected by leakage current, as follows... Figure 1As shown, a common solution involves adding a voltage-stabilizing capacitor C2 to the pixel circuit 01'. The voltage-stabilizing capacitor C2 is electrically connected to the gate c of the driving transistor T1. Compared to the absence of a voltage-stabilizing capacitor C2, it enhances the potential stability of the gate c, improves the operational stability of the driving transistor T1, and reduces the risk of screen flicker. However, in some operational phases, the presence of the voltage-stabilizing capacitor C2 also slows down the potential adjustment speed of the gate c. For example, during the data writing phase, as the data voltage is written to the gate c via the first transistor T3, the presence of the voltage-stabilizing capacitor C2 increases the data voltage writing time required for the gate c to reach the target potential. Furthermore, in the high-frequency display phase, due to the limited duration of the data writing phase, the presence of the voltage-stabilizing capacitor C2 makes it difficult for the gate c to reach the target potential within the data writing phase, thus affecting the on / off state of the driving transistor T1 and interfering with the display panel's display effect.

[0018] like Figure 1 As shown, the existing pixel circuit 01' may further include a data writing transistor T4, a first control transistor T5, a second control transistor T6, a second reset transistor T7, and a first capacitor C1. The connection relationships between the transistors and capacitors are shown in the figure and will not be repeated here. The existing pixel circuit 01' may also be electrically connected to the first power supply voltage line Vdd, the data signal line Data, the first reset line V1, and the second reset line V2. The output terminal of the existing pixel circuit 01' may be electrically connected to the first terminal of the light-emitting device 02, and the second terminal of the light-emitting device 02 may be electrically connected to the second power supply voltage line VEE.

[0019] Figure 2 An equivalent circuit diagram of a pixel circuit in a display panel provided in this application.

[0020] To address the aforementioned problems, this application provides a display panel, which includes a pixel circuit 01, such as... Figure 2 As shown, pixel circuit 01 can generate light-emitting driving current, which in turn drives light-emitting device 02 to emit light.

[0021] The pixel circuit 01 includes a driving transistor T1 and a variable capacitor C0. The driving transistor T1 is used to generate a light-emitting driving current. When the driving transistor T1 is turned on, it can generate the aforementioned light-emitting driving current in conjunction with the power supply voltage signal it receives.

[0022] The pixel circuit 01 may further include a first transistor T3 and a data writing transistor T4. The first terminal of the first transistor T3 is electrically connected to the second terminal of the driving transistor T1, and the second terminal of the first transistor T3 is electrically connected to the control terminal of the driving transistor T1. The control terminal of the first transistor T3 is also electrically connected to the first control line S1. The first terminal of the data writing transistor T4 is electrically connected to the data signal line Data, the second terminal of the data writing transistor T4 is electrically connected to the first terminal of the driving transistor T1, and the control terminal of the data writing transistor T4 is electrically connected to the second control line S2.

[0023] When the pixel circuit 01 is in the data writing stage, under the control of the electrical signals transmitted by the first control line S1 and the second control line S2 respectively, the data writing transistor T4 and the first transistor T3 are both turned on, and the data signal transmitted by the data signal line Data can be transmitted to the control terminal c of the driving transistor T1 through the data writing transistor T4, the driving transistor T1, and the first transistor T3 in sequence.

[0024] The variable capacitor C0 is electrically connected to the control terminal c of the driving transistor T1. The presence of the variable capacitor C0 increases the number of capacitors connected to the control terminal c (in this case, the control terminal c can be connected to both the first capacitor C1 and the variable capacitor C0), thus enhancing the potential stability of the control terminal c. The variable capacitor C0 can also be electrically connected to the adjustment signal line S3. Furthermore, the variable capacitor C0 can be a variable capacitor, meaning its capacitance value can be controlled to meet the operating requirements of the pixel circuit 01. For example, by increasing the capacitance value of the variable capacitor C0, the potential stability of the control terminal c can be enhanced as much as possible, reducing the impact of leakage current on the potential of the control terminal c. Conversely, by decreasing the capacitance value of the variable capacitor C0, the problem of incomplete data signal writing at the control terminal c due to excessive capacitance can be avoided.

[0025] When the display frequency of the display panel is greater than or equal to the preset value, the capacitance value of the variable capacitor C0 is c1; when the display frequency of the display panel is less than the preset value, the capacitance value of the variable capacitor C0 is c2, and c1 < c2.

[0026] In this embodiment, when the display frequency of the display panel is high, it means that the refresh rate of the display panel during the display process is high, and the number of image frames displayed per unit time is high. Therefore, the blanking phase duration between adjacent display stages is short. Considering that the data writing stage corresponding to the pixel circuit 01 can occur in the above blanking stage, the blanking phase duration corresponding to a high display frequency is limited, which determines that the data writing stage duration corresponding to the pixel circuit 01 is also limited. At this time, if the capacitance value corresponding to the control terminal c of the driving transistor T1 is too large, the limited data writing stage duration can easily lead to insufficient data signal writing at the control terminal c. Therefore, this embodiment sets a variable capacitor C0 with controllable capacitance value, and then adjusts the capacitance value corresponding to the control terminal c according to the display frequency of the display panel. When the display frequency is greater than or equal to a preset value (at this time, the display panel can be regarded as being in a high-frequency display mode), the capacitance value of the variable capacitor C0 can be adjusted to a smaller value c1 to reduce the risk of incomplete data signal writing at the control terminal c due to excessive capacitance. In addition, when the display frequency of the display panel is less than the preset value (at which time the display panel can be regarded as being in a low-frequency display mode), the data writing stage can be relatively longer. In this case, the capacitance value of the variable capacitor C0 can be adjusted to a larger value, such as C2, to reduce the impact of leakage current on the potential stability at the control terminal C, thereby improving the phenomenon of screen flickering.

[0027] like Figure 2 As shown, the pixel circuit 01 may further include a first reset transistor T2, a first control transistor T5, a second control transistor T6, a second reset transistor T7, and a first capacitor C1. The pixel circuit 01 may also be electrically connected to a first power supply voltage line Vdd, a data signal line Data, a first reset line V1, and a second reset line V2. The output terminal of the pixel circuit 01 may be electrically connected to the first terminal of the light-emitting device 02, and the second terminal of the light-emitting device 02 may be electrically connected to the second power supply voltage line VEE. The connection relationships between the aforementioned transistors, capacitors, and signal lines are detailed in the figure and will not be elaborated further here.

[0028] Figure 3 An equivalent circuit diagram of a partial structure of a pixel circuit provided in this application.

[0029] In one embodiment of this application, the variable capacitor C0 includes a semiconductor structure. Wherein, as... Figure 3As shown, the variable capacitor C0 may include a transistor structure (which may be referred to as the regulating transistor T0), and the regulating transistor T0 may include a semiconductor structure (e.g., an active layer). The control terminal of the regulating transistor T0 can be connected to the regulating signal line S3, and both the first and second terminals of the regulating transistor T0 can be electrically connected to the control terminal c of the driving transistor T1. By controlling the capacitance control signal transmitted through the regulating signal line S3, the capacitance value corresponding to the control terminal c of the driving transistor T1 can be changed, thereby realizing the scheme design of adjusting the capacitance corresponding to the control terminal c in conjunction with the display frequency of the display panel in this application. For example, when the display frequency of the display panel is greater than or equal to a preset value, the capacitance value corresponding to the regulating transistor T0 can be controlled to c1 through the capacitance control signal line S1; when the display frequency of the display panel is less than the preset value, the capacitance value corresponding to the regulating transistor T0 can be controlled to c2 through the regulating signal line S3.

[0030] In one embodiment of this application, the preset value of the display frequency is 120Hz. In this embodiment, the variable capacitor C0 may have a minimum capacitance value. Considering that the first capacitor C1 is also connected to the control terminal c, the capacitance value corresponding to the control terminal c has a minimum value, and this minimum value is difficult to further reduce by adjusting the variable capacitor C0. To avoid exceeding the adjustable range of data write integrity through controlling the variable capacitor C0, after repeated experimental verification, the preset value was set to 120Hz, which helps to reduce the risk of insufficient data write.

[0031] In one embodiment of this application, such as Figure 3 As shown, the first terminal of the variable capacitor C0 is electrically connected to the adjustment signal line S3, and the second terminal of the variable capacitor C0 is electrically connected to the control terminal c of the driving transistor T1. The first terminal of the variable capacitor C0 can refer to the control terminal of the adjustment transistor T0, and the second terminal of the variable capacitor C0 can refer to both the first and second terminals of the adjustment transistor T0 (the first and second terminals of the adjustment transistor T0 are electrically connected to the same node).

[0032] The adjustment voltage transmitted through the adjustment signal line S3 is used to control the capacitance value of the variable capacitor C0. The adjustment voltage transmitted through the adjustment signal line S3 can be obtained directly from the chip's power supply. The chip can adjust the magnitude of its output adjustment voltage based on the display frequency corresponding to the current display panel. This adjustment voltage ultimately acts on the first terminal of the variable capacitor C0, thereby adjusting the capacitance value of the variable capacitor C0.

[0033] In this embodiment, when the display frequency is greater than or equal to a preset value, the capacitance value of the variable capacitor C0 needs to be small. Therefore, the adjustment signal line S3 can transmit a smaller negative voltage signal to minimize the capacitance value corresponding to the control terminal c, thus reducing the impact on data write integrity. When the display frequency is less than the preset value, the capacitance value of the variable capacitor C0 needs to be larger. Therefore, the adjustment signal line S3 can transmit a larger negative voltage signal to increase the capacitance value corresponding to the control terminal c, enhancing the potential stability at the control terminal c and reducing screen flicker.

[0034] In one embodiment of this application, when the display frequency of the display panel is greater than or equal to a preset value, the adjustment voltage transmitted by the adjustment signal line S3 is V1, and when the display frequency of the display panel is less than the preset value, the adjustment voltage transmitted by the adjustment signal line S3 is V2, where V1 < V2.

[0035] In this embodiment, controlling the magnitude of the adjustment voltage to change the capacitance value of the variable capacitor C0 helps reduce the feasibility of controlling the capacitance value of the variable capacitor C0. Under the control of the chip, the magnitude of the adjustment voltage transmitted by the adjustment signal line S3 can be controlled in conjunction with the current display frequency. Considering that the capacitance value of the variable capacitor C0 is related to the magnitude of the voltage received at its first terminal, the design of V1 < V2 helps to reduce the capacitance value of the variable capacitor C0 at higher display frequencies.

[0036] Figure 4 This is a schematic diagram showing how the capacitance of the regulating transistor provided in this application changes with the regulating voltage.

[0037] like Figure 4 As shown, the capacitance value c0 corresponding to the regulating transistor T0 can change with the regulating voltage VG received at its control terminal. The regulating voltage transmitted by the regulating signal line S3 can satisfy Va < VG < Vb; within the range Va < VG < Vb, the capacitance value c0 of the regulating transistor T0 can change monotonically (monotonically increasing or monotonically decreasing) with the regulating voltage VG.

[0038] Figure 5 A schematic diagram showing the relationship between the adjustment voltage transmitted by the adjustment signal line and the display frequency.

[0039] In one embodiment of this application, such as Figure 5 As shown, the display frequency P1 of the display panel is negatively correlated with the adjustment voltage VG transmitted by the adjustment signal line S3.

[0040] To achieve the desired adjustment effect of "the higher the display frequency of the display panel, the smaller the capacitance value of the variable capacitor C0," this embodiment can control the voltage VG to change negatively with the display frequency P1 via a chip. This ensures that the capacitance value of the variable capacitor C0 is smaller at high frequencies and larger at low frequencies, thus adaptively adjusting the variable capacitor C0 according to the display frequency. This not only improves the flickering of the display screen caused by the unstable potential at the control terminal c, but also minimizes the impact of the variable capacitor C0 setting on the integrity of data signal writing.

[0041] In one embodiment of this application, such as Figure 5 As shown, the voltage value transmitted by the adjustment signal line S3 (which can refer to the adjustment voltage magnitude VG) gradually changes with the display frequency P1 of the display panel.

[0042] In this embodiment, within the range of display frequency P1, the adjustment voltage VG transmitted by the adjustment signal line S3 can change continuously. That is, different display frequencies P1 of the display panel correspond to different adjustment voltages VG (which can be understood as a one-to-one correspondence between display frequency P1 and adjustment voltage VG). In a display scenario where the display frequency P1 changes continuously, this design helps to achieve a continuous change in adjustment voltage VG, and the capacitance value corresponding to the control terminal c also changes continuously. This facilitates a smooth transition between improving potential stability and improving the integrity of data signal writing at the control terminal c, thereby enhancing the display effect.

[0043] Figure 6 A schematic diagram showing the relationship between the adjustment voltage transmitted by the adjustment signal line and the display frequency.

[0044] In one embodiment of this application, such as Figure 6 As shown, the voltage value VG transmitted by the adjustment signal line S3 changes in a stepwise manner with the display frequency P1 of the display panel. When the display frequency P1 is in the range Pa≤P1<Pb, the voltage value of the adjustment voltage can be M1; when the display frequency P1 is in the range Pb≤P1<Pc, the voltage value of the adjustment voltage can be M2; when the display frequency P1 is in the range Pc≤P1<Pd, the voltage value of the adjustment voltage can be M3.

[0045] In this embodiment, within a certain range of the display frequency variation, the voltage value of the adjustment voltage can remain constant. Compared to a design where the voltage value of the adjustment voltage varies continuously, a design where the voltage value of the adjustment voltage varies in a stepwise manner can reduce the number of times the voltage value of the adjustment voltage changes with the display frequency P1, which helps to reduce the frequency of chip adjustment of the adjustment voltage and save chip computing power.

[0046] Figure 7An equivalent circuit diagram of a partial structure of a pixel circuit provided in this application.

[0047] In one embodiment of this application, such as Figure 7 As shown, the first terminal of the variable capacitor C0 is electrically connected to the adjustment signal line S3, and the second terminal of the variable capacitor C0 is connected to the control terminal c of the driving transistor T1 through the switching transistor T8. When the switching transistor T8 is turned on, the variable capacitor C0 can be electrically connected to the control terminal c, which can be considered as the variable capacitor C0 being connected at the control terminal c. When the switching transistor T8 is turned off, the variable capacitor C0 is not connected to the control terminal c, which means that the variable capacitor C0 is not connected at the control terminal c.

[0048] Among them, the switching transistor T8 is turned off when the display frequency of the display panel is greater than X and turned on when the display frequency of the display panel is less than Y.

[0049] In this embodiment, when the display frequency is less than Y, the display panel can be considered to be in a low-frequency display mode. To ensure good potential stability at the control terminal c, the switching transistor T8 can be turned on to connect the variable capacitor C0 to the control terminal c, reducing the impact of leakage current on the potential at the control terminal c and improving screen flicker. Furthermore, when the display frequency is greater than X, the display panel can be considered to be in a high-frequency display mode. To avoid delaying the data signal writing progress at the control terminal c, the switching transistor T8 can be turned off, keeping the variable capacitor C0 disconnected from the control terminal c. This can be considered as not increasing the capacitance value corresponding to the control terminal c in the high-frequency display mode, avoiding the extra capacitor extending the data signal writing time, and helping to ensure complete data signal writing.

[0050] Figure 8 An equivalent circuit diagram of a partial structure of a pixel circuit provided in this application.

[0051] In one embodiment of this application, such as Figure 8 As shown, switching transistor T8 is an N-type transistor; when the control terminal of switching transistor T8 receives a high-level signal, switching transistor T8 is turned on; when the control terminal of switching transistor T8 receives a low-level signal, switching transistor T8 is turned off. In addition to switching transistor T8, all other transistors in pixel circuit 01 can be P-type transistors.

[0052] The first terminal of the switching transistor T8 is electrically connected to the second terminal of the variable capacitor C0. The second terminal of the switching transistor T8 is electrically connected to the control terminal c of the driving transistor T1. The control terminal of the switching transistor T8 is electrically connected to the adjustment signal line S3. It can be considered that the control terminal of the switching transistor T8 and the control terminal of the adjustment transistor T0 are electrically connected to the same node.

[0053] In this embodiment, when the display frequency of the display panel is less than a preset value, the adjustment signal line S3 can transmit a high-level voltage signal, resulting in a larger capacitance value corresponding to the adjustment transistor T0. Since the control terminal of the switching transistor T8 can also receive the high-level voltage signal transmitted by the adjustment signal line S3, the switching transistor T8 is turned on, and the adjustment transistor T0 is electrically connected to the control terminal c of the driving transistor T1. Correspondingly, the capacitance value corresponding to the control terminal c can be larger, which helps to weaken the influence of leakage current on the potential stability at the control terminal c and improve the display flicker phenomenon. When the display frequency of the display panel is greater than or equal to the preset value, the adjustment signal line S3 can transmit a low-level voltage signal, resulting in a smaller capacitance value corresponding to the adjustment transistor T0. Since the control terminal of the switching transistor T8 can also receive the low-level voltage signal transmitted by the adjustment signal line S3, the switching transistor T8 is turned off, and the adjustment transistor T0 is disconnected from the control terminal c of the driving transistor T1. Correspondingly, the capacitance value corresponding to the control terminal c can be smaller, which is beneficial to ensure the integrity of the data signal writing within the limited data writing phase. Therefore, the configuration method of this embodiment helps to control the switching transistor T8 to turn on and off according to the display frequency by adjusting the voltage, without the need to set an additional signal line to control the working state of the switching transistor T8, thus reducing the wiring difficulty.

[0054] Figure 9 This is a schematic diagram of a display device provided in this application.

[0055] This application provides a display device 20, such as... Figure 9 As shown, the display device 20 includes the display panel 10 provided in the above embodiments. The display device 20 can be a mobile phone, or it can be an electronic device such as a computer or television.

[0056] The display device 20 provided in this application embodiment effectively suppresses the phenomenon of screen flickering caused by leakage current at the control terminal c, and the corresponding data signal at the control terminal c is written more completely, resulting in a significant improvement in screen quality.

[0057] The same or similar parts between the various embodiments in this specification can be referred to mutually. In particular, the device embodiments and terminal embodiments are basically similar to the method embodiments, so the description is relatively simple, and the relevant parts can be referred to the description in the method embodiments.

Claims

1. A display panel, characterized by, The pixel circuit comprises a driving transistor and a variable capacitor, the driving transistor is used to generate a light-emitting driving current, and the variable capacitor is electrically connected with a control end of the driving transistor. When the display frequency of the display panel is greater than or equal to a preset value, the capacitance value of the variable capacitor is c1; and when the display frequency of the display panel is less than the preset value, the capacitance value of the variable capacitor is c2, c1 The preset value of the display frequency is X Hz.

2. The display panel of claim 1, wherein, The first end of the variable capacitor is electrically connected with an adjusting signal line, and the second end of the variable capacitor is electrically connected with the control end of the driving transistor.

3. The display panel of claim 1, wherein, The adjusting voltage transmitted by the adjusting signal line is used to control the capacitance value of the variable capacitor. When the display frequency of the display panel is greater than or equal to the preset value, the adjusting voltage transmitted by the adjusting signal line is V1; when the display frequency of the display panel is less than the preset value, the adjusting voltage transmitted by the adjusting signal line is V2; V1 4. The display panel of claim 3, wherein, The display frequency of the display panel is negatively correlated with the adjusting voltage transmitted by the adjusting signal line.

5. The display panel of claim 3, wherein, The voltage value transmitted by the adjusting signal line gradually changes with the display frequency of the display panel.

6. The display panel of claim 5, wherein, The voltage value transmitted by the adjusting signal line changes in a stepwise manner with the display frequency of the display panel.

7. The display panel of claim 5, wherein, The first end of the variable capacitor is electrically connected with an adjusting signal line, and the second end of the variable capacitor is connected with the control end of the driving transistor through a switch transistor.

8. The display panel of claim 1, wherein, The switch transistor is turned off when the display frequency of the display panel is greater than X and turned on when the display frequency of the display panel is less than Y. The switch transistor is an N-type transistor.

9. The display panel of claim 8, wherein, The first end of the switch transistor is electrically connected with the second end of the variable capacitor, the second end of the switch transistor is electrically connected with the control end of the driving transistor, and the control end of the switch transistor is electrically connected with the adjusting signal line. The variable capacitor comprises a semiconductor structure.

10. The display panel of claim 1, wherein, The display panel comprises any one of the pixel circuits in claims 1-10.

11. A display device, characterized by comprising: ​

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