Memory system, memory circuit and method for operating memory circuit

Abstract

The invention discloses a memory system, a memory circuit and a method for operating the memory circuit. In one aspect, a memory system includes a memory array, the memory array including bit lines. The memory system includes a tracking array of memory cells coupled to a tracking bit line that mimics an electrical characteristic of the bit line of the memory array. The memory system includes a tracking pre-charge circuit configured to pre-charge the tracking bit line according to a charge time of the bit line, thereby creating a sufficient margin for memory operations of the memory array.

Description

Technical Field

[0001] One embodiment of this disclosure provides a memory system, a memory circuit, and a method for operating the memory circuit. In particular, it relates to a memory system, a memory circuit, and a method for operating the memory circuit, which have tracking memory cells and delay circuits. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components, such as transistors, diodes, resistors, and capacitors. In most cases, this increase in integration density comes from a continuous reduction in the minimum feature size, which allows more components to be integrated into a given area. Summary of the Invention

[0003] According to one embodiment of this disclosure, a memory system is provided, comprising a memory array including a bit line; a tracking memory cell array coupled to the tracking bit line, the tracking bit line mimicking an electrical characteristic of the bit line of the memory array; a tracking precharge circuit for precharging the tracking bit line in response to a first operation of the memory array during a first time period corresponding to a charging time of the bit line; and a trigger circuit for generating a signal in response to a voltage of the tracking bit line satisfying a threshold, the signal causing the precharge circuit to charge the bit line after the first time period.

[0004] According to one embodiment of this disclosure, a memory circuit is provided, comprising a tracking bit line coupled to a tracking memory cell, wherein the tracking bit line and the tracking memory cell mimic multiple electrical characteristics of a bit line of a memory array; a first transistor coupled to the tracking bit line, the first transistor being configured to electrically couple the tracking bit line to a power supply voltage in response to a tracking precharge signal; and a clock generator circuit configured to generate an internal clock signal in a logic high state in response to a clock signal for memory operation, thereby generating the tracking precharge signal during a first time period corresponding to a charging time of the bit line of the memory array.

[0005] According to an embodiment of this disclosure, a method for operating a memory circuit is provided, comprising the following steps: initiating a first memory operation of a memory cell coupled to a bit line of a memory array; discharging a voltage of a tracking bit line during a first time period corresponding to a discharge time of the bit line of the memory array, the tracking bit line mimicking an electrical characteristic of the bit line; and generating a signal for initiating a second memory operation of the memory array based on the voltage of the tracking bit line after the first time period. Attached Figure Description

[0006] The various aspects of one embodiment of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with standard industry practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1 A schematic diagram illustrating an exemplary memory system, including delay circuitry to create sufficient margin, according to some embodiments;

[0008] Figure 2 Description of implementation according to some embodiments Figure 1 An exemplary circuit diagram of a memory system;

[0009] Figure 3 The description, based on some embodiments, illustrates that during memory operation, it is possible to... Figure 2 A schematic diagram of an exemplary waveform of the signal propagating in the memory circuit shown;

[0010] Figure 4 This illustration shows a schematic diagram of another exemplary memory circuit, including a delay circuit, to create sufficient margin using a Schmitt trigger, according to some embodiments.

[0011] Figure 5 The description explains that, according to some embodiments, memory operations can be performed via... Figure 4 A schematic diagram of an exemplary waveform of the signal propagating in the memory circuit shown;

[0012] Figure 6 The illustration shows a schematic diagram of an exemplary memory circuit, according to some embodiments, including a switching delay circuit to create different margins between different memory cells.

[0013] Figure 7 The description explains that, according to some embodiments, memory operations can be performed via... Figure 6 A schematic diagram of an exemplary waveform of the signal propagating in the memory circuit shown;

[0014] Figure 8 The illustration shows a schematic diagram of an exemplary memory system including delay circuitry according to some embodiments, which switches between tracking unit loads to create sufficient margin.

[0015] Figure 9 Description of implementation according to some embodiments Figure 8 An exemplary circuit diagram of a memory system;

[0016] Figure 10 The description explains that, according to some embodiments, memory operations can be performed via... Figure 9 A schematic diagram of an exemplary waveform of the signal propagating in the memory circuit shown;

[0017] Figure 11 The illustration shows a schematic diagram of an exemplary memory circuit including delay circuitry according to some embodiments, which traces input / output directional wiring to create sufficient margin between different memory cells;

[0018] Figure 12 Descriptions according to some embodiments may include in Figure 11 A schematic diagram of an exemplary tracking precharge circuit;

[0019] Figure 13 The description explains that, according to some embodiments, memory operations can be performed via... Figure 11 A schematic diagram of an exemplary waveform of the signal propagating in the memory circuit shown;

[0020] Figure 14 The flowchart illustrates an exemplary method of operating an exemplary memory circuit according to some embodiments, the exemplary memory circuit implementing a delay to create sufficient margin during memory operation.

[0021] [Symbol Explanation]

[0022] 100: Memory System

[0023] 102, 1111: Memory cell array

[0024] 104, 804A, 804B: Character line driver circuits

[0025] 106, 806A, 806B: Tracking Memory Cell Array

[0026] 108, 208, 408, 608, 808A, 808B, 908: Memory units

[0027] 110, 210, 410, 610, 810A, 810B, 910A, 910B, 1110: Tracking memory units

[0028] 112,812: Control circuit

[0029] 113, 213, 413, 613, 913, 1113: Clock generator circuits

[0030] 114,814:I / O circuit

[0031] 116, 202, 402, 602, 816, 902, 1102: Tracking precharge circuit

[0032] 118: Reset trigger circuit

[0033] 120,122,220,222,820,822: Buffer

[0034] 124, 224, 424, 624, 824, 924, 1124A~1124N: Pre-charge circuit

[0035] 200, 400, 600, 900, 1100: Memory circuit

[0036] 218, 418, 618, 918, 1118: Trigger circuit

[0037] 300, 500, 700, 1000, 1300: Schematic diagram

[0038] 302,502: Spare space

[0039] 604,1202: NOR gate

[0040] 606: Inverter

[0041] 802A, 802B: Memory Array

[0042] 817, 917: Switching circuit

[0043] 919: NAND Gate

[0044] 921: Inverter

[0045] 1104: First NOR gate

[0046] 1106: Second NOR gate

[0047] 1108: Third NOR gate

[0048] 1109: Fourth NOR gate

[0049] 1200: Tracking precharge circuit

[0050] 1204: First Inverter

[0051] 1400: Method

[0052] 1402, 1404, 1406: Operations

[0053] BL, BLB: Bitline

[0054] BLPREB: Bit line precharge signal

[0055] CLK: Clock

[0056] ICLK: Internal Clock

[0057] M1~M57: Transistors

[0058] PC: Precharge signal

[0059] PHASE: Phase (signal)

[0060] RST: Reset signal

[0061] SW: Switch signal

[0062] TRK: Tracking

[0063] TRKBL: Tracking Bit Line

[0064] TRKBL_D, TRKBL_U: Nodes

[0065] TRKWL: Tracking Character Lines

[0066] VDD: Power supply voltage

[0067] WL: Character Line Detailed Implementation

[0068] The following disclosure provides several different embodiments or instances for implementing various features of the provided object. Specific examples of components and arrangements described below are used to simplify one embodiment of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature above or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, an embodiment of this disclosure may repeat element symbols or letters in various instances. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0069] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “below,” “above,” and “above” may be used herein to describe the relationship between one element or feature and another as illustrated in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0070] Memory circuitry, including static random-access memory (SRAM) circuitry, typically comprises an array of memory cells selectively controlled to perform read and write operations. These operations are synchronous, and a challenge in designing memory devices includes ensuring that circuit elements start up with the correct timing to avoid unnecessary latency and power consumption. In pseudo-multiport memory, SRAM memory cells use the same physical ports for read and write operations. Before accessing a memory cell, the bit lines coupled to that cell need to be charged or discharged to the desired state. When performing consecutive memory operations in the memory array, a delay time, referred to herein as “inter-margin,” is implemented to ensure that the bit lines of the memory array are fully charged or discharged for the next memory operation.

[0071] A conventional approach to achieving sufficient margin of delay involves using inverter chains. An inverter chain comprises multiple inverters connected in series, creating a signal path delay that is proportional to the number of inverters in the chain and their respective propagation delays. However, conventional inverter chains cannot produce a consistent delay to achieve sufficient margin of delay based on process, voltage, and temperature (PVT) variations that may occur during device creation or operation.

[0072] This disclosure provides various techniques for implementing memory systems, including delay circuits that provide sufficient margin of delay even when subjected to PVT variations. The systems, circuits, and methods described herein do not merely implement conventional inverter chain delay circuits, but also provide delay circuits that implement memory circuit structures in parallel trace circuits, providing sufficient margin of delay based on PVT variations. Because the trace circuits and their corresponding input / output lines mimic the electrical characteristics of actual memory cells, the delays generated according to the techniques described herein always provide sufficient margin of delay, enabling designs with tighter timing tolerances and higher yields, while reducing overall device area.

[0073] Figure 1 The illustration shows an exemplary memory system 100, including delay circuitry to create sufficient margin, according to some embodiments. The memory system 100 may be included in any type of memory device or integrated circuit (IC) device. In at least one embodiment, the memory device is a separate IC device. In some embodiments, the memory device is part of a larger IC device that includes circuitry other than the memory device to perform additional functions.

[0074] Each component shown in memory system 100 may receive power from one or more voltage sources. Memory system 100 may include one or more logic gates and sub-circuits, each of which may be composed of one or more logic gates. A logic gate is an electronic device that performs logical operations on one or more input signals to produce a single output signal. Various embodiments of the circuitry and logic gates implementing memory system 100 may include various transistors. The transistors described herein may have a certain type (n-type or p-type), but the embodiments are not limited thereto. The transistor can be any suitable type of transistor, including but not limited to metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, P-channel metal-oxide semiconductors (PMOS), N-channel metal-oxide semiconductors (NMOS), bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, P-channel and / or N-channel field effect transistors (PFETs / NFETs), FinFETs, planar MOS transistors with convex source / drain electrodes, nanosheet FETs, nanowire FETs, etc.

[0075] It should be understood that, although Figure 1 The memory system 100 shown may be part of a larger memory circuit, including any number of bit line pairs BL and BLB or write lines WL, addressable by the respective memory cell selection circuitry. Similarly, although not shown here for visual clarity, various additional circuitry may be included to address (e.g., select) different portions of the memory cells or to perform different memory operations, such as write or read operations.

[0076] Memory system 100 is shown as including memory cell array 102, which includes memory cells 108 coupled between bit line pairs BL and BLB. Memory cells 108 can be any type of memory device capable of storing at least one bit of memory data, including but not limited to SRAM cells or dynamic random-access memory (DRAM) cells. In some implementations, bit lines BL and BLB and the memory cells 108 coupled therebetween can be part of a row of memory array. As shown, precharge circuitry 124 is coupled to bit lines BL and BLB. Precharge circuitry 124 can include any type of circuitry to charge bit lines BL and BLB to a predetermined voltage (e.g., approximately the power supply voltage) for write operations. Although not shown here for visual clarity, in some implementations, multiple memory cells 108 can be arranged in multiple columns and coupled to each of the bit line pairs BL and BLB. The memory array may include multiple rows, each row including a corresponding set of bit lines having multiple memory cells 108 coupled thereto.

[0077] A single memory cell 108 of the memory array can be addressed by accessing the corresponding bit lines BL and BLB (row-selected) and / or the corresponding word lines WL or source lines (column-selected). The addressed memory cell can be selected for write and / or read operations. Signals for selecting the memory cell and coordinating the read / write operations can be provided by memory control circuitry. Memory control circuitry can include any type of control circuitry that provides signals via the circuitry of memory system 100 to coordinate read or write operations. In some embodiments, one or more components of memory system 100 may form at least a portion of the memory control circuitry.

[0078] The memory system 100 is shown to include control circuitry 112, which includes clock generator circuitry 113. Clock generator circuitry 113 is shown to receive a clock (CLK) signal. The CLK signal is a timing signal that controls the timing of operations in the memory system 100. Clock generator circuitry 113 may generate an internal clock (ICLK) signal, which may be a timing signal used to coordinate read / write operations on one or more memory cells 108. Clock generator circuitry 113 may include any type of circuitry to generate the ICLK signal based on the input clock signal CLK. Figure 3 The example waveform of the ICLK signal relative to the input clock signal CLK is shown in the figure.

[0079] The memory system 100 is shown to include a word line driver circuit 104 that, upon startup, generates a startup signal on a WL coupled to a memory cell 108 to select the memory cell 108 for memory operation. The memory system 100 is also shown to include a tracking memory cell array 106, which may include at least one tracking memory cell 110. Figure 2 An exemplary circuit is shown, including an exemplary structure of a tracking memory cell 110. The tracking memory cell 110 may mimic the electrical characteristics of memory cell 108 relative to WL startup and bit line precharge / discharge. Memory system 100 is shown as including input / output (I / O) circuitry 114, which includes precharge circuitry 124 coupled to bit lines BL and BLB.

[0080] The ICLK signal generated by clock generator circuit 113 is provided as input to buffers 120 and 122. Buffers 120 and 122 may include any even number of inverters to buffer the ICLK signal to maintain signal strength or introduce a small delay during transmission to other circuits in memory system 100. Buffer 120 provides the buffered ICLK signal as input to tracking memory cell 110 as a tracking word line (TRKWL) signal, which mimics the determination of word line WL by word line driver circuit 104. As shown, tracking (TRK) memory cell 110 is coupled to tracking bit line (TRKBL), which mimics the electrical characteristics of bit line BL.

[0081] The control circuit 112 is shown to include a TRK precharge circuit 116, which receives the ICLK signal and controls the voltage level of the TRKBL node coupled to the TRK memory cell 110. (This will be combined with...) Figure 2 Further details describe the TRK precharge circuit 116. The TRKBL node is coupled to a reset trigger circuit 118, which controls the reset signal RST of the clock generator circuit 113. This will be combined with... Figure 3 The waveforms corresponding to the signals shown in the memory system 100 are described in further detail.

[0082] See Figure 2 This describes the implementation according to some embodiments. Figure 1 An exemplary memory circuit 200 comprising at least a portion of a memory system 100. The memory circuit 200 can realize [something related to memory system 100]. Figure 1 The memory system 100 shown has similar functions and may include the same as... Figure 1The memory system 100 shown has a similar structure. Each component shown in the memory circuit 200 can receive power from one or more voltage sources (such as power supply voltage VDD). The memory circuit 200 may include one or more logic gates and sub-circuits, each of which may be composed of one or more logic gates. A logic gate is an electronic device that performs logical operations on one or more input signals to produce a single output signal.

[0083] Various embodiments of the circuitry and logic gates implementing memory circuitry 200 may include various transistors. The transistors described herein may have a certain type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain terminals, nanosheet FETs, nanowire FETs, etc. It should be understood that... Figure 2 The memory circuit 200 shown may be part of a larger memory circuit that includes memory cells (e.g., memory cell 108) and corresponding read / write circuitry. For example, although not shown here for visual clarity, it may include various additional circuitry to address (e.g., select) or otherwise access memory cells or perform different memory operations, including but not limited to CIM operations, write operations, or read operations.

[0084] Memory circuit 200 is shown as including transistors M1, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11, and M12. Transistors M1 and M2 are shown as part of TRK precharge circuit 202. Transistors M3 and M4 are shown as part of TRK memory cell 210. Transistors M5, M6, M7, M8, M9, and M10 are shown as part of memory cell 208. Transistors M11 and M12 are shown as part of precharge circuit 224. TRK precharge circuit 202, clock generator circuit 213, TRK memory cell 210, precharge circuit 224, and memory cell 208 may be similar to and include any structure, and may be implemented and combined. Figure 1 The described memory system 100 includes any of the functions of the TRK precharge circuit 116, clock generator circuit 113, TRK memory cell 110, precharge circuit 124, and memory cell 108.

[0085] Although each transistor M1 to M12 in memory circuit 200 is shown as a single transistor, the embodiments are not limited thereto. For example, each transistor may include multiple transistors (“sub-transistors”) connected in parallel with each other. For example, in embodiments, each sub-transistor of any transistor described herein may include a respective gate, drain, and source terminal, each of which may be connected in parallel with each other. For example, in some implementations, each of devices M1 and M2 may each include four parallel transistors, and each of transistors M11 and M12 may each include two parallel transistors.

[0086] The TRK precharge circuit 202 includes transistors M1 and M2. In some embodiments, transistors M1 and M2 are pMOSFET transistors. It should be understood that each of transistors M1 and M2 may include any of a variety of other types of transistors (e.g., bipolar junction transistors, high electron mobility transistors, etc.) while still remaining within the scope of one embodiment of this disclosure. As shown, the source of transistor M1 is coupled to the supply voltage VDD, and the source of transistor M2 is coupled to the drain of transistor M1. The drain of transistor M2 is coupled to the TRKBL node. The gates of the transistors each receive an ICLK signal generated by the clock generator circuit 213.

[0087] As shown in the figure, the memory circuit 200 includes buffers 220 and 222, which can be similar to and include combinations of... Figure 1 The memory system 100 described includes buffers 120 and 122, with any configuration. The TRK memory cell 110 is shown as including transistors M3 and M4. In some implementations, transistors M3 and M4 are nMOSFET transistors. It should be understood that each of transistors M3 and M4 may include any of a variety of other types of transistors (e.g., bipolar junction transistors, high electron mobility transistors, etc.) while still remaining within the scope of one embodiment of this disclosure. The first source / drain terminal of transistor M3 is coupled to the TRKBL node, and the second source / drain terminal of transistor M3 is coupled to the first source / drain terminal of transistor M4. The gate terminal of transistor M4 is coupled to the power supply voltage VDD, and the second source / drain terminal of transistor M4 is coupled to ground.

[0088] Buffer 222 provides a buffered ICLK signal to the gate terminals of transistors M11 and M12, shown here as a low-level quasi-active bit line pre-charge signal (BLPREB). Pre-charge circuit 224 is shown including transistors M11 and M12. In some embodiments, transistors M11 and M12 are pMOSFET transistors. It should be understood that each of transistors M11 and M12 may include any of a variety of other types of transistors (e.g., bipolar junction transistors, high electron mobility transistors, etc.) while still within the scope of one embodiment of this disclosure. The first source / drain terminal of transistor M11 is coupled to bit line BL, and the second source / drain terminal of transistor M11 is coupled to the power supply voltage VDD. The first source / drain terminal of transistor M12 is coupled to the power supply voltage VDD, and the second source / drain terminal of transistor M12 is coupled to the second bit line BLB.

[0089] Memory cell 208 may be an SRAM memory cell. Memory cell 208 is shown as including transistors M5, M6, M7, M8, M9, and M10. In some embodiments, transistors M5, M7, M9, and M10 are nMOSFET transistors. In some embodiments, transistors M6 and M8 are pMOSFET transistors. It should be understood that each of transistors M5, M6, M7, M8, M9, and M10 may include any of a variety of other types of transistors (e.g., bipolar junction transistors, high electron mobility transistors, etc.) while still remaining within the scope of one embodiment of this disclosure. Transistors M6, M7, M8, and M9 are shown in a cross-coupled arrangement. The sources of transistors M6 and M8 are coupled to the power supply voltage VDD, and the sources of transistors M7 and M9 are coupled to ground.

[0090] The gates of transistors M6 and M7 are coupled to each other and to the drain terminals of transistors M8 and M9, which are also coupled to each other. The gates of transistors M8 and M9 are coupled to each other and to the drain terminals of transistors M6 and M7, which are also coupled to each other. The first source / drain terminal of transistor M5 is coupled to bit line BL, and the second source / drain terminal of transistor M5 is coupled to the drain terminals of transistors M6 and M7. The first source / drain terminal of transistor M10 is coupled to bit line BLB, and the second source / drain terminal of transistor M10 is coupled to the drain terminals of transistors M8 and M9.

[0091] When clock generator circuit 213 receives the rising edge of clock signal CLK, it generates a high-level active ICLK signal (e.g., logic high, approximately the supply voltage). This causes transistors M11 and M12 to turn off (e.g., BLPREB behaves as a low-level active signal), thereby disabling precharge circuit 224. This also causes transistors M1 and M2 to turn off, and TRKWL is determined, causing the TRKBL node to discharge via transistors M3 and M4. A logic high state (e.g., approximately the supply voltage) of TRKWL causes transistor M3 to turn on and conduct, while transistor M4 remains on and conducts. This mimics the discharge behavior of bit lines BL and BLB. Although only one TRK memory cell 210 is shown here, it should be understood that in some implementations, multiple TRK memory cells 210 may be coupled to TRKBL (and not to TRKWL, to simulate an unselected transistor) to mimic the electrical characteristics of bit line BL.

[0092] When the TRKBL node discharges to approximately half of the power supply voltage, the trigger circuit 218 (possibly similar to...) Figure 1 The trigger circuit 218 generates a logic high RST signal. In this example, the trigger circuit 218 is an inverter that produces a logic high output once the input (e.g., the voltage at the TRKBL node) reaches the inverter's threshold start value. The threshold start value can be any value that the inverter detects as a logic zero or a logic low signal, possibly around half the supply voltage VDD. The reset signal RST causes the clock generator circuit 213 to set the ICLK signal to a logic low state.

[0093] When the ICLK signal is in the logic low phase, transistors M1 and M2 of the TRK precharge circuit 202 are turned on and conducting, while transistor M3 is turned off and not conducting, thereby charging the TRKBL node to approximately the supply voltage. Transistors M11 and M12 of the precharge circuit are turned on and conducting, precharging bit lines BL and BLB. In some implementations, a stacked configuration of pMOSFET transistors M1 and M2 is used to slow down the precharging of the TRKBL node, ensuring sufficient timing margin. Once the TRKBL node transitions to the logic high state, the trigger circuit 218 outputs a logic low reset signal RST, causing the clock generator circuit 213 to generate a logic high ICLK signal for the next memory operation. Figure 3 Describe the exemplary waveforms corresponding to these memory operations.

[0094] See Figure 3 , combined Figure 2 The components described herein, illustrating how they can be used during memory operation according to some embodiments, are shown. Figure 2A schematic diagram 300 illustrates an exemplary waveform of the signal propagating in the memory circuit shown. Schematic diagram 300 illustrates two read operations, one of which is performed on an exemplary memory array (e.g., ...). Figure 1 The memory operation is performed at the first port of the memory array 102, and another read operation is performed at the second port. As shown, the memory operation is initiated at the rising edge of the input clock signal CLK. (For example, a corresponding rising edge is generated on the ICLK signal by the clock generator circuit 213, with a slight delay due to the internal logic of the clock generator circuit.)

[0095] Such as combination Figure 2 This causes the word line WL, the tracking word line TRKWL, and the precharge signal BLPREB to transition to a logic high state, thereby selecting memory cell 208 and TRK memory cell 210, and disabling the precharge circuit 224 and TRK precharge circuit 202. When the precharge circuit 224 and TRK precharge circuit 202 are disabled, the voltage at the tracking bit line TRKBL and bit line BL begins to decrease over time. When the tracking bit line TRKBL reaches a threshold voltage, a trigger circuit (e.g., trigger circuit 218) causes the reset signal RST to transition to a logic high state (e.g., approximately the supply voltage). Because the electrical characteristics of the tracking bit line TRKBL match those of the bit line BL, the voltage discharge at the tracking bit line TRKBL mimics the voltage discharge at the bit line BL, as shown in the figure.

[0096] When the reset signal RST is determined in a logic high state, clock generator circuit 213 causes the ICLK signal to transition to a logic low state after an appropriate delay (which can be implemented via the logic of clock generator circuit 213). When the ICLK signal transitions to a logic low state, word line WL, track word line TRKWL, and precharge signal BLPREB each transition to a logic low state. This causes precharge circuit 224 and TRK precharge circuit 202 to be activated, resulting in a voltage rise at the TRKBL node and bit line BL, as shown. When the TRKBL node rises to the threshold voltage, a trigger circuit (e.g., trigger circuit 218) causes the reset signal RST to transition to a logic low state.

[0097] When the reset signal RST is determined to be in a low logic state, clock generator circuit 213 causes the ICLK signal to transition to a high logic state after an appropriate delay (which can be implemented via the logic of clock generator circuit 213). This initializes subsequent memory operations within the same clock cycle as the input clock signal (e.g., on the second memory port of the memory array). As shown, a similar operation is performed in response to the determination that the ICLK signal is in a high logic state.

[0098] Because the voltage delay at TRKBL is a function of device characteristics, this delay provides an appropriate margin 302 between memory operations (e.g., between the determination of the ICLK signal in a logic high state), thereby achieving higher throughput compared to other methods. The delay is adjusted accordingly when the PVT characteristics of the memory device change (e.g., temperature rise), as shown by the dashed waveforms of the TRKBL node and the reset signal RST. In this example, if electrical characteristics cause TRKBL to charge faster, the reset signal is determined in both logic high and logic low states to compensate for these changes, as illustrated. Although the foregoing is shown as a read / read operation, it should be understood that memory operations can be any suitable sequence of memory operations, including write / read, read / write, or write / write operations.

[0099] See Figure 4 The diagram illustrates another exemplary memory circuit 400 according to some embodiments, which includes delay circuitry to create sufficient margin using a Schmitt trigger. The memory circuit 400 can implement similar functionality and may include... Figure 2 The memory circuit 200 shown has a similar structure and can be implemented as follows: Figure 1 This is part of a memory system 100. Each component shown in the memory circuit 400 may receive power from one or more voltage sources (such as power supply voltage VDD). The memory circuit 400 may include one or more logic gates and sub-circuits, each of which may be composed of one or more logic gates. A logic gate is an electronic device that performs logical operations on one or more input signals to produce a single output signal.

[0100] Various embodiments of the circuitry and logic gates implementing memory circuitry 400 may include various transistors. The transistors described herein may have a certain type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain terminals, nanosheet FETs, nanowire FETs, etc. It should be understood that... Figure 4 The memory circuit 400 shown may be part of a larger memory circuit that includes memory cells (e.g., memory cell 108) and corresponding read / write circuitry. For example, although not shown here for visual clarity, it may include various additional circuitry to address (e.g., select) or otherwise access memory cells or perform different memory operations, including but not limited to CIM operations, write operations, or read operations.

[0101] Memory circuit 400 is shown as including transistors M14, M15, M16, M17, M18, M19, M20, M21, M22, M140, M141, and M141. Transistors M14 and M15 are shown as part of TRK precharge circuit 402. Transistors M16 and M17 are shown as part of TRK memory cell 410. Transistors M18, M19, M20, M21, M22, and M140 are shown as part of memory cell 408. Transistors M141 and M142 are shown as part of precharge circuit 424. TRK precharge circuit 402, clock generator circuit 413, TRK memory cell 410, precharge circuit 424, and memory cell 408 may be similar to and include any structure, and are combined. Figure 2 The described memory circuit 200 includes any of the following functions: TRK precharge circuit 202, clock generator circuit 213, TRK memory cell 210, precharge circuit 224, and memory cell 208.

[0102] Although each of transistors M14 to M25 in memory circuit 400 is shown as a single transistor, the embodiments are not limited thereto. For example, each transistor may include multiple transistors (“sub-transistors”) connected in parallel with each other. For example, in embodiments, each sub-transistor of any transistor described herein may include a respective gate, drain, and source terminal, each of which may be connected in parallel with each other. For example, in some implementations, each of devices M14 and M15 may each include four parallel transistors, and each of transistors M24 and M25 may each include two parallel transistors. Each of the source, drain, and gate terminals of transistors M14 to M25 may be combined with... Figure 2 The source, drain, and gate terminals of transistors M1 to M12 are connected in a similar manner.

[0103] Memory circuit 400 can be with Figure 2The memory circuit 200 operates in a similar manner. As shown, the memory circuit 400 includes a trigger circuit 418, which in this example is a Schmitt trigger. A Schmitt trigger is an electronic circuit that converts a slowly changing input signal into a clearly defined output signal with a logic high or logic low state. The Schmitt trigger may include an amplifier stage with two thresholds (or hysteresis points). One hysteresis point may be a threshold that switches to a logic high output state, while the second threshold defines when the output switches back to a logic low output state. As described herein, the reset signal RST is used to control the state of the ICLK signal via clock generator circuit 413. Using a Schmitt trigger as part of the trigger circuit 418 allows the state of the RST signal to be changed by a threshold different from approximately half the supply voltage (e.g., in the case of an inverter), thereby allowing for a longer duration of the inter-proximity delay. Figure 5 An exemplary waveform that can be propagated via memory circuit 400 is shown.

[0104] See Figure 5 , combined Figure 4 The components described herein illustrate that, according to some embodiments, they can be accessed via... Figure 4 A schematic diagram 500 illustrates an exemplary waveform of the signal propagating in the memory circuitry shown. Schematic diagram 500 illustrates two read operations, one of which is performed on an exemplary memory array (e.g., ...). Figure 1 The read operation is performed at the first port of the memory array 102, and the other read operation is performed at the second port. Figure 2 The operation shown is similar, with memory operations initiated at the rising edge of the input clock signal CLK, resulting in (e.g., via clock generator circuit 413) a corresponding rising edge on the ICLK signal, slightly delayed due to the internal logic of the clock generator circuit.

[0105] Such as combination Figure 4 This causes the word line WL, the tracking word line TRKWL, and the precharge signal BLPREB to transition to a logic high state, thereby selecting memory cell 408 and TRK memory cell 410, and disabling the precharge circuit 424 and TRK precharge circuit 402. When the precharge circuit 424 and TRK precharge circuit 402 are disabled, the voltage at the tracking bit line TRKBL and the bit line BL begins to decrease over time. When the tracking bit line TRKBL reaches the threshold voltage of the Schmitt trigger of the trigger circuit 418, the reset signal RST transitions to a logic high state (e.g., approximately the supply voltage). In this example, the threshold for the Schmitt trigger to transition to a logic high state is approximately half the supply voltage, but it should be understood that other thresholds are also possible.

[0106] As described herein, when the reset signal RST is determined in a logic high state, clock generator circuit 413 causes the ICLK signal to transition to a logic low state after an appropriate delay (which can be implemented via the logic of clock generator circuit 413). When the ICLK signal transitions to a logic low state, word line WL, trace word line TRKWL, and precharge signal BLPREB each transition to a logic low state. This causes precharge circuit 424 and TRK precharge circuit 402 to be activated, resulting in a voltage rise at the TRKBL node and bit line BL, as shown in the figure. When the TRKBL node rises to the second threshold voltage of the Schmitt trigger, trigger circuit 418 causes the reset signal RST to transition to a logic low state. As shown in the figure, the threshold for transitioning to a logic low state is different from the threshold for transitioning to a logic high state. In this example, the threshold is closer to the supply voltage than half of the supply voltage, such as... Figure 3 The waveform is shown.

[0107] When the reset signal RST is determined in a logic low state, clock generator circuit 413 causes the ICLK signal to transition to a logic high state after an appropriate delay (which can be implemented via the logic of clock generator circuit 413). This initializes subsequent memory operations within the same clock cycle as the input clock signal (e.g., on the second memory port of the memory array). As shown, a similar operation is performed in response to the determination of the ICLK signal in a logic high state. The waveform corresponding to half the supply voltage is shown as a dashed line, overriding the solid line waveform. As shown, using different thresholds via a Schmitt trigger results in a larger period for the margin 502 compared to the implementation using an inverter.

[0108] See Figure 6 The illustration shows an exemplary memory circuit 600 according to some embodiments, which includes a switching delay circuit to create different margins between different memory cells. The memory circuit 600 can implement similar functionality and may include... Figure 2 The memory circuit 200 shown has a similar structure and can be implemented as follows: Figure 1 This is part of a memory system 100. Each component shown in the memory circuit 600 may receive power from one or more voltage sources (such as power supply voltage VDD). The memory circuit 600 may include one or more logic gates and sub-circuits, each of which may be composed of one or more logic gates. A logic gate is an electronic device that performs logical operations on one or more input signals to produce a single output signal.

[0109] Various embodiments of the circuitry and logic gates implementing memory circuitry 600 may include various transistors. The transistors described herein may have a certain type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain terminals, nanosheet FETs, nanowire FETs, etc. It should be understood that... Figure 6 The memory circuitry 600 shown may be part of a larger memory circuitry that includes memory cells (e.g., memory cell 108) and corresponding read / write circuitry. For example, although not shown here for visual clarity, it may include various additional circuitry to address (e.g., select) or otherwise access memory cells or perform different memory operations, including but not limited to CIM operations, write operations, or read operations.

[0110] Memory circuit 600 is shown as including transistors M26, M27, M28, M29, M30, M31, M32, M33, M34, M35, M36, and M37. Transistors M26 and M27 are shown as part of TRK precharge circuit 602. Transistors M28 and M29 are shown as part of TRK memory cell 610. Transistors M30, M31, M32, M33, M34, and M260 are shown as part of memory cell 608. Transistors M26 and M27 are shown as part of precharge circuit 624. Clock generator circuit 613, TRK memory cell 610, precharge circuit 624, and memory cell 608 may be similar to and include any structure, and are combined. Figure 2 The clock generator circuit 213, TRK memory cell 210, precharge circuit 224, and memory cell 208 of the memory circuit 200 described herein may be used for any of the functions described herein.

[0111] Although each of transistors M26 to M37 in memory circuit 600 is shown as a single transistor, the embodiments are not limited thereto. For example, each transistor may include multiple transistors (“sub-transistors”) connected in parallel with each other. For example, in embodiments, each sub-transistor of any transistor described herein may include a respective gate, drain, and source terminal, each of which may be connected in parallel with each other. For example, in some implementations, each of devices M26 and M27 may each include four parallel transistors, and each of transistors M36 and M37 may each include two parallel transistors. Each of the source, drain, and gate terminals of transistors M26 to M37 may be combined with... Figure 2 The source, drain, and gate terminals of transistors M1 to M12 are connected in a similar manner.

[0112] The memory circuit 600 includes a TRK precharge circuit 602, shown as including a NOR gate 604, an inverter 606, and transistors M26 and M27. Each of transistors M26 and M27 (although shown as separate transistors) may include two respective transistors connected in parallel and includes connections similar to those of the components of the memory circuit 600. In this example, the TRK precharge circuit 602 receives a PHASE signal from a clock generator circuit 613. The clock generator circuit 613 can control the logic state of the PHASE signal based on an input clock signal CLK and a reset signal RST. When the ICLK signal transitions from a logic low state to a logic high state, the clock generator circuit 613 can transition the logic state of the PHASE signal to a logic high state. For example, if the PHASE signal is in a logic low state and the ICLK signal transitions to a logic high state, the clock generator circuit 613 can transition the PHASE signal to a logic high state. Further in this example, if the PHASE signal is in a logic high state and the ICLK signal transitions to a logic high state, the clock generator circuit 613 can transition the PHASE signal to a logic low state. An example of this transition is... Figure 7 As shown.

[0113] As shown in the figure, NOR gate 604 receives the ICLK and PHASE signals as inputs and provides an output to inverter 606 to generate a precharge signal PC. When either the ICLK or PHASE signal is high, the precharge signal PC is high. If both the ICLK and PHASE signals are low, the precharge signal PC is low. As shown in the figure, transistor M26 receives the ICLK signal at its gate, and transistor M27 receives the PC signal. (The last sentence appears to be incomplete and possibly refers to a different function.) Figure 7 To describe it further, this allows TRKBL to charge more quickly when the PHASE and ICLK signals are in a logic low state, thereby turning on transistors M26 and M27 to charge the track bit line TRKBL.

[0114] See Figure 7 , combined Figure 6 The components described herein illustrate that, according to some embodiments, they can be accessed via... Figure 6 A schematic diagram 700 illustrates an exemplary waveform of the signal propagating in the memory circuitry shown. Schematic diagram 700 illustrates two read operations, one of which is performed on an exemplary memory array (e.g., ...). Figure 1 The read operation is performed at the first port of the memory array 102, and the other read operation is performed at the second port. Figure 2The operation shown is similar, with memory operations initiated at the rising edge of the input clock signal CLK, resulting in (e.g., via clock generator circuit 613) a corresponding rising edge on the ICLK signal, slightly delayed due to the internal logic of the clock generator circuit.

[0115] Furthermore, as shown in the figure, the clock generator circuit 613 transitions the PHASE signal to a logic high state. Since both the PHASE and ICLK signals are logic high, the inverter 606 generates a PC signal that is also logic high. During this stage, because the ICLK and PC signals are logic high, transistors M26 and M27 are both off and not conducting. The word line signal WL, the trace word line TRKWL, and the precharge signal BLPREB are also transitioned to logic high, as described herein, thereby selecting memory cell 608, TRK memory cell 610, and disabling the precharge circuit 624.

[0116] Because transistors M26 and M27 are off and not conducting, and transistors M28 and M29 are on and conducting, the voltage at the tracking bit line TRKBL begins to decrease (e.g., by discharging via transistors M28 and M29), as described herein. When the tracking bit line TRKBL reaches the threshold voltage of the trigger circuit 618 (e.g., which may include an inverter or a Schmitt trigger), the reset signal RST transitions to a logic high state (e.g., approximately the supply voltage). In this example, the threshold voltage is approximately half of the supply voltage VDD.

[0117] As described herein, when the reset signal RST is determined in a logic high state, the clock generator circuit 613 causes the ICLK signal to transition to a logic low state after an appropriate delay (which can be implemented via the logic of the clock generator circuit 613). When the ICLK signal transitions to a logic low state, the word line WL, the track word line TRKWL, and the precharge signal BLPREB each transition to a logic low state. This causes the precharge circuit 624 to be activated, resulting in a voltage rise at the bit line BL, as shown in the figure. As shown in the figure, the PHASE signal remains in a logic high state, causing the PC signal to remain in a logic high state, keeping transistor M27 off and not conducting. However, when the ICLK signal is in a logic high state, transistor M26 turns on and conducts, causing TRKBL to recharge at a first rate. As shown in the figure, the charging rate of TRKBL is slower than the charging rate when transistors M26 and M27 are both on, as shown by the dashed waveform.

[0118] When the TRKBL node rises to the threshold voltage of trigger circuit 618, the reset signal RST transitions to a logic low state. In this example, the threshold for transitioning to a logic low state is approximately half of the supply voltage VDD. However, in some implementations (e.g., if a Schmitt trigger is used to implement hysteresis, etc.), a different threshold than the threshold for transitioning to a logic high state can be used. When the reset signal RST is determined to be in a logic low state, clock generator circuit 613 causes the ICLK signal to transition to a logic high state after an appropriate delay (which can be implemented via the logic of clock generator circuit 613). This initializes subsequent memory operations within the same clock cycle as the input clock signal (e.g., on the second memory port of the memory array).

[0119] As shown in the figure, in response to the ICLK signal being in a logic high state, a similar operation is performed. When the ICLK signal transitions to a logic high state, the clock generator circuit transitions the PHASE signal to a logic low state. Since the PHASE signal is in a logic low state, the PC signal is also set to logic low whenever the ICLK signal is in a logic low state. During the second memory operation, when the ICLK signal transitions to a logic low state, transistors M26 and M27 are both turned on and conducting, thereby making the charging time of the trace bit line TRKBL faster compared to the first memory operation, as shown in the figure.

[0120] Figure 8 The illustration depicts an exemplary memory system 800 according to some embodiments, which includes delay circuitry that switches between tracking cell loads to create sufficient margin. The memory system 800 may be included in any type of memory device or IC device. In at least one embodiment, the memory device is a separate IC device. In some embodiments, the memory device is part of a larger IC device that includes circuitry other than the memory device to perform other functions. The memory system 800 may be similar to and include... Figure 1 Any structure and function of the memory system 100.

[0121] Various embodiments of the circuitry and logic gates implementing memory circuitry 800 may include various transistors. The transistors described herein may have a certain type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain terminals, nanosheet FETs, nanowire FETs, etc. It should be understood that... Figure 8The memory circuitry 800 shown may be part of a larger memory circuitry that includes memory cells (e.g., memory cell 108) and corresponding read / write circuitry. For example, although not shown here for visual clarity, it may include various additional circuitry to address (e.g., select) or otherwise access memory cells or perform different memory operations, including but not limited to CIM operations, write operations, or read operations.

[0122] It should be understood that, although Figure 8 The memory system 800 shown may be part of a larger memory circuit, including any number of bit line pairs BL and BLB or write lines WL, addressable by the respective memory cell selection circuitry. Similarly, although not shown here for visual clarity, various additional circuitry may be included to address (e.g., select) different portions of the memory cells or to perform different memory operations, such as write or read operations.

[0123] The memory system 800 is shown as including multiple memory arrays 802A and 802B, each of which includes one or more corresponding memory cells 808A and 808B. The memory arrays 802A and 802B may each be similar to and include... Figure 1 The memory array 102 can have any structure and implement any function of the memory array 102. Memory cells 808A and 808B may be similar to and include... Figure 1 The memory cell 108 can have any structure and implement any function of the memory cell 108. In some implementations, memory arrays 802A and 802B share a set of bit lines BL and BLB.

[0124] In some implementations, bit lines BL and BLB and memory cells 808A and 808B coupled therebetween may be part of rows of memory arrays 802A and 802B. The memory system 800 is shown as including input / output (I / O) circuitry 814, which includes a precharge circuitry 824 coupled to bit lines BL and BLB. As shown, the precharge circuitry 824, coupled to bit lines BL and BLB, may similarly include... Figure 1 The precharge circuit 124 may have any structure and function. Although not shown here for visual clarity, in some implementations, the plurality of memory cells 808A or 808B of memory arrays 802A and 802B may be arranged in multiple columns and coupled to each of the bit line pairs BL and BLB. Memory arrays 802A and 802B may include multiple rows, each row including a corresponding set of bit lines having a plurality of memory cells 808A and 808B coupled thereto.

[0125] The memory system 800 is shown to include a control circuit 812, which may be similar to and implement Figure 1 The control circuit 812 may have any structure or function. As shown, the control circuit 812 includes a clock generator circuit 813. The clock generator circuit 813 is shown as receiving a clock signal CLK and generating an internal clock signal ICLK and a phase signal PHASE, which can be similar to combining... Figure 6 and Figure 7 The described PHASE signal. The clock generator circuit 813 may include any type of circuitry to generate an ICLK signal and a PHASE signal based on the input clock signal CLK.

[0126] The memory system 800 is shown as including word line driver circuits 804A and 804B, which can be similar to and implement Figure 1 The word line driver circuit 104 may have any structure or function. Word line driver circuits 804A and 804B may each include one or more word lines, respectively selecting corresponding column memory cells in memory arrays 802A and 802B. Upon startup, word line driver circuits 804A or 804B may generate a startup signal on a corresponding WL coupled to memory cell 808A or 808B to select that memory cell for memory operation. Memory system 800 is shown as including corresponding trace memory cell arrays 806A and 806B, each of which may resemble trace memory array 106.

[0127] Each tracking memory cell array 806A and 806B may include one or more corresponding tracking memory cells 810A or 810B. Figure 9 An exemplary circuit is shown, including exemplary structures of tracking memory cells 810A and 810B. The tracking memory cells 810A and 810B can respectively mimic the electrical characteristics of memory cells 808A and 810B by being powered on with respect to WL and pre-charge / discharged by bit lines.

[0128] The ICLK signal generated by clock generator circuit 813 is provided as input to buffers 820 and 822. Buffers 820 and 822 may include any even number of inverters to buffer the ICLK signal to maintain signal strength or introduce a small delay during transmission to other circuits in memory system 800. Buffer 820 provides the buffered ICLK signal as input to tracking memory cell 810 as a tracking word line (TRKWL) signal, which mimics the determination of word line WL by word line driver circuit 804. As shown, tracking (TRK) memory cell 810 is coupled to tracking bit line (TRKBL), which mimics the electrical characteristics of bit line BL.

[0129] The control circuit 812 is shown as including a TRK precharge circuit 816, which receives an ICLK signal and controls the voltage level of the TRKBL_U node (corresponding to the upper TRK memory array 806A) coupled to the TRK memory cell 810A. The TRK precharge circuit 816 may be similar to any TRK precharge circuit described herein (e.g., TRK precharge circuit 116, TRK precharge circuit 202, TRK precharge circuit 402, TRK precharge circuit 602, etc.). Figure 9 Further details describe the TRK precharge circuit 816. TRKBL_U (corresponding to the upper TRK memory array 806A) is coupled to a reset trigger circuit 818, which controls the reset signal RST of the clock generator circuit 813. This will be combined with... Figure 12 The waveforms corresponding to the signals shown in the memory system 800 are described in further detail.

[0130] As shown in the figure, the TRKBL_U node is coupled to a switching circuit 817, which receives the PHASE and ICLK signals as inputs. The switching circuit 817 can switch between the upper memory array 802A and the lower memory array 802B based on the memory operation being performed. This allows for the selection of either the TRKBL_D or TRKBL_U node to mimic the performance of bit lines BL and BLB to create sufficient margin. (This will be combined with...) Figure 9 Further details are described regarding the switching circuit 817.

[0131] See Figure 9 This describes the implementation according to some embodiments. Figure 8 An exemplary circuit diagram of a memory system. Memory circuit 900 can implement similar functions and may include... Figure 2 The memory circuit 200 shown has a similar structure and can be implemented as follows:Figure 8 This is part of a memory system 800. Each component shown in the memory circuit 900 may receive power from one or more voltage sources (such as power supply voltage VDD). The memory circuit 900 may include one or more logic gates and sub-circuits, each of which may be composed of one or more logic gates. A logic gate is an electronic device that performs logical operations on one or more input signals to produce a single output signal.

[0132] Various embodiments of the circuitry and logic gates implementing memory circuitry 900 may include various transistors. The transistors described herein may have a certain type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain terminals, nanosheet FETs, nanowire FETs, etc. It should be understood that... Figure 9 The memory circuitry 900 shown may be part of a larger memory circuitry that includes memory cells (e.g., memory cells 818A or 818B) and corresponding read / write circuitry. For example, although not shown here for visual clarity, it may include various additional circuitry to address (e.g., select) or otherwise access memory cells or perform different memory operations, including but not limited to CIM operations, write operations, or read operations.

[0133] Memory circuit 900 is shown as including transistors M40, M15, M41, M42, M43, M44, M45, M46, M47, M400, M401, and M402. Transistors M40 and M15 are shown as part of TRK precharge circuit 902. Transistors M41 and M42 are shown as part of TRK memory cell 910. Transistors M43, M44, M45, M46, M47, and M400 are shown as part of memory cell 908. Transistors M401 and M402 are shown as part of precharge circuit 924. TRK precharge circuit 902, clock generator circuit 913, TRK memory cells 910A and 910B, precharge circuit 924, and memory cell 908 may be similar to and include any structure, and are combined. Figure 2 The memory circuit 200 described includes a TRK precharge circuit 202, a clock generator circuit 213, a TRK memory cell 210, a precharge circuit 224, and a memory cell 208.

[0134] Although each of the transistors M40 to M50 in the memory circuit 900 is shown as a single transistor, the embodiments are not limited thereto. For example, each transistor may include multiple transistors (“sub-transistors”) connected in parallel with each other. For example, in an embodiment, each sub-transistor of any transistor described herein may include a respective gate, drain, and source terminal, each of which may be connected in parallel with each other. For example, in some implementations, each of devices M40 and M15 may each include four parallel transistors, and each of transistors M49 and M50 may each include two parallel transistors. Each of the source, drain, and gate terminals of transistors M40 to M50 may be combined with... Figure 2 The source, drain, and gate terminals of transistors M1 to M12 are connected in a similar manner.

[0135] As shown in the figure, the drain terminals of transistors M41 and M52 of the tracking memory cells 910A and 910B are coupled to nodes TRKBL_U and TRKBL_D, respectively. In this example, the TRKBL_U node is similar to... Figure 2 The TRKBL node is coupled to trigger circuit 918 and TRK precharge circuit 902. Switching circuit 917 (which can be similar to and implemented) Figure 8 The switching circuit 817 (with any structure and function) is shown as including an inverter 921, a NAND gate 919, and transistors M38 and M39. In some implementations, transistor M39 may include an nMOSFET device, and transistor M38 may include a pMOSFET device. The inverter 921 generates an inverted ICLK signal, which is provided as an input to the NAND gate 919, which also receives a PHASE signal from the clock generator circuit 913 as an input.

[0136] When the inverted clock signal and phase signal are in a logic high state, the NAND gate 919 generates a logic low switching signal SW; otherwise, it generates a logic high switching signal SW. The SW signal is provided to the gate terminals of transistors M38 and M39. The drain terminal of transistor M38 is coupled to the TRKBL_D node, and the source terminal of transistor M38 is coupled to the TRKBL_U node, as shown in the figure. The drain terminal of transistor M39 is coupled to the TRKBL_D node, and the source terminal of transistor M39 is coupled to ground, as shown in the figure.

[0137] When the switch signal SW is in a logic high state, transistor M38 is off and not conducting, while transistor M39 is on and conducting, causing the TRKBL_D node to discharge to approximately ground voltage. When the switch signal SW is in a logic low state, transistor M38 is on and conducting, while transistor M39 is off and not conducting, causing the TRKBL_D node to be electrically coupled to the TRKBL_U node via transistor M39. If the ICLK signal is in a logic low state in this case, the TRKBL_U node and the TRKBL_D node can be charged to approximately the power supply voltage via transistor M40.

[0138] As shown in the figure, the TRK precharge circuit 902 includes a single transistor (or, in some embodiments, four transistors connected in parallel with each other), with its drain terminal coupled to the TRKBL_U node and its source voltage coupled to the supply voltage VDD. As shown, a trigger circuit 918 (which may include an inverter or Schmitt trigger as described herein) is coupled to the TRKBL_U node and generates the reset signal RST as described herein. Figure 10 Description of the signal via Figure 9 Further details regarding the propagation of the memory circuit 900.

[0139] See Figure 10 This illustrates that, according to some embodiments, memory operations can be performed via... Figure 9 A schematic diagram 1000 illustrates an exemplary waveform of the signal propagated by the memory circuit 900 shown. Schematic diagram 1000 shows two read operations, one of which is performed on an exemplary memory array (e.g., ...). Figure 1 The read operation is performed at the first port of the memory array 102, and the other read operation is performed at the second port. Figure 2 The operation shown is similar, with memory operations initiated at the rising edge of the input clock signal CLK, resulting in (e.g., via clock generator circuit 913) a corresponding rising edge on the ICLK signal, slightly delayed due to the internal logic of the clock generator circuit.

[0140] Furthermore, as shown in the figure, the clock generator circuit 913 switches the PHASE signal to a logic high state. Since the logic inversions of the PHASE and ICLK signals are in a logic high state, the NAND gate 919 generates a switching signal SW in a logic high state. During this stage, transistors M40 and M38 are off and not conducting, while transistor M39 is on and conducting, thereby pulling the voltage of the TRKBL_D line to approximately ground. The word line signal WL, the trace word line TRKWL, and the precharge signal BLPREB are also switched to a logic high state, as described herein, thereby selecting memory cell 908 and TRK memory cell 910A, and disabling the precharge circuit 924. Since the gate of M52 is coupled to ground, TRK memory cell 910B is deselected.

[0141] Because transistor M38 is off and not conducting, and transistors M41 and M42 are on and conducting, the voltage at the tracking bit line TRKBL_U begins to decrease (e.g., by discharging via transistors M28 and M29), as described herein. When the tracking bit line TRKBL_U reaches the threshold voltage of the trigger circuit 918 (e.g., which may include an inverter or a Schmitt trigger), the reset signal RST transitions to a logic high state (e.g., approximately the supply voltage). In this example, the threshold voltage is approximately half of the supply voltage VDD.

[0142] As described herein, when the reset signal RST is determined in a logic high state, the clock generator circuit 913 causes the ICLK signal to transition to a logic low state after an appropriate delay (which can be implemented via the logic of the clock generator circuit 913). When the ICLK signal transitions to a logic low state, the word line WL, the track word line TRKWL, and the precharge signal BLPREB each transition to a logic low state. This causes the precharge circuit 924 to be activated, resulting in a voltage rise at the bit line BL, as shown in the figure. Since the logic inversion of the ICLK and PHASE signals is in a logic high state, the NAND gate 919 generates a logic low switching signal SW, causing transistor M38 to turn on and conduct, while transistor M39 turns off and does not conduct. This causes the TRKBL_D node to be electrically coupled to the TRKBL_U node via transistor M38, and charges these nodes to the supply voltage, as shown in the figure.

[0143] When the TRKBL_U / TRKBL_D nodes rise to the threshold voltage of trigger circuit 918, the reset signal RST transitions to a logic low state. In this example, the threshold for transitioning to a logic low state is approximately half of the supply voltage VDD. However, in some implementations (e.g., if a Schmitt trigger is used to implement hysteresis, etc.), other thresholds different from the threshold for transitioning to a logic high state can be used. When the reset signal RST is determined to be in a logic low state, clock generator circuit 913 causes the ICLK signal to transition to a logic high state after an appropriate delay (which can be implemented via the logic of clock generator circuit 913). This initializes subsequent memory operations within the same clock cycle as the input clock signal (e.g., on the second memory port of the memory array).

[0144] As shown in the figure, in response to the ICLK signal's high state, a similar operation is performed. When the ICLK signal transitions to a high state, the clock generator circuit transitions the PHASE signal to a low state. This causes the switch signal SW to transition to a high state, thereby turning off transistor M38 and turning on transistor M39. This decouples the voltage at node TRKBL_D from the voltage at node TRKBL_U, and causes the voltage at node TRKBL_D to discharge to approximately ground voltage, as shown in the figure. During the second memory operation, when the ICLK signal transitions to a low state, transistor M40 is turned on while transistor M38 remains off, resulting in a faster charging time for the tracking bit line node TRKBL_U compared to the first memory operation, as shown in the figure.

[0145] See Figure 11 The illustration shows an exemplary memory circuit 1100 according to some embodiments, which includes tracking input / output directional wiring to create delay circuitry with sufficient margin between different memory cells. The memory circuit 1100 can implement similar functionality and may include... Figure 2 The memory circuit 200 shown has a similar structure and can be implemented as follows: Figure 1 This is part of a memory system 100. Each component shown in the memory circuit 1100 may receive power from one or more voltage sources (such as power supply voltage VDD). The memory circuit 1100 may include one or more logic gates and sub-circuits, each of which may be composed of one or more logic gates. A logic gate is an electronic device that performs logical operations on one or more input signals to produce a single output signal.

[0146] Various embodiments of the circuitry and logic gates implementing memory circuitry 1100 may include various transistors. The transistors described herein may have a certain type (n-type or p-type), but the embodiments are not limited thereto. The transistors may be any suitable type, including but not limited to MOSFETs, CMOS transistors, PMOS, NMOS, BJTs, high-voltage transistors, high-frequency transistors, PFETs / NFETs, FinFETs, planar MOS transistors with convex source / drain terminals, nanosheet FETs, nanowire FETs, etc. It should be understood that... Figure 11 The memory circuit 1100 shown may be part of a larger memory circuit that includes memory cells (e.g., memory cell 108) and corresponding read / write circuitry. For example, although not shown here for visual clarity, it may include various additional circuitry to address (e.g., select) or otherwise access memory cells or perform different memory operations, including but not limited to CIM operations, write operations, or read operations.

[0147] The memory circuit 1100 is shown as including transistors M51, M52, and M53. Transistor M51 is shown as part of the TRK precharge circuit 1102, while transistors M52 and M53 are shown as part of the TRK memory cell 1110. The clock generator circuit 1113, the TRK memory cell 1110, the precharge circuits 1124A to 1124N (sometimes collectively referred to as "precharge circuit 1124"), and the memory cell array 1111 can be similar to and include any structure, and can be combined. Figure 1 and Figure 2 The memory circuit 200 described includes a clock generator circuit 213, a TRK memory cell 210, a precharge circuit 224, and a memory cell array 102.

[0148] Although each transistor M51-M53 in memory circuit 1100 is shown as a single transistor, the embodiments are not limited thereto. For example, each transistor may include multiple transistors (“sub-transistors”) connected in parallel with each other. For example, in an embodiment, each sub-transistor of any transistor described herein may include a respective gate, drain, and source terminal, each of which may be connected in parallel with each other. The source, drain, and gate terminals of transistors M52 and M53 may be combined with... Figure 2 The source, drain, and gate terminals of transistors M3 and M4 are connected in a similar manner.

[0149] The memory circuit 1100 includes a TRK precharge circuit 1102, shown as including a first NOR gate 1104, a second NOR gate 1106, a third NOR gate 1108, and a fourth NOR gate 1109. In some embodiments, transistor M51 includes one or more pMOSFET transistors. In this example, the TRK precharge circuit 1102 receives a PHASE signal and an ICLK signal from a clock generator circuit 1113. The clock generator circuit 1113 can control the logic state of the PHASE signal based on the input clock signal CLK and the reset signal RST. The clock generator circuit 1113 can transition the logic state of the PHASE signal to a logic high state when the ICLK signal transitions from a logic low state to a logic high state. For example, if the PHASE signal is in a logic low state and the ICLK signal transitions to a logic high state, the clock generator circuit 1113 can transition the PHASE signal to a logic high state. Further in this example, if the PHASE signal is in a logic high state and the ICLK signal transitions to a logic high state, then the clock generator circuit 1113 can transition the PHASE signal to a logic low state. An example of this transition is... Figure 13 As shown.

[0150] As shown in the figure, the first NOR gate 1104 receives the ICLK signal and the internal clock response signal ICLK_RET. The internal clock response signal ICLK_RET can be a signal generated by propagating the ICLK signal along a path that mimics the electrical characteristics (e.g., resistance, capacitance, etc.) and delay of the path taken by the precharge signal BLPREB through the precharge circuits 1124A-1124N. In some implementations, the path that generates the ICLK_RET signal may include one or more buffers (e.g., a series of inverters) to match the delay of the propagating BLPREB signal.

[0151] The second NOR gate 1106 of the TRK precharge circuit 1102 receives the ICLK signal and the PHASE signal from the clock generator circuit 1113. When the PHASE signal and the ICLK signal are not in a logic high state, the output of the second NOR gate 1106 is in a logic high state; otherwise, it is in a logic low state. When the ICLK signal and the ICLK_RET signal are not in a logic high state, the output of the first NOR gate 1104 is in a logic high state; otherwise, it is in a logic low state. The third NOR gate 1108 receives the inverted output of the first NOR gate 1104 and the PHASE signal. When the inverted output of the first NOR gate 1104 is in a logic high state (e.g., if the ICLK signal or the ICLK_RET signal is in a logic high state), and the inverted phase signal is in a logic high state, the output of the third NOR gate 1108 is in a logic low state. Otherwise, the output of the third NOR gate 1108 is in a logic low state. The fourth NOR gate 1109 receives the outputs of the second NOR gate 1106 and the third NOR gate 1108 (as shown in the figure) and generates a low-level active precharge signal PC, which is coupled to the gate of transistor M51.

[0152] The source terminal of transistor M51 is coupled to the supply voltage VDD, and the drain terminal of transistor M51 is coupled to the tracking bit line TRKBL. As described herein, the tracking bit line TRKBL is coupled to a trigger circuit 1118, which may include an inverter or a Schmitt trigger to generate a reset signal RST for the clock generator circuit 1113. The timing of initiating precharging of the tracking bit line TRKBL can be switched between the timing of the ICLK signal and the timing of ICLK_RET using different states of the PHASE signal using the TRK precharge circuit 1102. When the PHASE signal is in a logic low state, precharging begins according to the timing of the ICLK signal. When the PHASE signal is in a logic high state, precharging begins according to the timing of the ICLK_RET signal. This allows the tracking bit line TRKBL to begin precharging synchronously with the precharge timing of the bit lines BL / BLB, while mimicking the wiring resistance of the BLPREB signal to ensure sufficient margin. Figure 13 More details describing the timing of the TRK precharge circuit 1102.

[0153] See Figure 12 , combined Figure 11 The components described herein, according to some embodiments, may include in Figure 11 A schematic diagram of an exemplary tracking precharge circuit 1200 is shown. In some implementations, the tracking precharge circuit 1200 may be... Figure 11An alternative to the TRK precharge circuit 1102. The tracking precharge circuit 1200 is shown as comprising four transistors M54, M55, M56, and M57, which may be pMOSFET transistors. The tracking precharge circuit 1200 is also shown as comprising a NOR gate 1202, a first inverter 2014, and a second inverter 1206. While each of transistors M54, M55, M56, and M57 is shown as a single device, any number may be included.

[0154] The output of NOR gate 1202 is provided as input to a first inverter 1204, which generates a precharge signal PC. The NOR gate 1202 coupled to the first inverter 1204 is logically equivalent to an OR gate; therefore, when the ICLK signal or the ICLK_RET signal is low, the PC signal is low, and otherwise it is high. As shown, the source terminals of transistors M54 and M56 are coupled to the power supply voltage VDD, and the source terminals of transistors M55 and M57 are coupled to the drain terminals of transistors M54 and M56, respectively. The gate terminal of transistor M54 is coupled to the ICLK signal, the gate terminal of transistor M55 is coupled to the PHASE signal, the gate terminal of transistor M57 is coupled to the inverted PHASE signal (e.g., generated by the second inverter 1206), and the gate terminal of transistor M56 is coupled to the precharge signal PC. The drain terminals of transistors M55 and M57 are each coupled to the TRKBL node. Figure 13 Further details describe the timing of the TRK precharge circuit 1200.

[0155] See Figure 13 , combined Figure 11 and Figure 12 The components described herein illustrate that, according to some embodiments, they can be accessed via... Figure 11 and / or Figure 12 A schematic diagram 1300 illustrates an exemplary waveform of the signal propagating in the memory circuit shown. Schematic diagram 1300 illustrates two read operations, one of which is performed on an exemplary memory array (e.g., ...). Figure 11 The read operation is performed at the first port of the memory array 1111, and the other read operation is performed at the second port. Figure 2 The operation shown is similar, with memory operations initiated at the rising edge of the input clock signal CLK, resulting in (e.g., via clock generator circuit 1113) a corresponding rising edge on the ICLK signal, slightly delayed due to the internal logic of the clock generator circuit.

[0156] Furthermore, as shown in the figure, the clock generator circuit 1113 causes the PHASE signal to transition to a logic high state. Since the PHASE and ICLK signals are in a logic high state, the TRK precharge circuit 1102 (or TRK precharge circuit 1200) generates the PC signal in the logic high state. The word line signal WL, the trace word line TRKWL, and the precharge signal BLPREB are also transitioned to a logic high state, as described herein, thereby selecting the memory cell of the memory cell array 1111, TRK memory cell 1110, and disabling the precharge circuit 1124.

[0157] Since transistor M51 is off and not conducting, and transistors M52 and M53 are on and conducting, the voltage at the tracking bit line TRKBL begins to decrease (e.g., by discharging via transistors M52 and M53), as described herein. When the tracking bit line TRKBL reaches the threshold voltage of the trigger circuit 1118 (e.g., which may include an inverter or a Schmitt trigger), the reset signal RST transitions to a logic high state (e.g., approximately the supply voltage). In this example, the threshold voltage is approximately half of the supply voltage VDD.

[0158] As described herein, when the reset signal RST is determined in a logic high state, the clock generator circuit 1113 causes the ICLK signal to transition to a logic low state after an appropriate delay (which can be implemented via the logic of the clock generator circuit 1113). When the ICLK signal transitions to a logic low state, the word line WL, the track word line TRKWL, and the precharge signal BLPREB each transition to a logic low state. This causes the precharge circuit 1124 to be activated, resulting in a voltage rise at the bit line BL, as shown in the figure. As shown in the figure, the PHASE signal remains in a logic high state, causing the PC signal to remain in a logic high state, and the delayed ICLK_RET signal remains in a logic high state, causing the precharge signal PC to remain determined.

[0159] When the PC signal is in a logic high state, transistor M51 remains off, keeping the voltage at the TRKBL node low, as shown in the figure. When the ICLK_RET signal transitions to a logic low state, the PC signal transitions to a logic low state, causing transistor M51 to turn on and conduct. This causes the voltage at the TRKBL node to increase to approximately the supply voltage, as shown in the figure.

[0160] When the TRKBL node rises to the threshold voltage of trigger circuit 1118, the reset signal RST transitions to a logic low state. When the reset signal RST is determined to be in the logic low state, clock generator circuit 1113 causes the ICLK signal to transition to a logic high state after an appropriate delay (which may be implemented via the logic of clock generator circuit 1113). This initializes subsequent memory operations within the same clock cycle as the input clock signal (e.g., on the second memory port of the memory array).

[0161] As shown in the figure, in response to the ICLK signal being in a logic high state, similar operations are performed. When the ICLK signal transitions to a logic high state, the clock generator circuit transitions the PHASE signal to a logic low state. When the PHASE signal is in a logic low state, the PC signal is also set to a logic high state with timing matching that of the ICLK signal, as shown in the figure. During the second memory operation, when the ICLK signal transitions to a logic low state, transistors M52 and M53 are turned on and conduct, thereby making the charging time of the trace bit line TRKBL faster compared to the first memory operation, as shown in the figure.

[0162] Figure 14 This is a flowchart illustrating an exemplary method 1400 for operating an exemplary memory circuit according to some embodiments. Method 1400 implements delays to reduce contention during memory operation. Method 1400 can be used to operate memory circuits (e.g., memory circuits 200, 400, 600, 900, or 1100, memory systems 100, 800, etc.). For example, at least some of the operations described in method 1400 use... Figure 1 , Figure 2 , Figure 4 , Figure 6 , Figure 8 , Figure 9 , Figure 11 and Figure 12 The layout and schematic diagram described herein. Note that method 1400 is merely an example and is not intended to limit an embodiment of this disclosure. Therefore, it should be understood that... Figure 14 Additional operations are provided before, during, and after Method 1400, and this document may only briefly describe some of these additional operations.

[0163] In a brief overview, method 1400 begins with operation 1402: initiating a first memory operation of a memory cell coupled to a bit line of the memory array. Method 1400 continues with operation 1404: discharging the voltage of a tracking bit line that mimics the electrical characteristics of the bit line. Method 1400 continues with operation 1406: generating a signal for initiating a second memory operation of the memory array based on the charge on the tracking bit line during the first memory operation.

[0164] Referring to operation 1402, the first memory operation targets memory cells (e.g., memory cells 108, 808A, 808B) coupled to bit lines (e.g., BL) of the memory array (e.g., memory arrays 102, 802A, 802B). For example, the memory controller may provide an input clock signal (e.g., input clock signal CLK) to memory circuitry (e.g., memory circuitry 200, 400, 600, 900, or 1100, memory system 100, 800, etc.). In some implementations, a clock generator circuit (e.g., clock generator circuitry 113) may thereby generate a PHASE signal and an ICLK signal. The memory operation may be a read operation or a write operation. In some implementations, the memory array may be a pseudo-dual-port memory array.

[0165] Referring to operation 1404, the voltage of the tracking bit line (e.g., TRKBL, TRKBL_U, TRKBL_D) is discharged, which mimics the electrical characteristics of the bit line. The step of discharging the bit line can be performed by activating one or more tracking memory cells (e.g., TRK memory cells 110, 210, etc.) coupled to the tracking bit line. In some implementations, the number of tracking memory cells coupled to the tracking bit line can be matched with the number of memory cells coupled to the bit line addressed for memory operations. The means for discharging TRKBL can be selected such that the timing of discharging TRKBL corresponds to the timing of discharging the bit line, such as... Figure 3 , Figure 5 , Figure 7 , Figure 10 and Figure 13 As shown.

[0166] Referring to operation 1406, a signal (e.g., a reset signal RST, etc.) for initiating a second memory operation of the memory array is generated based on the charge on the tracking bit lines during the first memory operation. The signal may be generated, for example, by a trigger circuit (e.g., trigger circuits 118, 218, etc.), which may include an inverter or a Schmitt trigger circuit. The trigger circuit may generate the signal when the voltage of the TRKBL node reaches a transition threshold. In some embodiments, the transition threshold may be approximately half the supply voltage of the memory circuit. In some embodiments, the trigger circuit may generate the signal at a voltage greater than half the supply voltage. The TRKBL node may be charged by a corresponding TRK precharge circuit (e.g., TRK precharge circuits 202, 402, 602, 902, 1102, 1200, etc.). In some embodiments, the second memory operation may be a write operation or a read operation.

[0167] In one embodiment of this disclosure, a memory system is disclosed. The memory system includes a memory array comprising bit lines. The memory system includes a tracking memory cell array coupled to the tracking bit lines, the tracking bit lines mimicking the electrical characteristics of the bit lines of the memory array. The memory system includes a tracking precharge circuit for precharging the tracking bit lines in response to a first operation of the memory array during a first time period corresponding to the charging time of the bit lines. The memory system includes a trigger circuit for generating a signal in response to a voltage threshold being met by the tracking bit lines, the signal causing the precharge circuit to charge the bit lines after the first time period.

[0168] In some embodiments, the memory array includes at least one memory cell coupled to a bit line.

[0169] In some embodiments, the tracking bit line is coupled to a plurality of tracking memories corresponding to a plurality of memory cells coupled to the bit line.

[0170] In some embodiments, the tracking precharge circuit is activated in response to an internal clock signal generated by a clock generator circuit.

[0171] In some embodiments, the signal generated by the trigger circuit is provided as a reset signal for the clock generator circuit.

[0172] In some embodiments, the trigger circuit includes one or more inverter or Schmitt trigger circuits.

[0173] In some embodiments, the precharge circuit is used to charge the bit lines to a power supply voltage in response to a precharge signal, which is generated by the clock generator circuit in response to a reset signal.

[0174] In some embodiments, the tracking precharge circuitry is further configured to precharge the tracking bit line according to a phase signal.

[0175] In some embodiments, the tracking precharge circuit is configured to: charge the tracking bit line at a first rate in response to a phase signal being in a logic high state; and charge the tracking bit line at a second rate in response to a phase signal being in a logic low state.

[0176] In some embodiments, the memory system further includes a switching circuit for generating a switching signal to activate a transistor that couples a trace bit line to a second trace bit line, the second trace bit line including a second electrical characteristic that increases the charging time of the trace bit line.

[0177] In another embodiment of this disclosure, a memory circuit is disclosed. The memory circuit includes tracking bit lines coupled to tracking memory cells. The tracking bit lines and tracking memory cells mimic the electrical characteristics of bit lines in a memory array. The memory circuit includes a first transistor coupled to the tracking bit lines. The first transistor is configured to electrically couple the tracking bit lines to a power supply voltage in response to a tracking precharge signal. The tracking bit lines and tracking memory cells mimic the electrical characteristics of bit lines coupled to memory cells. The memory circuit includes a clock generator circuit for generating an internal clock signal in a logic high state in response to a clock signal for memory operation, thereby causing a tracking precharge signal to be generated during a first time period corresponding to the charging time of the bit lines in the memory array.

[0178] In some embodiments, an internal clock signal is provided as a tracking precharge signal to a gate terminal of the first transistor.

[0179] In some embodiments, the first transistor charges the tracking bit line at a rate corresponding to a charging time of the bit line of the memory array.

[0180] In some embodiments, the memory circuit further includes a second transistor coupled in series with the first transistor, the second transistor being coupled to a power supply voltage, wherein a first gate terminal of the first transistor and a second gate terminal of the second transistor each receive a tracking precharge signal.

[0181] In some embodiments, the memory circuitry further includes a delay path that matches the electrical characteristics of a signal path of a precharge circuit coupled to a bit line, wherein the tracking precharge signal is further generated based on a signal propagating via the delay path.

[0182] In some embodiments, the delay path includes at least one buffer circuit.

[0183] In some embodiments, the memory circuitry further includes a buffer circuit for generating a precharge signal for the precharge circuitry based on an internal clock signal.

[0184] In some embodiments, the memory circuitry further includes an inverter for receiving a voltage on a self-tracking bit line and for generating a reset signal for a clock generator circuit in response to the voltage satisfying a threshold.

[0185] In another embodiment of this disclosure, a method is disclosed. The method includes the steps of: initiating a first memory operation of a memory cell coupled to a bit line of a memory array. The method includes the steps of: discharging a voltage of a tracking bit line during a first time period corresponding to the discharge time of the bit line of the memory array, the tracking bit line mimicking the electrical characteristics of the bit line. The method includes the steps of: generating a signal for initiating a second memory operation of the memory array based on the voltage of the tracking bit line after the first time period.

[0186] In some embodiments, the step of generating a signal to initiate operation of the second memory is in response to a voltage on the tracking bit line satisfying a threshold.

[0187] As used herein, the terms “about” and “approximately” generally refer to plus or minus 10% of the stated value. For example, about 0.5 would include 0.45 and 0.55, about 10 would include 9 to 11, and about 1000 would include 900 to 1100.

[0188] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the various aspects of an embodiment of this disclosure. Those skilled in the art should understand that an embodiment of this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of an embodiment of this disclosure, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of an embodiment of this disclosure.

Claims

1. A memory system, comprising: Comprising: a memory array comprising a bit line; a tracking memory cell array coupled to a tracking bit line that emulates an electrical characteristic of the bit line of the memory array; a tracking pre-charge circuit to pre-charge the tracking bit line for a first time period corresponding to a charge time of the bit line in response to a first operation of the memory array; and a trigger circuit to generate a signal that causes a pre-charge circuit to charge the bit line after the first time period in response to a voltage of the tracking bit line satisfying a threshold.

2. The memory system of claim 1, wherein, wherein the memory array comprises at least one memory cell coupled to the bit line, wherein the tracking bit line is coupled to a plurality of tracking memories corresponding to a plurality of memory cells coupled to the bit line.

3. The memory system of claim 1, wherein, wherein the tracking pre-charge circuit is enabled in response to an internal clock signal generated by a clock generator circuit, wherein the signal generated by the trigger circuit is provided as a reset signal to the clock generator circuit.

4. The memory system of claim 1, wherein, wherein the trigger circuit comprises one or more inverters or Schmitt trigger circuits.

5. The memory system of claim 1, wherein, wherein the tracking pre-charge circuit is further to pre-charge the tracking bit line in accordance with a phase signal, wherein the tracking pre-charge circuit is to: charge the tracking bit line at a first rate in response to the phase signal being in a logic high state; and charge the tracking bit line at a second rate in response to the phase signal being in a logic low state.

6. The memory system of claim 1, wherein, further comprising a switching circuit to generate a switch signal to enable a transistor that couples the tracking bit line to a second tracking bit line that comprises a second electrical characteristic that increases a charge time of the tracking bit line.

7. A memory circuit, comprising: Comprising: a tracking bit line coupled to a tracking memory cell, wherein the tracking bit line and the tracking memory cell emulate a plurality of electrical characteristics of a bit line of a memory array; a first transistor coupled to the tracking bit line, the first transistor to electrically couple the tracking bit line to a supply voltage in response to a tracking pre-charge signal; and a clock generator circuit to generate an internal clock signal in a logic high state in response to a clock signal for a memory operation, thereby generating the tracking pre-charge signal for a first time period corresponding to a charge time of the bit line of the memory array.

8. The memory circuit of claim 7, wherein, wherein the internal clock signal is provided as the tracking pre-charge signal to a gate terminal of the first transistor.

9. The memory circuit of claim 7, wherein, further comprising a second transistor coupled in series with the first transistor, the second transistor coupled to the supply voltage, wherein a first gate terminal of the first transistor and a second gate terminal of the second transistor each receive the tracking pre-charge signal.

10. A method of operating a memory circuit, comprising: comprising the steps of: enabling a first memory operation of a memory cell coupled to a bit line of a memory array; discharging a voltage of a tracking bit line for a first time period corresponding to a discharge time of the bit line of the memory array, the tracking bit line emulating an electrical characteristic of the bit line; and Based on the voltage of the tracking bit line after the first time period, a signal for initiating a second memory operation of the memory array is generated.

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