Memory device, system and operating method of memory device

Abstract

The invention discloses a memory device, a system and an operation method of the memory device, and belongs to the technical field of memorizing.According to the method, in the process of erasing a memory block, a first voltage is applied to the first end of a memory string, and a second voltage smaller than the first voltage is applied to a word line coupled to a first memory unit of the memory string; as the voltage difference between the first voltage and the second voltage is greater than or equal to the tunneling voltage of the first memory cell, invalid data stored in the first memory cell can be erased, and in addition, a third voltage smaller than the first voltage is configured to a word line coupled to the second memory cell of the memory string. The voltage difference between the first voltage and the third voltage is smaller than the tunneling voltage of the second storage unit, so that the stored effective data are protected from being erased, the effective data do not need to be migrated, the time for migrating the effective data back and forth is saved, and the erasing efficiency of the storage block is improved.

Description

[0001] This application is a divisional application of Chinese patent application filed on December 31, 2021, with application number 202111672655X and entitled "Storage device, system and method of operation of storage device". Technical Field

[0002] This application relates to the field of storage technology, and in particular to a storage device, system, and method of operating the storage device. Background Technology

[0003] With the development of semiconductor technology, three-dimensional (3D) memory devices have been widely used. In related technologies, the memory blocks of 3D memory devices store data, such as photos. When a photo in a memory block needs to be deleted, the 3D memory device must erase the corresponding data in the memory block. The data to be erased is invalid data, while the other data that needs to be retained is valid data.

[0004] During the data erasure process, the 3D storage device first migrates the valid data in the storage block to the selected over-provisioning block, then erases the data in the storage block, and finally migrates the valid data in the over-provisioning block back to the original storage location.

[0005] This block-based erasure method requires migrating valid data back and forth within the storage block, increasing the data erasure time and reducing data erasure efficiency. Therefore, there is an urgent need for an operation method that can improve erasure efficiency. Summary of the Invention

[0006] This application provides a storage device, a system, and a method for operating the storage device, which can improve the data erasure efficiency of the storage device. The technical solution is as follows:

[0007] In a first aspect, a storage device is provided, the storage device including a storage array and peripheral circuitry;

[0008] The storage array includes a storage string and multiple word lines. The storage string includes at least one first storage unit and at least one second storage unit. The first storage unit is a storage unit in the storage string that stores invalid data, and the second storage unit is a storage unit in the storage string that stores valid data.

[0009] The plurality of word lines are respectively coupled to the memory array;

[0010] The peripheral circuitry is coupled to the plurality of word lines and is configured as follows:

[0011] A first voltage is applied to a first end of the memory string, wherein the first end is either coupled to a bit line contact corresponding to the memory string or coupled to a source contact corresponding to the memory string.

[0012] A second voltage is applied to the word line coupled to the first memory cell, the second voltage being less than the first voltage, and the voltage difference between the first voltage and the second voltage being greater than or equal to the first tunneling voltage;

[0013] A third voltage is configured for the word line coupled to the second memory cell, the third voltage being less than the first voltage, and the voltage difference between the first voltage and the third voltage being less than the second tunneling voltage.

[0014] In one possible implementation, the peripheral circuit is further configured as follows:

[0015] The third voltage is applied to the word line coupled to the second memory cell.

[0016] In one possible implementation, the peripheral circuit is further configured as follows:

[0017] The word lines coupled to the second memory cell are floated.

[0018] In one possible implementation, the memory string further includes at least one first select transistor, the first select transistor being located near the first end; the peripheral circuitry is further configured to:

[0019] A fourth voltage is applied to the selection line coupled to the first selection tube. The fourth voltage is less than the first voltage, and the voltage difference between the first voltage and the fourth voltage satisfies the voltage difference condition for band tunneling.

[0020] In one possible implementation, the first end is coupled to a bit line contact corresponding to the memory string, the bit line contact being an N-type doped conductive structure, and the doping concentration of the impurity being greater than or equal to a first concentration.

[0021] In one possible implementation, the first concentration is 5*10^8.

[0022] In one possible implementation, the first end is coupled to the source contact corresponding to the memory string.

[0023] In one possible implementation, the memory string further includes at least one first select transistor, the first select transistor being located near the first end, the first end being coupled to the source contact portion corresponding to the memory string, the source contact portion being a P-type doped conductive structure; the peripheral circuit is further configured as follows:

[0024] A fifth voltage, which is less than the first voltage, is applied to the selection line coupled to the first selection transistor.

[0025] In one possible implementation, the first storage unit is located close to the first end, and the second storage unit is located away from the first end.

[0026] In one possible implementation, the memory string further includes at least one second selection transistor located away from the first end; the peripheral circuitry is further configured to:

[0027] A sixth voltage is configured for the selection line coupled to the second selection tube, the sixth voltage being less than the first voltage, and the voltage difference between the first voltage and the sixth voltage being less than the third tunneling voltage.

[0028] In one possible implementation, the first storage unit is located away from the first end, and the second storage unit is located close to the first end; the peripheral circuitry is further configured to:

[0029] Before the channel voltage of the memory string reaches the seventh voltage, an eighth voltage is applied to the word line coupled to the second memory cell. The seventh voltage is greater than the eighth voltage and less than or equal to the first voltage. The voltage difference between the seventh voltage and the eighth voltage is less than the second tunneling voltage.

[0030] After the channel voltage of the memory string reaches the seventh voltage, the step of configuring the third voltage for the word line coupled to the second memory cell is performed.

[0031] In one possible implementation, the memory string further includes at least one second selection transistor located away from the first end; the peripheral circuitry is further configured to:

[0032] Before the channel voltage of the memory string reaches the seventh voltage, a ninth voltage is applied to the select line coupled to the second select transistor. The seventh voltage is greater than the ninth voltage and less than or equal to the first voltage. The voltage difference between the seventh voltage and the ninth voltage is less than the third tunneling voltage.

[0033] After the channel voltage of the memory string reaches the seventh voltage, a sixth voltage is configured for the select line coupled to the second select transistor. The sixth voltage is less than the first voltage, and the voltage difference between the first voltage and the sixth voltage is less than the third tunneling voltage.

[0034] In a second aspect, a system is provided, the system including a storage device configured to store data, the storage device including a storage array and peripheral circuitry;

[0035] The storage array includes a storage string and multiple word lines. The storage string includes at least one first storage unit and at least one second storage unit. The first storage unit is a storage unit in the storage string that stores invalid data, and the second storage unit is a storage unit in the storage string that stores valid data.

[0036] The plurality of word lines are respectively coupled to the plurality of storage cells of the storage string;

[0037] The peripheral circuitry is coupled to the memory array and is configured as follows:

[0038] A first voltage is applied to a first end of the memory string, wherein the first end is either coupled to a bit line contact corresponding to the memory string or coupled to a source contact corresponding to the memory string.

[0039] A second voltage is applied to the word line coupled to the first memory cell, the second voltage being less than the first voltage, and the voltage difference between the first voltage and the second voltage being greater than or equal to the first tunneling voltage;

[0040] A third voltage is configured for the word line coupled to the second memory cell, the third voltage being less than the first voltage, and the voltage difference between the first voltage and the third voltage being less than the second tunneling voltage.

[0041] In one possible implementation, the peripheral circuit is further configured as follows:

[0042] The third voltage is applied to the word line coupled to the second memory cell.

[0043] In one possible implementation, the peripheral circuit is further configured as follows:

[0044] The word lines coupled to the second memory cell are floated.

[0045] In one possible implementation, the memory string further includes at least one first select transistor, the first select transistor being located near the first end; the peripheral circuitry is further configured to:

[0046] A fourth voltage is applied to the selection line coupled to the first selection tube. The fourth voltage is less than the first voltage, and the voltage difference between the first voltage and the fourth voltage satisfies the voltage difference condition for band tunneling.

[0047] In one possible implementation, the first end is coupled to a bit line contact corresponding to the memory string, the bit line contact being an N-type doped conductive structure, and the doping concentration of the impurity being greater than or equal to a first concentration.

[0048] In one possible implementation, the first concentration is 5*10^8.

[0049] In one possible implementation, the first end is coupled to the source contact corresponding to the memory string.

[0050] In one possible implementation, the memory string further includes at least one first select transistor, the first select transistor being located near the first end, the first end being coupled to the source contact portion corresponding to the memory string, the source contact portion being a P-type doped conductive structure; the peripheral circuit is further configured as follows:

[0051] A fifth voltage, which is less than the first voltage, is applied to the selection line coupled to the first selection transistor.

[0052] In one possible implementation, the first storage unit is located close to the first end, and the second storage unit is located away from the first end.

[0053] In one possible implementation, the memory string further includes at least one second selection transistor located away from the first end; the peripheral circuitry is further configured to:

[0054] A sixth voltage is configured for the selection line coupled to the second selection tube, the sixth voltage being less than the first voltage, and the voltage difference between the first voltage and the sixth voltage being less than the third tunneling voltage.

[0055] In one possible implementation, the first storage unit is located away from the first end, and the second storage unit is located close to the first end; the peripheral circuitry is further configured to:

[0056] Before the channel voltage of the memory string reaches the seventh voltage, an eighth voltage is applied to the word line coupled to the second memory cell. The seventh voltage is greater than the eighth voltage and less than or equal to the first voltage. The voltage difference between the seventh voltage and the eighth voltage is less than the second tunneling voltage.

[0057] After the channel voltage of the memory string reaches the seventh voltage, the step of configuring the third voltage for the word line coupled to the second memory cell is performed.

[0058] In one possible implementation, the memory string further includes at least one second selection transistor located away from the first end; the peripheral circuitry is further configured to:

[0059] Before the channel voltage of the memory string reaches the seventh voltage, a ninth voltage is applied to the select line coupled to the second select transistor. The seventh voltage is greater than the ninth voltage and less than or equal to the first voltage. The voltage difference between the seventh voltage and the ninth voltage is less than the third tunneling voltage.

[0060] After the channel voltage of the memory string reaches the seventh voltage, a sixth voltage is configured for the select line coupled to the second select transistor. The sixth voltage is less than the first voltage, and the voltage difference between the first voltage and the sixth voltage is less than the third tunneling voltage.

[0061] In one possible implementation, the system further includes a host and a memory controller;

[0062] The host is configured to send data to or receive data from the storage device;

[0063] The memory controller is coupled to the host and the memory device and is configured to control the memory device.

[0064] Thirdly, a method for operating a storage device is provided, the storage device including a storage array, the storage array including a storage string and a plurality of word lines, the storage string including at least one first storage cell and at least one second storage cell, the first storage cell being a storage cell storing invalid data in the storage string, the second storage cell being a storage cell storing valid data in the storage string, and the plurality of word lines being respectively coupled to the plurality of storage cells in the storage string; the method includes:

[0065] A first voltage is applied to a first end of the memory string, wherein the first end is either coupled to a bit line contact corresponding to the memory string or coupled to a source contact corresponding to the memory string.

[0066] A second voltage is applied to the word line coupled to the first memory cell, the second voltage being less than the first voltage, and the voltage difference between the first voltage and the second voltage being greater than or equal to the first tunneling voltage;

[0067] A third voltage is configured for the word line coupled to the second memory cell, the third voltage being less than the first voltage, and the voltage difference between the first voltage and the third voltage being less than the second tunneling voltage.

[0068] In one possible implementation, configuring a third voltage for the word line coupled to the second memory cell includes:

[0069] The third voltage is applied to the word line coupled to the second memory cell.

[0070] In one possible implementation, configuring a third voltage for the word line coupled to the second memory cell includes:

[0071] The word lines coupled to the second memory cell are floated.

[0072] In one possible implementation, the storage string further includes at least one first select transistor, the first select transistor being located near the first end; the method further includes:

[0073] A fourth voltage is applied to the selection line coupled to the first selection tube. The fourth voltage is less than the first voltage, and the voltage difference between the first voltage and the fourth voltage satisfies the voltage difference condition for band tunneling.

[0074] In one possible implementation, the first end is coupled to a bit line contact corresponding to the memory string, the bit line contact being an N-type doped conductive structure, and the doping concentration of the impurity being greater than or equal to a first concentration.

[0075] In one possible implementation, the first concentration is 5*10^8.

[0076] In one possible implementation, the first end is coupled to the source contact corresponding to the memory string.

[0077] In one possible implementation, the memory string further includes at least one first select transistor, the first select transistor being located near the first end, the first end being coupled to the source contact portion corresponding to the memory string, the source contact portion being a P-type doped conductive structure; the method further includes:

[0078] A fifth voltage, which is less than the first voltage, is applied to the selection line coupled to the first selection transistor.

[0079] In one possible implementation, the first storage unit is located close to the first end, and the second storage unit is located away from the first end.

[0080] In one possible implementation, the storage string further includes at least one second selector located away from the first end; the method further includes:

[0081] A sixth voltage is configured for the selection line coupled to the second selection tube, the sixth voltage being less than the first voltage, and the voltage difference between the first voltage and the sixth voltage being less than the third tunneling voltage.

[0082] In one possible implementation, the first storage unit is located away from the first end, and the second storage unit is located close to the first end; the method further includes:

[0083] Before the channel voltage of the memory string reaches the seventh voltage, an eighth voltage is applied to the word line coupled to the second memory cell. The seventh voltage is greater than the eighth voltage and less than or equal to the first voltage. The voltage difference between the seventh voltage and the eighth voltage is less than the second tunneling voltage.

[0084] After the channel voltage of the memory string reaches the seventh voltage, the step of configuring the third voltage for the word line coupled to the second memory cell is performed.

[0085] In one possible implementation, the storage string further includes at least one second selector located away from the first end; the method further includes:

[0086] Before the channel voltage of the memory string reaches the seventh voltage, a ninth voltage is applied to the select line coupled to the second select transistor. The seventh voltage is greater than the ninth voltage and less than or equal to the first voltage. The voltage difference between the seventh voltage and the ninth voltage is less than the third tunneling voltage.

[0087] After the channel voltage of the memory string reaches the seventh voltage, a sixth voltage is configured for the select line coupled to the second select transistor. The sixth voltage is less than the first voltage, and the voltage difference between the first voltage and the sixth voltage is less than the third tunneling voltage.

[0088] The technical solution provided in this application applies a first voltage to the first end of the storage string during the erasure of the storage block. A second voltage, less than the first voltage, is applied to the word line coupled to the first storage cell of the storage string. Since the voltage difference between the first voltage and the second voltage is greater than or equal to the tunneling voltage of the first storage cell, the invalid data stored therein can be erased. In addition, a third voltage, less than the first voltage, is applied to the word line coupled to the second storage cell of the storage string. Since the voltage difference between the first voltage and the third voltage is less than the tunneling voltage of the second storage cell, the valid data stored therein is protected from being erased. Therefore, there is no need to migrate the valid data, saving the time of migrating the valid data back and forth and improving the erasure efficiency of the storage block. Attached Figure Description

[0089] Figure 1 This is a schematic diagram of a system provided in an embodiment of this application;

[0090] Figure 2 This is a schematic diagram of a memory card provided in an embodiment of this application;

[0091] Figure 3 This is a schematic diagram of a solid-state driver provided in an embodiment of this application;

[0092] Figure 4 This is a block diagram of a storage device provided in an embodiment of this application;

[0093] Figure 5 This is a schematic diagram of the structure of a storage device provided in an embodiment of this application;

[0094] Figure 6This is a schematic diagram of the structure of a storage block provided in an embodiment of this application;

[0095] Figure 7 This is a cross-sectional side view of a storage string provided in an embodiment of this application;

[0096] Figure 8 This is a schematic diagram of a peripheral circuit provided in an embodiment of this application;

[0097] Figure 9 This is a flowchart of an operation method for a storage device provided in an embodiment of this application;

[0098] Figure 10 This is a schematic diagram illustrating the distribution of storage cells in a storage string according to an embodiment of this application;

[0099] Figure 11 This is a schematic diagram of the voltage waveform during the data erasure process in case 1.1 provided in an embodiment of this application;

[0100] Figure 12 This is a schematic diagram of the voltage waveform during the data erasure process in case 1.2 provided in an embodiment of this application;

[0101] Figure 13 This is a schematic diagram of the voltage waveform during the data erasure process under one of the circumstances 2.1.1 provided in the embodiments of this application;

[0102] Figure 14 This is a schematic diagram of the voltage waveform during the data erasure process under one of the circumstances 2.1.2 provided in the embodiments of this application;

[0103] Figure 15 This is a schematic diagram of the voltage waveform during the data erasure process under one of the circumstances 2.2.1 provided in the embodiments of this application;

[0104] Figure 16 This is a schematic diagram of the voltage waveform during the data erasure process under one of the circumstances 2.2.2 provided in the embodiments of this application;

[0105] Figure 17 Here is a flowchart of another method for operating a storage device provided in this application embodiment:

[0106] Figure 18 This is a schematic diagram of the voltage waveform during the data erasure process in case 3 provided in the embodiment of this application. Detailed Implementation

[0107] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0108] In this application, the terms "first," "second," etc., are used to distinguish identical or similar items that have essentially the same function. It should be understood that there is no logical or temporal dependency between "first," "second," and "nth," nor does it limit the quantity or execution order. It should also be understood that although the following description uses the terms "first," "second," etc., to describe various elements, these elements should not be limited by the terms.

[0109] These terms are simply used to distinguish one element from another. For example, without departing from the various examples, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element. Both the first and second elements can be elements, and in some cases, they can be separate and distinct elements.

[0110] "At least one" means one or more elements. For example, at least one element can be one element, two elements, three elements, or any integer number of elements greater than or equal to one. "At least two" means two or more elements. For example, at least two elements can be two elements, three elements, or any integer number of elements greater than or equal to two.

[0111] Figure 1 This is a schematic diagram of a system provided in an embodiment of this application. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0112] like Figure 1 As shown, system 100 includes a host 101 and a storage subsystem 102. The host 101 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 101 may be configured to send data to storage device 103. Alternatively, the host 101 may be configured to receive data from storage device 103.

[0113] The storage subsystem 102 includes one or more storage devices 103 and a memory controller 104. The storage device 103 can be any memory disclosed herein. Optionally, the storage device 103 is a NAND flash memory device, such as a 3D NAND flash memory device.

[0114] According to some embodiments, memory controller 104 is coupled to host 101 and storage device 103, and is configured to control storage device 103. Memory controller 104 can manage data stored in storage device 103 and communicate with host 101.

[0115] In one possible implementation, the memory controller 104 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0116] In one possible implementation, the memory controller 104 is designed to operate in a high duty cycle environment solid-state drive (SSD) or embedded multimedia card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays.

[0117] The memory controller 104 can be configured to control the operation of the storage device 103, such as read, erase, and program operations. The memory controller 104 can also be configured to manage various functions relating to data stored or to be stored in the storage device 103, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In one possible implementation, the memory controller 104 is also configured to process error correction codes (ECC) relating to data read from or written to the storage device 103.

[0118] The memory controller 104 may also perform any other suitable functions, such as formatting the storage device 103. The memory controller 104 may communicate with external devices (e.g., the host 101) according to a specific communication protocol. For example, the memory controller 104 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), Firewire, etc.

[0119] The memory controller 104 and one or more storage devices 103 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the system 100 can be implemented and packaged into different types of end electronic products.

[0120] Figure 2 This is a schematic diagram of a memory card provided in an embodiment of this application, as shown below. Figure 2 As shown, the memory controller 104 and a single storage device 103 can be integrated into the memory card 200. The memory card 200 may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 200 may also include a connection between the memory card 200 and a host computer (e.g., Figure 11 The memory card connector 201 is coupled to the host 101.

[0121] Figure 3 This is a schematic diagram of a solid-state driver provided in an embodiment of this application, as shown below. Figure 3 As shown, the memory controller 104 and multiple storage devices 103 can be integrated into the solid-state drive (SSD) 300. The solid-state drive 300 may also include a connection between the solid-state drive 301 and a host (e.g., Figure 1 The solid-state drive connector 310 is coupled to the host 101. In one possible implementation, the storage capacity and / or operating speed of the solid-state drive 310 is greater than the storage capacity and / or operating speed of the memory card 200.

[0122] Figure 4 This is a block diagram of a storage device provided in an embodiment of this application. The storage device 103 includes a storage array 301 and peripheral circuits 302. The storage array 301 is used to store data, and the peripheral circuits 302 are used to control the storage array 301 to implement the operation method of the storage device provided below.

[0123] For further explanation of the internal structure of storage array 301, see [link to documentation]. Figure 5 This is a schematic diagram of the structure of a storage device provided in an embodiment of the application. For example... Figure 5 As shown, the memory array 301 includes a plurality of memory strings 11 arranged in an array above a substrate (not shown) of the memory array 301, with each memory string 11 extending vertically above the substrate.

[0124] Each memory string 11 includes a plurality of memory cells 111 connected in series, and the plurality of memory cells 111 are vertically stacked above the substrate of the memory array 301. In different memory strings 11, memory cells at the same or similar height from the substrate bearing surface are located on the same layer.

[0125] The storage cell 111 includes a source (S), a drain (D), a control gate (CG), and a storage layer. The control gate of the storage cell 111 is also simply referred to as the gate (G). The storage layer is used to store electrons. The number of electrons stored in the storage layer determines the data stored in the storage cell, thus enabling the storage cell 111 to store data. Optionally, the storage cell 111 includes a floating-gate field-effect transistor (FET) or a charge-trap FET. A floating-gate FET is a special type of FET that includes a source, a drain, a control gate, and a floating gate (FG). The floating gate is the cell used to store electrons and serves as the storage layer of the storage cell 111. A charge-trap FET, also called a charge-trap device, includes a source, a drain, a control gate, and a charge-trap layer. This charge-trap layer is the cell used to store electrons and serves as the storage layer of the storage cell 111.

[0126] In some implementations, each memory cell 111 is a single-level cell having two possible memory states and thus being able to store one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range.

[0127] In some implementations, each memory cell 111 is a cell capable of storing more than a single bit of data in more than four memory states. For example, it may store two bits per cell (also known as a multi-level cell), three bits per cell (also known as a three-level cell), or four bits per cell (also known as a four-level cell). Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC may be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to that cell. A fourth nominal storage value may be used for the erase state.

[0128] Continue to refer to Figure 5 Multiple storage cells 111 in the same layer of multiple storage strings 11 share the same word line (WL).

[0129] Each memory string 11 also includes an upper select transistor 112 and a lower select transistor 113, which are used to activate the selected memory string when erasing or programming memory cells. The upper select transistor 112, also referred to as a top select gate (TSG), is present in at least one per memory string 11, and is vertically stacked above the memory cells 111 in the memory string 11. The lower select transistor 113, also referred to as a bottom select gate (BSG), is present in at least one per memory string 11, and is vertically stacked below the memory cells 111 and above the substrate in the memory string 11.

[0130] Multiple upper select transistors in the same layer of multiple memory strings 11 share the same drain select line (DSL). Multiple lower select transistors in the same layer of multiple memory strings 11 share the same source select line (SSL). In some embodiments, each memory string 11 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the TSG) or a deselect voltage (e.g., 0V) to the gate of the corresponding TSG via one or more DSLs. And / or, in some embodiments, each memory string 11 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of the BSG) or a deselect voltage (e.g., 0V) to the gate of the corresponding BSG via one or more SSLs.

[0131] Each storage string 11 also includes a dummy cell 114, and there is at least one dummy cell 114 on each storage string 11. Multiple dummy cells 114 at the same level in multiple storage strings 11 share the same dummy word line (DWL).

[0132] One end of each memory string 11 is directly or indirectly connected to a bit line (BL), and the other end of each memory string 11 is indirectly connected to a source line (SL). The end of the memory string 11 that is directly or indirectly connected to the bit line can be called the drain end, and the end that is indirectly connected to the source line can be called the source end.

[0133] All memory strings 11 sharing a set of word lines in memory array 302 are called a memory block 11A. Memory block 11A is the smallest physical addressing unit for data erasure. For further illustration of the structure of memory block 11A, see, for example, [link to documentation]. Figure 6 The diagram shown is a structural schematic of a storage block provided in an embodiment of this application. Figure 5The storage block 11A shown includes n storage strings 11, each storage string 11 including m storage cells 111. m WL lines (WL_1 to WL_m) arranged along the Z direction are connected to the respective storage cells 111 located in the same layer. j DSL lines (DSL_1 to DSL_j) arranged along the Y direction are connected to a TSG layer, and j SSL lines (SSL_0 to SSL_j) arranged along the Y direction are connected to a BSG layer. n BL lines (BL_1 to BL_n) are arranged along the X direction. Each storage string 11 shares the same source line contact connected to the source line, thus enabling each storage string 11 to share the same source line. This source line contact can also be called the array common source (ACS). Multiple virtual storage cells in the same layer of multiple storage strings 11 share the same pseudoword line DWL. Where n and m are both integers greater than 1. Figure 6 In this context, i is an integer greater than 1 and less than m, and j is an integer greater than 1 and less than n.

[0134] It should be understood that, in some examples, erasure operations can be performed at the half-block level, at the quarter-block level, or at any level with any suitable number of blocks or any suitable fraction of blocks.

[0135] Storage string 11 also includes channels, see Figure 7 The embodiment shown in this application provides a cross-sectional side view of a storage string, as shown below. Figure 7 As shown, the memory string 11 also includes a channel 115 perpendicularly passing through the memory string 11. The channels of each device in the memory string 11 are connected in series to form the channel 115, and the control lines connected to each device are formed around the channel 115. One end of the channel 115 is connected to a bit line through a bit line contact 116, and the other end is coupled to a source contact 304 in the substrate 303. The source contact 304 is coupled to a source line contact. In some embodiments, the source contact 304 is part of the substrate 303, such as... Figure 7 As shown. In another possible implementation, the source contact 304 serves as the substrate of the memory device.

[0136] The storage string 11 includes storage cells 111, an upper select transistor 112, a lower select transistor 113, and virtual storage cells 114. The control lines of storage cells 111 are the word lines connected to them, the control lines of the upper select transistor 112 are the drain select lines connected to it, the control lines of the lower select transistor 113 are the source select lines connected to it, and the control lines of the virtual storage cells 114 are the pseudo-word lines connected to them. The peripheral circuit 302 provides appropriate voltages to the control lines of the devices in the storage string of the storage array 301 during data reading, writing, or erasing operations.

[0137] Return to reference Figure 5 The peripheral circuitry 302 can be coupled to the memory array 301 via bit lines, word lines, source lines, DSL, SSL lines, and DWL. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory array 301 by applying voltage and / or current signals to each target memory cell and sensing voltage and / or current signals from each target memory cell via bit lines, word lines, source lines, DSL, SSL lines, and DWL.

[0138] Peripheral circuitry 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 8 The diagram shown is a schematic representation of a peripheral circuit provided in an embodiment of this application. Figure 8 The peripheral circuitry 302 shown includes a page buffer / sensor amplifier 804, a column decoder / bit line (BL) driver 806, a row decoder / word line (WL) driver 808, a voltage generator 810, a control logic unit 812, a register 814, an interface 816, and a data bus 818. In some examples, it also includes... Figure 8 Additional peripheral circuitry is not shown. The page buffer / sensor amplifier 804 can be configured to read data from and program (write) data to the memory array 301 according to control signals from the control logic unit 812. In one example, the page buffer / sensor amplifier 804 can store a page of programming data (write data) to be programmed into a page of the memory array 301. In another example, the page buffer / sensor amplifier 804 can perform a programming verification operation to ensure that data has been correctly programmed into the memory cell 111 coupled to the selected word line. In yet another example, the page buffer / sensor amplifier 804 can also sense a low-power signal from the bit line representing a data bit stored in the memory cell 111 and amplify a small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 806 can be configured to be controlled by the control logic unit 812 and select one or more memory strings 11 by applying a bit line voltage generated from the voltage generator 810.

[0139] The line decoder / word line driver 808 can be configured to be controlled by the control logic unit 812 and to select / deselect the word line 1620 of the memory block 11A of the memory array 301, selecting / deselecting the word line 1620 of the block 1615. The line decoder / word line driver 808 can also be configured to use the word line voltage (V) generated from the voltage generator 810. WLThe line decoder / word line driver 808 can also select / deselect and drive DSL and SSL. As described in detail below, the line decoder / word line driver 808 is configured to perform an erase operation on memory cells 111 coupled to one or more selected word lines. The voltage generator 810 can be configured to be controlled by the control logic unit 812 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 301.

[0140] Control logic unit 812 can be coupled to each of the peripheral circuits 302 described above and is configured to control the operation of each peripheral circuit 302. Register 814 can be coupled to control logic unit 812 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit 302. Interface 816 can be coupled to control logic unit 812 and acts as a control buffer to buffer control commands received from a host (not shown) and relay them to control logic unit 812, as well as to buffer status information received from control logic unit 812 and relay it to the host. Interface 816 can also be coupled to column decoder / bit line driver 806 via data bus 1618 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 301.

[0141] The erasure principle of storage cells in a storage block will be further explained below:

[0142] A bit line voltage is applied to the bit line of the memory string containing the memory cell to generate holes at one end of the memory string near the bit line. These holes propagate into the channel of the memory string, causing the channel voltage to rise. An erase voltage is applied to the word line coupled to the memory cell. This erase voltage is less than the channel voltage, and the voltage difference between them is greater than the tunneling voltage of the memory cell. This voltage difference causes a tunneling effect between the channel and the gate of the memory cell, allowing holes in the channel of the memory cell to tunnel into the memory layer of the memory cell, thereby eliminating electrons in the memory layer and erasing the memory cell.

[0143] Based on the above introduction, the following will combine... Figure 9 The flowchart shown in this application embodiment illustrates an operation method for a storage device, describing the process of erasing a memory string.

[0144] 901. Apply a first voltage to the first end of the storage string.

[0145] The memory string refers to any memory string within any memory block to be erased in the storage device. Optionally, the first voltage ranges from 10V to 30V or from 15V to 25V.

[0146] The two ends of the memory string are coupled to the corresponding bit line contact and source contact, respectively. For ease of description, the two ends of the memory string are referred to as the first end and the second end. The first end is coupled to either the corresponding bit line contact or the corresponding source contact. The second end is the other end of the memory string besides the first end. For example, if the first end is coupled to the bit line contact, then the second end is coupled to the source contact; if the first end is coupled to the source contact, then the second end is coupled to the bit line contact.

[0147] A first voltage is applied to the first end of the memory string to generate holes. Initially, the channel voltage is less than the first voltage, causing holes to move from the first end of the memory string into the channel and along the channel to the second end. As the holes move in the channel, they are distributed to various positions within the channel, gradually increasing the voltage of the entire channel to the first voltage. Additionally, the first voltage is applied to the second end of the memory string to ensure that the voltages at both ends of the channel are equal, preventing the channel from conducting.

[0148] 902. Apply a second voltage to the word line coupled to the first memory cell, the second voltage being less than the first voltage, and the voltage difference between the first voltage and the second voltage being greater than or equal to the first tunneling voltage.

[0149] The first storage cell is the storage cell in the storage string that stores invalid data. There is at least one first storage cell in the storage string, and the invalid data is data that the user specifies to be erased. Optionally, the second voltage ranges from 0V to 3V, the first tunneling voltage is the tunneling voltage of the first storage cell, and the first tunneling voltage is the minimum voltage required to erase the data stored in the first storage cell. The first tunneling voltage ranges from 15V to 30V.

[0150] As holes move in the channel, the voltage of the channel of the first memory cell gradually reaches the first voltage. Since the voltage difference between the first voltage and the second voltage is greater than or equal to the first tunneling voltage, and the first tunneling voltage is the minimum voltage that can erase the data stored in the first memory cell, the voltage difference is sufficient to cause a tunneling effect between the channel of the first memory cell and the gate of the first memory cell, thereby erasing the data stored in the first memory cell.

[0151] 903. Configure a third voltage for the word line coupled to the second memory cell, the third voltage being less than the first voltage, and the voltage difference between the first voltage and the third voltage being less than the second tunneling voltage.

[0152] The second storage cell is a storage cell in a storage string that stores valid data. There is at least one second storage cell in the storage string, and the valid data is the data stored in the storage string excluding invalid data. Optionally, the third voltage ranges from 10V to 25V, and the second tunneling voltage is the tunneling voltage of the second storage cell. The second tunneling voltage is the minimum voltage required to erase the data stored in the second storage cell, and the second tunneling voltage ranges from 15V to 30V.

[0153] In one possible implementation, the third voltage is applied to the word line coupled to the second memory cell; or, the word line coupled to the second memory cell is floated to configure the third voltage for the word line coupled to the second memory cell. Floating the word line coupled to the second memory cell puts it in a floating state. When the word line is in a floating state, if the channel voltage increases, the voltage across the capacitor will rise due to the voltage jump principle, such as rising to the third voltage. For example, the connection between the word line and the power supply can be disconnected to float the word line.

[0154] As holes move in the channel, the voltage of the channel of the second memory cell gradually reaches the first voltage. Since the voltage difference between the first voltage and the third voltage is less than the second tunneling voltage, and the second tunneling voltage is the minimum voltage required to erase the data stored in the second memory cell, the voltage difference is insufficient to cause a tunneling effect between the channel and the gate of the second memory cell, thus protecting the data stored in the second memory cell from being erased.

[0155] It should be noted that the execution order of steps 901-903 is not fixed. For example, steps 901-903 can be executed simultaneously, or step 901 can be executed first, followed by steps 902 and 903 simultaneously. Alternatively, step 903 can be executed first, followed by step 902, and then step 901. In this embodiment, the execution order of steps 901-903 is not limited.

[0156] The method provided in this application applies a first voltage to the first end of the storage string during the erasure of the storage block, and applies a second voltage less than the first voltage to the word line coupled to the first storage cell of the storage string. Since the voltage difference between the first voltage and the second voltage is greater than or equal to the tunneling voltage of the first storage cell, the invalid data stored therein can be erased. In addition, a third voltage less than the first voltage is configured on the word line coupled to the second storage cell of the storage string. Since the voltage difference between the first voltage and the third voltage is less than the tunneling voltage of the second storage cell, the valid data stored therein can be protected from being erased, thereby eliminating the need to migrate the valid data, saving the time of migrating the valid data back and forth, and improving the erasure efficiency of the storage block.

[0157] In one possible implementation, the first storage unit of the storage string is close to the first end, and the second storage unit is far from the first end. In another possible implementation, the first storage unit of the storage string is far from the first end, and the second storage unit is close to the first end.

[0158] Depending on the different distributions of the first storage cells in the storage string, holes are controlled to move from different directions into the channel of the storage string. For example, by applying a first voltage to the first end closest to the first storage cell, holes are controlled to move from that first end into the channel of the storage string. As another example, by applying a first voltage to the first end furthest from the first storage cell, holes are controlled to move from that first end into the channel of the storage string.

[0159] The process of controlling the movement of holes from the end closest to the first storage cell in the memory string into the channel of the memory string is described below:

[0160] Since the first end of the memory string may be coupled to the bit line contact corresponding to the memory string or to the source contact corresponding to the memory string, there are two cases for the memory string, namely Case 1 and Case 2 as described below.

[0161] Case 1: The first storage cell in the storage string is close to the first end, the second storage cell is far from the first end, and the first end is coupled to the bit line contact corresponding to the storage string.

[0162] by Figure 10 Taking the schematic diagram of the distribution of storage cells in a storage string provided in this application embodiment as an example, when the first end is coupled to the bit line contact corresponding to the storage string, for example, the storage string that satisfies condition 1 is... Figure 7The storage string 1001 is shown. The first storage cell in storage string 1001 is located in an adjacent layer and is close to the bit line contact coupled to storage string 1001, serving as the upper storage cell of storage string 1001. The second storage cell in storage string 1001 is located in an adjacent layer and is close to the source contact coupled to storage string 1001, serving as the lower storage cell of storage string 1001.

[0163] Case 2: The first storage cell in the storage string is close to the first end, the second storage cell is far from the first end, and the first end is coupled to the source contact of the corresponding storage string.

[0164] When the first end is coupled to the source contact corresponding to the storage string, structure 2 is, for example, Figure 10 The storage string 1002 shown has a first storage cell located in an adjacent layer and close to the source contact of the storage string 1002, serving as the lower storage cell of the storage string 1002. The second storage cell in the storage string 1002 is located in an adjacent layer and close to the bit line contact of the storage string 1002, serving as the upper storage cell of the storage string 1002.

[0165] The process of controlling holes moving along the channel from the first end to the second end of the storage string varies depending on the specific case of the storage string. Here, taking case 1 as an example, the process of controlling holes moving along the channel from the first end to the second end of the storage string is described as follows:

[0166] In case 1, when the first memory cell is close to the first end and the first end is close to the bit line contact corresponding to the memory string, if the bit line contact is an N-type doped conductive structure and the doping concentration of the impurities is greater than or equal to the first concentration, by applying a first voltage to the bit line contact, the holes are controlled to move from the first end of the memory string to the channel of the memory string.

[0167] In this context, a doped conductive structure is an impurity semiconductor obtained by doping an intrinsic semiconductor with a certain impurity. For example, an impurity semiconductor obtained by doping with a pentavalent impurity element is an N-type impurity semiconductor, i.e., an N-type doped conductive structure. Conversely, an impurity semiconductor obtained by doping with a trivalent impurity element is a P-type impurity semiconductor, i.e., a P-type doped conductive structure.

[0168] Based on the different doping concentrations of impurities, doped conductive structures are classified into heavily doped, moderately doped, and lightly doped conductive structures. A heavily doped conductive structure is a conductive structure where the impurity doping concentration is greater than or equal to a first concentration. For example, an N-type doped conductive structure with a doping concentration greater than or equal to the first concentration is an N-type heavily doped conductive structure, and a P-type doped conductive structure with a doping concentration greater than or equal to the first concentration is a P-type heavily doped conductive structure. A moderately doped conductive structure is a conductive structure where the impurity doping concentration is less than the first concentration but greater than a second concentration. For example, an N-type doped conductive structure with a doping concentration less than the first concentration but greater than the second concentration is an N-type moderately doped conductive structure, and a P-type doped conductive structure with a doping concentration less than the first concentration but greater than the second concentration is a P-type moderately doped conductive structure. A lightly doped conductive structure is a conductive structure where the impurity doping concentration is less than or equal to the second concentration. For example, an N-type doped conductive structure with a doping concentration less than or equal to the second concentration is an N-type lightly doped conductive structure, and a P-type doped conductive structure with a doping concentration less than or equal to the second concentration is a P-type lightly doped conductive structure. In addition, for ease of description, both medium-doped and lightly doped conductive structures are referred to as ordinary doped conductive structures. For example, both N-type medium-doped and N-type lightly doped conductive structures can be referred to as N-type ordinary doped conductive structures, and both P-type medium-doped and P-type lightly doped conductive structures can be referred to as P-type ordinary doped conductive structures.

[0169] The second concentration is less than the first concentration. In one possible implementation, the first concentration is 5*10^8. The second concentration can be set according to the application scenario; however, this application embodiment does not limit the second concentration.

[0170] If the first memory cell is close to the first end, the first end is coupled to a bit line contact, and the bit line contact is an N-type heavily doped conductive structure, the source contact of the memory string may be made of different materials. For example, the source contact may be an N-type heavily doped conductive structure or a P-type doped conductive structure (such as a P-type heavily doped conductive structure).

[0171] Based on the source contact portion made of different materials, Case 1 can be further extended to Case 1.1 and Case 1.2.

[0172] Case 1.1: The bit line contact coupled to the first end is an N-type heavily doped conductive structure, the source contact coupled to the memory string is an N-type heavily doped conductive structure, the first memory cell is close to the first end, and the second memory cell is far from the first end and close to the source contact.

[0173] Case 1.2: The bit line contact coupled to the first end is an N-type heavily doped conductive structure, the source contact coupled to the memory string is a P-type heavily doped conductive structure, the first memory cell is close to the first end, and the second memory cell is far from the first end and close to the source contact.

[0174] In one possible implementation, the memory string further includes at least one first select transistor located near the first end. For example, if the first end is coupled to a bitline contact, then the first select transistor is also the upper select transistor. If the first end is coupled to a source contact, then the first select transistor is also the lower select transistor.

[0175] For each of cases 1.1 and 1.2, by applying a first voltage to the bit line contact, the first select transistor of the memory string is controlled to generate gate-induced drain leakage (GIDL). GIDL generates electron-hole pairs between the gate and drain of the first select transistor. The hole in the electron-hole pair moves towards and enters the channel of the memory string. Here, the hole refers to the effect of losing an electron to a covalent bond, leaving a vacancy in the covalent bond.

[0176] For example, a first voltage is applied to the bit line connected to the bit line contact, and a first voltage is applied to the source line, so that the voltages at both ends of the channel of the memory string are the same, thereby preventing the channel of the memory string from being turned on. A fourth voltage is applied to the select line coupled to the first select transistor. The fourth voltage is less than the first voltage, and the voltage difference between the first voltage and the fourth voltage satisfies the voltage difference condition for band-to-band tunneling (B2B). The voltage difference formed between the gate and drain of the first select transistor causes B2B to occur between the gate and drain of the first select transistor, generating electron-hole pairs. The holes in the electron-hole pairs move towards the channel of the memory string and enter the channel of the memory string.

[0177] In one possible implementation, before the channel voltage of the memory string increases to the tenth voltage, an eleventh voltage is configured for the select line coupled to the first select transistor. The channel voltage of the memory string is the voltage of the channel of the memory string. The tenth voltage is less than the first voltage but greater than the fourth voltage, and the voltage difference between the tenth and fourth voltages is less than or equal to the fourth tunneling voltage, which is the minimum voltage required for the first select transistor to tunnel, i.e., the tunneling voltage of the first select transistor. The eleventh voltage is less than the first voltage, and the voltage difference between the first and eleventh voltages is less than the fourth tunneling voltage. Therefore, after the channel voltage increases to the first voltage, the voltage difference between the gate and channel of the first select transistor is less than the fourth tunneling voltage, preventing the threshold voltage of the first select transistor from drifting.

[0178] In one possible implementation, the memory string further includes at least one second select transistor located away from the first end. For example, if the first end is coupled to a bitline contact, the second select transistor is also a lower select transistor. If the first end is coupled to a source contact, the second select transistor is also an upper select transistor.

[0179] Furthermore, a sixth voltage is configured for the select line coupled to the second select transistor in the memory string. This sixth voltage is lower than the first voltage, and the voltage difference between the first voltage and the sixth voltage is less than the third tunneling voltage. The third tunneling voltage is the minimum voltage required for the second select transistor to tunnel, i.e., the tunneling voltage of the second select transistor. As holes move in the channel, the voltage of the channel of the second select transistor gradually reaches the first voltage, thereby generating a voltage difference between the channel and the gate of the second select transistor, i.e., the difference between the first voltage and the sixth voltage. Since this voltage difference is less than the third tunneling voltage, it is insufficient to generate a tunneling effect between the channel and the gate of the second select transistor, thus protecting the threshold voltage of the second select transistor from drifting.

[0180] It should be noted that if the first select transistor is an upper select transistor, the select line coupled to the first select transistor is DSL; if the first select transistor is a lower select transistor, the select line coupled to the first select transistor is SSL. If the second select transistor is an upper select transistor, the select line coupled to the second select transistor is DSL; if the second select transistor is a lower select transistor, the select line coupled to the second select transistor is SSL. Optionally, the values ​​of the sixth voltage and the eleventh voltage are both in the range of 10V to 25V, and the values ​​of the third tunneling voltage and the fourth tunneling voltage are in the range of 15V to 30V. The process of configuring the sixth voltage for the select line coupled to the second select transistor in the memory string is the same as the process of configuring the third voltage for the word line coupled to the second memory cell. For example, the sixth voltage is applied to the select line coupled to the second select transistor, or the select line coupled to the second select transistor is floated so that the voltage of the word line coupled to the second memory cell reaches the sixth voltage. The process of configuring an eleventh voltage for the select line coupled to the first select transistor in the memory string is similar to configuring a third voltage for the word line coupled to the second memory cell. For example, an eleventh voltage can be applied to the select line coupled to the first select transistor, or the select line coupled to the first select transistor can be floated so that the voltage of the word line coupled to the first memory cell reaches the eleventh voltage.

[0181] To further illustrate the voltage application to each device in the memory string during the data erasure process in Case 1.1, see [link to relevant documentation]. Figure 11 The diagram shown illustrates the voltage waveform during data erasure in scenario 1.1, as provided in an embodiment of this application. Figure 11As shown, the first memory cell, as the upper memory cell of the memory string, is located near the first end of the memory string, and the bit line contact coupled to the first end is an N-type heavily doped conductive structure. The second memory cell, as the lower memory cell of the memory string, is located away from the first end and near the source contact of the memory string. The source line contact is connected to both the source contact and the source line, wherein both the source contact and the source line contact are N-type heavily doped conductive structures (represented as "N+" in the figure).

[0182] During the data erasure process of the storage string, in the time period t1-t3, the voltages of BL and SL gradually increase from their respective initial voltages until they reach the first voltage, and remain at the first voltage in the time period t3-t4.

[0183] During the time interval t1-t2, the TSG acts as the first select transistor in the memory string, and its coupled select line maintains the fourth voltage. The voltage difference between the BL voltage and the select line voltage causes holes to be generated at the corresponding position of the TSG. At this time, the channel voltage is lower than the first voltage, so the holes move towards the lower voltage channel, causing the channel voltage to gradually increase. During the time interval t2-t3, the select line coupled to the TSG is floated. When the channel voltage increases, the voltage jump across the capacitor causes the select line voltage to increase. For example, the select line voltage coupled to the TSG gradually increases from the fourth voltage until it reaches the eleventh voltage. This ensures that the voltage difference between the gate and the channel of the TSG is less than the tunneling voltage of the TSG, thus preventing the threshold voltage of the TSG from drifting.

[0184] During the time period t2-t4, the word line coupled to the first memory cell maintains the second voltage. As the channel voltage increases, when the voltage difference between the channel voltage and the second voltage is greater than the tunneling voltage of the first memory cell, the data stored in the first memory cell can be erased.

[0185] During the time period t1-t3, the word line coupled to the second memory cell is floated. In this floating state, when the channel voltage increases, the voltage jump across the capacitor causes the word line voltage to increase. For example, the word line voltage gradually increases from its initial value until it reaches a third voltage. As the word line voltage increases, the voltage difference between the channel voltage and the word line voltage becomes less than the tunneling voltage of the second memory cell, thus preventing the data stored in the second memory cell from being erased.

[0186] During the time interval t2-t3, similar to the floating of the select line coupled to the TSG, the BSG, as the second select transistor of the memory string, also has its coupled select line floating. This causes the voltage of the select line to gradually increase from its initial voltage until it reaches the sixth voltage. As the select line voltage increases, the voltage difference between the channel voltage and the select line voltage is less than the tunneling voltage of the BSG, thus preventing the threshold voltage of the BSG from drifting.

[0187] To further illustrate the voltage application to each device in the memory string during the data erasure process in Case 1.2, see [link to Case 1.2]. Figure 12 The diagram shown illustrates the voltage waveform during data erasure in scenario 1.2, as provided in an embodiment of this application. Figure 12 As shown, the first memory cell, as the upper memory cell of the memory string, is located near the first end of the memory string, and the bit line contact coupled to the first end is an N-type heavily doped conductive structure. The second memory cell, as the lower memory cell of the memory string, is located away from the first end and near the source contact of the memory string. The source contact is connected to both the source contact and the source line, wherein the source contact is a P-type heavily doped conductive structure (represented as "P+" in the figure), and the source contact is an N-type heavily doped conductive structure.

[0188] During the data erasure process of the storage string, in the time period t1-t3, the voltages of BL and SL gradually increase from their respective initial voltages until they reach the first voltage, and remain at the first voltage in the time period t3-t4.

[0189] During the time interval t1-t2, the TSG acts as the first select transistor in the memory string, and its coupled select line maintains the fourth voltage. The voltage difference between the BL voltage and the select line voltage causes holes to be generated at the corresponding position of the TSG. At this time, the channel voltage is lower than the first voltage, so the holes move towards the lower voltage channel, causing the channel voltage to gradually increase. During the time interval t2-t3, the select line coupled to the TSG is floated. When the channel voltage increases, the voltage jump across the capacitor causes the select line voltage to increase. For example, the select line voltage coupled to the TSG gradually increases from the fourth voltage until it reaches the eleventh voltage. This ensures that the voltage difference between the gate and the channel of the TSG is less than the tunneling voltage of the TSG, thus preventing the threshold voltage of the TSG from drifting.

[0190] During the time period t2-t4, the word line coupled to the first memory cell maintains the second voltage. As the channel voltage increases, when the voltage difference between the channel voltage and the second voltage is greater than the tunneling voltage of the first memory cell, the data stored in the first memory cell can be erased.

[0191] During the time period t1-t3, the word line coupled to the second memory cell is floated. In this floating state, when the channel voltage increases, the voltage jump across the capacitor causes the word line voltage to increase. For example, the word line voltage gradually increases from its initial value until it reaches a third voltage. As the word line voltage increases, the voltage difference between the channel voltage and the word line voltage becomes less than the tunneling voltage of the second memory cell, thus preventing the data stored in the second memory cell from being erased.

[0192] During the time interval t2-t3, similar to the floating of the select line coupled to the TSG, the BSG, as the second select transistor of the memory string, also has its coupled select line floating. This causes the voltage of the select line to gradually increase from its initial voltage until it reaches the sixth voltage. As the select line voltage increases, the voltage difference between the channel voltage and the select line voltage is less than the tunneling voltage of the BSG, thus preventing the threshold voltage of the BSG from drifting.

[0193] The process of controlling the movement of holes from the first end to the second end of the storage string varies depending on the specific case of the storage string. Here, taking case 2 as an example, the process of controlling the movement of holes from the first end to the second end of the storage string is described as follows:

[0194] In case 2, the first storage cell in the storage string is close to the first end, the second storage cell is far from the first end, and the first end is coupled to the source contact portion corresponding to the storage string, controlling the holes to move from the first end of the storage string to the second end of the storage string.

[0195] In different implementations, the source contact is made of different materials. For example, the source contact is an N-type heavily doped conductive structure or a P-type heavily doped conductive structure. Based on the source contact with different materials, Case 2 can be further extended to Case 2.1 and Case 2.2 as follows.

[0196] Case 2.1: The first storage cell in the storage string is close to the first end, the second storage cell is far from the first end, the first end is coupled to the source contact corresponding to the storage string, and the source contact is an N-type heavily doped conductive structure.

[0197] Case 2.2: The first storage cell in the storage string is close to the first end, the second storage cell is far from the first end, the first end is coupled to the source contact corresponding to the storage string, and the source contact is a P-type heavily doped conductive structure.

[0198] For source contact portions made of different materials in cases 2.1 and 2.2, the way in which control holes move from the first end to the second end of the memory string is different. The following is a description of the process of controlling holes moving from the first end coupled to the source contact portion to the second end of the memory string for cases 2.1 and 2.2 respectively:

[0199] For case 2.1, the bit line contacts coupled to the memory string may also be made of different materials. For example, the bit line contacts may be N-type heavily doped conductive structures or N-type ordinary doped conductive structures. Based on the different materials of the bit line contacts, case 2.1 can be further extended to the following cases 2.1.1 and 2.1.2.

[0200] Case 2.1.1: The bit line contact coupled to the memory string is an N-type heavily doped conductive structure, the source contact coupled to the first end is an N-type heavily doped conductive structure, the first memory cell is close to the first end, and the second memory cell is far from the first end and close to the bit line contact.

[0201] Case 2.1.2: The bit line contact coupled to the memory string is an N-type ordinary doped conductive structure, the source contact coupled to the first end is an N-type heavily doped conductive structure, the first memory cell is close to the first end, and the second memory cell is far from the first end and close to the bit line contact.

[0202] For each of cases 2.1.1 and 2.1.2, in one possible implementation, by applying a first voltage to the source contact, the first select transistor of the memory string is controlled to generate electron-hole pairs, in which holes move toward the channel of the memory string and enter the channel of the memory string.

[0203] For example, a first voltage is applied to the bit line connected to the bit line contact, and a first voltage is applied to the source line, so that the voltages at both ends of the channel of the memory string are the same, thereby preventing the channel of the memory string from conducting. A second voltage is applied to the word line coupled to the first select transistor, so that a voltage difference between the first voltage and the second voltage is formed between the source and the gate of the first select transistor. This voltage difference causes band-to-band tunneling between the gate and the source of the first select transistor, generating GIDL. Holes in the GIDL move towards the channel of the memory string and enter the channel of the memory string.

[0204] Additionally, before the channel voltage of the memory string increases to the tenth voltage, an eleventh voltage is configured for the select line coupled to the first select transistor to prevent the threshold voltage of the first select transistor from drifting as the channel voltage increases. A sixth voltage is configured for the select line coupled to the second select transistor in the memory string to prevent the threshold voltage of the second select transistor from drifting as the channel voltage increases.

[0205] To further illustrate the voltage application to each device in the memory string during the data erasure process in Case 2.1.1, please refer to [link to relevant documentation]. Figure 13 The diagram illustrates a voltage waveform during the data erasure process in scenario 2.1.1, as provided in an embodiment of this application. Figure 13As shown, the second memory cell, as the upper memory cell of the memory string, is located away from the first end of the memory string and close to the bit line contact coupled to the memory string. This bit line contact is an N-type heavily doped conductive structure. The first memory cell, as the lower memory cell of the memory string, is located close to the first end, and the first end is coupled to the source contact. The source line contact is connected to both the source contact and the source line, wherein both the source contact and the source line contact are N-type heavily doped conductive structures.

[0206] During the data erasure process of the storage string, in the time period t1-t3, the voltages of BL and SL gradually increase from their respective initial voltages until they reach the first voltage, and remain at the first voltage in the time period t3-t4.

[0207] During the time interval t1-t2, the BSG acts as the first select transistor in the memory string, and its coupled select line maintains the fourth voltage. The voltage difference between the source line and the select line causes holes to be generated at the corresponding location of the BSG. At this time, the channel voltage is lower than the first voltage, so the holes move towards the lower-voltage channel, causing the channel voltage to gradually increase. During the time interval t2-t3, the select line coupled to the BSG is floated. When the channel voltage increases, the voltage jump across the capacitor causes the select voltage to increase. For example, the select line coupled to the BSG gradually increases from the fourth voltage until it reaches the eleventh voltage. This ensures that the voltage difference between the gate and the channel of the BSG is less than the tunneling voltage of the BSG, thus preventing the threshold voltage of the BSG from drifting.

[0208] During the time period t2-t4, the word line coupled to the first memory cell maintains the second voltage. As the channel voltage increases, when the voltage difference between the channel voltage and the second voltage is greater than the tunneling voltage of the first memory cell, the data stored in the first memory cell can be erased.

[0209] During the time period t1-t3, the word line coupled to the second memory cell is floated. In this floating state, when the channel voltage increases, the voltage jump across the capacitor causes the word line voltage to increase. For example, the word line voltage gradually increases from its initial value until it reaches a third voltage. As the word line voltage increases, the voltage difference between the channel voltage and the word line voltage becomes less than the tunneling voltage of the second memory cell, thus preventing the data stored in the second memory cell from being erased.

[0210] During the time interval t2-t3, similar to the floating of the select line coupled to the BSG, the TSG, as the second select transistor of the memory string, also has its coupled select line floating. This causes the voltage of the select line to gradually increase from its initial voltage until it reaches the sixth voltage. As the select line voltage increases, the voltage difference between the channel voltage and the select line voltage is less than the tunneling voltage of the TSG, thus preventing the threshold voltage of the TSG from drifting.

[0211] To further illustrate the voltage application to each device in the memory string during the data erasure process in scenario 2.1.2, see [link to relevant documentation]. Figure 14 The diagram shown illustrates the voltage waveform during data erasure in scenario 2.1.2, as provided in an embodiment of this application. Figure 14 As shown, the second memory cell, as the upper-level memory cell of the memory string, is located near the bit line contact of the memory string. This bit line contact is an N-type ordinary doped conductive structure (represented by "N" in the figure). The first memory cell, as the lower-level memory cell of the memory string, is located near the first end of the memory string, and the source contact coupled to this first end is an N-type heavily doped conductive structure. The source line contact is connected to both the source contact and the source line, wherein the source line contact is an N-type heavily doped conductive structure.

[0212] During the data erasure process of the storage string, in the time period t1-t3, the voltages of BL and SL gradually increase from their respective initial voltages until they reach the first voltage, and remain at the first voltage in the time period t3-t4.

[0213] During the time interval t1-t2, the BSG acts as the first select transistor in the memory string, and its coupled select line maintains the fourth voltage. The voltage difference between the source line and the select line causes holes to be generated at the corresponding location of the BSG. At this time, the channel voltage is lower than the first voltage, so the holes move towards the lower-voltage channel, causing the channel voltage to gradually increase. During the time interval t2-t3, the select line coupled to the BSG is floated. When the channel voltage increases, the voltage jump across the capacitor causes the select voltage to increase. For example, the select line coupled to the BSG gradually increases from the fourth voltage until it reaches the eleventh voltage. This ensures that the voltage difference between the gate and the channel of the BSG is less than the tunneling voltage of the BSG, thus preventing the threshold voltage of the BSG from drifting.

[0214] During the time period t2-t4, the word line coupled to the first memory cell maintains the second voltage. As the channel voltage increases, when the voltage difference between the channel voltage and the second voltage is greater than the tunneling voltage of the first memory cell, the data stored in the first memory cell can be erased.

[0215] During the time period t1-t3, the word line coupled to the second memory cell is floated. In this floating state, when the channel voltage increases, the voltage jump across the capacitor causes the word line voltage to increase. For example, the word line voltage gradually increases from its initial value until it reaches a third voltage. As the word line voltage increases, the voltage difference between the channel voltage and the word line voltage becomes less than the tunneling voltage of the second memory cell, thus preventing the data stored in the second memory cell from being erased.

[0216] During the time interval t2-t3, similar to the floating of the select line coupled to the BSG, the TSG, acting as the second select transistor of the memory string, also has its coupled select line floating. This causes the voltage of the select line to gradually increase from its initial voltage until it reaches a sixth voltage, which is maintained during the time interval t3-t4. As the select line voltage increases, the voltage difference between the channel voltage and the select line voltage is less than the tunneling voltage of the TSG, thus preventing the threshold voltage of the TSG from drifting.

[0217] The above describes the process of generating holes at the position corresponding to the first select transistor in conjunction with situation 2.1, enabling the holes to move into the channel of the memory string. In conjunction with situation 2.2, the process of controlling the holes to move from the first end to the second end of the memory string is described as follows:

[0218] Regarding case 2.2, in one possible implementation, when the first end is coupled to the source contact corresponding to the memory string, and the source contact is a P-type heavily doped conductive structure, the bit line contacts coupled to the memory string may also be made of different materials, such as an N-type ordinary doped conductive structure or an N-type heavily doped conductive structure. Based on the different materials of the bit line contacts, case 2.2 can be further extended to cases 2.2.1 and 2.2.2 as follows.

[0219] Case 2.2.1: The source contact coupled to the first end is a P-type heavily doped conductive structure, the bit line contact coupled to the memory string is an N-type ordinary doped conductive structure, the first memory cell is close to the first end, and the second memory cell is far from the first end and close to the bit line contact.

[0220] Case 2.2.2: The substrate coupled to the first end is a P-type heavily doped conductive structure, the bit line contact coupled to the memory string is an N-type heavily doped conductive structure, the first memory cell is close to the first end, and the second memory cell is far from the first end and close to the bit line contact.

[0221] For each of cases 2.2.1 and 2.2.2, in one possible implementation, the source contact is controlled to generate holes, and the holes generated by the source contact move toward the channel of the memory string and enter the channel of the memory string.

[0222] For example, a first voltage is applied to the bit line connected to the bit line contact, and a first voltage is applied to the source line, so that the voltages at both ends of the channel of the memory string are the same, thereby preventing the channel of the memory string from conducting. The first voltage of the source line is applied to the source contact portion through the source line contact, continuously outputting a positive potential to the substrate. Since the source contact portion is a P-type heavily doped conductive structure, the continuously input positive potential causes holes to be generated in the source contact portion. The holes generated in the source contact portion move towards the channel of the memory string and enter the channel of the memory string.

[0223] In addition, a fifth voltage is applied to the selection line coupled to the first selection transistor of the memory string, wherein the fifth voltage is less than the first voltage, so that the holes generated at the source contact move toward the channel of the first selection transistor and can move toward the channel of the second selection transistor through the channel of the first selection transistor.

[0224] Before the channel voltage of the memory string increases to the tenth voltage, an eleventh voltage is configured for the select line coupled to the first select transistor to prevent the threshold voltage of the first select transistor from drifting as the channel voltage increases. A sixth voltage is configured for the select line coupled to the second select transistor in the memory string to prevent the threshold voltage of the second select transistor from drifting as the channel voltage increases.

[0225] To further illustrate the voltage application to each device in the memory string during the data erasure process in Case 2.2.1, please refer to [link to relevant documentation]. Figure 15 The diagram shown illustrates the voltage waveform during data erasure under scenario 2.2.1, as provided in an embodiment of this application. Figure 15 As shown, the second memory cell, as the upper memory cell of the memory string, is located away from the first end and close to the bit line contact coupled to the memory string. This bit line contact is an N-type ordinary doped conductive structure. The first memory cell, as the lower memory cell of the memory string, is located close to the first end, and the source contact coupled to the first end is a P-type heavily doped conductive structure. The source line contact is connected to both the source contact and the source line. The source line contact is an N-type heavily doped conductive structure.

[0226] During the data erasure process of the memory string, in the time period t1-t3, the voltages of BL and SL gradually increase from their initial voltages until they reach a first voltage, and then remain at the first voltage in the time period t3-t4. The voltage of SL is applied to the source contact through the source line contact, and as the voltage at the source contact increases, holes are generated in the source contact.

[0227] During the time interval t1-t2, the BSG acts as the first select transistor in the memory string, and its coupled select line maintains a fifth voltage. This fifth voltage is low. As the voltage at the source contact increases, the voltage difference between the source contact voltage and the fifth voltage causes holes generated at the source contact to move towards the BSG channel and enter the memory string channel. Since the channel voltage is lower than the first voltage at this time, holes move towards the lower-voltage channel, causing the channel voltage to gradually increase. During the time interval t2-t3, the select line coupled to the BSG is floated. In this floating state, when the channel voltage increases, the voltage jump across the capacitor causes the select voltage to increase. For example, the select line coupled to the BSG gradually increases from the fourth voltage up to the eleventh voltage. This ensures that the voltage difference between the gate and channel of the BSG is less than the tunneling voltage of the BSG, preventing the threshold voltage of the BSG from drifting.

[0228] During the time period t2-t4, the word line coupled to the first memory cell maintains the second voltage. As the channel voltage increases, when the voltage difference between the channel voltage and the second voltage is greater than the tunneling voltage of the first memory cell, the data stored in the first memory cell can be erased.

[0229] During the time period t1-t3, the word line coupled to the second memory cell is floated. In this floating state, when the channel voltage increases, the voltage jump across the capacitor causes the word line voltage to increase. For example, the word line voltage gradually increases from its initial value until it reaches a third voltage. As the word line voltage increases, the voltage difference between the channel voltage and the word line voltage becomes less than the tunneling voltage of the second memory cell, thus preventing the data stored in the second memory cell from being erased.

[0230] During the time interval t2-t3, similar to the floating of the select line coupled to the BSG, the TSG, as the second select transistor of the memory string, also has its coupled select line floating. This causes the voltage of the select line to gradually increase from its initial voltage until it reaches the sixth voltage. As the select line voltage increases, the voltage difference between the channel voltage and the select line voltage is less than the tunneling voltage of the TSG, thus preventing the threshold voltage of the TSG from drifting.

[0231] To further illustrate the voltage application to each device in the memory string during the data erasure process in Case 2.2.2, please refer to [link to relevant documentation]. Figure 16 The diagram shown illustrates the voltage waveform during data erasure under scenario 2.2.2, as provided in an embodiment of this application. Figure 16As shown, the second memory cell, as the upper memory cell of the memory string, is located away from the first end and close to the bit line contact coupled to the memory string. This bit line contact is an N-type heavily doped conductive structure. The first memory cell, as the lower memory cell of the second memory string, is located close to the first end, and the source contact coupled to the first end is a P-type heavily doped conductive structure. The source line contact is connected to both the source contact and the source line, and the source line contact is an N-type heavily doped conductive structure.

[0232] During the data erasure process of the memory string, in the time period t1-t3, the voltages of BL and SL gradually increase from their initial voltages until they reach a first voltage, and then remain at the first voltage in the time period t3-t4. The voltage of SL is applied to the source contact through the source line contact, and as the voltage at the source contact increases, holes are generated in the source contact.

[0233] During the time interval t1-t2, the BSG acts as the first select transistor in the memory string, and its coupled select line maintains a fifth voltage. This fifth voltage is low. As the voltage at the source contact increases, the voltage difference between the source contact voltage and the fifth voltage causes holes generated at the source contact to move towards the BSG channel and enter the memory string channel. Since the channel voltage is lower than the first voltage at this time, holes move towards the lower-voltage channel, causing the channel voltage to gradually increase. During the time interval t2-t3, the select line coupled to the BSG is floated. In this floating state, when the channel voltage increases, the voltage jump across the capacitor causes the select voltage to increase. For example, the select line coupled to the BSG gradually increases from the fourth voltage up to the eleventh voltage. This ensures that the voltage difference between the gate and channel of the BSG is less than the tunneling voltage of the BSG, preventing the threshold voltage of the BSG from drifting.

[0234] During the time period t2-t4, the word line coupled to the first memory cell maintains the second voltage. As the channel voltage increases, when the voltage difference between the channel voltage and the second voltage is greater than the tunneling voltage of the first memory cell, the data stored in the first memory cell can be erased.

[0235] During the time period t1-t3, the word line coupled to the second memory cell is floated. In this floating state, when the channel voltage increases, the voltage jump across the capacitor causes the word line voltage to increase. For example, the word line voltage gradually increases from its initial value until it reaches a third voltage. As the word line voltage increases, the voltage difference between the channel voltage and the word line voltage becomes less than the tunneling voltage of the second memory cell, thus preventing the data stored in the second memory cell from being erased.

[0236] During the time interval t2-t3, similar to the floating of the select line coupled to the BSG, the TSG, as the second select transistor of the memory string, also has its coupled select line floating. This causes the voltage of the select line to gradually increase from its initial voltage until it reaches the sixth voltage. As the select line voltage increases, the voltage difference between the channel voltage and the select line voltage is less than the tunneling voltage of the TSG, thus preventing the threshold voltage of the TSG from drifting.

[0237] The above describes the process of controlling the movement of holes into the channel of the memory string from the end closest to the first memory cell. In another possible implementation, the movement of holes into the channel of the memory string is controlled from the end furthest from the first memory cell. See also... Figure 17 The flowchart shown is an embodiment of another method for operating a storage device provided in this application. This method is executed by peripheral circuitry within the storage device.

[0238] 1701. Apply a first voltage to the first end of the storage string.

[0239] A hole is generated at the first end of the memory string by applying a first voltage, for example by generating a hole at the source contact or at the corresponding position of the first select transistor. This process has been described above and will not be repeated here.

[0240] In addition, a first voltage is applied to the second end of the memory string, so that the voltages at both ends of the channel of the memory string are the same, so as to prevent the channel of the memory string from being turned on.

[0241] 1702. If the first memory cell is far from the first end of the memory string and the second memory cell is close to the first end, before the channel voltage of the memory string reaches the seventh voltage, an eighth voltage is applied to the word line coupled to the second memory cell, the seventh voltage being greater than the eighth voltage and less than or equal to the first voltage, and the voltage difference between the seventh voltage and the eighth voltage being less than the second tunneling voltage.

[0242] The seventh voltage is a voltage that occurs before the channel voltage of the memory string reaches the first voltage during the movement of holes into the channel of the memory string. Therefore, the seventh voltage is less than the first voltage. Furthermore, the seventh voltage is greater than the eighth voltage, creating a voltage difference between the channel and gate of the second memory cell. This voltage difference is less than the tunneling voltage of the second memory cell, protecting the data stored in the second memory cell from erasure. The eighth voltage is also less than the first voltage at the first terminal, causing holes to move from the first terminal towards the channel of the second memory cell and enter the channel. The value of the eighth voltage ranges from 0V to 5V, optionally from 0V to 3V. For example, the third gate voltage is 0V, 1V, or 2V. Optionally, the third gate voltage is equal to the first gate voltage.

[0243] An eighth voltage, which is less than the voltage at the first end, is applied to the word line coupled to the second memory cell, so that holes from the first end, after entering the channel of the memory string, move toward the channel of the second memory cell which is at a lower potential, and enter the channel of the first memory cell through the channel of the second memory cell.

[0244] When a hole enters the channel of the memory string and moves within it, the voltage across the channel gradually increases, eventually reaching a first voltage. Before the channel voltage reaches a seventh voltage, an eighth voltage is continuously applied to the word line coupled to the second memory cell. This seventh voltage is greater than the eighth voltage, ensuring that the voltage difference between the channel and the gate of the second memory cell is less than the tunneling voltage of the second memory cell, thereby protecting the data stored in the second memory cell from erasure.

[0245] 1703. After the channel voltage of the memory string reaches the seventh voltage, a third voltage is configured for the word line coupled to the second memory cell, the third voltage being lower than the first voltage, and the voltage difference between the first voltage and the third voltage being less than the second tunneling voltage.

[0246] As the channel voltage increases, when the channel voltage reaches the seventh voltage, a third voltage is configured for the word line coupled to the second memory cell, so that the voltage difference formed between the channel and the gate of the second memory cell is less than that of the tunneling cell of the second memory cell, so as to prevent the data stored in the second memory cell from being erased.

[0247] The process of configuring the second voltage for the word line coupled to the second memory cell is described in step 903 above and will not be repeated here.

[0248] 1704. Apply a second voltage to the word line coupled to the first memory cell, the second voltage being less than the first voltage, and the voltage difference between the first voltage and the second voltage being greater than or equal to the first tunneling voltage.

[0249] This step 1704 is the same as step 902 above. Therefore, this embodiment of the application will not repeat step 1704.

[0250] Additionally, before the channel voltage of the memory string increases to the tenth voltage, an eleventh voltage is configured for the select line coupled to the first select transistor to prevent the threshold voltage of the first select transistor from drifting as the channel voltage increases. A sixth voltage is configured for the select line coupled to the second select transistor in the memory string to prevent the threshold voltage of the second select transistor from drifting as the channel voltage increases.

[0251] It should be noted that the execution order of steps 1701, 1702, and 1704 is not fixed. For example, steps 1701, 1702, and 1704 can be executed simultaneously, or step 901 can be executed first, followed by steps 1702 and 1704 simultaneously. Alternatively, step 1704 can be executed first, followed by step 1702, and then step 1701. In this embodiment, the execution order of steps 1701, 1702, and 1704 is not limited.

[0252] To facilitate understanding of steps 1701-1304, let's take case 3 as an example: the first memory cell is far from the first end of the memory string, the second memory cell is close to the first end, the source contact of the first end is a heavily doped P-type conductive structure, and the bit line contact of the memory string is a normally doped N-type conductive structure.

[0253] In case 3, the bit line contacts coupled to the memory string are N-type ordinary doped conductive structures, and the upper select transistor cannot be used. When using GIDL for data erasure, holes can be generated at the source contact. After the holes generated at the source contact enter the channel of the memory string, they first move to the channel of the second memory cell, and then move from the channel of the second memory cell to the channel of the first memory cell.

[0254] To further illustrate scenario 3, the voltage applied to each device in the memory string during the data erasure process, please refer to [reference needed]. Figure 18 The diagram shown illustrates the voltage waveform during data erasure in scenario 3, as provided in an embodiment of this application. Figure 18As shown, the first memory cell, as the upper memory cell of the memory string, is located away from the first end of the memory string and close to the bit line contact coupled to the memory string. This bit line contact is an N-type ordinary doped conductive structure. The second memory cell, as the lower memory cell of the memory string, is located close to the first end, and the source contact coupled to the first end is a P-type heavily doped conductive structure. The source line contact is connected to both the source contact and the source line, wherein the source line contact is an N-type heavily doped conductive structure.

[0255] During the data erasure process of the memory string, in the time period t1-t3, the voltages of BL and SL gradually increase from their initial voltages until they reach a first voltage, and then remain at the first voltage in the time period t3-t4. The voltage of SL is applied to the source contact through the source line contact, and as the voltage at the source contact increases, holes are generated in the source contact.

[0256] During the time interval t1-t2, the BSG acts as the first select transistor in the memory string, and its coupled select line maintains a fifth voltage. This fifth voltage is low. As the voltage at the source contact increases, the voltage difference between the source contact voltage and the fifth voltage causes holes generated at the source contact to move towards the BSG channel and enter the memory string channel. Since the channel voltage is lower than the first voltage at this time, holes move towards the lower-voltage channel, causing the channel voltage to gradually increase. During the time interval t2-t3, the select line coupled to the BSG is floated. In this floating state, when the channel voltage increases, the voltage jump across the capacitor causes the select voltage to increase. For example, the select line coupled to the BSG gradually increases from the fourth voltage up to the eleventh voltage. This ensures that the voltage difference between the gate and channel of the BSG is less than the tunneling voltage of the BSG, preventing the threshold voltage of the BSG from drifting.

[0257] During the time interval t1-t2, the word line coupled to the second memory cell maintains an eighth voltage, which is lower than the first voltage. This allows holes generated at the source contact to move through the BSG channel towards the channel of the second memory cell, and then through the channel of the second memory cell towards the channel of the first memory cell. During the time interval t2-t3, the word line coupled to the second memory cell is floated. In this floating state, when the channel voltage increases, the voltage jump across the capacitor causes the word line voltage to increase. For example, the word line voltage gradually increases from its initial voltage until it reaches the third voltage. As the word line voltage increases, the voltage difference between the channel voltage and the word line voltage becomes less than the tunneling voltage of the second memory cell, thus preventing the data stored in the second memory cell from being erased.

[0258] During the time period t2-t4, the word line coupled to the first memory cell maintains the second voltage. As the channel voltage increases, when the voltage difference between the channel voltage and the second voltage is greater than the tunneling voltage of the first memory cell, the data stored in the first memory cell can be erased.

[0259] During the time interval t2-t3, similar to the floating of the select line coupled to the BSG, the TSG, as the second select transistor of the memory string, also has its coupled select line floating. This causes the voltage of the select line to gradually increase from its initial voltage until it reaches the sixth voltage. As the select line voltage increases, the voltage difference between the channel voltage and the select line voltage is less than the tunneling voltage of the TSG, thus preventing the threshold voltage of the TSG from drifting.

[0260] The method provided in this application, during the erasure of a memory block, applies a first voltage to the first end of the memory string and applies a second voltage less than the first voltage to the word line coupled to the first memory cell of the memory string. Since the voltage difference between the first and second voltages is greater than or equal to the tunneling voltage of the first memory cell, invalid data stored therein can be erased. Furthermore, a third voltage less than the first voltage is applied to the word line coupled to the second memory cell of the memory string. Since the voltage difference between the first and third voltages is less than the tunneling voltage of the second memory cell, valid data stored therein can be protected from erasure, thus eliminating the need to migrate valid data, saving time spent migrating valid data back and forth, and improving the erasure efficiency of the memory block. Moreover, by controlling holes to move from the end of the second memory cell closest to the memory cell in the memory string towards the channel of the memory string, the channel voltage is raised. Before the channel voltage reaches a seventh voltage, an eighth voltage is applied to the word line coupled to the second memory cell, allowing the holes entering the channel to move to the channel of the first memory cell to erase the data stored in the first memory cell. When the channel voltage reaches the seventh voltage, a third voltage is configured for the word line coupled to the second memory cell to prevent the data stored in the second memory cell from being erased.

[0261] It should be noted that, since the first and second memory cells within each memory string of this memory block are arranged identically, and the memory strings of the memory block share the same source line, applying a first voltage to the source line is equivalent to applying the same voltage to the end of each memory string coupled to the source line within the memory block. The first voltage is then applied to the bit lines corresponding to each memory string within the memory block. By applying voltage to the word lines coupled to each memory cell in the memory string and the select lines coupled to each select transistor, the data stored in the first memory cell of each memory string in the memory block can be erased, and the data stored in the second memory cell of each memory string can be protected from erasure.

[0262] In addition to the two cases of storage string 1001 and storage string 1002 described above, there are other possible distributions of the storage string. When the storage string is distributed in other possible ways, the data can still be erased based on the above-described operation method for the storage device.

[0263] Other possible distribution scenarios include, for example Figure 10 The storage string can be any one of 1003-1005. The second storage cell in storage string 1003 is located in an adjacent layer and in the middle of storage string 1003. The first storage cell in storage string 1003 is divided into two parts: one part is located in an adjacent layer and close to the bit line contact coupled to storage string 1003, and the other part is located in an adjacent layer and close to the source contact coupled to storage string 1003.

[0264] The first storage cell in storage string 1004 is located in an adjacent layer and in the middle of storage string 1004. The second storage cell in storage string 1004 is divided into two parts: one part is located in an adjacent layer and is close to the bit line contact coupled to storage string 1004, and the other part is located in an adjacent layer and is close to the source contact coupled to storage string 1004.

[0265] The first and second storage units in storage string 1005 are located in adjacent layers. Of course, in addition to storage strings 1001-1005, storage strings may have other distribution methods. For example, a layer of first storage units may be distributed every two layers of second storage units, or the first and second storage units may be distributed alternately in the storage string. Here, the embodiments of this application do not limit the distribution of the first and second storage units in the storage string.

[0266] It should be understood that the phrase "some embodiments" mentioned throughout the specification means that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "in some embodiments" or "in other embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0267] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0268] The above description is merely an embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory device, comprising: The memory device includes: the memory array includes a memory string, the memory string includes a first memory cell and a second memory cell, the first memory cell is an upper layer memory cell, and the second memory cell is a lower layer memory cell; A plurality of word lines are respectively coupled to the memory string; A bit line is coupled to the memory string; The peripheral circuit is coupled to the bit line and the plurality of word lines, and is configured to: apply a first voltage to the bit line; during a period in which the first voltage is applied to the bit line, apply a second voltage to a word line to which the first memory cell is coupled, the second voltage being less than the first voltage; during the period in which the first voltage is applied to the bit line, float a word line to which the second memory cell is coupled.

2. The memory device of claim 1, wherein, The peripheral circuit is further configured to: float the word line to which the second memory cell is coupled when the voltage of the bit line begins to rise.

3. The memory device of claim 1, wherein, The peripheral circuit is further configured to: float the word line to which the second memory cell is coupled after the voltage of the bit line begins to rise.

4. The memory device of claim 1, wherein, The memory string further includes a first select transistor, the first select transistor being proximate to the bit line; the peripheral circuit is further configured to: during a first period in which the first voltage is applied to the bit line, apply a fourth voltage to a select line to which the first select transistor is coupled, the fourth voltage being less than the first voltage; during a second period in which the first voltage is applied to the bit line, float the select line to which the first select transistor is coupled, the second period being after the first period.

5. The memory device of claim 1, wherein, The memory string further includes a first select transistor, the first select transistor being proximate to the bit line; the peripheral circuit is further configured to: during a period in which the first voltage is applied to the bit line, float a select line to which the first select transistor is coupled.

6. The memory device of claim 1, wherein, The memory device further includes a source line coupled to the memory string, the memory string further includes a second select transistor, the second select transistor being proximate to the source line; the peripheral circuit is further configured to: during a period in which the first voltage is applied to the bit line, float a select line to which the second select transistor is coupled.

7. The memory device of claim 3, wherein: The memory device further includes a source line coupled to the memory string, the memory string further includes a second select transistor, the second select transistor being proximate to the source line; the peripheral circuit is further configured to: float the select line to which the second select transistor is coupled after the voltage of the bit line begins to rise.

8. The memory device of claim 7, wherein, The time at which the second memory cell begins to float is the same as the time at which the select line to which the second select transistor is coupled begins to float.

9. The memory device of claim 1, wherein, The first memory cell is proximate to the bit line, and the second memory cell is distal to the bit line.

10. A storage system, characterized by comprising: The memory device of any one of claims 1-9; a memory controller coupled to the memory device and configured to control the memory device.

11. A method of operating a memory device, comprising: The memory array includes a memory string, the memory string includes a first memory cell and a second memory cell, the first memory cell is a lower layer memory cell, and the second memory cell is an upper layer memory cell; A plurality of word lines are respectively coupled to the memory string; A source line is coupled to the memory string; the method includes: applying a first voltage to the source line; applying a second voltage to a word line coupled to the first memory cell for a period of time during which the first voltage is applied to the source line, the second voltage being less than the first voltage; floating a word line coupled to the second memory cell for a period of time during which the first voltage is applied to the source line.

12. The method of claim 11, wherein, floating a word line coupled to the second memory cell when the voltage of the source line begins to rise.

13. The method of claim 11, wherein, floating a word line coupled to the second memory cell after the voltage of the source line begins to rise.

14. The method of claim 11, wherein, the memory string further comprises a first select gate proximate to the source line; the method further comprises: applying a fourth voltage to a select line coupled to the first select gate for a first period of time during which the first voltage is applied to the source line, the fourth voltage being less than the first voltage; floating the select line coupled to the first select gate for a second period of time after the first period of time during which the first voltage is applied to the source line.

15. The method of claim 11, wherein, the memory string further comprises a first select gate proximate to the source line; the method further comprises: floating a select line coupled to the first select gate for a period of time during which the first voltage is applied to the source line.

16. The method of claim 11, wherein, the memory device further comprises a bit line coupled to the memory string, the memory string further comprises a second select gate proximate to the bit line; the method further comprises: floating a select line coupled to the second select gate for a period of time during which the first voltage is applied to the source line.

17. The method of claim 13, wherein, the memory device further comprises a bit line coupled to the memory string, the memory string further comprises a second select gate proximate to the bit line; the method further comprises: floating a select line coupled to the second select gate after the voltage of the source line begins to rise.

18. The method of claim 17, wherein, the method further comprises: applying a fifth voltage to a select line coupled to the second select gate before floating the select line coupled to the second select gate, the fifth voltage being less than the first voltage.

19. The method of claim 11, wherein, the second memory cell is proximate to the bit line, the first memory cell is distal to the bit line.

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