Selector-only memory and memory system

Abstract

The present disclosure provides a selector-only memory including a plurality of memory cells and a peripheral circuit coupled to the plurality of memory cells, the peripheral circuit configured to perform a plurality of program operations on a target memory cell to cause the target memory cell to store a plurality of bits of data, the programming operation comprises the following steps: applying a corresponding first programming voltage to a first conductive wire coupled to a target memory cell; applying a corresponding second programming voltage to the first conductive wire coupled to the target memory cell; the polarity of the first programming voltage is different from that of the second programming voltage.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and for example to a selector-only memory and memory system. Background Technology

[0002] To bridge the performance gap between Dynamic Random Access Memory (DRAM) and NAND flash memory, Storage Class Memory (SCM) has been proposed as a new storage medium technology. SCM is a non-volatile storage medium situated between DRAM and NAND flash memory, with access latency typically less than 1 microsecond. It holds promise for improving current computer architectures and applications, breaking through bottlenecks in computer system performance enhancement. Mainstream SCM media include Phase-Change Memory (PCM), Resistive Random Access Memory (ReRAM), and Magnetic Random Access Memory (MRAM). However, with the ever-increasing demands on computer system performance, memory devices, including SCM, and their systems still have significant room for improvement.

[0003] Currently, the proposed solution is to use SCM (Synchronous Memory) to bridge DRAM and SSD, aiming to improve the current storage architecture. SCM needs to achieve speeds significantly faster than NAND and good non-volatile characteristics. Among the emerging SCM storage technologies, phase-change memory is the most mature, with 3D XPoint being the most promising, offering advantages such as large capacity, high speed, non-volatility, and good cycle performance.

[0004] Recently, research on high-capacity non-volatile memory technologies aimed at mitigating the weaknesses of 3D XPoint memory has become active. This type of non-volatile memory is called "Selector Only Memory (SOM)," "Self-Selecting Memory (SSM)," or "Single-chalcogenide Xpoint (SXM)" technology. Major semiconductor memory companies such as Samsung Electronics, SK Hynix, and Micron are all conducting research and development on this technology. The difference between SOM and 3D XPoint memory (and similar 3D crossbar memories) is that SOM uses a crossbar structure where each memory cell consists of only one selector. SOM memory offers advantages such as simple structure, high scalability, fast SET / RESET speed, good cycle life, vertical stackability, and no write crosstalk caused by thermal effects. It is a promising non-volatile memory with significant advantages in areas such as Compute Express Link (CXL) and High Bandwidth Memory (HBM). Summary of the Invention

[0005] In view of the above, embodiments of this disclosure provide a selector-only memory and its operation method, as well as a memory system.

[0006] To achieve the above objectives, the technical solution of this disclosure embodiment is implemented as follows:

[0007] In a first aspect, embodiments of this disclosure provide a selector-only memory, the selector-only memory including a plurality of memory cells and peripheral circuitry coupled to the plurality of memory cells, the peripheral circuitry being configured to perform multiple programming operations on a target memory cell to cause the target memory cell to store multiple bits of data, the programming operations including:

[0008] A corresponding first programming voltage is applied to the first conductive line coupled to the target memory cell;

[0009] A corresponding second programming voltage is applied to the first conductive line coupled to the target memory cell; the first programming voltage and the second programming voltage have different polarities.

[0010] In one alternative implementation, the polarity of the first programming voltage applied in different programming operations is the same, the polarity of the second programming voltage applied in different programming operations is the same, and the magnitude of the first programming voltage applied in different programming operations is different, and / or the magnitude of the second programming voltage applied in different programming operations is different.

[0011] In one optional implementation, the polarity of the first programming voltage is negative, and the polarity of the second programming voltage is positive; the magnitude of the first programming voltage applied in different programming operations is the same, and the magnitude of the second programming voltage applied in the programming operations arranged in sequence in multiple programming operations is smaller than the magnitude of the second programming voltage applied in the programming operations arranged in sequence.

[0012] In one alternative implementation, the multiple second programming voltages applied in the sequentially arranged programming operations exhibit a step-like or linear increasing trend.

[0013] In one optional implementation, the polarity of the first programming voltage is negative, and the polarity of the second programming voltage is positive; the magnitude of the second programming voltage applied in different programming operations is the same, and the absolute value of the first programming voltage applied in the preceding programming operations is smaller than the absolute value of the first programming voltage applied in the subsequent programming operations.

[0014] In one optional implementation, the polarity of the first programming voltage is negative, and the polarity of the second programming voltage is positive; the absolute value of the first programming voltage applied in the sequentially preceding programming operation is smaller than the absolute value of the first programming voltage applied in the sequentially following programming operation, and the magnitude of the second programming voltage applied in the sequentially preceding programming operation is smaller than the magnitude of the second programming voltage applied in the sequentially following programming operation.

[0015] In one alternative implementation, the polarity of the first programming voltage applied in different programming operations is the same, the polarity of the second programming voltage applied in different programming operations is the same, the duration of the first programming voltage is different in different programming operations, and / or the duration of the second programming voltage is different in different programming operations.

[0016] In one alternative implementation, the duration of the first programming voltage in the sequentially preceding programming operation is less than the duration of the first programming voltage in the sequentially following programming operation; and / or, the duration of the second programming voltage in the sequentially preceding programming operation is less than the duration of the second programming voltage in the sequentially following programming operation.

[0017] In one optional embodiment, the storage unit includes a first electrode structure, a functional structure, and a second electrode structure stacked along a first direction; the first electrode structure includes a resistive layer, a conductive layer, and an isolation layer stacked sequentially along the first direction; the isolation layer is located between the conductive layer and the functional structure.

[0018] In a second aspect, embodiments of this disclosure provide a memory system, including:

[0019] At least one selector-only memory as described in any of the embodiments above;

[0020] A controller, which is coupled to the selector-only memory and configured to control the selector-only memory.

[0021] In the technical solution provided in this disclosure, the peripheral circuitry of the selector memory is configured to perform multiple programming operations on the target memory cell to enable the target memory cell to store multiple bits of data. Each programming operation includes applying a corresponding first programming voltage and a corresponding second programming voltage, wherein the polarities of the first programming voltage and the second programming voltage are different. This embodiment of the disclosure enables multi-bit storage of the memory cell through specific configuration of the peripheral circuitry, thereby effectively increasing the storage capacity of the selector memory. Attached Figure Description

[0022] Figure 1 Schematic diagram of the structure of the storage unit provided in the embodiments of this disclosure Figure 1 ;

[0023] Figure 2A A schematic diagram of the threshold voltage distribution of storage cells in the selector memory provided in this embodiment of the disclosure. Figure 1 ;

[0024] Figure 2B Schematic diagram 2 of the threshold voltage distribution of the memory cells in the selector memory provided in this embodiment of the present disclosure;

[0025] Figure 2C Schematic diagram three showing the threshold voltage distribution of memory cells in the selector memory provided in this embodiment of the disclosure;

[0026] Figure 3A A schematic diagram of the voltage applied in the operation method of the selector memory provided in this embodiment of the disclosure. Figure 1 ;

[0027] Figure 3B Schematic diagram 2 of the voltage applied in the operation method of the selector memory provided in this embodiment of the disclosure;

[0028] Figure 4A Schematic diagram three showing the voltage applied in the operation method of the selector memory provided in this embodiment of the disclosure;

[0029] Figure 4B Schematic diagram four of the voltage applied in the operation method of the selector memory provided in this embodiment of the disclosure;

[0030] Figure 5ASchematic diagram five showing the voltage applied in the operation method of the selector memory provided in this embodiment of the disclosure;

[0031] Figure 5B Schematic diagram six of the voltage applied in the operation method of the selector memory provided in this embodiment of the disclosure;

[0032] Figure 6A Schematic diagram seven of the voltage applied in the operation method of the selector memory provided in this embodiment of the disclosure;

[0033] Figure 6B A schematic diagram of the voltage applied in the operation method of the selector memory provided in this embodiment of the disclosure. Figure 8 ;

[0034] Figure 6C A schematic diagram of the voltage applied in the operation method of the selector memory provided in this embodiment of the disclosure. Figure 9 ;

[0035] Figure 6D A schematic diagram of the voltage applied in the operation method of the selector memory provided in this embodiment of the disclosure. Figure 10 ;

[0036] Figure 6E A schematic diagram of the voltage applied in the operation method of the selector memory provided in this embodiment of the disclosure. Figure 10 one;

[0037] Figure 6F A schematic diagram of the voltage applied in the operation method of the selector memory provided in this embodiment of the disclosure. Figure 10 two;

[0038] Figure 7A This is a schematic diagram illustrating the relationship between the programming voltage and the threshold voltage provided in an embodiment of the present disclosure;

[0039] Figure 7B This is a schematic diagram illustrating the relationship between the programming voltage duration and the threshold voltage provided in an embodiment of this disclosure;

[0040] Figure 7C This is a schematic diagram illustrating the relationship between the programming voltage magnitude, programming voltage duration, and threshold voltage provided in an embodiment of this disclosure;

[0041] Figure 8 Schematic diagram 2 of the structure of the storage unit provided in the embodiments of this disclosure;

[0042] Figure 9 Schematic diagram of the storage layer provided in the embodiments of this disclosure Figure 1 ;

[0043] Figure 10 Schematic diagram 2 of the storage layer structure provided in the embodiments of this disclosure;

[0044] Figure 11 Schematic diagram three of the structure of the storage unit provided in the embodiments of this disclosure;

[0045] Figure 12 This is a flowchart illustrating the operation method of the selector memory provided in an embodiment of this disclosure. Detailed Implementation

[0046] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0047] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0048] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0049] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0051] In some embodiments, such as Figure 1 As shown, the selector memory includes at least one storage unit 100, which includes a first electrode structure 101, a functional structure 200, and a second electrode structure 102 stacked along a first direction.

[0052] In this embodiment of the disclosure, the first direction can be the Z direction.

[0053] In this embodiment of the present disclosure, the first electrode structure 101 can be connected to a first conductive line, and the second electrode structure can be connected to a second conductive line. Here, the first conductive line can be one of a bit line and a word line, and the second conductive line can be the other of a bit line and a word line.

[0054] In this embodiment, the functional structure 200 can serve as a storage device. Specifically, different programming voltages can be applied to the functional structure 200 to create different threshold voltages. By applying a reset pulse (negative pulse) to the functional structure 200, the threshold voltage of the functional structure 200 can be made to fall within a first threshold voltage range. By applying a set pulse (positive pulse) to the functional structure 200, the threshold voltage of the functional structure 200 can be made to fall within a second threshold voltage range, and the minimum threshold voltage within the second threshold voltage range is greater than the maximum threshold voltage within the first threshold voltage range. Thus, the storage cell 100 can store one bit of data. Figure 2A As shown, each storage unit stores one of two logic states, 0 or 1, and different logic states correspond to different threshold voltage ranges.

[0055] To increase the storage density of the selector-only memory, a single memory cell 100 can store multiple bits of data, and different threshold voltages of the memory cell 100 can serve as different stored information. These multiple bits can include 2, 3, 4, or more bits. For example, ... Figure 2BAs shown, when a memory cell stores 2 bits of data, each memory cell in the selector memory can store one of four logic states: 00, 01, 10, and 11. Different logic states correspond to different threshold voltage ranges; for example... Figure 2C As shown, when a memory cell stores 3 bits of data, each memory cell in the selector memory can store one of eight logic states: 000, 001, 010, 011, 100, 101, 110, and 111. Different logic states correspond to different threshold voltage ranges.

[0056] This disclosure provides a selector-only memory, which includes a plurality of memory cells and peripheral circuitry coupled to the plurality of memory cells. The peripheral circuitry is configured to perform multiple programming operations on a target memory cell to store multiple bits of data in the target memory cell. The programming operations include: applying a corresponding first programming voltage to a first conductive line coupled to the target memory cell; applying a corresponding second programming voltage to the first conductive line coupled to the target memory cell; wherein the polarities of the first programming voltage and the second programming voltage are different.

[0057] The first conductive line here can be either a bit line or a word line. That is, the first programming voltage and the second programming voltage here can be applied to either the word line coupled to the target memory cell or the bit line coupled to the target memory cell.

[0058] The peripheral circuitry of the selector-only memory provided in this embodiment is configured to perform multiple programming operations on the target memory cell to enable the target memory cell to store multiple bits of data. Each programming operation includes applying a corresponding first programming voltage and a corresponding second programming voltage, wherein the polarities of the first programming voltage and the second programming voltage are different. This embodiment, through specific configuration of the peripheral circuitry, enables multi-bit storage of the memory cell, thereby effectively increasing the storage capacity of the selector-only memory.

[0059] The different polarities of the first programming voltage and the second programming voltage can include several cases, specifically: 1. The polarity of the first programming voltage is positive and the polarity of the second programming voltage is negative; 2. The polarity of the first programming voltage is negative and the polarity of the second programming voltage is positive.

[0060] In some embodiments, the polarity of the first programming voltage applied in different programming operations is the same, the polarity of the second programming voltage applied in different programming operations is the same, and the magnitude of the first programming voltage applied in different programming operations is different, and / or the magnitude of the second programming voltage applied in different programming operations is different.

[0061] The magnitudes of the first programming voltage applied in different programming operations are different, and / or the magnitudes of the second programming voltage applied in different programming operations are different, including several cases, specifically: 1. The magnitudes of the first programming voltage applied in different programming operations are the same, but the magnitudes of the second programming voltage applied in different programming operations are different; 2. The magnitudes of the first programming voltage applied in different programming operations are different, but the magnitudes of the second programming voltage applied in different programming operations are the same; 3. The magnitudes of the first programming voltage applied in different programming operations are different, and the magnitudes of the second programming voltage applied in different programming operations are also different.

[0062] In some embodiments, the polarity of the first programming voltage is negative, and the polarity of the second programming voltage is positive; the magnitude of the first programming voltage applied in different programming operations is the same, and the magnitude of the second programming voltage applied in the programming operations arranged in sequence in multiple programming operations is smaller than the magnitude of the second programming voltage applied in the programming operations arranged in sequence.

[0063] like Figure 3A As shown, taking three programming operations on the target memory cell as an example, the first programming operation applies a first programming voltage and a first programming voltage; the second programming operation applies a second first programming voltage and a second second programming voltage; and the third programming operation applies a third first programming voltage and a third second programming voltage. The polarity of the first programming voltage applied in each programming operation is negative, the polarity of the second programming voltage applied in each programming operation is positive, and the magnitude of the first programming voltage applied in each programming operation is equal, while the magnitude of the second programming voltage applied in each programming operation is different. The magnitude of the second programming voltage applied later is greater than the magnitude of the second programming voltage applied earlier.

[0064] In some embodiments, the multiple second programming voltages applied in the sequentially arranged programming operations exhibit a step-like increasing trend or a linear increasing trend.

[0065] In other embodiments, such as Figure 3B As shown, the polarity of the first programming voltage applied in different programming operations is positive, the polarity of the second programming voltage applied in different programming operations is negative, and the magnitude of the second programming voltage applied in different programming operations is equal, while the magnitude of the first programming voltage applied in different programming operations is different. The magnitude of the first programming voltage applied later is greater than the magnitude of the first programming voltage applied earlier.

[0066] In some embodiments, the polarity of the first programming voltage is negative, and the polarity of the second programming voltage is positive; the magnitude of the second programming voltage applied in different programming operations is the same, and the absolute value of the first programming voltage applied in the preceding programming operations in multiple programming operations is smaller than the absolute value of the first programming voltage applied in the subsequent programming operations.

[0067] like Figure 4A As shown, taking three programming operations on the target memory cell as an example, the polarity of the first programming voltage applied in each programming operation is negative, the polarity of the second programming voltage applied in each programming operation is positive, and the magnitude of the second programming voltage applied in each programming operation is equal. However, the magnitude of the first programming voltage applied in each programming operation is different. The absolute value of the first programming voltage applied later is greater than the absolute value of the first programming voltage applied earlier.

[0068] In other embodiments, such as Figure 4B As shown, the polarity of the first programming voltage applied in different programming operations is positive, the polarity of the second programming voltage applied in different programming operations is negative, and the magnitude of the first programming voltage applied in different programming operations is equal, while the magnitude of the second programming voltage applied in different programming operations is different. The absolute value of the second programming voltage applied later is greater than the absolute value of the second programming voltage applied earlier.

[0069] In some embodiments, such as Figure 5A As shown, the polarity of the first programming voltage is negative, and the polarity of the second programming voltage is positive; in multiple programming operations, the absolute value of the first programming voltage applied in the preceding programming operation is smaller than the absolute value of the first programming voltage applied in the subsequent programming operation, and the magnitude of the second programming voltage applied in the preceding programming operation is smaller than the magnitude of the second programming voltage applied in the subsequent programming operation.

[0070] In other embodiments, such as Figure 5B As shown, the polarity of the second programming voltage is negative, and the polarity of the first programming voltage is positive; in multiple programming operations, the absolute value of the second programming voltage applied in the preceding programming operation is smaller than the absolute value of the second programming voltage applied in the subsequent programming operation, and the magnitude of the first programming voltage applied in the preceding programming operation is smaller than the magnitude of the first programming voltage applied in the subsequent programming operation.

[0071] In some embodiments, the polarity of the first programming voltage applied in different programming operations is the same, the polarity of the second programming voltage applied in different programming operations is the same, the duration of the first programming voltage is different in different programming operations, and / or the duration of the second programming voltage is different in different programming operations.

[0072] Here, the duration of the first programming voltage differs in different programming operations; and / or, the duration of the second programming voltage differs in different programming operations, including various cases, specifically including: 1. such as Figure 6A As shown, the duration of the first programming voltage is the same in different programming operations, while the duration of the second programming voltage is different in different programming operations; II. As Figure 6B As shown, the duration of the first programming voltage differs in different programming operations, while the duration of the second programming voltage is the same in different programming operations; III. As Figure 6C As shown, the duration of the first programming voltage is different in different programming operations, and the duration of the second programming voltage is different in different programming operations.

[0073] In some embodiments, the polarity of the first programming voltage applied in different programming operations is the same, and the polarity of the second programming voltage applied in different programming operations is the same; the duration of the first programming voltage is different in different programming operations, and the magnitude of the first programming voltage is different in different programming operations; and / or, the duration of the second programming voltage is different in different programming operations, and the magnitude of the second programming voltage is different in different programming operations.

[0074] like Figure 6D As shown, the duration and magnitude of the first programming voltage are the same in different programming operations, while the duration and magnitude of the second programming voltage differ in different programming operations. Figure 6E As shown, the duration and magnitude of the first programming voltage differ in different programming operations, while the duration and magnitude of the second programming voltage are the same in different programming operations. Figure 6F As shown, the duration of the first programming voltage is different in different programming operations, and the magnitude of the first programming voltage is different in different programming operations. The duration of the second programming voltage is different in different programming operations, and the magnitude of the second programming voltage is different in different programming operations.

[0075] In some embodiments, the duration of the first programming voltage in a sequentially preceding programming operation is less than the duration of the first programming voltage in a sequentially following programming operation; and / or, the duration of the second programming voltage in a sequentially preceding programming operation is less than the duration of the second programming voltage in a sequentially following programming operation.

[0076] like Figure 6D As shown, the duration of the first programming voltage is the same in different programming operations, while the duration of the second programming voltage is different in different programming operations. Furthermore, in multiple programming operations, the duration of the second programming voltage in the earlier programming operations is shorter than the duration of the second programming voltage in the later programming operations. Figure 6E As shown, the duration of the first programming voltage differs in different programming operations, while the duration of the second programming voltage is the same in different programming operations. Furthermore, in multiple programming operations, the duration of the first programming voltage in the sequentially preceding programming operations is shorter than the duration of the first programming voltage in the sequentially following programming operations. Figure 6F As shown, the duration of the first programming voltage is different in different programming operations, the duration of the second programming voltage is different in different programming operations, and in multiple programming operations, the duration of the first programming voltage in the programming operations arranged in sequence is shorter than the duration of the first programming voltage in the programming operations arranged in sequence, and the duration of the second programming voltage in the programming operations arranged in sequence is shorter than the duration of the second programming voltage in the programming operations arranged in sequence.

[0077] It should be noted that, Figure 6A , Figure 6B , Figure 6C , Figure 6D , Figure 6E , Figure 6F The example provided only uses the case where the polarity of the first programming voltage is negative and the polarity of the second programming voltage is positive. The polarity of the first programming voltage can also be positive, and the polarity of the second programming voltage can also be negative.

[0078] Selector-only memory has two threshold voltage states: a high threshold voltage state (positive programming voltage polarity) and a low threshold voltage state (negative programming voltage polarity). These two states can be switched between each other using positive and negative programming voltages; these two programming voltages are bidirectional. For example... Figure 7A As shown, different programming voltages with positive polarity result in different threshold voltages for the memory cells. The threshold voltage of the memory cells can be adjusted by changing the programming voltage. Different threshold voltages correspond to different logic states, allowing the memory cells to store different information. For example... Figure 7BAs shown, programming voltages with negative polarity for different durations can make the memory cell have different threshold voltages. The threshold voltage of the memory cell can be adjusted by adjusting the duration of the programming voltage. Different threshold voltages can correspond to different logic states, so that the memory cell stores different information. Figure 7A as well as Figure 7B The diagram illustrates the material relationships for three different functional structures. At the same programming voltage, different materials in the functional structures will result in different threshold voltages for the memory cells. For example... Figure 7C As shown, different programming voltage magnitudes and different programming voltage durations result in different threshold voltages for memory cells.

[0079] It is understood that the embodiments of this disclosure provide various ways to realize multi-bit storage of the storage unit. Applying a programming voltage to the storage unit will form a wire composed of traps. The polarity, duration and magnitude of the programming voltage applied to the storage unit will affect the concentration of the traps formed, resulting in different conductive wires. For example, the size of the conductive wires formed will be different, thereby making the storage unit have different threshold voltages, so that the storage unit can store multiple bits of data.

[0080] In some embodiments, the peripheral circuit is configured as follows:

[0081] A read voltage is applied to the first conductive line coupled to the target memory cell.

[0082] In some embodiments, such as Figure 8 As shown, the storage unit 100 includes a first electrode structure 101, a functional structure 200, and a second electrode structure 102 stacked along a first direction; the first electrode structure 101 includes a resistive layer 1011, a conductive layer 1012, and an isolation layer 1013 stacked sequentially along the first direction, with the isolation layer 1013 located between the conductive layer 1012 and the functional structure 200.

[0083] In this embodiment of the disclosure, the first electrode structure 101 needs to be further connected to the first conductive line. The resistive layer 1011 can reduce the contact resistance between the conductive layer 1012 and the first conductive line, and the isolation layer 1013 can reduce the interference of voltage changes in the first conductive line on the functional structure 200.

[0084] In some specific examples, the conductive layer 1012 may have the same material as the second electrode structure 102, while the materials of the resistive layer 1011, the conductive layer 1012, and the isolation layer 1013 are all different. The isolation layer 1013 may include a high-resistivity nitride, the resistive layer 1011 may include a doped semiconductor material, and the conductive layer may include a metal material.

[0085] In some embodiments, the functional structure 200 includes at least two elements selected from Se, As, Ge, Te, In, Si, and B.

[0086] In some specific examples, the materials of functional structure 200 include but not limited to GeSe, AsSe, AsTe, SiTe, SiSe, GeAs, SiAs, GeAsTe, GeAsSe, AlAsTe, AlAsSe, SiAsSe, SiAsTe, GeSeTe, GeSeSb, GaAsSe, G G eAsTeSb、GeAsTeBi、GeAsSeBi、GeAsSeIn、GeAsSeGa、GeAsseAl、GeAsSeTl、GeAsSeSn、GeAsSeZn、GeAsTeIn、GeAstega、GeAsteAl、GeAsteTl、GeAsteSn、GeAsteZn、Gesiassete、GeAssetes、Gesiassetes、Gesiassetes、GesiasseP、GesiasteP、GeAsseteP、Gesiassein、GesiasseGa、GesiasseAl、Ge SiAsSeTl, GeSiAsseZn, GeSiAsseSn, GeSiAsteIn, GeSiAstega, GeSiAsteAl, GeSiAsteTl, GeSiAsteZn, GeSiAstesN, GeAsSeTeIn, GeAsSeTega, GeAsSeTeAl, GeAsSeTeTl, GeAsSeTeZn, GeAsSeTeSn, GeASSeSIn, GeAsSeSGa, GeAsSeSAl, GeAsSeSTl, GeAsSeSZn, GeAsSeSSn, GeAsTeSIn, GeAsTeSGa, GeAsTe SAL, GeAsTeSTl, GeAsTeSZn, GeAsteSSn, GeAsSeInGa, GeAsSeInAl, GeAsSeInTl, GeAsSeInZn, GeAsSeInSn, GeAsseGaAl, GeAsseGaTl, GeAsseGaZn, GeAsseGaSn, GeAsseAlTl, GeAsseAlZn, GeAsSEAlSn, GeAsSeTlZn, GeAsSeTlSn, GeAsseZnsn, GeSiAssetes, GeSiAsseteIn, GeSiAssetega, GeSiAsseteAl,GeSiAsSeTeTl, GeSiAsSeTeZn, GeSiAsSeTeSn, GeSiAsSeTeP, GeSiAsSeSIn, GeSiAsSeSGa, GeSiAsSeSAl, GeSiAsSeSTl, GeSiAsSeSZn, GeSiAsSeSSn, GeAsSeTeSIn, GeAsSeTeSGa, GeAsSeTeSAl, Ge AsSeTeSTl, GeAsSeTeSZn, GeAsSeTeSSn, GeAsSeTePIn, GeAsSeTePGa, GeAsSeTePAl, GeAsSeTePTl, GeAsSeTePZn, GeAsSeTePSn, GeSiAsSeInGa, GeSiAsSeInAl, GeSiAsSeInTl, GeSiAsSeInZn, GeSi AsSeInSn, GeSiAsSeGaAl, GeSiAsSeGaTl, GeSiAsSeGaZn, GeSiAsSeGaSn, GeSiAsSeAlSn, GeAsSeTeInGa, GeAsSeTeInAl, GeAsSeTeInTl, GeAsSeTeInZn, GeAsSeTeInSn, GeAsSeTeGaAl, GeAsSeTeGa Tl, GeAsSeTeGaZn, GeAsSeTeGaSn, GeAsSeTeAlSn, GeAsSeSInGa, GeAsSeSInAl, GeAsSeSInTl, GeA sSeSInZn, GeAsSeSInSn, GeAsSeSGaAl, GeAsSeSGaTl, GeAsSeSGaZn, GeAsSeSGaSn, GeAsSeSAlSn. ,

[0087] In some embodiments, the selector memory includes a storage layer, which may include a plurality of storage cells 100. Figure 9 and Figure 10 This is a schematic diagram of the structure of the storage layer 300 provided in an embodiment of the present disclosure, wherein, Figure 10 for Figure 9 Cross-sectional view along line AA'. (Refer to reference) Figure 9 and Figure 10The storage layer 300 includes: a plurality of storage cells 100 arranged in an array along a second direction and a third direction; the second direction and the third direction intersect, and both the second direction and the third direction are perpendicular to the first direction; a plurality of first conductive lines 301 extending along the second direction and arranged along the third direction, and a plurality of second conductive lines 302 extending along the third direction and arranged along the second direction; a storage cell 100 is located between a first conductive line 301 and a second conductive line 302; a first conductive line 301 is connected to a first electrode structure 101 of the plurality of storage cells 100 arranged along the second direction; a second conductive line 302 is connected to a second electrode structure 102 of the plurality of storage cells 100 arranged along the third direction. Here, the second direction can be the X direction, and the third direction can be the Y direction.

[0088] In this embodiment of the present disclosure, a memory cell 100 in the memory layer 300 can be selected by applying a voltage to a first conductive line 301 and a second conductive line 302. The voltage applied to the first conductive line 301 can be transmitted to one side of the functional structure 200 through the first electrode structure 101, and the voltage applied to the second conductive line 302 can be transmitted to the other side of the functional structure 200 through the second electrode structure 102. Thus, a voltage difference can be formed on both sides of the functional structure 200 to perform programming or reading operations on the memory cell 100.

[0089] In some embodiments, such as Figure 11 This is a schematic diagram of the structure of a storage unit 100 provided in an embodiment of the present disclosure. The storage unit 100 includes a first electrode structure 101, a functional structure 200, and a second electrode structure 102 arranged sequentially along a first direction. The functional structure 200 includes at least a first functional layer 201 and a second functional layer 202. The first functional layer 201 is located between the second functional layer 202 and the first electrode structure 101 in the first direction. The material of the first functional layer 201 is different from the material of the second functional layer 202.

[0090] In some embodiments, the first functional layer 201 is in contact with the second functional layer 202, that is, there are no other structures between the first functional layer 201 and the second functional layer 202.

[0091] To increase the storage density of the memory device, a single memory cell 100 can store multiple bits of data. In this case, it is necessary to widen the threshold voltage range of the functional structure 200, that is, to increase the width of the first threshold voltage range and the width of the second threshold voltage range, so as to increase the number of bits of data stored in each memory cell 100 without compressing the read window.

[0092] In this embodiment, the functional structure 200 includes at least a first functional layer 201 and a second functional layer 202. The material of the first functional layer 201 is different from that of the second functional layer 202. It is understood that the difference in materials can lead to differences in electrical performance, including threshold voltage, threshold voltage drift, and leakage current. This broadens the threshold voltage range of the functional structure 200, further improving the storage density of the memory device.

[0093] Based on a concept similar to the selector-only memory described above, this disclosure also provides a memory system comprising: at least one selector-only memory as described in any of the above embodiments; and a controller coupled to the selector-only memory and configured to control the selector-only memory.

[0094] Based on a concept similar to the selector-only memory described above, this disclosure also provides a method for operating a selector-only memory, the selector-only memory including multiple storage cells, the method comprising performing multiple programming operations on a target storage cell to cause the target storage cell to store multiple bits of data, such as... Figure 12 As shown, the programming operation includes the following steps.

[0095] Step S10: Apply a corresponding first programming voltage to the first conductive line coupled to the target memory cell;

[0096] Step S20: Apply a corresponding second programming voltage to the first conductive line coupled to the target memory cell; the polarity of the first programming voltage and the second programming voltage are different.

[0097] In some embodiments, the polarity of the first programming voltage applied in different programming operations is the same, the polarity of the second programming voltage applied in different programming operations is the same, and the magnitude of the first programming voltage applied in different programming operations is different, and / or the magnitude of the second programming voltage applied in different programming operations is different.

[0098] In some embodiments, the polarity of the first programming voltage is negative, and the polarity of the second programming voltage is positive; the magnitude of the first programming voltage applied in different programming operations is the same, and the magnitude of the second programming voltage applied in the programming operations arranged in sequence in multiple programming operations is smaller than the magnitude of the second programming voltage applied in the programming operations arranged in sequence.

[0099] In some embodiments, the multiple second programming voltages applied in the sequentially arranged programming operations exhibit a step-like increasing trend or a linear increasing trend.

[0100] In some embodiments, the polarity of the first programming voltage is negative, and the polarity of the second programming voltage is positive; the magnitude of the second programming voltage applied in different programming operations is the same, and the absolute value of the first programming voltage applied in the preceding programming operations in multiple programming operations is smaller than the absolute value of the first programming voltage applied in the subsequent programming operations.

[0101] In some embodiments, the polarity of the first programming voltage is negative, and the polarity of the second programming voltage is positive; the absolute value of the first programming voltage applied in the sequentially preceding programming operation in multiple programming operations is smaller than the absolute value of the first programming voltage applied in the sequentially following programming operation, and the magnitude of the second programming voltage applied in the sequentially preceding programming operation in multiple programming operations is smaller than the magnitude of the second programming voltage applied in the sequentially following programming operation.

[0102] In some embodiments, the polarity of the first programming voltage applied in different programming operations is the same, the polarity of the second programming voltage applied in different programming operations is the same, the duration of the first programming voltage is different in different programming operations, and / or the duration of the second programming voltage is different in different programming operations.

[0103] In some embodiments, the operation method further includes applying a read voltage to the first conductive line coupled to the target memory cell.

[0104] The operation method of the selector memory described above has been described in detail in the corresponding embodiment of the selector memory, and will not be repeated here for the sake of simplicity.

[0105] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0106] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0107] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A select-only memory, characterized by, The only selector memory includes a plurality of storage units and a peripheral circuit coupled with the plurality of storage units, and the peripheral circuit is configured to perform a plurality of programming operations on a target storage unit to store a plurality of bits of data in the target storage unit, and the programming operation includes: applying a corresponding first programming voltage to a first conductive line coupled with the target storage unit; applying a corresponding second programming voltage to the first conductive line coupled with the target storage unit; the first programming voltage and the second programming voltage are different in polarity.

2. The selector-only memory of claim 1, wherein, The polarity of the first programming voltage applied in different programming operations is the same, and the polarity of the second programming voltage applied in different programming operations is the same; and the size of the first programming voltage applied in different programming operations is different, and / or the size of the second programming voltage applied in different programming operations is different.

3. The selector-only memory of claim 2, wherein, The polarity of the first programming voltage is negative, and the polarity of the second programming voltage is positive; the size of the first programming voltage applied in different programming operations is the same, and the size of the second programming voltage applied in the programming operation arranged in front in sequence in the plurality of programming operations is smaller than the size of the second programming voltage applied in the programming operation arranged behind in sequence.

4. The selector-only memory of claim 3, wherein, The plurality of second programming voltages applied in the plurality of programming operations arranged in sequence has a stepwise increasing trend or a linear increasing trend.

5. The select-only memory of claim 2, wherein, The polarity of the first programming voltage is negative, and the polarity of the second programming voltage is positive; the size of the second programming voltage applied in different programming operations is the same, and the absolute value of the size of the first programming voltage applied in the programming operation arranged in front in sequence in the plurality of programming operations is smaller than the absolute value of the size of the first programming voltage applied in the programming operation arranged behind in sequence.

6. The select-only memory of claim 2, wherein, The polarity of the first programming voltage is negative, and the polarity of the second programming voltage is positive; the absolute value of the size of the first programming voltage applied in the programming operation arranged in front in sequence in the plurality of programming operations is smaller than the absolute value of the size of the first programming voltage applied in the programming operation arranged behind in sequence, and the size of the second programming voltage applied in the programming operation arranged in front in sequence in the plurality of programming operations is smaller than the size of the second programming voltage applied in the programming operation arranged behind in sequence.

7. The select-only memory of any of claims 1 to 6, wherein, The polarity of the first programming voltage applied in different programming operations is the same, and the polarity of the second programming voltage applied in different programming operations is the same; the duration of the first programming voltage in different programming operations is different; and / or the duration of the second programming voltage in different programming operations is different.

8. The select-only memory of claim 7, wherein, The duration of the first programming voltage in the programming operation arranged in front in sequence in the plurality of programming operations is smaller than the duration of the first programming voltage in the programming operation arranged behind in sequence; and / or the duration of the second programming voltage in the programming operation arranged in front in sequence in the plurality of programming operations is smaller than the duration of the second programming voltage in the programming operation arranged behind in sequence.

9. The selector-only memory of claim 1, wherein, The storage unit includes a first electrode structure, a functional structure, and a second electrode structure arranged in a stack along a first direction; the first electrode structure includes a resistance layer, a conductive layer, and a separation layer arranged in a stack along the first direction in sequence; The separation layer is located between the conductive layer and the functional structure.

10. A memory system, characterized by, It includes: A selector-only memory according to any one of claims 1 to 9; A controller coupled to the selector-only memory and configured to control the selector-only memory.

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