Selector-only memory write operations

Abstract

Techniques for programming selector-only memory cells in a cross-point memory structure. The threshold switch memory element may include, but is not limited to, a bi-directional threshold switch (OTS). The memory system removes the Vth drift of the threshold switch memory element prior to programming. The Vth drift is removed by applying a first voltage and a second voltage having opposite polarities to all of the SOM cells to be programmed. Then, two programming voltages having two polarities are applied to program the cell into two states.

Description

Background Technology

[0001] Memory is widely used in a variety of electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, non-mobile computing devices, and data servers. Memory can include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when it is not connected to a power source (e.g., a battery).

[0002] Memory cells can reside in a cross-point memory array. In a memory array with a cross-point architecture, one set of conductive lines extends across the surface of the substrate, and another set of conductive lines is formed above the first set, extending orthogonally relative to the initial layer. The memory cells are located at the intersection of these two sets of conductive lines. Cross-point memory arrays are sometimes referred to as cross-strip memory arrays.

[0003] One type of memory cell contains programmable resistive memory elements, such as magnetoresistive memory elements. Magnetoresistive random access memory (MRAM) cells use magnetization to represent the stored data. Data bits are written to the MRAM cell by changing the magnetization direction of magnetic elements (“free layers”) within the MRAM cell, and bits are read by measuring the resistance of the MRAM cell, which changes with the magnetization direction. However, crosspoint memory arrays can have other types of memory cells. For example, crosspoint memory arrays can have memory cells using other technologies such as ReRam, PCM (phase-change memory), or FeRam.

[0004] In some crosspoint memory architectures, each memory cell includes a threshold switch selector connected in series with a programmable resistive memory element. In such architectures, the programmable resistive memory element is programmed to store data, while the threshold switch selector is used to select the memory cell. The threshold switch selector has a high resistance (off or non-conductive) until it is biased to a voltage higher than its threshold voltage (Vt) or a current higher than its threshold current (It), and until its voltage bias drops below Vhold (“Voffset”) or its current drops below the holding current Ihold. After exceeding Vt and beyond Vhold across the threshold switch selector, the threshold switch selector has a relatively low resistance (on or conductive). The threshold switch selector remains on until its current drops below the holding current Ihold, or its voltage drops below the holding voltage Vhold. When this occurs, the threshold switch selector returns to the off (higher) resistance state. An example of a threshold switch selector is a bidirectional threshold switch (OTS). Other examples of threshold switch selectors include, but are not limited to, volatile conductive bridges (VCBs), metal-insulator-metal (MIMs), or other materials that provide a highly nonlinear dependence of current on the selection voltage.

[0005] In some cross-point architectures, memory cells contain threshold switch selectors that function as both selectors and programmable memory elements. Such architectures may be referred to as selector-only memory (SOM) cells or self-selecting memory cells. When read at a voltage of a given polarity, the threshold voltage (Vth) of the SOM cell can depend on the polarity of the write voltage used to program the SOM cell. An SOM cell written and read at the same polarity voltage exhibits a lower Vth compared to writing and reading at the opposite polarity voltage. The memory system can assign a default polarity to the read voltage, which allows the SOM cell to be programmed to a first state using a first polarity write voltage and to a second state using a second polarity write voltage opposite to the first polarity.

[0006] However, over time, the Vth of the threshold switch selector may drift, which presents a technical challenge. Figure 1A A graph depicting the threshold voltage of the SOM cell over time is presented.

[0007] Figure 1B is a table illustrating a conventional programming scheme used in conjunction with an SOM cell. In this programming scheme, state W0 is written with a voltage of the same polarity as the read voltage. However, state W1 is written with a voltage of the opposite polarity to the read voltage. Reads can be performed using the default polarity voltage. The read voltage polarity can be selected by the memory system, but it will be the same for each read. Column 60 shows the final voltage applied to the memory cell, which causes the cell to fire (e.g., turn on a selector). The up and down arrows in the table in Figure 1B are used to indicate the relative polarity of the voltage. Column 62 shows the new data to be written to the cell.

[0008] See now Figure 1A A SOM cell programmed to state W0 (at the "lower polarity write voltage") and read immediately (at the "lower polarity read voltage") will have a Vth close to star 20. A SOM cell programmed to state W1 (at the "upper polarity write voltage") and read immediately (at the "lower polarity read voltage") will have a Vth close to star 22. Curve 10 shows the upward drift of Vth for a W0 state cell. If a read is made after a significant time delay (at the lower polarity read voltage), the W0 cell may have a Vth close to B level Vth, as indicated by arrow 30. If a read is made after a significant time delay (at the lower polarity read voltage), the W1 cell may have a Vth close to A level Vth, as indicated by arrow 32. Column 64 of the table in Figure 1B summarizes the Vth of a particular cell, which depends on the relative polarity of the final trigger voltage (column 60) and the polarity of the write voltage (column 62). The cell with final firing of W1 and new data of W1 has the same polarity voltage for both voltages; therefore, the writing of new data W1 experiences the low Vth of B. However, the cell with final firing of W1 and new data of W0 has opposite polarity voltages for both voltages; therefore, the writing of new data W0 experiences the high Vth of A. The cell with final firing of W0 (or R0) and new data of W1 has opposite polarity voltages for both voltages; therefore, the writing of new data W1 experiences the high Vth of A. The cell with final firing of W0 (or R0) and new data of W0 has the same polarity voltage for both voltages; therefore, the writing of new data W0 experiences the low Vth of B.

[0009] A "half-selection" problem can occur when reading or programming memory cells in a crossbar architecture. When programming a memory cell, the full programming voltage is applied across the selected memory cell. The memory system may apply 0V across some cells that will not be programmed ("completely unselected cells"). However, in some technologies, the memory system applies half the programming voltage across some cells that will not be programmed. These cells are called "half-selected cells." Depending on the Vth of the half-selected cell, it is possible for a threshold switch selector to unexpectedly turn on during programming operations. A similar half-selection problem can occur during read operations.

[0010] See you again Figure 1A The diagram illustrates the semi-selection (HS) margin. The HS margin can be calculated as Vth_Max / 2 – Vth_Min. Figure 1A In the example, Vth_Max is the maximum value (“A”) of curve 12, and Vth_Min is the minimum value of curve 10. Therefore, the HS margin is the difference between dashed line 42 and dashed line 44. Attached Figure Description

[0011] Components with similar numbers refer to common parts in different drawings.

[0012] Figure 1A A graph depicting the threshold voltage of the SOM cell over time is presented.

[0013] Figure 1B is a table showing the conventional programming scheme used in conjunction with the SOM unit.

[0014] Figure 2 This is a block diagram of one implementation of a non-volatile memory system connected to a host computer.

[0015] Figure 3A This is a block diagram of one implementation scheme for a memory die.

[0016] Figure 3B It is a block diagram of one embodiment of an integrated memory assembly that includes a control die and a memory structure die.

[0017] Figure 4A An implementation of a memory array forming a cross-point architecture is depicted in oblique view.

[0018] Figure 4B and Figure 4C They were presented respectively Figure 4A Side and top views of the intersection structure.

[0019] Figure 4D An implementation of a portion of a two-level memory array forming a cross-point architecture is depicted in oblique view.

[0020] Figure 5 An implementation scheme of the SOM unit structure is illustrated.

[0021] Figure 6A and Figure 6B An implementation scheme for accessing a selected SOM cell in a crosspoint memory structure is illustrated.

[0022] Figure 7 This is a flowchart of an implementation of the process of programming the memory cell of a two-terminal threshold switch selector in a crosspoint array.

[0023] Figure 8 Two “Vth distributions” for implementing the programming of SOM units are described.

[0024] Figure 9A This is a table showing details of one implementation of programming the SOM cell in a crosspoint memory structure.

[0025] Figure 9B The threshold voltage over time is depicted in one embodiment of the SOM cell in an operating crosspoint memory structure.

[0026] Figure 10 This is a flowchart of an implementation scheme for programming the SOM cell in the crosspoint memory structure.

[0027] Figure 11 This is a flowchart of an implementation scheme for programming the SOM cell in the crosspoint memory structure.

[0028] Figure 12 This is a flowchart of an implementation scheme for programming the SOM cell in the crosspoint memory structure. Detailed Implementation

[0029] Techniques for programming selector-only memory cells in a crosspoint memory structure are disclosed. Threshold-switch memory elements may include, but are not limited to, bidirectional threshold switches (OTS). In one embodiment, the memory system removes the Vth drift of the threshold-switch memory element before programming. Removing the Vth drift allows the memory system to use a lower value of the programming voltage. A lower value of the programming voltage reduces accidental selection of half-select memory cells. In one embodiment, the Vth drift is removed by applying a first voltage and a second voltage of opposite polarities to all SOM cells in the SOM cell to be programmed. Then, two programming voltages of two polarities are applied to program the cell into two states. Furthermore, the value of the voltage used to remove the Vth drift can be selected based on factors such as the expected Vth drift of the SOM cell.

[0030] Referring again to Figure 1B, the high (or A) Vth in column 64 of Vth is a problematic threshold voltage that can potentially lead to accidental selection of half-select memory cells. This is because the HS margin decreases as the "A level" increases. An implementation of the programming process can reduce the Vth of the cell before programming, thus eliminating such a problem. Therefore, the magnitude of the programming voltage can be reduced while still maintaining sufficient HS margin. This prevents or at least reduces accidental selection of half-select memory cells.

[0031] In one embodiment, the memory system includes SOM cells residing in a cross-point memory array structure. In a memory array with a cross-point architecture, one set of conductive lines extends across the surface of a substrate, and another set of conductive lines is formed above the first set of conductive lines, extending over the substrate in a direction perpendicular to the first set of conductive lines. Memory cells are located at the intersection of these two sets of conductive lines. Cross-point memory arrays are sometimes referred to as cross-strip memory arrays.

[0032] The terms “top” and “bottom,” “upper” and “lower,” and “vertical” and “horizontal,” and their forms, as used herein, are used only by way of example and for illustrative purposes, and are not intended to limit the description of the technique, as the items cited may be interchanged in position and orientation. Additionally, as used herein, the terms “substantially,” “approximately,” and / or “about” mean that a specified dimension or parameter may vary within acceptable tolerances for a given application.

[0033] Figure 2 This is a block diagram of one embodiment of a non-volatile memory system (or more simply, a “memory system”) 100 connected to a host system 120. In one embodiment, the memory cell has a threshold switch selector such as an OTS. Many types of memory systems can be used with the techniques presented herein. Exemplary memory systems include dual in-line memory modules (DIMMs), solid-state drives (“SSDs”), memory cards, and embedded memory devices; however, other types of memory systems may also be used.

[0034] Figure 2The memory system 100 includes a memory controller 102, a memory 104 for storing data, and a local memory 140 (e.g., SOM, MRAM, ReRAM, DRAM). The local memory 140 may be non-volatile and retain data after power loss. Alternatively, the local memory 140 may be volatile and not expected to retain data after power loss. In one embodiment, the local memory 140 includes SOM cells. In one embodiment, the local memory does not need to retain data after power loss. However, the local memory may retain data after power loss. In one embodiment, the memory controller 102 and / or the local memory controller 164 provide access to the SOM cells in the local memory 140. For example, the memory controller 102 may provide access to a cross-point array of SOM cells in the local memory 140. In another embodiment, the memory controller 102 or interface 126, or both, are omitted, and the memory packages are directly connected to the host 120 via a bus such as DDRn. Alternatively, they are connected to the host memory management unit (MMU). In another scenario, memory controller 102 or a portion thereof is moved onto memory 104 to directly connect memory 104 to the host, such as by providing parity bits, ECC, and wear leveling on memory 104, along with a DDRn interface to / from the host or MMU. As used throughout this document, the term "memory system" is not limited to memory system 100. For example, local memory 140, or a combination of local memory 140 and local memory controller 164, can be considered a memory system. Similarly, host memory 124, or a combination of host processor 122 and host memory 124, can be considered a memory system.

[0035] Figure 2The components of the memory system 100 depicted are electronic circuits. The memory controller 102 includes a host interface 152, a processor 156, an ECC engine 158, a memory interface 160, a local memory controller 164, refresh logic 172, and a loss equalization 174. The host interface 152 is connected to and communicates with the host 120. The host interface 152 is also connected to a network on-chip (NOC) 154. The NOC is a communication subsystem on an integrated circuit. The NOC can span synchronous and asynchronous clock domains, or use non-clocked asynchronous logic. NOC technology applies network theory and methods to on-chip communication and brings significant improvements compared to conventional bus and cross-switch interconnects. Compared to other designs, the NOC improves the scalability of the system-on-chip (SoC) and the power efficiency of complex SoCs. The lines and links of the NOC are shared by many signals. Because all links in the NOC can operate simultaneously on different data packets, a high degree of parallelism is achieved. Therefore, as the complexity of integrated subsystems increases, the NOC offers enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal lines, shared buses, or segmented buses with bridges). In other embodiments, the NOC 154 can be replaced by a bus. The processor 156, ECC engine 158, memory interface 160, local memory controller 164, refresh logic 172, and wear leveling 174 are connected to and communicate with the NOC 154. The local memory controller 164 is used to operate and communicates with the local high-speed memory 140 (e.g., MRAM). In other embodiments, the local high-speed memory 140 can be DRAM, SRAM, or another type of volatile memory.

[0036] ECC engine 158 performs error correction services. For example, ECC engine 158 performs data encoding and decoding of parity bits provided on or off memory as part of codewords used to correct errors in data retrieved from memory 140 or 104. In one embodiment, ECC engine 158 is a software-programmable electronic circuit. For example, ECC engine 158 may be a programmable processor. In other embodiments, ECC engine 158 is a custom-designed dedicated hardware circuit without any software. In one embodiment, the functionality of ECC engine 158 is implemented by processor 156. In one embodiment, local memory 140 has an ECC engine, with or without a wear leveling engine. In one embodiment, memory 104 has an ECC engine, with or without a wear leveling engine.

[0037] Processor 156 performs various controller memory operations, such as programming, erasing, reading, and memory management processes including wear leveling. A separate wear leveling 174 is depicted, but wear leveling 174 can be implemented by processor 156. Additionally, refresh logic 172 is depicted, but refreshing can also be implemented by processor 156. In one embodiment, processor 156 is programmed by firmware. In other embodiments, processor 156 is custom-designed dedicated hardware circuitry without any software. Processor 156 also implements a translation module, either as a software / firmware process or as dedicated hardware circuitry. In many systems, non-volatile memory is addressed inward to the memory system using physical addresses associated with one or more memory dies. However, the host system will use logical addresses to address various memory locations. This allows the host to allocate data to consecutive logical addresses while the memory system is idle to store data between locations of one or more memory dies as desired. To implement such a system, memory controller 102 (e.g., a translation module) performs address translation between logical addresses used by the host and physical addresses used by the memory dies. One exemplary implementation is to maintain a table that identifies the current translation between logical addresses and physical addresses (i.e., the L2P table mentioned above). Entries in the L2P table may include identifiers for logical addresses and their corresponding physical addresses. While logical address-to-physical address tables (or L2P tables) use the word "table," they do not have to be tables in the literal sense. Rather, logical address-to-physical address tables (or L2P tables) can be any type of data structure. In some examples, the memory space of the storage system is so large that local memory 140 cannot hold all the L2P tables. In this case, the entire set of L2P tables is stored in memory 104, and a subset of the L2P tables (the L2P cache) is cached in local memory 140.

[0038] Memory interface 160 communicates with storage device 104. In one embodiment, storage device 104 includes SOM cells in a crosspoint array. In one embodiment, storage device 104 includes NAND memory cells. In one embodiment, the memory interface provides a switching mode interface. Other interfaces may also be used. In some exemplary embodiments, memory interface 160 (or another part of controller 102) implements a scheduler and buffer for sending data to and receiving data from one or more memory dies.

[0039] In one embodiment, local memory 140 has an ECC engine. Local memory 140 can be used to assist in performing other functions, such as wear leveling. Further details of on-chip memory maintenance are described in U.S. Patent 10,545,692, entitled "Memory Maintenance Operations During Refresh Window," and U.S. Patent 10,885,991, entitled "Data Rewrite During Refresh Window," both of which are incorporated herein by reference in their entirety. In one embodiment, local memory 140 is synchronous. In one embodiment, local memory 140 is asynchronous.

[0040] In one embodiment, the storage device 104 includes a plurality of memory packages. Each memory package includes one or more memory dies. Therefore, the memory controller 102 is connected to one or more memory dies. In one embodiment, the memory packages may include various types of memory, such as storage-class memory (SCM) or phase-change memory (PCM) based on programmable resistor random access memory (such as SOM, ReRAM, MRAM, FeRAM, or RRAM). In one embodiment, the memory controller 102 provides access to memory cells in a cross-point array within the storage device 104.

[0041] Memory controller 102 communicates with host system 120 via interface 152 implementing a protocol such as Compute Fast Link (CXL). Alternatively, this controller can be omitted, and the memory package can be placed directly on the host bus (e.g., DDRn or CXL). To work with memory system 100, host system 120 includes host processor 122, host memory 124, and interface 126 connected along bus 128. Host memory 124 is the host's physical memory and can be SOM, DRAM, SRAM, ReRAM, MRAM, non-volatile memory, or another type of memory device. In one embodiment, host memory 124 includes a crosspoint array of programmable resistive memory cells, where each memory cell includes a threshold switch selector to act as an SOM cell.

[0042] The host system 120 is external to and separate from the memory system 100. In one embodiment, the memory system 100 is embedded within the host system 120. The host memory 124 may be referred to herein as a memory system. The combination of the host processor 122 and the host memory 124 may be referred to herein as a memory system. In one embodiment, such host memory may be a cross-point memory using SOM cells.

[0043] Figure 3A This is a block diagram illustrating an example of a memory die 292 that can implement the techniques described herein. In one embodiment, the memory die 292 is included in local memory 140, and in another embodiment, the memory die 292 is included in storage device 104. In one embodiment, the memory die 292 is included in host memory 124. The memory die 292 includes a memory structure 202, which may include any of the memory cells described below. The memory structure 202 may include one or more memory arrays. The array terminal lines of the memory structure 202 include one or more various word line layers organized in rows, and one or more various bit line layers organized in columns. However, other orientations may also be implemented, including, for example, a diagonal pattern to save space. The memory die 292 includes row control circuitry 220, the output 208 of which is connected to a corresponding word line of the memory structure 202. Row control circuitry 220 receives a set of M row address signals and one or more various control signals from system control logic circuitry 260, and typically includes circuitry such as row decoder 222, row driver 224, and block select circuitry 226 for both read and write operations. Row control circuitry 220 may also include read / write circuitry. In one embodiment, row decoding and control circuitry 220 has sense amplifiers 228, each containing circuitry for sensing the condition (e.g., voltage) of word lines in memory structure 202. In one embodiment, by sensing the word line voltage, the condition or bit state of memory cells (e.g., SOM cells) in the crosspoint array is determined by directly comparing the accessed memory cell voltage with a reference voltage via the sense amplifiers. Memory die 292 also includes column decoding and control circuitry 210, whose inputs / outputs 206 are connected to the corresponding bit lines of memory structure 202. Although only a single block is shown for memory structure 202, memory die may include multiple arrays or "strips" that can be accessed individually. The column control circuit 210 receives a set of N column address signals and one or more various control signals from the system control logic 260, and typically includes circuits such as column decoder 212, column decoder and driver 214, block select circuit 216, read / write circuit and I / O multiplexer.

[0044] System control logic 260 receives data and commands from the host system and provides output data and status to the host system. In other embodiments, system control logic 260 receives data and commands from a separate controller circuit and provides output data to that controller circuit, which communicates with the host system. Such a controller system may implement interfaces such as DDR, DIMM, CXL, PCIe, etc. In another embodiment, this data and commands are transferred and received directly from the memory package to the host without a separate controller, and any required controller is within each die or within a die added to the multi-chip memory package. In some embodiments, system control logic 260 may include a state machine 262 that provides die-level control for memory operations. In one embodiment, state machine 262 is programmable by software. In other embodiments, state machine 262 does not use software and is implemented entirely in hardware (e.g., electronic circuitry). In another embodiment, state machine 262 is replaced by a microcontroller or microprocessor. System control logic 260 may also include a power control module 264 that controls the power, current source current, and voltage supplied to the rows and columns of memory structure 202 during memory operation, and may include charge pump and regulator circuitry for generating regulated voltages, and on / off control for selecting each of the word lines and bit lines for memory cells. In some embodiments, power control 264 includes one or more current sources. The current sources(s) may be used to provide read and / or write currents. System control logic 260 includes a storage device 266 that may be used to store parameters for operating memory structure 202. System control logic 260 also includes refresh logic 272 and wear leveling logic 274. This system control logic may be commanded by host 120 or memory controller 102 to refresh logic 272, which may load row and column addresses (pointers) stored on the chip that may increment after a refresh. Only such address bits may be selected (to refresh the OTS). Alternatively, such addresses can be read, corrected via manipulation by ECC engine 269, and then stored in an "idle" location that is also incremented (thus periodically reading, correcting, and repositioning all codewords throughout the chip under the control of loss leveling logic 274) to effectively level the loss, resulting in more even use of each bit across the entire chip. This operation can be more directly controlled by the host computer of an external controller, such as a PCIe, CXL, or DDRn controller located separately from the memory chip or on the memory die.

[0045] Commands and data are passed between memory controller 102 and memory die 292 via memory controller interface 268 (also referred to as the "communication interface"). This interface can be, for example, PCIe, CXL, or DDRn. Memory controller interface 268 is an electrical interface for communicating with memory controller 102. Examples of memory controller interface 268 also include a switching mode interface. Other I / O interfaces may also be used. For example, memory controller interface 268 may implement a switching mode interface connected to the switching mode interface of memory interface 228 / 258 of memory controller 102. In one embodiment, memory controller interface 268 includes a set of input and / or output (I / O) pins connected to controller 102. In another embodiment, the interface is a JEDEC standard DDRn or LPDDRn, such as DDR5 or LPDDR5, or a subset thereof with smaller page size and / or relaxed timing.

[0046] The system control logic 260 in the controller located on the memory die within the memory package may include an error correction code (ECC) engine 269. The ECC engine 269 may be referred to as an on-die ECC engine because it resides on the same semiconductor die as the memory cell. That is, the on-die ECC engine 269 can be used to encode data and parity bits stored in the memory structure 202, and to decode and correct the decoded data. The encoded data may be referred to herein as a codeword or ECC codeword. The ECC engine 269 can be used to execute decoding algorithms and to perform error correction. Therefore, the ECC engine 269 can decode ECC codewords. In one embodiment, the ECC engine 269 can decode data more quickly by direct decoding without iteration. Having the ECC engine 269 on the same die as the memory cell allows for faster decoding. The ECC engine 269 can use a variety of decoding algorithms, including but not limited to Reed Solomon, Bose-Chaudhuri-Hocquenghem (BCH), and Low-Density Parity Check (LDPC).

[0047] In some embodiments, all components of memory die 292 (including system control logic 260) may be formed as part of a single die. In other embodiments, some or all of the system control logic in system control logic 260 may be formed on different dies (e.g., external controller chips).

[0048] In one embodiment, memory structure 202 includes a three-dimensional memory array of non-volatile or volatile memory cells, wherein multiple memory levels are formed over a single substrate, such as a wafer. The memory structure may include any type of non-volatile or volatile memory integrally formed in one or more physical levels of memory cells having active regions disposed over a silicon-on-insulator (or other type of) substrate. In another embodiment, memory structure 202 includes a two-dimensional memory array of non-volatile memory cells.

[0049] The exact type of memory array architecture or memory cell included in memory structure 202 is not limited to the examples above. Many different types of memory array architectures or memory technologies can be used to form memory structure 202. Implementing the new embodiments claimed herein does not require a specific non-volatile memory technology. Examples of suitable technologies for the memory cell architecture of memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bitline arrays, and so on.

[0050] An example of a SOM crosspoint memory includes an OTS selector / memory element arranged in a crosspoint array accessed by X-rays and Y-rays (e.g., word lines and bit lines). In another embodiment, the memory cell may include a conductive bridge memory element. A conductive bridge memory element may also be referred to as a programmable metallized cell. Based on the physical repositioning of ions within a solid electrolyte, the conductive bridge memory element can be used as a state-changing element. In some cases, the conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of solid electrolyte between the two electrodes. As temperature increases, ion mobility also increases, leading to a decrease in the programming threshold of the conductive bridge memory cell. Therefore, the conductive bridge memory element can have a wide range of programming thresholds across the entire temperature range.

[0051] In some implementations, the memory structure incorporates a phase-change memory (PCM). PCMs utilize the unique properties of chalcogenide glasses. One implementation uses a GeTe-Sb₂Te₃ superlattice to achieve a non-thermal phase transition by altering the coordination state of germanium atoms using only laser pulses (or light pulses from another source). The memory cell is programmed by current pulses that can alter the coordination of the PCM material or switch between an amorphous and crystalline state. Note that the use of "pulse" in this document does not require a square pulse, but includes (continuous or discontinuous) vibrations or pulse trains of sound, current, voltage, light, or other waves. The current forced for writing can, for example, be rapidly driven to a peak and then linearly sloped down at a marginal rate of, for example, 500 ns. This peak current forcing may be subject to partition voltage compliance, which varies with the location of the memory cell along the word line or bit line. In one implementation, the PCM cell has a PCM element connected in series with a threshold switch selector (such as an OTS).

[0052] Those skilled in the art will recognize that the techniques described herein are not limited to a single particular memory structure, memory configuration, or material composition, but encompass many related memory structures within the technical essence and scope as described herein and as understood by those skilled in the art.

[0053] Can Figure 3A The components are divided into two parts: memory structure 202 and peripheral circuitry (including all other components). A key characteristic of the memory circuitry is its capacity, which can be increased by increasing the area allocated to the memory die 292 of memory structure 202; however, this reduces the area of ​​memory dies available for peripheral circuitry or increases chip area-related costs. This can impose significant limitations on these peripheral components. For example, the need to mount sense amplifier circuitry within the available area can be a major constraint on sense amplifier design architecture. Regarding system control logic 260, reduced available area may limit the available functionality that can be implemented on the chip. Therefore, a fundamental trade-off needs to be struck between the amount of dedicated area for memory structure 202 and the amount of dedicated area for peripheral circuitry in the design of memory die 292. This trade-off may result in greater IR drop due to the use of a larger xy memory array between word lines and bit lines, which may benefit more from using voltage limits and partitioning for voltage compliance through memory cell locations along word lines and bit lines.

[0054] Another area where memory structure 202 often conflicts with peripheral circuitry is the processing involved in forming these areas, as these areas typically involve different processing techniques and trade-offs when implementing different techniques on a single die. For example, components such as sense amplifier circuitry, charge pumps, logic elements in state machines, and other peripheral circuitry in system control logic 260 often employ PMOS devices. In some cases, the memory structure will be based on CMOS devices. The processing operations used to manufacture CMOS dies will differ in many ways from those optimized solely for NMOS technology.

[0055] To mitigate these limitations, the implementation scheme described below can... Figure 3A The components are separated onto individually formed dies, and then these dies are joined together. Figure 3B An integrated memory assembly 270 is depicted having a memory structure die 280 and a control die 290. A memory structure 202 is formed on the memory structure die 280, and some or all of the peripheral circuitry elements, including one or more control circuitry, are formed on the control die 290. For example, the memory structure die 280 may be formed only of memory elements, such as an array of SOM cells or other memory types. Some or all of the peripheral circuitry, even including elements such as decoders, current sources, and sense amplifiers, can then be moved to the control die. This allows for individual optimization of each die in the semiconductor die according to its technology. This provides more space for peripheral elements, and additional capabilities that might not be easily combined can now be incorporated if peripheral elements are confined to the edges of the same die that houses the array of memory cells. Two dies can then be bonded together in a bonded multi-die integrated memory assembly, with an array on one die connected to peripheral elements on the other die. For example, while the integrated memory assembly with one memory die and one control die will be described in focus below, other embodiments may use additional dies, such as two memory dies and one control die.

[0056] and Figure 3A The memory die 292 is the same. Figure 3B The memory structure die 280 includes a memory structure 202, which may include multiple independently accessible arrays or "strips". System control logic 260, row control circuitry 220, and column control circuitry 210 are located in control die 290. In some embodiments, all or a portion of the column control circuitry 210 and all or a portion of the row control circuitry 220 are located on memory structure die 280. In some embodiments, a portion of the circuitry in system control logic 260 is located on memory structure die 280.

[0057] Figure 3BA column control circuit 210 on a control die 290 is shown, which is coupled to a memory structure 202 on a memory structure die 280 via an electrical path 293. For example, electrical path 293 may provide electrical connections between a column decoder 212, a column driver circuit 214, a block select 216, and bit lines of the memory structure 202. The electrical path may extend from the column control circuit 210 in the control die 290 through pads on the control die 290 that bond to corresponding pads on the memory structure die 280 that are connected to bit lines of the memory structure 202. Each bit line of the memory structure 202 may have a corresponding electrical path in electrical path 293 connected to the column control circuit 210, including a pair of bonded pads. Similarly, row control circuitry 220, including a row decoder 222, a row driver 224, a block select 226, and a sense amplifier 228, is coupled to the memory structure 202 via an electrical path 294. Each electrical path in electrical path 294 may correspond to, for example, a word line. Additional electrical paths can also be provided between the control die 290 and the memory structure die 280.

[0058] For the purposes of this document, the phrase "control circuitry" may include one or more of the following: memory controller 102, local memory controller 164, processor 156, system control logic 260, column control circuitry 210, row control circuitry 220, host processor 122, microcontroller, state machine, and / or other control circuitry, or other similar circuitry for controlling non-volatile memory. Control circuitry may consist only of hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of control circuitry. Control circuitry may include processors, FPGAs, ASICs, integrated circuits, or other types of circuitry. Such control circuitry may include drivers, such as direct drivers that connect nodes via fully on transistors (gate-to-power) driven to a fixed voltage (such as a power supply). Such control circuitry may include current source drivers.

[0059] For the purposes of this document, the term “device” may include, but is not limited to, one or more of the following: memory system 100, local memory 140, local memory controller 164 and / or a combination of memory controller 102 and local memory 140, storage device 104, memory die 292, integrated memory assembly 270 and / or control die 290.

[0060] In the following discussion, Figure 3A and Figure 3BThe memory structure 202 will be discussed in the context of a crosspoint architecture. In a crosspoint architecture, a first set of conductive lines or lines (such as word lines) extends in a first direction relative to the underlying substrate, and a second set of conductive lines or lines (such as bit lines) extends in a second direction relative to the underlying substrate. Memory cells are located at the intersections of word lines and bit lines. These memory cells at the crosspoints can be formed according to any of a variety of techniques (including those described above). The following discussion will focus primarily on an implementation based on a crosspoint architecture using SOM cells, each SOM cell having a threshold switch selector (such as a bidirectional threshold switch (OTS)) to include selectable memory bits. However, the implementation is not limited to the selector being an OTS.

[0061] Figure 4A An implementation of a portion of the memory array 402 forming the cross-point architecture is depicted in oblique view. Figure 4A The memory array 402 is Figure 3A or Figure 3B An example of a specific implementation of memory structure 202 is provided, wherein memory die 292 or memory structure die 280 may include multiple such memory arrays 402. Memory array 402 may be included in local memory 140 or host memory 124. Bit lines BL1-BL5 are arranged along a first direction (indicated as extending into the page) relative to the lower substrate of the die, and word lines WL1-WL5 are arranged along a second direction perpendicular to the first direction or along a diagonal to provide an intersection of memory cells interconnected between WL and BL. Figure 4A This is an example of a horizontal crossover structure, where word lines WL1-WL5 and BL1-BL5 both extend horizontally relative to the substrate, and memory cells (two of which are indicated by 401) are oriented such that the current through the memory cells (such as I) 单元 (As shown) flows vertically. In memory arrays with additional layers of memory cells, such as those described below... Figure 4D The discussion will involve corresponding additional layers for bit lines and word lines. For example, a pattern will come from the bottom layer: WL, memory cell, BL, memory cell, WL, WL, memory cell, BL memory cell, WL.

[0062] like Figure 4AAs depicted, memory array 402 includes a plurality of memory cells 401. Memory cells 401 may include rewritable memory elements, such as those implemented using a threshold switch selector operable to have programmable resistors. Memory cell 401 may be referred to herein as a programmable resistor memory cell. Memory cell 401 may also be referred to herein as a self-selecting memory cell or a selector-only memory cell. The threshold switch selector may be implemented using a bidirectional threshold switch (OTS), a volatile conductive bridge (VCB), a metal-insulator-metal (MIM), or other materials that provide a highly nonlinear dependence of current or resistance on a changing selection voltage. The following discussion will focus on memory cells composed of OTS memory elements, but much of the discussion can be applied more generally. The current in a memory cell of the first memory level is shown as shown by arrow I. 单元 The current is indicated to flow upwards, but it can flow in either direction to read or write the state of a memory cell bit, as discussed in more detail below.

[0063] Figure 4B and Figure 4C They were presented respectively Figure 4A Side and top views of the intersection structure. Figure 4B The side view shows a bottom line or word line WL1, and multiple top lines or bit lines BL1-BL1. n At the intersection of each top and bottom line is the SOM memory cell 401. Figure 4C This is an example of M baselines WL1-WL M and N top lines BL1-BL N A top view of the intersection structure. In a binary implementation, the SOM cell at each intersection can be programmed into one of two resistance states—a high-resistance state and a low-resistance state. Further details regarding implementation schemes for SOM memory cell designs and their programming techniques are given below. In some implementations, these sets of lines are arranged consecutively as “strips,” and such strips can be paired adjacently in the word line (WL) direction and orthogonally in the bit line direction to form modules. Such modules can consist of 2×2 strips to form a four-strip combination, where the WL drivers between the strips are “center-driven” between the strips, with the approximate center of the WL line running continuously on the transistor driver. Similarly, BL drivers can be positioned between paired strip pairs in the BL direction, thus being center-driven, whereby the transistor driver and its area are shared between a pair of strips. Copper or other types of low-resistance vias can decode and connect the transistor driver / selector to the WL or BL. In addition to memory elements in the memory cells between the WL and BL, cascaded select elements such as OTS may also be included.

[0064] Figure 4A The cross-point array illustrates an implementation with a single layer of word lines and bit lines, where a SOM or other memory technology for memory cells is located at the intersection of these two sets of conductive lines. To increase the storage density of a memory die, multiple layers of such memory cells and conductive lines can be formed. A dual-layer example is shown in... Figure 4D Example in.

[0065] Figure 4D An implementation of a portion of a two-level memory array forming a cross-point architecture is depicted in oblique view. (See diagram below.) Figure 4A Like in the middle, Figure 4D The memory array 403 shows the first layer 418 memory cells 401, which are connected to the first layer word line WL above. 1,1 -WL 1,4 At the intersection with bit lines BL1-BL5. Memory array 403 may be included. Figure 3A or Figure 3B In memory structure 202, the second layer 420 memory cells are formed above bit lines BL1-BL5 and in the second set WL of these bit lines and word lines. 2,1 -WL 2,4 Between. In fact, the BL is shared. In an alternative, the second layer may include another BL layer above the BL shown and below the 2WL layer. Although Figure 4D Two layers of 418 and 420 memory cells are shown, but the structure can extend upwards in a similar pattern through additional alternating layers of word lines and bit lines. Depending on the implementation, Figure 4D The word lines and bit lines of the array can be biased for read or program operations, such that current in each layer flows from the word line layer to the bit line layer or circulates in the opposite direction. For a given operation, the two layers can be configured to have current in the same direction in each layer, or to have current in opposite directions by selecting the driver in the positive or negative direction. Memory cells can be placed in the same orientation within the first and second layers, allowing reads or writes to be performed layer by layer using current in opposite directions. Alternatively, when placed between BL and WL in the second layer, the memory cells are placed in an inverted or flipped orientation (allowing the use of current in the same direction, such as for reading or writing memory cells within the first layer). It will be apparent to those skilled in the art that these two layers can be extended to three or more layers.

[0066] The use of a crosspoint architecture allows for arrays with a small footprint, and several such arrays can be formed on a single die. The memory cell formed at each crosspoint can be a resistor-type memory cell, where data values ​​are encoded as different resistance levels. Depending on the implementation, the memory cell can be a binary value with a low-resistance state or a high-resistance state, or a multilayer cell (MLC) that may have an additional resistance between the low-resistance and high-resistance states. The crosspoint arrays described herein can be used for... Figure 3A memory die 292, Figure 2 Local memory 140 and / or Figure 2 The host memory 124, or any other configuration in which additional memory is useful. Resistor-type memory cells can be formed according to many of the techniques mentioned herein, such as OTS. The following discussion is presented primarily in the context of memory arrays using crosspoint architecture with OTS memory cells having binary values, but much of the discussion is more generally applicable to other memory elements in memory cells within a crosspoint array or other configurations that are obvious to those skilled in the art.

[0067] Figure 5 The structure of one embodiment of the SOM unit is illustrated. The SOM unit 401 can be used as, for example... Figures 4A to 4D The programmable resistive memory cell 401 is described. The SOM cell includes a bottom electrode 501, a spacer layer 512, a threshold switch selector (TSS) memory element 502, a spacer layer 514, and a top electrode 511. In some embodiments, the bottom electrode 501 is a word line and the top electrode 511 is a bit line. In other embodiments, the bottom electrode 501 is a bit line and the top electrode 511 is a word line. The state of the memory cell is based on the state of the TSS memory element 502.

[0068] Data is written to the SOM memory cell by programming the TSS memory element 502 with a programming (or writing) signal (e.g., programming current, programming voltage) of the desired polarity. In one embodiment, the SOM memory cell is programmed to a first state (W0) using a first polarity programming signal and to a second state (W1) using a second polarity programming signal. The SOM memory cell can be read using a read signal (e.g., read current, read voltage). The polarity of the read signal relative to the polarity of the programming signal can affect the Vth of the SOM cell. In one embodiment, a read signal with the same polarity as the programming signal results in a lower Vth compared to a read signal with the opposite polarity to the programming signal. Typically, the memory system selects the polarity of the read signal and then aligns it with that polarity when determining the state of the SOM cell. Therefore, when reading with a read signal of the selected polarity, the polarity of the programming signal will actually result in a higher / lower Vth.

[0069] Threshold switch selector 502 can also function as a selector for selecting memory cells used in memory operations. Threshold switch selector 502 has high resistance (in an off or non-conductive state) until it is biased to a voltage higher than its threshold voltage (Vth) or a current higher than its threshold current, and until its voltage bias drops below Vhold (also known as "Voffset") or its current drops below Ihold. After exceeding Vth and exceeding Vhold across the selector, the selector has low resistance (in an on or conductive state). The threshold switch selector remains on until its current drops below the holding current Ihold, or its voltage drops below the holding voltage Vhold. When this occurs, the threshold switch selector returns to the off (higher) resistance state. Therefore, to select a memory cell at a crossover point, a voltage or current sufficient to turn on the associated threshold switch selector is applied. An example set of threshold switch selectors is a bidirectional threshold switch (OTS) material. Exemplary threshold switch materials include Ge-Se, Ge-Se-N, Ge-Se-As, Ge-Se-Sb-N, Ge58Se42, GeTe6, Si-Te, Zn-Te, C-Te, B-Te, Ge-As-Te-Si-N, Ge-As-Se-Te-Si, and Ge-Se-As-Te, wherein the atomic percentage of each element ranges from a few percent to over 90%. In one embodiment, the threshold switch selector is a two-terminal device. The threshold switch selector 502 may also include additional conductive layers. For example, a spacer layer 514 is depicted between the switch selector 502 and the top electrode 511. The spacer layer 514 may be a single conductive layer or composed of multiple conductive layers. The threshold switch selector 502 may also include additional conductive layers at the interface with the bottom electrode 501. For example, a spacer layer 512 is depicted between the switch selector 502 and the bottom electrode 501. The spacer layer 512 at the interface with the bottom electrode 501 may be a single conductive layer or composed of multiple conductive layers. Examples of conductive layers adjacent to the OTS include carbon, carbon nitride, carbon silicon, tungsten carbide, titanium, titanium nitride, tungsten, tungsten nitride, tantalum, tantalum nitride, and others. Threshold voltage switches have a threshold voltage (Vt) above which the resistance of the device essentially changes from insulating or quasi-insulating to conductive.

[0070] Figure 6A An embodiment of a memory array 600 with a crosspoint architecture is depicted. The memory array 600 may be included in... Figure 3A or Figure 3BIn the memory structure 202, array 600 has a first set of conductive lines 606a to 606h and a second set of conductive lines 608a to 608d. In one embodiment, the first set of conductive lines 606a to 606h are word lines, and the second set of conductive lines 608a to 608b are bit lines. For ease of discussion, the first set of conductive lines 606a to 606h may be referred to as word lines, and the second set of conductive lines 608a to 608b may be referred to as bit lines. However, the first set of conductive lines 606a to 606h can be bit lines, and the second set of conductive lines 608a to 608b can be word lines.

[0071] The memory array 600 has a plurality of programmable resistor memory cells 401. The programmable resistor memory cells 401 may be referred to as self-select memory cells or selector-only memory cells. In one embodiment, each cell 401 has a similar... Figure 5 The structure of the cells in the memory. Each memory cell 401 is connected between a first conductive line in the first conductive line 606 and a second conductive line in the second conductive line 608 (e.g., at the intersection of a first conductive line in the first conductive line 606 and a second conductive line in the second conductive line 608). Each SOM cell 401 has a threshold switch selector ( Figure 6A (Not depicted in the image). The threshold switch selector 502 becomes conductive in response to an applied voltage level exceeding its threshold voltage and remains conductive with lower resistance until the current through the switch selector 502 decreases below the selector holding current Ihold. The threshold switch selector 502 may be a two-terminal device. In one embodiment, the threshold switch selector 502 includes an OTS.

[0072] Techniques for programming SOM cells are disclosed. For discussion purposes, memory cell 401a is selected for memory operations such as read or write. An example of programming a threshold switch selector 502 will be discussed. The selected memory cell 401a is located at the intersection of a selected word line 606g and a selected bit line 608b. A selected memory cell refers to a memory cell selected for memory operations (such as read or write). The selected memory cell is connected between the selected word line and the selected bit line. In one embodiment, to program the selected memory cell 401a, a selection voltage, such as near-ground, is provided to the selected bit line (e.g., bit line 608b) and a programming (or write) voltage (Vs) is applied to the selected word line (e.g., word line 606g). A selected word line refers to a word line connected to at least one selected memory cell. Alternatively, a memory cell can be selected by applying a programming voltage (Vs) to the selected bit line while simultaneously applying a selection voltage to the selected word line.

[0073] In one method, word lines not connected to the selected memory cell can be driven by a voltage approximately half the magnitude of the voltage across the selected cell. For example... Figure 6A As depicted, word lines 606a, 606b, 606c, 606d, 606e, 606f, and 606h each have a so-called half-select voltage (Vs / 2) applied to them. The half-select voltage (Vs / 2) is approximately half the magnitude of the voltage (Vs) across the selected cell. For programming, voltage Vs may be referred to as the programming voltage. For example, voltage Vs may be referred to as the read voltage.

[0074] In one method, bit lines not connected to the selected memory cell can be driven by a voltage approximately half the magnitude of the voltage across the selected cell. For example... Figure 6A As depicted, bit lines 608a, 608c, and 608d each have a so-called half-select voltage (Vs / 2) applied to them. As mentioned above, the half-select voltage (Vs / 2) has approximately half the magnitude of the voltage (Vs) across the selected cell.

[0075] Some memory cells connected to the selected word line are referred to herein as half-select memory cells. The voltage across the half-select memory cell is approximately half the voltage across the selected memory cell. Each half-select memory cell 401b connected to the selected word line has a Vs applied to the selected word line and a Vs / 2 applied to its corresponding bit line. Therefore, each half-select memory cell 401b has a Vs / 2 applied across the memory cell.

[0076] Some memory cells connected to the selected bit lines are referred to herein as half-select memory cells. The voltage across these half-select memory cells is approximately half the voltage across the selected memory cell. Each half-select memory cell 401c connected to the selected bit line has 0V applied to the selected bit line and Vs / 2 applied to its corresponding word line. Therefore, each half-select memory cell 401c has Vs / 2 applied across the memory cell.

[0077] The threshold switch selector 502 in the half-select memory cells 401b and 401c should not be turned on during operations such as read or write. However, if the Vth of the threshold switch selector 502 is less than Vs / 2, the threshold switch selector 502 may be turned on during memory operations. This document discloses techniques for preventing the threshold switch selector 502 in the half-select memory cells 401b and 401c from being turned on (or at least reducing the chance of it being turned on during memory operations such as read or write). In one embodiment, the Vth drift is removed from the memory cell before programming, which allows the programming voltage to have a lower value. Using a lower value for the programming voltage will reduce the value of Vs / 2, which reduces the probability of accidental selection of the half-select memory cell.

[0078] Other memory cells are completely unselected, meaning they have approximately 0V across memory cells. Figure 6A The document indicates a completely unselected memory cell 401d. In this example, each completely unselected memory cell 401d applies Vs / 2 to its word line and applies Vs / 2 to its bit line.

[0079] exist Figure 6A In one example, the number of word lines in the cross-point array exceeds the number of bit lines. In another implementation, the number of bit lines in the cross-point array exceeds the number of word lines. In yet another implementation, the number of bit lines in the cross-point array equals the number of word lines. Figure 6A In the example, the number of word lines in the cross-point array is twice the number of bit lines; however, different ratios can be used. This allows for different stripe sizes. For example, a stripe could have 1024 BLs multiplied by 2048 WLs, which can be configured as a 2048×4096-cell module by center-driving the WLs and BLs between four stripes. In one implementation, a read or write operation is performed on a set of memory cells by, for example, selecting a memory cell in each of a plurality of stripes. In some implementations, more than one memory cell from a stripe can be selected for a read operation.

[0080] Figure 6A A voltage forcing method is shown and described, in which voltage is supplied to a selected word line. In one embodiment, a current forcing method is used to access the SOM cell. This current forcing method can be used to read or write the SOM cell. Figure 6B An example of a current-forced method is depicted. In the current-forced method, an access current (e.g., I0) is used. 存取 Driven to (or drawn from the selected word line) the access current, depending on I. 存取The selected bit line can be kept grounded. Therefore, current charges the voltage on the selected word line. In one embodiment, the maximum magnitude of the selected word line voltage will be limited to Vs. Alternatively, the selected bit line can be kept at a higher voltage, where current is drawn from the selected word line. Unselected word lines and unselected bit lines are voltaged. The magnitude of the voltage to the unselected word lines and unselected bit lines can be similar to... Figure 6A Examples are provided. The semi-selection problem discussed in conjunction with the voltage-forced method can also occur in the current-forced method. In this document, terms such as programming signal can include both programming voltage and programming current. Similarly, terms such as read signal can include both read voltage and read current.

[0081] Figure 7 This is a flowchart of one embodiment of the process 700 for programming SOM cells 401 in a crosspoint array. Process 700 can be used to program SOM cells 401 (such as...) Figure 5 The SOM unit 401 is programmed (as discussed in the document). In one embodiment, the SOM unit 401 includes an OTS that acts as a programmable resistive memory element. The process 700 can be executed in parallel across a number of memory cells, such as in selected memory cells within different blocks 600. In one embodiment, the process 700 is executed by one or more control circuits (such as, but not limited to, memory controller 102, system control logic 260, column control circuitry 210, row control circuitry 220, microcontroller, state machine, host processor 122 and / or other control circuitry, or one or more other similar circuitry for controlling non-volatile memory).

[0082] Step 702 includes selecting a first polarity for a future read signal applied to SOM cell 401. Step 702 can be omitted if the selection of the first polarity has already been set and does not need to be changed. The first polarity can be positive or negative. The current polarity can be defined based on the voltage across the cell generated by the current. Here, the positive or negative polarity can be defined relative to, for example, selected word lines and selected bit lines.

[0083] Step 704 includes determining whether to store the first bit value or the second bit value in SOM unit 401. As an example, the first bit value is "0" and the second bit value is "1". As another example, the first bit value is "1" and the second bit value is "0". However, the bit value can be the opposite of this example.

[0084] If the first value is to be stored, step 706 is executed. Step 706 involves applying a programming (or writing) signal with a first polarity to SOM cell 401. Therefore, if the cell is read in the future, the programming signal in step 706 has the same polarity as the read signal.

[0085] If a second bit value is to be stored, step 708 is executed. Step 708 includes applying a programming signal with a second polarity to SOM cell 401. The second polarity is opposite to the first polarity. Therefore, the programming signal in step 708 has a polarity opposite to the future read signal. In steps 702, 706, and 708, current-forced or voltage-forced techniques can be used to apply the signal.

[0086] Figure 8 An exemplary Vth distribution of a set of SOM units 402 is depicted after programming using process 700. Figure 8 Two “Vth distributions” for SOM cell 401 are depicted, as they will be measured when read using a read signal of the first polarity discussed in process 700. Vth distribution 810 represents SOM cell 401 storing the first bit value. Vth distribution 820 represents SOM cell 401 storing the second bit value. The vertical axis represents the number of memory cells and is on a logarithmic scale. The horizontal axis represents the Vth of the threshold switch selector, assuming that SOM cell 401 is read with a read voltage having a pre-assigned first polarity. A reference resistor R_ref is depicted between the two Vth distributions 810 and 820. In one embodiment, R_ref is used to distinguish the two Vth distributions. Note that if the SOM cell is instead read using a read signal with the second polarity, Vth distributions 810 and 820 can be reversed.

[0087] Figure 9A Table 950 details one implementation of programming SOM cells in a crosspoint memory structure. Before programming, the memory cell can be in either a W0 or W1 state. The “Final Strike” column 952 refers to the final signal that fires (e.g., turns on) the memory cell to be programmed. The final strike can be a write signal or a read signal. In this example, for a normal read operation, the read signal has the same polarity as the write signal used to program to the W0 state. The arrows in Table 950 depict the relative polarities of the read and write signals. The normal read signal is referred to as R0 because it has the same polarity as the signal used to program to the W0 state. Read and write signals can be voltage or current. The “New Data” column 954 indicates how the memory cell will be programmed. In this example, a cell currently in the W1 state can be programmed to either the W1 or W0 state. A cell currently in the W0 state can be programmed to either the W1 or W0 state.

[0088] Step 1 in this example is referred to as "read down," which refers to the downward arrow in Step 1 of Table 950. The "up arrow" and "down arrow" in Table 950 refer to the relative polarity of the signal. Step 2 in this example is referred to as "read up," which refers to the upward arrow in Step 2 of Table 950. The term "read" is used for steps 1 and 2 because the signal magnitude is similar to a normal read signal (and less than a typical programming voltage). However, the memory system does not need to determine the state of a memory cell in response to the application of a "read signal." In steps 1 and 2, a read signal can be applied to all memory cells in the group to be programmed. Step 3 in this example encompasses both "write down" and "write up." Write down refers to the downward arrow in Step 3 of Table 950. Write up refers to the upward arrow in Step 3 of Table 950. Only the write signal is selectively applied to those memory cells that will be programmed to the state associated with the write signal. Steps 1 and 2 are referred to as reads and are performed before programming in step 3. However, the order of reads in steps 1 and 2 can be switched. Write-up and write-down can be separated into separate write-up and write-down steps.

[0089] Reference Figure 9B Let’s discuss Table 950 in more detail. Figure 9B The threshold voltage over time is depicted for one embodiment of a SOM cell in an operational crosspoint memory structure. A memory cell programmed to the W0 state may have a Vth at approximately C_low only after programming (t0). A memory cell programmed to the W1 state may have a Vth at approximately C_high only after programming (t0). The foregoing assumes that a read is performed with an R0 signal having the same polarity as the signal used for programming to W0. In this document, the terms "low Vth state" and "high Vth state" are used to refer to two such states with different threshold voltages (programmed with different polarity programming voltages) assuming a default polarity read signal. Curve 906 depicts the upward drift of the Vth of the threshold switch selector in the SOM cell programmed to the W0 state. By t1, the Vth of the W0 cell has drifted to "B". Curve 908 depicts the upward drift of the Vth of the threshold switch selector in the SOM cell programmed to the W1 state. By t1, the Vth of the W1 cell has drifted to "A". Figure 9B The amount of Vth drift described in the paper is quite large, but even smaller Vth drifts can lead to problems such as the semi-selection problem.

[0090] Figure 9ATable 950, column 956, outlines the Vth of a particular cell, which depends on the relative polarity of the final trigger voltage (column 952) and the polarity of the write voltage (column 954). A cell with a final trigger of W1 and new data of W1 has the same polarity voltage for both; therefore, during the write of new data, the cell has a low Vth of B. However, a cell with a final trigger of W1 and new data of W0 has opposite polarity voltages for both; therefore, during the write of new data, the cell has a high Vth of A. A cell with a final trigger of W0 (or R0) and new data of W1 has opposite polarity voltages for both; therefore, during the write of new data, the cell has a high Vth of A. A cell with a final trigger of W0 (or R0) and new data of W0 has the same polarity voltage for both; therefore, during the write of new data, the cell has a low Vth of B.

[0091] Referring now to one embodiment of the programming procedure, step 1 may include applying a read-down signal to all cells in a set of cells to be programmed. For ease of discussion, the read signal will be referred to as the read voltage. However, the read signal may be a read current that increases (or decreases) the selected word line voltage to produce a voltage across the selected memory cell (this voltage may be clamped or otherwise limited to the maximum read voltage). Step 1 triggers (connects) all memory cells having a value Vth at or below the maximum read voltage. Reference Figure 9B The maximum read voltage can be "MaxV for reading". This downward read voltage will activate the selector in the cell that ultimately fires to W0. Furthermore, the selector can refresh Vth, causing Vth to decrease from B to C. See also Figure 9B Curve 906 shows that Vth refreshes from level B (at t1) back to level C_low (at t0). However, cell W1 has a Vth higher than the MaxV used for reading and is therefore not triggered (fired) by the down-read voltage. Therefore, cell W1 is not refreshed.

[0092] Step 2 is an upward read, whose firing (activation) ultimately programs the memory cell to W1. This upward read signal can be applied to all memory cells in the group to be programmed. Note that the upward read has the same polarity as the W1 signal. Therefore, this has a lower Vth effect for the W1 cell. Thus, step 2 indicates that the W1 cell has a Vth of B. (Reference) Figure 9BThe maximum value of the read voltage can be in the "MaxV for Read". However, the polarity of the read voltage is opposite to that of the read voltage in step 1. This upward read voltage will turn on the selector in the cell that is ultimately triggered as W1. Therefore, curve 908 can be viewed as the curve of Vth under the assumption of downward read. However, applying an upward read voltage can be seen as moving cell W1 from curve 906 to curve 908. As a result, the upward read voltage has a sufficient value to turn on (trigger) the selector in cell W1. Therefore, the selector in cell W1 can be refreshed. Vth can decrease from B to C. See also Figure 9B Curve 906 in the diagram shows that, assuming the cell is read again with an upward read voltage, Vth can be refreshed from level B (at t1) to level C_low (at t0). However, reading the cell again with a downward read voltage produces a Vth of C_high.

[0093] Step 3 in this example covers both write-down and write-up. Only the write-down signal is applied to those cells that will be written to the W0 state. Assuming the default read signal is write-down, all cells written by defining write-down end in the C_low state. Only the write-up signal is applied to those cells that will be written to the W1 state. Assuming the default read signal is write-down, all cells written by defining write-up end in the C_high state.

[0094] The programming process allows for a reduction in the programming voltage while still maintaining sufficient HS margin. (Reference) Figure 9B Below are some exemplary values ​​to illustrate. The value of C_low can be approximately 2.5V. The value of C_high can be approximately 3.5V. The Vth drift amount during the exemplary time period can be approximately 0.5V (for both states). Therefore, the maximum drift value for the high Vth state can be approximately 4.0V, and the maximum drift value for the low Vth state can be approximately 3.0V. In this example, the value of MaxV used for reading can be approximately 3.25V. Therefore, the MaxV used for reading can be at the midpoint between the maximum drift value for low Vth and the maximum drift value for high Vth. Applying +3.25V across cells turns on the threshold switch selector for the low Vth state. Applying -3.25V across cells turns on the threshold switch selector for the high Vth state. Assuming that the cell used for the high Vth state is refreshed to approximately 3.5V (positive in this example for the default read polarity), a programming voltage of approximately 3.7V can be used to allow for a safety margin. The programming voltages used for both states can have the same magnitude but opposite polarities.

[0095] Figure 10This is a flowchart of one embodiment of a process 1000 for programming SOM cells in a crosspoint memory structure. Each SOM cell has a threshold switch selector, such as, but not limited to, an OTS. Process 1000 may employ voltage forcing techniques (such as in...) Figure 6A (in) or current forcing technology (such as in) Figure 6B (Middle). Step 1002 includes applying a first signal having a first polarity to a set of memory cells selected for programming. In one embodiment, the set includes one memory cell in each of a plurality of blocks. The first signal activates a threshold switch selector in a first set of the memory cells. The first set of memory cells may be, for example, memory cells ultimately programmed as W0. In one embodiment, a memory cell ultimately programmed as W1 will not fire (e.g., the threshold switch selector will not be activated). Step 1002 may refresh the Vth of the threshold switch selector in the first set of cells. See also Figure 9B Curve 906 in the example demonstrates how Vth can be refreshed from level B to level C_low. (See reference...) Figure 6A The voltage Vs can be replaced by Vread. Step 1002 may include applying Vread to the selected word line while simultaneously applying 0V to the selected bit line. (See reference) Figure 6B Iaccess can be replaced by Iread, and Vs can be replaced by Vread. Step 1002 may include applying Iread to the selected word line while applying 0V to the selected bit line. In both the voltage-forced example and the current-forced example, there will be a positive voltage across the selected cell from the selected word line to the selected bit line. Additionally, in step 1002, Vread / 2 may be applied to both the unselected word line and the unselected bit line.

[0096] Step 1004 includes applying a second signal with a second polarity to the selected set of memory cells for programming. This second signal activates a threshold switch selector in the second set of memory cells. The second set of memory cells may be, for example, memory cells ultimately programmed as W1. The second signal may have the same magnitude as the first signal (but with the opposite polarity). Step 1004 may refresh the Vth of the threshold switch selector in the second set of cells. Step 1004 may include applying Vread to the selected bit line while applying 0V to the selected word line. Step 1004 may include applying a negative read current to the selected word line while applying Vs to the selected bit line. Here, the negative read current refers to the current driver drawing current from the selected word line. Additionally, in step 1004, Vread / 2 may be applied to both the unselected word line and the unselected bit line. In both the voltage-forced and current-forced examples, a negative voltage will exist across the selected cells from the selected word line to the selected bit line.

[0097] Step 1006 includes applying a third signal having the first polarity to a third set of the memory cells after both the first and second signals have been applied to the group of memory cells. The third signal programs the threshold switch selector of the memory cell in the third set to a first state. The third set of cells may include, for example, cells to be programmed to W0. See also Figure 9A This third set may include some units with a final firing 952 (before reading) having W1 and some units with a final firing 952 (before reading) having W0. (See reference) Figure 6A The voltage Vs can be replaced by Vwrite. Step 1006 may include applying Vwrite to the selected word line while simultaneously applying 0V to the selected bit line. (See reference) Figure 6B Iaccess can be replaced by Iwrite, and Vs can be replaced by Vwrite. Step 1006 may include applying Iwrite to the selected word line while applying 0V to the selected bit line. Additionally, in step 1006, Vwrite / 2 may be applied to both the unselected word line and the unselected bit line. In both the voltage-forced and current-forced examples, a positive voltage will exist across the selected cell from the selected word line to the selected bit line.

[0098] Step 1008 includes applying both the first signal and the second signal to the group of memory cells, followed by applying a fourth signal having the second polarity to a fourth set of memory cells in the group. The fourth signal programs the threshold switch selector of the memory cell in the fourth set to a second state. The fourth set of cells may include, for example, a cell to be programmed as W1. See also... Figure 9A This fourth set may include some units with a final firing 952 (before reading) having W1 and some units with a final firing 952 (before reading) having W0. (See reference) Figure 6A Step 1008 may include applying Vwrite to the selected bit line while simultaneously applying 0V to the selected word line. For unselected word lines and unselected bit lines, Vs may be replaced by Vwrite. (See reference) Figure 6B Iaccess can be replaced by Iwrite with a negative value (e.g., a current driver draws Iwrite from the selected word line 606g). Vs can be replaced by Vwrite. Additionally, in step 1008, Vwrite / 2 can be applied to the unselected word line and the unselected bit line. In both the voltage-forced example and the current-forced example, a negative voltage will exist across the selected cell from the selected word line to the selected bit line.

[0099] In one implementation, steps 1006 and 1008 are performed simultaneously. For example, selected SOM cells in each stripe of a first set of stripes may be written in step 1006, while selected SOM cells in each stripe of a second set of stripes may be written in step 1008. In one implementation, step 1006 is performed before step 1008. In one implementation, step 1008 is performed before step 1006.

[0100] Figure 11 This is a flowchart of one embodiment of a process 1100 for programming SOM cells in a crosspoint memory structure. Each SOM cell has a threshold switch selector, such as, but not limited to, an OTS. Process 1100 provides further details of one embodiment of process 1000. In one embodiment, the group of cells to be programmed contains one memory cell in each of a plurality of blocks. Process 1100 may employ voltage forcing techniques (such as...) Figure 6A (in) or current forcing technology (such as in) Figure 6B (In the middle). Step 1102 includes applying a first read signal to a group of memory cells to trigger cells programmed to a first state instead of a second state. As an example, the first read signal may trigger cells programmed to W0 instead of those programmed to W1. Triggering the cell causes the threshold switch selector to turn on, which refreshes the Vth of the threshold switch selector. Step 1102 may include applying Vread to the selected word line while applying 0V to the selected bit line. Step 1102 may include applying Iread to the selected word line while applying 0V to the selected bit line. When Iread is applied, the voltage across each memory cell may be limited or restricted.

[0101] Step 1104 includes applying a second read signal to a group of memory cells. The second read signal has the opposite polarity to the first read signal. Applying the second read signal generates the same maximum voltage across the memory cells as when the first read signal was applied. The second signal activates a threshold switch selector in at least a second set of the memory cells. The second set of memory cells may be, for example, memory cells ultimately programmed as W1. Step 1104 may refresh the Vth of the threshold switch selector in the second set of cells. Step 1104 may include applying Vread to a selected bit line while applying 0V to a selected word line. Step 1104 may include absorbing Iread from the selected word line while applying a selection voltage to the selected bit line. When Iread is applied, the voltage across each memory cell may be limited or restricted.

[0102] Step 1106 includes applying a first write signal to a first set of the group of cells to program the first set into the first state. The first write signal has the same polarity as the first read signal. The first set of cells may include, for example, cells to be programmed as W0. Step 1106 may include applying Vwrite to a selected word line while applying 0V to a selected bit line. Step 1106 may include applying Iwrite to a selected word line while applying 0V to a selected bit line.

[0103] Step 1108 includes applying a second write signal to a second set of the group of cells to program the second set into the second state. The second write signal has the opposite polarity to the first write signal. The second set of cells may include, for example, cells to be programmed as W1. Step 1108 may include applying Vwrite to a selected bit line while simultaneously applying 0V to a selected word line. Step 1108 may include absorbing Iwrite from the selected word line while simultaneously applying a selection voltage to the selected bit line.

[0104] In one embodiment, steps 1106 and 1108 are performed simultaneously. In one embodiment, step 1106 is performed before step 1108. In one embodiment, step 1108 is performed before step 1106.

[0105] Figure 12 This is a flowchart of one embodiment of a process 1200 for programming SOM cells in a crosspoint memory structure. Each SOM cell has a threshold switch selector, such as, but not limited to, an OTS. Process 1200 provides further details of one embodiment of process 1000. In one embodiment, the group of SOM cells to be programmed contains one memory cell in each of a plurality of blocks. Process 1200 may employ voltage forcing techniques (such as...) Figure 6A (in) or current forcing technology (such as in) Figure 6B (Middle). Step 1202 includes generating a first voltage across each cell in a set of memory cells to reduce threshold voltage drift of the threshold switch selector in the memory cells in the set most recently programmed to a first state. The first set of memory cells may be, for example, memory cells that were eventually programmed to W0. Step 1202 may include applying the first voltage to a selected word line while applying 0V to a selected bit line. Step 1202 may include applying current to the selected word line while applying 0V to the selected bit line to generate the first voltage across each cell. In one embodiment, the first voltage has a maximum value. In a current-forced method, a fixed value of current may be used to charge the selected word line, but the word line voltage may be limited to the maximum voltage.

[0106] Step 1204 includes generating a second voltage across each cell in the group of memory cells after the first voltage. The second voltage has the same magnitude as the first voltage but has the opposite polarity. This second voltage reduces the threshold voltage drift of the threshold switch selector in the memory cells in the group that were most recently programmed to a second state (e.g., W1). Step 1204 may include applying the second voltage to a selected bit line while applying 0V to a selected word line. Step 1204 may include drawing current from the selected word line while applying a high voltage to the selected bit line to generate the second voltage across each cell. In a current-forced method, the selected word line and the selected bit line may each be pre-charged to approximately half the final voltage of the selected bit line (e.g., 1.65V). The selected bit line can then be raised to a higher voltage (e.g., 3.3V) using current to reduce the voltage on the selected word line. In this example, the lowest voltage achievable by the selected word line is 0V. Therefore, the voltage across the selected cell is limited to the maximum voltage.

[0107] Step 1206 includes generating a third voltage with a first polarity across each cell in a first set of memory cells to program the threshold switch selector in the first set of memory cells into the first state. The first set of cells may include, for example, cells to be programmed as W0. Step 1206 may include applying Vwrite to a selected word line while simultaneously applying 0V to a selected bit line. Step 1206 may include applying a write current to the selected word line while simultaneously applying 0V to the selected bit line to generate the third voltage across each cell.

[0108] Step 1208 includes generating a fourth voltage with a second polarity across each cell in a second set of memory cells to program the threshold switch selector in the second set of memory cells into the second state. The second set of cells may include, for example, cells to be programmed as W1. Step 1208 may include applying Vwrite to a selected bit line while simultaneously applying 0V to a selected word line. Step 1208 may include drawing write current from the selected word line while simultaneously applying a high voltage to the selected bit line to generate a fourth voltage across each cell.

[0109] In one embodiment, steps 1206 and 1208 are performed simultaneously. In one embodiment, step 1206 is performed before step 1208. In one embodiment, step 1208 is performed before step 1206.

[0110] In view of the foregoing, it can be seen that, according to one embodiment, an apparatus includes one or more control circuits configured to be connected to a cross-point structure having self-selectable memory cells. Each self-selectable memory cell has a threshold switch selector. The one or more control circuits are configured to apply a first signal having a first polarity to a set of memory cells selected for programming. The first signal activates the threshold switch selector in a first set of the memory cells. The one or more control circuits are configured to apply a second signal having a second polarity to the set of memory cells selected for programming. The second signal activates the threshold switch selector in a second set of the memory cells. The one or more control circuits are configured to, after applying both the first signal and the second signal to the set of memory cells, apply a third signal having the first polarity to a third set of the set of memory cells. The third signal programs the threshold switch selector in the third set of memory cells to a first state. The one or more control circuits are configured to, after applying both the first signal and the second signal to the set of memory cells, apply a fourth signal having the second polarity to a fourth set of the set of memory cells. The fourth signal programs the threshold switch selector in the fourth set of the memory cells to a second state.

[0111] In another embodiment, the one or more control circuits are configured to set the magnitude of the first signal to generate a maximum voltage across the memory cells in the group between a first maximum drift threshold voltage of the memory cell most recently programmed to the first state and a second maximum drift threshold voltage of the memory cell most recently programmed to the second state.

[0112] In another embodiment, the one or more control circuits are configured to set the magnitude of the first signal to generate a maximum voltage across the memory cells in the group at the midpoint between a first maximum drift threshold voltage of the memory cells programmed to a low threshold voltage state and a second maximum drift threshold voltage of the memory cells programmed to a high threshold voltage state in the group.

[0113] In another embodiment, the first set of memory cells was recently programmed to the first state. The first signal has a magnitude and polarity that turns on the threshold switch selector of the memory cell recently programmed to the first state, but does not turn on the threshold switch selector of the memory cell recently programmed to the second state.

[0114] In another embodiment, the first signal has a magnitude and polarity for removing the drift of the threshold voltage of the threshold switch selector of the first set of memory cells, but does not turn on the threshold switch selector in the second set of memory cells.

[0115] In another embodiment, the second signal has a magnitude and polarity of the threshold voltage drift of the threshold switch selector of the second set of memory cells recently programmed to the second state.

[0116] In another embodiment, the first signal has a magnitude for distinguishing the first state from the second state. The second signal also has the magnitude for distinguishing the first state from the second state.

[0117] In another embodiment, the one or more control circuits are configured to simultaneously apply the third signal to the third set of the set of memory cells and apply the fourth signal to the fourth set of the set of memory cells.

[0118] In another embodiment, the one or more control circuits are configured to apply the third signal to the third set of memory cells and the fourth signal to the fourth set of memory cells without determining the state of the memory cells in response to the first signal or the second signal.

[0119] In another embodiment, the first signal and the second signal are voltages having substantially the same magnitude.

[0120] In another embodiment, the first signal and the second signal are currents having substantially the same magnitude.

[0121] One embodiment includes a method for operating a crosspoint memory structure having self-selecting memory cells. The method includes applying a first read signal to a group of memory cells, the first read signal triggering memory cells recently programmed to a first state but not triggering memory cells recently programmed to a second state. The first read signal has a first polarity and generates a first maximum voltage across each specific cell in the group. The method includes, after applying the first read signal to the group, applying a second read signal to the group of memory cells. The second read signal has a second polarity opposite to the first polarity and generates the first maximum voltage across each specific cell in the group. The method includes, after applying both the first read signal and the second read signal to the group of memory cells, applying a first write signal to a first set of the group of memory cells to write the first set to the first state. The first write signal has the first polarity. The method includes, after applying both the first read signal and the second read signal to the group of memory cells, applying a second write signal to a second set of the group of memory cells to write the second set to the second state. The second write signal has the second polarity.

[0122] One embodiment includes a memory system comprising a crosspoint memory structure having a first conductive line, a second conductive line, and memory cells. Each memory cell is located at a junction of a first conductive line and a second conductive line. Each memory cell has a threshold switch selector. The memory system has one or more control circuits in communication with the crosspoint memory structure. The one or more control circuits are configured to generate a first voltage across each memory cell in a set of memory cells selected for programming. The first voltage has a first maximum value and a first polarity, the first polarity reducing the threshold voltage drift of the threshold switch selector in the memory cell in the set most recently programmed to a first state. The one or more control circuits are configured to generate a second voltage across each memory cell in the set of memory cells after generating the first voltage. The second voltage substantially has the first maximum value and a second polarity opposite to the first polarity. The one or more control circuits are configured to generate a third voltage having the first polarity across each memory cell in a first set of memory cells in the set to program the threshold switch selector in the first set of memory cells to the first state. The third voltage is generated after both the first and second voltages are generated. The one or more control circuits are configured to generate a fourth voltage of the second polarity across each memory cell in a second set of memory cells in the group to program the threshold switch selector in the second set of memory cells into a second state. The fourth voltage is generated after both the first and second voltages are generated.

[0123] For the purposes of this document, the terms “implementation scheme,” “one implementation scheme,” “some implementation schemes,” or “another implementation scheme” used in the specification may be used to describe different implementation schemes or the same implementation scheme.

[0124] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is mentioned as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via an intermediary element. When an element is mentioned as being directly connected to another element, there is no intermediary element between the two elements. If two devices are directly or indirectly connected, the two devices are “communicating”, enabling them to communicate electronic signals between them.

[0125] For the purposes of this document, the term “based on” may be understood as “at least partially based on”.

[0126] For the purposes of this document, the use of numerical terms such as “first” object, “second” object, and “third” object without additional context may not imply an ordering of objects, but may be used for identification purposes to distinguish different objects.

[0127] The terms “top” and “bottom,” “upper” and “lower,” and “vertical” and “horizontal,” and their forms, as used herein, are used only by way of example and for illustrative purposes, and are not intended to limit the description of the technique, as the items cited may be interchanged in position and orientation. Additionally, as used herein, the terms “substantially” and / or “about” mean that a specified dimension or parameter may vary within acceptable tolerances for a given application.

[0128] The specific embodiments described above have been provided for illustrative and descriptive purposes. They are not intended to be exhaustive or to limit the precise forms disclosed in the invention. Many modifications and variations are possible based on the teachings above. The described embodiments were chosen to best explain the principles of the proposed technology and its practical application, thereby enabling others skilled in the art to best utilize it in various embodiments and various modifications suitable for the specific intended use. The scope of the invention is intended to be defined by the appended claims.

Claims

1. An apparatus, the apparatus comprising: one or more control circuits configured to connect to a cross-point structure having self-selecting memory cells, each self-selecting memory cell having a threshold switch selector, the one or more control circuits configured to: apply a first signal having a first polarity to a set of memory cells selected for programming, the first signal turning on the threshold switch selectors in a first set of the memory cells; apply a second signal having a second polarity to the set of memory cells selected for programming, the second signal turning on the threshold switch selectors in a second set of the memory cells; after applying both the first signal and the second signal to the set of memory cells, apply a third signal having the first polarity to a third set of the set of memory cells, the third signal programming the threshold switch selectors in the third set of the memory cells to a first state; and after applying both the first signal and the second signal to the set of memory cells, apply a fourth signal having the second polarity to a fourth set of the set of memory cells, the fourth signal programming the threshold switch selectors in the fourth set of the memory cells to a second state.

2. The apparatus of claim 1, wherein the one or more control circuits are configured to set a magnitude of the first signal to produce a maximum voltage across the memory cells in the set between a first highest drift threshold voltage of a memory cell in the set most recently programmed to the first state and a second highest drift threshold voltage of a memory cell in the set most recently programmed to the second state.

3. The apparatus of claim 1, wherein the one or more control circuits are configured to set a magnitude of the first signal to produce a maximum voltage across the memory cells in the set at a midpoint between a first highest drift threshold voltage of a memory cell in the set programmed to a low threshold voltage state and a second highest drift threshold voltage of a memory cell in the set programmed to a high threshold voltage state.

4. The apparatus of claim 1, wherein the first set of the memory cells are most recently programmed to the first state, the first signal having a magnitude and polarity that turns on the threshold switch selectors of memory cells most recently programmed to the first state but not the threshold switch selectors of memory cells most recently programmed to the second state.

5. The apparatus of claim 1, wherein the first signal has a magnitude and polarity to remove a drift of threshold voltages of the threshold switch selectors of the first set of the memory cells but does not turn on the threshold switch selectors in the second set of the memory cells.

6. The apparatus of claim 5, wherein the second signal has a magnitude and polarity to remove a drift of a threshold voltage of the threshold switch selector of the second set of the memory cells that were most recently programmed to the second state.

7. The apparatus of claim 1, wherein: the first signal has a magnitude to distinguish the first state from the second state; and the second signal has the magnitude to distinguish the first state from the second state.

8. The apparatus of claim 1, wherein the one or more control circuits are configured to simultaneously apply the third signal to the third set of the group of memory cells and apply the fourth signal to the fourth set of the group of memory cells.

9. The apparatus of claim 1, wherein the one or more control circuits are configured to: apply the third signal to the third set of the memory cells and apply the fourth signal to the fourth set of the memory cells without determining a memory cell state in response to the first signal or the second signal.

10. The apparatus of claim 1, wherein the first signal and the second signal are voltages having substantially the same magnitude.

11. The apparatus of claim 1, wherein the first signal and the second signal are currents having substantially the same magnitude.

12. A method for operating a cross-point memory structure having self-selecting memory cells, the method comprising: applying a first read signal to a group of the memory cells, the first read signal triggering memory cells that were most recently programmed to a first state but not triggering memory cells that were most recently programmed to a second state, the first read signal having a first polarity and producing a first maximum voltage across each particular cell in the group; after applying the first read signal to the group, applying a second read signal to the group of the memory cells, the second read signal having a second polarity opposite the first polarity and producing the first maximum voltage across each particular cell in the group; after applying both the first read signal and the second read signal to the group of the memory cells, applying a first write signal to a first set of the group of memory cells to program the first set to the first state, the first write signal having the first polarity; and after applying both the first read signal and the second read signal to the group of the memory cells, applying a second write signal to a second set of the group of memory cells to program the second set to the second state, the second write signal having the second polarity.

13. The method of claim 12, the method further comprising: ​ The magnitude of the first read signal is set to produce a maximum voltage across the memory cells in the group between a first highest drifted threshold voltage of a memory cell in the group most recently programmed to the first state and a second highest drifted threshold voltage of a memory cell in the group most recently programmed to the second state.

14. The method of claim 12, further comprising: The magnitude of the first read signal is set to produce a maximum voltage across the memory cells in the group at a midpoint between a first highest drifted threshold voltage of a memory cell programmed to a low threshold voltage state and a second highest drifted threshold voltage of a memory cell programmed to a high threshold voltage state.

15. The method of claim 12, wherein applying the first write signal to the first set of the group and applying the second write signal to the second set of the group is performed without determining a memory cell state in response to the first read signal or the second read signal.

16. A memory system, comprising: a cross-point memory structure having first conductive lines, second conductive lines, and memory cells, each memory cell at a junction of one of the first conductive lines and one of the second conductive lines, each memory cell having a threshold switch selector; one or more control circuits in communication with the cross-point memory structure, the one or more control circuits configured to: produce a first voltage across each memory cell in a group of memory cells selected for programming, the first voltage having a first maximum magnitude and a first polarity that reduces a threshold voltage drift of the threshold switch selector in a memory cell in the group most recently programmed to a first state; after producing the first voltage across the group of memory cells, produce a second voltage across each memory cell in the group of memory cells, the second voltage having substantially the first maximum magnitude and a second polarity opposite the first polarity; produce a third voltage having the first polarity across each memory cell in a first set of memory cells in the group to program the threshold switch selector in the first set of memory cells to the first state, the third voltage produced after both the first voltage and the second voltage are produced; and produce a fourth voltage having the second polarity across each memory cell in a second set of memory cells in the group to program the threshold switch selector in the second set of memory cells to a second state, the fourth voltage produced after both the first voltage and the second voltage are produced.

17. The memory system of claim 16, wherein the one or more control circuits are configured to cause the first maximum magnitude of the first voltage to be between a first highest drifted threshold voltage of the memory cells most recently programmed to the first state and a second highest drifted threshold voltage of memory cells most recently programmed to the second state.

18. The memory system of claim 16, wherein the one or more control circuits are configured to cause the first maximum magnitude of the first voltage to be at a midpoint between a first highest drifted threshold voltage of memory cells programmed to a low threshold voltage state and a second highest drifted threshold voltage of memory cells programmed to a high threshold voltage state.

19. The memory system of claim 16, wherein the one or more control circuits are configured to: cause the first maximum magnitude of the first voltage to refresh drifted threshold voltages of the memory cells most recently programmed to the first state without triggering the threshold switch selector in the memory cells most recently programmed to the second state.

20. The memory system of claim 16, wherein the one or more control circuits are configured to: generate the third voltage across memory cells in the first set and the fourth voltage across memory cells in the second set simultaneously.

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