Driver circuitry for high density memory banks

Abstract

The invention relates to driver circuitry for high density memory banks. A memory bank of a memory device may include a plurality of memory cells arranged along a plurality of column select lines and row select lines. Column driver circuitry may include a column driver coupled to the column select line. The column driver may generate a column select signal having a plurality of voltage steps for accessing target memory cells coupled to respective column select lines. A column decoder may include circuitry to adjust a voltage level and / or duration of each voltage step of the column select signal based on a placement of a target memory cell along a column select line to provide a desired voltage level to the target memory cell. For example, the column decoder may output a higher voltage level and then a lower voltage level to access the target memory cell. The higher voltage level and the lower voltage level may be higher than a threshold voltage level for accessing the target memory cell.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 664,868, filed June 27, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to memory devices. More specifically, this disclosure relates to column decoder circuitry and row decoder circuitry of memory devices. Background Technology

[0004] A memory device may include multiple memory banks. Each memory bank may include multiple memory cells arranged in multiple columns and rows. Each memory cell in a memory bank may be coupled to column select lines and row select lines of the memory bank. The memory device may receive memory access requests for one or more of the memory cells. In response to a memory access request, the column decoder of the memory device may output a column select signal to the column select line coupled to the target memory cell. Furthermore, the row decoder of the memory device may output a row select signal to the row select line coupled to the target memory cell. The target memory cell may be accessed based on the received column select signal and row select signal. The target memory cell may be accessed for writing data or reading stored data.

[0005] It is generally desirable to increase the storage capacity of a memory bank and / or memory device. A memory bank may include additional memory cells to increase storage capacity. For example, additional memory cells may be arranged along columns and rows of memory cells, thereby increasing the length of the column select lines and / or row select lines. A column decoder may be coupled to one side of a column. Furthermore, the resistance and parasitic capacitance for accessing a target memory cell are at least partially based on the length of the column select lines that couple the column decoder to the target memory cell. Therefore, the resistance and / or parasitic capacitance for accessing distant memory cells in the memory bank may be increased based on the increased length of the corresponding column select lines. The distant memory cells may be located at the far end of the column select lines, close to the side of the memory bank opposite to the side coupled to the column decoder. Without compensation, the increased resistance and / or parasitic capacitance would reduce the voltage and / or current of the column select signal used to access the distant memory cells. Therefore, it is desirable to compensate for the increased resistance and / or parasitic capacitance associated with accessing memory cells at the far end of the column decoder and / or row decoder or near its opposite side. Summary of the Invention

[0006] On one hand, this disclosure provides a memory device comprising: a plurality of memory cells coupled to a plurality of column select lines; and a column driver coupled to one of the column select lines, wherein the column driver is configured to generate a single column select signal having at least two voltage levels to access a target memory cell among the plurality of memory cells coupled to the column select lines.

[0007] On the other hand, this disclosure further provides a memory device comprising: a plurality of memory cells coupled to a plurality of column select lines; a first supply voltage; a second supply voltage; and a column driver coupled to one of the plurality of column select lines, wherein the column driver is configured to generate a single column select signal having at least two voltage levels based on the coupling to the first supply voltage and the second supply voltage.

[0008] On the other hand, this disclosure further provides a memory device comprising: a plurality of memory cells coupled to a plurality of column select lines; a first supply voltage; a voltage adjustment circuit configured to provide a second supply voltage based on a column address of a first target memory cell among the plurality of memory cells; and a column driver coupled to the first supply voltage, the second supply voltage, and the column select lines among the plurality of column select lines, wherein the column driver is configured to generate a single column select signal having a first voltage level based on coupling to the first supply voltage and to generate a single column select signal having a second voltage level based on coupling to the second supply voltage. Attached Figure Description

[0009] A better understanding of the various aspects of this disclosure can be achieved by reading the following detailed description and referring to the diagrams described below, wherein similar numbers refer to similar parts.

[0010] Figure 1 A simplified block diagram illustrating certain features of a memory device according to embodiments of the present disclosure;

[0011] Figure 2 It has a control circuit system according to embodiments of the present disclosure. Figure 1 A block diagram of the storage bank of a memory device;

[0012] Figure 3 According to embodiments of this disclosure Figure 1 and 2 A block diagram of the column driver circuit system for a memory device;

[0013] Figure 4 It is an embodiment of the present disclosure having near and far ground terminals of the column select line coupled to the memory bank. Figures 1 to 3 A block diagram of the first column driver group of the column driver circuit system of the memory device;

[0014] Figure 5 According to embodiments of this disclosure Figure 4 The column driver of the first column driver group;

[0015] Figure 6 It is a pull-up switch according to an embodiment of the present disclosure. Figure 4 The column driver of the first column driver group;

[0016] Figure 7 This describes an embodiment of the present disclosure for controlling Figure 5 A block diagram showing the switching of a column driver of 6 to provide a control signal with a common supply voltage having two voltage steps;

[0017] Figure 8 This describes an embodiment of the present disclosure that has a basis Figure 7 The two voltage steps of the control signal are caused by Figures 4 to 6 A graph of the column selection signal generated by the selected column driver;

[0018] Figure 9 This describes the embodiments according to the present disclosure. Figure 5 Or 6 column drivers based Figure 4 Or the column selection line on the near and far sides of column 6 Figure 7 The control signal generated Figure 8 A graph showing the voltage levels of the column selection signal;

[0019] Figure 10 This is an embodiment of the present disclosure for adjusting based on the column address of the target memory cell. Figure 4 , 5 A second voltage adjustment circuit for multiple voltage levels of the column driver of column 6;

[0020] Figure 11 The generation of a three-level array selection signal is based on an embodiment of this disclosure. Figures 1 to 3 The second column driver group of the column driver circuit system for the memory device;

[0021] Figure 12 According to embodiments of this disclosure Figure 11 The column driver of the second column driver group;

[0022] Figure 13 This describes an embodiment of the present disclosure for controlling Figure 11 and 12 The timing diagram of the column driver switches to provide a control signal with a common supply voltage having three voltage steps;

[0023] Figure 14This describes the embodiments according to the present disclosure. Figure 12 The column driver is based on the above regarding Figures 11 to 13 The discussion arises from the three voltage steps. Figure 11 and 12 The graph of the column selection signal;

[0024] Figure 15 This describes the embodiments according to the present disclosure. Figure 12 Column driver based Figure 11 and 12 The column selection line on the proximal and distal sides Figure 13 The control signal generated Figure 14 A graph showing the voltage levels of the column selection signal;

[0025] Figure 16 This is an embodiment of the present disclosure for adjusting based on the column address of the target memory cell. Figure 11 and 12 A second voltage adjustment circuit for multiple voltage levels of the column driver;

[0026] Figure 17 This is an embodiment of the present disclosure for adjusting the column address of the target memory cell to provide Figures 13 to 15 A delay circuit for the duration of multiple voltage levels of the column selection signal; and

[0027] Figure 18 It is an embodiment of the present disclosure having separate column select line drivers for near and far memory cells of the memory bank. Figures 1 to 3 The third column driver group of the column driver circuit system for the memory device. Detailed Implementation

[0028] When elements of the various embodiments of this disclosure are introduced, the articles “a” and “described” are intended to mean the presence of one or more elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that additional elements besides those listed may be present. Furthermore, it should be understood that reference to “an embodiment” or “an embodiment” of this disclosure is not intended to be interpreted as excluding the existence of additional embodiments also incorporated into the described features. Additionally, specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. The use of the terms “approximately,” “almost,” “about,” “close to,” and / or “substantially” should be understood to mean including approximate targets (e.g., designs, values, quantities), such as within any suitable or acceptable tolerance of error (e.g., within 0.1% of the target, within 1% of the target, within 5% of the target, within 10% of the target, within 25% of the target, etc.). Furthermore, it should be understood that any exact values, numbers, measurements, etc., provided herein should be considered as including approximate values ​​(e.g., within suitable or acceptable tolerances of error). Additionally, the term "group" can contain one or more. That is, a group can contain a single member, but a group can also contain a group of multiple members.

[0029] This disclosure relates to a column driver circuit system for a memory device. The memory bank of the memory device may include a plurality of memory cells arranged along multiple column select lines and row select lines. The column driver circuit system may include a column driver coupled to the column select lines. The column driver may generate a column select signal with a desired voltage level for accessing a target memory cell coupled to the corresponding column select line. In some cases, without compensation, the resistance and / or parasitic capacitance of the column select line used to access the target memory cell may reduce the voltage level of the column select signal. For example, the column select line may have increasingly higher resistance and / or parasitic capacitance for accessing memory cells located further away than the column driver. The column decoder may include circuitry to adjust the voltage level of the column select signal to provide a desired voltage level to the target memory cell by compensating for the resistance and / or parasitic capacitance used to access the target memory cell. In some embodiments, the column decoder may include circuitry to adjust the voltage level of the column select signal based on the distance between the target memory cell and the column decoder.

[0030] Figure 1 A simplified block diagram illustrating certain features of a memory device 100 (e.g., a memory subsystem of a device) according to embodiments of the present disclosure is provided. Specifically, Figure 1The block diagram illustrates certain functionalities of the memory device 100. The memory device 100 may include random access memory (RAM) devices, ferroelectric RAM (FeRAM) devices, dynamic RAM (DRAM) devices, static RAM (SRAM) devices (including double data rate SRAM devices), flash memory, and / or a 3D memory array including phase-change (PC) memory and / or other chalcogenide-based memories (e.g., self-select memory (SSM)). Each memory cell of such a memory device may include a corresponding logic storage device (e.g., a capacitor, resistor, or resistor made of chalcogenide material).

[0031] The memory device 100 may include several memory banks 102, each comprising one or more memory arrays. Depending on the application and / or design of the memory device 100 in an electrical system, various configurations, organization, and sizes of the memory banks 102 on the memory device 100 may be used. For example, in different embodiments, the memory banks 102 may contain different numbers of rows and / or columns of memory cells. Each memory bank 102 may contain several segments (e.g., groups) of memory cells. In some embodiments, each segment of the memory bank 102 may contain several sections (e.g., subgroups) of memory cells.

[0032] The memory device 100 may also include a command interface 104 and an input / output (I / O) interface 106. The command interface 104 is configured to provide several signals received from a processor (e.g., a processor subsystem of the device) or a controller (e.g., a memory controller 108). For example, the electronic device may include a processor coupled to the memory device 100. In various embodiments, the memory controller 108 may include one or more processors (e.g., memory processors), one or more programmable logic structures, or any other suitable processing components.

[0033] In some embodiments, bus 110 may provide signal paths or groups of signal paths to allow bidirectional communication between memory controller 108, command interface 104, and I / O interface 106. For example, memory controller 108 may receive memory access requests from the I / O interface via command interface 104 and bus 110. A memory access request may indicate a request to access one or more target memory cells. Memory controller 108 may provide commands and / or instructions for performing memory operations to command interface 104 via bus 110.

[0034] Similarly, the external bus 112 can provide another signal path or group of signal paths to allow bidirectional signal transmission, such as data signals and access commands (e.g., read / write requests), between the I / O interface 106, memory controller 108, command decoder 120, and / or other components. Therefore, the memory controller 108 can provide various signals (e.g., access commands, access instructions, or other signals) to different components of the memory device 100 to facilitate the transfer and reception of data written to or read from the memory bank 102.

[0035] Command interface 104 can receive one or more clock signals (e.g., external clock signals) from an external device. Command interface 104 can provide (e.g., generate) an internal clock signal (CLK) based on one or more clock signals (e.g., external clock signals). In some embodiments, command interface 104 can provide CLK to command decoder 120 and an internal clock generator, such as delay phase-locked loop (DLL) 118 circuitry. DLL 118 can generate a phase-controlled internal clock signal (LCLK) based on the received CLK. For example, DLL 118 can provide LCLK to I / O interface 106. Subsequently, I / O interface 106 can use the received LCLK as a clock signal for transmitting read data using external bus 112. Furthermore, in some cases, DLL 118 can generate latch signals and one or more delayed latch signals based on the received CLK. In such cases, DLL 118 can provide latch signals and delayed latch signals to memory bank 102 to facilitate access to one or more memory cells in the memory array.

[0036] Command interface 104 can also provide an internal clock signal CLK to various other memory components. As mentioned above, command decoder 120 can receive the internal clock signal CLK. In some cases, command decoder 120 can also receive access commands received via external bus 112 via bus 122 and / or via I / O interface 106. For example, command decoder 120 can receive access commands transmitted from one or more external devices via I / O interface 106. In some cases, the processor can transmit access commands.

[0037] Command decoder 120 can decode access commands and / or memory access requests to provide corresponding access instructions for accessing target memory cells. For example, command decoder 120 can provide access instructions to one or more control circuitry systems 132 associated with memory bank 102 via bus path 126. In some cases, command decoder 120 can provide access instructions to control circuitry system 132 in coordination with providing access instructions to DLL 118 via bus 124. For example, command decoder 120 can coordinate the generation of access instructions consistent with CLK and / or LCLK (e.g., synchronous).

[0038] Command decoder 120 can decode access commands (e.g., memory access requests) to provide access instructions. In some cases, command decoder 120 can receive access commands using the rising and / or falling edge of an external clock signal. For example, the processor can use a memory command protocol, such as a multi-clock-cycle memory command protocol, to transmit access commands. Furthermore, the processor can use a specific memory command protocol based at least in part on the number of pins of memory device 100 or I / O interface 106, the number of rows and / or columns of memory bank 102, and the number of memory banks 102. Subsequently, command decoder 120 can provide access instructions to memory bank 102 based on receiving and decoding the access commands.

[0039] Command decoder 120 may provide access instructions to memory bank 102 via bus path 126 using one or more clock cycles of CLK. Command decoder 120 may also transmit various signals to one or more registers 128 via, for example, one or more global lines 130. For example, one or more registers 128 may provide instructions to configure various modes of programmable operation and / or configuration of memory device 100. In addition, memory device 100 may include other decoders (e.g., row decoders and column decoders) to facilitate access to memory bank 102, as discussed below.

[0040] In some embodiments, each memory bank 102 may include a corresponding control block 132. In some cases, each of the control circuitry 132 may also provide row decoding and column decoding capabilities based on received access instructions. Thus, the control block 132 may facilitate access to the memory array of the corresponding memory bank 102. For example, the control circuitry 132 may include circuitry (e.g., logic circuitry) to facilitate access to memory cells of one or more memory arrays, segments, and / or sections of the corresponding memory bank 102 based on received access instructions.

[0041] In some cases, the control circuitry 132 may receive access instructions and determine the target memory bank 102 associated with the target memory cell. In certain cases, the command decoder 120 may include the control circuitry 132. Furthermore, the control circuitry 132 may provide timing control and data control functions to facilitate the execution of different commands regarding the corresponding memory bank 102.

[0042] It should be understood that, in different embodiments, the memory device 100 may include additional or alternative components. That is, the memory device 100 may include additional or alternative components such as power supply circuitry (for receiving external VDD and VSS signals), read / write amplifiers (for amplifying signals during read / write operations), temperature sensors (for sensing the temperature of the memory device 100), etc. Therefore, it should be understood that... Figure 1The block diagram is provided only to highlight certain functional features of the memory device 100 to aid in a detailed description thereafter.

[0043] Figure 2 This is a block diagram of a memory bank 102 of a memory device 100 having the control circuitry 132 discussed above, according to an embodiment of the present disclosure. The memory device 100 may include a memory bank 102, a column decoder circuitry 160, a column driver circuitry 162, and a row driver circuitry 164. In some embodiments, the control circuitry 132 may include the column decoder circuitry 160, the column driver circuitry 162, and / or the row driver circuitry 164. The column driver circuitry 162 may include a plurality of column driver groups 166. Each memory bank 102 may include a plurality of memory cells arranged along a plurality of column select lines and row select lines. The column select lines of the memory bank 102 may be coupled to the column driver groups 166 on the proximal side of the memory bank 102. The row select lines of the memory bank 102 may be coupled to the row driver circuitry 164. Thus, each memory bank 102 may be coupled to a corresponding column driver group 166 and row driver circuitry 164.

[0044] Each column driver group 166 may include circuitry to generate and output a column select signal for accessing a target memory cell of the corresponding memory bank 102. For example, the memory controller 108 described above may provide instructions for accessing one or more target memory cells. Each column driver group 166 may generate a column select signal 168 for accessing the target memory cell based on received instructions. Accessing the target memory cell may include writing data to the target memory cell and / or reading data stored on the target memory cell.

[0045] Each memory bank 102 may include multiple segments 170, which in turn include multiple sections 172. Each section 172 may include multiple memory cells. For example, segments 170 and / or sections 172 may each include one or more memory arrays containing multiple memory cells. Furthermore, each section 172 of the memory bank 102 is positioned at a different distance from the column driver group 166 coupled to the proximal side of the memory bank 102. The column driver group 166 may include circuitry to generate a column select signal based on the segment address or section address of the target memory cell. The column driver group 166 may generate a column select signal with a boost voltage step. The column driver group 166 may adjust the voltage level and / or duration of the boost voltage step of the column select signal based on the segment address or section address of the target memory cell. For example, the column driver group 166 may increase the voltage level and / or duration of the boost voltage step corresponding to the segment address or section address of the target memory cell located further along the column select line.

[0046] Figure 3This refers to the column driver circuitry 162 of the memory device 100 described above according to embodiments of the present disclosure. The column driver circuitry 162 may include a power switch 174 and a plurality of column driver groups 166. Each column driver group 166 may each include a plurality of column drivers 176. Each column driver 176 may be coupled to a column select line 178 of the memory bank 102. The column driver group 166 may receive a column address 180 (CA) for accessing a target memory cell. The column driver 176 may generate a column select signal 168 (CS) for accessing the target memory cell based on the received column address 180. The column driver 176 may output the column select signal 168 to the corresponding column select line 178 coupled thereto for accessing the target memory cell.

[0047] It should be understood that, in different embodiments, the column driver circuitry 162 may include a different number of column driver groups 166. Furthermore, in different embodiments, the column driver groups 166 may include a different number of column drivers 176. In the depicted embodiment, each column driver group 166 may be coupled to two power switches 174. It should be understood that, in alternative or additional embodiments, each column driver group 166 may be coupled to a different number of power switches 174.

[0048] Figures 4 to 10 Some embodiments relate to a column driver 176 for generating a column select signal 168 having a single voltage step or two voltage steps. The column driver 176 can generate a column select signal 168 with a logic high bit to access a target memory cell coupled to a corresponding column select line 178. A logic high bit with a single voltage step may have a first voltage level based on a first supply voltage 182 (V1). A logic high bit with two voltage steps may include a first portion having a second voltage level based on a second supply voltage (V2) and then a second portion having a first voltage level based on the first supply voltage 182. The voltage level of the second supply voltage 184 may be higher than the voltage level of the first supply voltage 182. In some embodiments, the column driver 176 can increase the slope of the rising edge of the logic high bit received by the target memory cell by outputting a column select signal 168 with two voltage steps. Therefore, in some cases, the target memory cell can receive the logic high bit with a shorter time (e.g., faster) and / or higher voltage level based on the logic high bit with two voltage steps.

[0049] Figure 4This is a block diagram of a first column driver group 166-1 according to an embodiment of the present disclosure, having a column driver circuitry 162 coupled to near and far ground terminals 186 and 188 of the memory bank 102 via column select lines 178. As mentioned above, each column driver group 166 may include a plurality of column drivers 176. In the depicted embodiment, the first column driver group 166-1 may include a plurality of top column drivers 176-1 and a plurality of bottom column drivers 176-2. It should be understood that in different embodiments, the first column driver group 166-1 may include different circuit components.

[0050] Column drivers 176 may each include a first inverter 192 (e.g., a low-voltage driver) and a second inverter 194 (e.g., a low-voltage driver, a column select line driver). It should be understood that in different embodiments, column drivers 176 may have different circuit systems. It should be understood that the positive supply voltage input of the first inverter 192 may be coupled to a first supply voltage 182 or switched between being coupled to the first supply voltage 182 and the second supply voltage 184. The negative supply voltage input of the first inverter 192 of the top column driver 176-1 may be coupled to first control logic 196. The negative supply voltage input of the first inverter 192 of the bottom column driver 176-2 may be coupled to second control logic 198. The supply voltage inputs of the first control logic 196 and the second control logic may be coupled to (or may be coupled to) the first supply voltage 182 or switched between being coupled to the first supply voltage 182 and the second supply voltage 184, as described below regarding... Figure 5 and 6 As discussed above. It should be understood that, in alternative or additional embodiments, the first column driver group 166-1 may include a different number of column drivers 176 and / or control logic.

[0051] The column driver circuitry 162 may include a first ground terminal 186 coupled to the negative supply voltage input of the second inverter 194. The column driver circuitry 162 may include a second ground terminal 188 coupled to the column select line 178 (e.g., the edge of the column select line 178) at the distal side of the memory bank 102. The column driver circuitry 162 may include a ground switch 202 to couple and decouple the column select line 178 from the second ground terminal 188. The distal side of the memory bank 102 may be the opposite side of the memory bank 102 compared to the proximal side of the column drivers 176 coupled to the first column driver group 166-1. The first ground terminal 186 and the second ground terminal 188 may have a ground voltage.

[0052] The first inverter 192 of the top column driver 176-1 can each input the corresponding bit (CA) of the first column address 180. <0> CA <1> (etc.). First control logic 196 may activate (e.g., enable) the first inverter 192 of the top column driver 176-1 based on the received high portion of clock signal 204 and the high bit of the first column address 180. The high bit of the first column address 180 may indicate a memory cell coupled to at least one of the top column drivers 176-1. Clock signal 204 may contain the information described above regarding... Figure 1 The discussion covers the internal clock signal and / or the phase-controlled internal clock signal.

[0053] The first control logic 196 may deactivate (e.g., disable) the first inverter 192 of the top column driver 176-1 based on the absence of clock signal 204 or the receipt of a logic low portion of clock signal 204. Alternatively or additionally, the first control logic 196 may deactivate (e.g., disable) the first inverter 192 of the top column driver 176-1 based on the indication from the first column address 180 that a memory cell coupled to the top column driver 176-1 is not targeted. It should be understood that a logic high voltage and a logic high bit may correspond to a signal or a portion of a signal having a voltage level equal to or higher than a threshold. Furthermore, a logic low voltage and a logic low bit may correspond to a signal or a portion of a signal having a voltage level lower than a threshold. For example, a logic low voltage or a logic low bit may have a voltage level equal to or close to ground.

[0054] The first inverter 192 of the bottom column driver 176-2 can be input to a corresponding bit of the second column address 180. The second control logic 198 can activate (e.g., enable) the first inverter 192 of the bottom column driver 176-2 based on the received high portion of the clock signal 204 and the high bit of the second column address 180. The high bit of the second column address 180 can indicate a memory cell coupled to at least one of the bottom column drivers 176-2. The second control logic 198 can deactivate (e.g., disable) the first inverter 192 in the bottom column driver 176-2 based on the absence of the clock signal 204 or the receipt of the low portion of the clock signal 204. Alternatively or additionally, the first control logic 196 can deactivate (e.g., disable) the first inverter 192 of the bottom column driver 176-2 based on the indication from the second column address 180 that a memory cell coupled to the bottom column driver 176-2 is not targeted.

[0055] As mentioned above, the positive supply voltage input of the first inverter 192 can receive a first supply voltage 182. The first inverter 192 can become activated upon receiving the first supply voltage 182 to invert the input signal. Furthermore, the first inverter 192, coupled to the column driver 176 of the target memory cell, can input the logic high bit of column address 180. In some cases, the top column driver 176-1 and / or the bottom column driver 176-2 can each receive a portion (e.g., one bit) of column address 180 in parallel. In some embodiments, the logic high bit can have a voltage level equal to (or nearly equal to) the voltage level of the first supply voltage 182. The activated first inverter 192 can output a logic low bit (CAB) to the second inverter 194 coupled thereto based on the logic high bit of the input column address 180.

[0056] A second inverter 194 coupled to the target memory cell can receive a logic low bit generated by the first inverter 192. The positive supply voltage input of the second inverter 194 can receive a common supply voltage 206 (e.g., a voltage common source (VCS)). The second inverter 194 can become activated upon receiving the common supply voltage 206 to invert the input signal. Therefore, the second inverter 194 can generate a column select signal 168 with a logic high bit based on the input logic low bit and the received common supply voltage 206. It should be understood that the second inverter 194 can generate the column select signal 168 with a voltage level based on the voltage level of the common supply voltage 206. The activated second inverter 194 with the input logic low bit can output the column select signal 168 to the corresponding column select line 178 for accessing the target memory cell of the memory bank 102. Therefore, the column driver circuitry 162 can output the column select signal 168 to the selected column select line 178 based on the column address 180.

[0057] In the depicted embodiment, the common supply voltage 206 may have a high voltage level having a single voltage step or switching between two voltage steps. As mentioned above, the second inverter 194 may generate a column select signal 168 having a voltage level based on the voltage level of the common supply voltage 206. Specifically, when a corresponding negative supply voltage input is coupled to the first ground terminal 186, the second inverter 194 may generate the column select signal 168 based on the voltage level of the common supply voltage 206 received at the corresponding positive supply voltage input. Thus, the second inverter 194 may generate a logic high bit of the column select signal 168 having a single voltage step or two voltage steps based on the voltage level of the common supply voltage 206.

[0058] The column driver circuit system 162 (or the first column driver group 166-1) may include a first switch 210 coupled to a first supply voltage 182 and a second switch 212 coupled to a second supply voltage 184. The first switch 210 may couple and decouple the first supply voltage 182 to the positive supply voltage input of the second inverter 194. The second switch 212 may couple and decouple the second supply voltage 184 to the positive supply voltage input of the second inverter 194. In some cases, the first switch 210 may couple the first supply voltage 182 to the second inverter 194 to provide a single voltage step. Alternatively, the second switch 212 may couple the second supply voltage 184 to the second inverter 194 to provide a single voltage step. Thus, depending on the positions of the first switch 210 and the second switch 212, a single voltage step may have the voltage level of either the first supply voltage 182 or the second supply voltage 184.

[0059] The two voltage steps may include a first voltage step having a voltage level based on the second supply voltage 184 and a second voltage step having a voltage level based on the first supply voltage 182. A second switch 212 may couple the second supply voltage 184 to the second inverter 194 during the first voltage step. A first switch may be open during the first voltage step. Furthermore, a first switch 210 may couple the first supply voltage to the second inverter 194 during the second voltage step. A second switch 212 may be open during the second voltage step. For example, the memory controller 108 discussed above may generate control signals to open and close the first switch 210 and the second switch 212 to provide a common supply voltage 206 having one or both voltage levels. Alternatively or additionally, any other feasible circuitry may generate control signals, for example, based on the received column address 180.

[0060] As mentioned above, the second supply voltage 184 may have a higher voltage level than the first supply voltage 182. Furthermore, the column driver 176 may generate a column select signal 168 with a second voltage level based on the voltage level of the second supply voltage 184 and subsequently generate a column select signal 168 with a first voltage level based on the voltage level of the first supply voltage 182. Therefore, in some cases, compared to outputting a column select signal 168 with a single voltage step having the first voltage level, the column driver 176 can increase the slope of the rising edge of the logic high bit by outputting a column select signal 168 with two voltage steps, one with the second voltage level and the other with the first voltage level. For example, compared to receiving a logic high bit (or column select signal 168) with a single voltage step, the target memory cell can receive a logic high bit (or column select signal 168) with two voltage steps in a shorter time (e.g., faster) and / or at a higher voltage level.

[0061] When column address 180 does not select the corresponding column driver 176, the first inverter 192 can input the low-order logic bit of column address 180. Each of the first inverters 192 can output a logic high signal to the corresponding second inverter 194 based on the low-order logic bit of the input column address 180. The second inverter 194 can couple the column select line 178 to the first ground terminal 186 based on the input logic high signal. Furthermore, the ground switch 202 can couple the second ground terminal 188 to the opposite side of the corresponding column select line 178 at the distal end of the memory bank 102. Therefore, the column driver circuitry 162 can ground both the near and far sides (e.g., both edges) of the corresponding column select line 178. For example, such column select lines 178 may not be coupled to the target memory cell.

[0062] For example, when the corresponding column select line 178 is not coupled to the target memory cell, the ground switch 202 may receive an instruction to couple the corresponding column select line 178 to the second ground terminal 188. For instance, each of the ground switches 202 may be coupled to a first inverter 192 and / or a second inverter 194 coupled to the corresponding column select line 178 to receive the instruction. Alternatively or additionally, the ground switch 202 may be coupled to the memory controller 108 discussed above to receive the instruction. The ground switch 202 may couple the second ground terminal 188 to the column select line X based on the received instruction. It should be understood that in some embodiments, the column driver circuitry 162 may not include the ground switch 202.

[0063] In some embodiments, column driver circuitry 162 may couple the near and far sides of the unselected column select line 178 to ground. Furthermore, after the output column select signal 168 and / or after the corresponding logic high bit of the input column address 180, column driver circuitry 162 may couple the near and far sides of the selected column select line 178 to ground. For example, the column driver 176 for the selected column select line 178 may input a logic low voltage after the logic high bit of the input column address 180. Column driver circuitry 162 may increase the slope of the falling edge of the column select signal 168 based on coupling the near and far sides of the column select line 178 to ground. Therefore, the target memory cell can receive the ground voltage in a shorter time (e.g., faster) by grounding both the near and far sides of the column select line 178.

[0064] Figure 5This refers to column driver 176 of the first column driver group 166-1 described above according to embodiments of this disclosure. Column driver 176 may include a first inverter 192 and a second inverter 194 coupled to memory bank 102 via column select line 178. The positive supply voltage input of the first inverter 192 may be coupled to a common supply voltage 206. The negative supply voltage input of the first inverter 192 may be coupled to a first control logic 196 or a second control logic 198. The supply voltage input of the first control logic 196 or the second control logic 198 may be coupled to a first supply voltage 182. A first switch 210 may couple the first supply voltage 182 to the positive supply voltage input of the second inverter 194. A second switch 212 may couple the second supply voltage 184 to the positive supply voltage input of the second inverter 194. A ground switch 202 may couple the distal side of column select line 178 to a second ground terminal 188.

[0065] The first inverter 192 can generate a logic low bit based on the logic high bit of the column address 180 of the input select column driver 176. The second inverter 194 can generate a column select signal 168 with a logic high bit. In some cases, the logic high bit of the column select signal 168 can have two voltage steps. The column select signal 168 can have a first voltage step with a voltage level based on the voltage level of the second supply voltage 184 and a second voltage step with a voltage level based on the voltage level of the first supply voltage 182. The voltage level of the first voltage step can be higher than the voltage level of the second voltage step. Furthermore, after outputting the column select signal 168, the second inverter 194 and the ground switch 202 can couple the near side and far side of the column select line 178 to the ground voltage.

[0066] Figure 6 This refers to column driver 176 of the first column driver group 166-1 described above, which has a pull-up switch 214, according to an embodiment of this disclosure. Column driver 176 may include a first inverter 192 and a second inverter 194 coupled to memory bank 102 via column select line 178. Positive supply voltage inputs of the first inverter 192 and the second inverter 194 may be coupled to a common supply voltage 206. Negative supply voltage input of the first inverter 192 may be coupled to a first control logic 196 or a second control logic 198. Negative supply voltage input of the second inverter 194 may be coupled to a first ground terminal 186. Furthermore, the supply voltage inputs of the first control logic 196 or the second control logic 198 may be coupled to the common supply voltage 206.

[0067] In some embodiments, level shifter 216 may output the logic high bit of column address 180 of column driver 176 to first inverter 192. In some cases, level shifter 216 may provide the logic high bit based on the voltage levels of first supply voltage 182 and / or second supply voltage 184. For example, when common supply voltage 206 is coupled to second supply voltage 184, level shifter 216 may up-convert the voltage level of column address 180. (The above refers to...) Figure 1 and 2 The control circuitry 132 and / or column decoder circuitry 160 of the memory device 100 may include a level shifter 216. Therefore, the first inverter 192, the second inverter 194, and the control logic 196 or 198 may operate based on the voltage level of the common supply voltage 206.

[0068] The first switch 210 couples a first supply voltage 182 to the positive supply voltage inputs of the first inverter 192 and the second inverter 194, and to the supply voltage inputs of control logic 196 or 198. The second switch 212 couples a second supply voltage 184 to the positive supply voltage inputs of the first inverter 192 and the second inverter 194, and to the supply voltage inputs of control logic 196 or 198. The column driver circuitry 162 may include a pull-up switch 214 coupled to the first switch 210, the second switch 212, the output port of the first inverter 192, and the input port of the second inverter 194. Additionally, a ground switch 202 couples the distal side of the column select line 178 to a second ground terminal 188. It should be understood that in some embodiments, the column driver circuitry 162 may not include a ground switch 202.

[0069] Pull-up switch 214 may include a p-channel metal-oxide-semiconductor (pMOS) transistor and other possibilities. In some cases, pull-up switch 214 may synchronize or pull up the voltage levels at the output port of the first inverter 192 and the input port of the second inverter 194 based on the voltage level of the common supply voltage 206. In some cases, pull-up switch 214 may close based on receiving a gate voltage corresponding to the voltage level (e.g., a transient voltage level) of the common supply voltage 206. That is, pull-up switch 214 may receive a voltage level having the same, reciprocal, a portion thereof, and / or a multiple thereof as the voltage level of the common supply voltage 206. For example, pull-up switch 214 may receive a voltage level corresponding to the voltage level of the first supply voltage 182 when the first switch is closed and may receive a voltage level corresponding to the voltage level of the second supply voltage 184 when the second switch is closed.

[0070] Figure 7 This describes the control of switches 210 and 212 according to embodiments of the present disclosure, as discussed above. Figure 5The column driver 176 of the 6-way system provides a timing diagram for control signals 220 and 222 of a common supply voltage 206 with two voltage steps. A first switch 210 and a second switch 212 can receive the first control signal 220 and the second control signal 222, respectively. For example, the first switch 210 and the second switch 212 can each include a pMOS transistor. The column driver 176 (e.g., a first inverter 192) can receive the rising edge of the logic high bit of column address 180 at time T1.

[0071] During the time period between T1 and T2, the first control signal 220 may have a high voltage level and the second control signal 222 may have a low voltage level. Therefore, the first switch 210 may be open and the second switch 212 may be closed. The second inverter 194 of the column driver 176 may be coupled to the second supply voltage 184 during the time period between T1 and T2. Furthermore, the column driver 176 (e.g., the first inverter 192, the second inverter 194) may receive a portion of the logic high bits of the column address 180. Therefore, the second inverter 194 may generate a column select signal 168 with a second voltage level based on the voltage level of the second supply voltage 184 during the time period between T1 and T2.

[0072] During the time period between T2 and T3, the first control signal 220 may have a low voltage level and the second control signal 222 may have a high voltage level. Therefore, the first switch 210 may be closed and the second switch 212 may be open. The second inverter 194 of the column driver 176 may be coupled to the first supply voltage 182 during the time period between T2 and T3. Furthermore, the column driver 176 (e.g., the first inverter 192, the second inverter 194) may receive the remaining high-order bits of the column address 180. Therefore, the second inverter 194 may generate a column select signal 168 with a first voltage level based on the voltage level of the first supply voltage 182 during the time period between T2 and T3.

[0073] Column driver 176 (e.g., first inverter 192) may receive the falling edge of the logic high bit of column address 180 at time T3. Therefore, second inverter 194 and ground switch 202 may couple the near and far sides of column select line 178 to ground voltage. It should be understood that the time periods between T1 and T2 and between T2 and T3 may differ in different embodiments. Furthermore, it should be understood that in alternative or additional embodiments, the first switch 210 and the second switch 212 of column driver 176 may each comprise different switching circuits and / or transistor types. In such alternative or additional embodiments, the first control signal 220 and the second control signal 222 may differ based on the switching circuits and / or transistor types of the first switch 210 and the second switch 212. For example, the first control signal 220 and the second control signal 222 may each be inverted, delayed, or have different voltage levels and / or relative timing.

[0074] Figure 8 This describes an embodiment of the present disclosure where the selected column driver 176 is based on the foregoing description of... Figures 4 to 7 The graph illustrates the column selection signal 168 generated by the two voltage steps discussed. In some embodiments, the column selection signal 168 may initially have a voltage level (V2) based on the second supply voltage 184 coupled to the second supply voltage 184 by the second inverter 194. The common supply voltage 206 may subsequently have a voltage level (V1) based on the first supply voltage 182 coupled to the first supply voltage 182 by the second inverter 194. The voltage level difference (ΔV) between the voltage levels of the first supply voltage 182 and the second supply voltage 184 may be adjusted by a first voltage adjustment circuit. The duration (ΔT) of the voltage level used to provide the second supply voltage may be adjusted by a delay circuit.

[0075] Figure 9 This describes the embodiments according to the present disclosure. Figure 5 The column driver 176 (e.g., the second inverter 194) is based on the proximal and distal sides of the column select line 178. Figure 7 The graph illustrates the voltage level of the column select signal 168 generated by the control signals 220 and 222. Specifically, the graph shows two voltage steps for the column select signal 168: one near or on the near side of the memory bank 102, and the other near or on the far side of the memory bank 102. The column select signal 168 may have a first voltage step 224 with a voltage level based on the second supply voltage 184, and then a second voltage step 226 with a voltage level based on the first supply voltage 182. The voltage level of the first voltage step 224 may be higher than the voltage level of the second voltage step 226.

[0076] The resistance and / or parasitic capacitance of the column select line 178 used to access the target memory cell can reduce the voltage level of the column select signal 168. For example, the column select line 178 may have higher resistance and / or parasitic capacitance for accessing a target memory cell located near the proximal side of the memory bank 102 compared to accessing a target memory cell located near the proximal side of the memory bank 102. Furthermore, the target memory cell may be accessed based on receiving the column select signal 168 with a voltage level equal to or higher than a voltage threshold 228 (e.g., a threshold voltage level) for a period of time equal to or higher than a desired time 230.

[0077] The first voltage step 224 and the second voltage step 226 may have voltage levels higher than the voltage threshold 228. The higher voltage level of the first voltage step 224 of the column select signal 168 may compensate for at least a portion of the resistance and / or parasitic capacitance of the target memory cell located near the distal side of the memory bank 102 (or coupled to the column select line 178). In some cases, the higher voltage level of the first voltage step 224 may increase the rising edge slope or time of the column select signal 168 at or near the distal side of the memory bank 102. Thus, the target memory cell coupled to the column select line 178 at or near the distal side of the memory bank 102 may receive the column select signal 168 with a voltage level equal to or higher than the voltage threshold 228 for a period of time equal to or higher than the desired time 230. Furthermore, after outputting the column select signal 168, the second inverter 194 and the ground switch 202 may couple the near and distal sides of the column select line 178 to the ground voltage.

[0078] In some embodiments, column select line 178 may be coupled to an additional memory cell to increase the capacity of memory bank 102 based on two voltage steps of the logic high bit of column select signal 168. In a particular embodiment, a first voltage adjustment circuit may adjust the voltage level of the second supply voltage 184 based on the length of column select line 178 or the placement of the target memory cell along column select line 178. In alternative or additional embodiments, a delay circuit may adjust the duration (ΔT) for providing the voltage level of the second supply voltage 184 based on the length of column select line 178 or the placement of the target memory cell along column select line 178. For example, the first voltage adjustment circuit and / or the delay circuit may adjust the voltage level of the second supply voltage 184 and / or the duration (ΔT) for providing the voltage level of the second supply voltage 184 based on the column address 180 of the target memory cell, the segment address or section address of the target memory cell, and other possibilities.

[0079] Figure 10This is a first voltage adjustment circuit 240 according to an embodiment of the present disclosure for adjusting the voltage level of a second supply voltage 184 based on column address 180. The first voltage adjustment circuit 240 may include a multiplexer 242 that receives column address 180 associated with a first column driver group 166-1. The input ports of the multiplexer 242 may each be coupled to different resistors or coupled between different resistors in a resistor string 244. The resistor string 244 may be coupled to a voltage source on one side and to a ground terminal on the other side. The voltage source may include the first supply voltage 182 or... Figure 1 Any other feasible voltage source for the memory device 100.

[0080] Multiplexer 242 can generate reference voltage 246 (REF) by selecting input ports based on column address 180. In certain non-limiting cases, column address 180 may indicate one or more memory cells for a single memory cell, a single memory segment, or a memory sub-segment. In some embodiments, multiplexer 242 may have several input ports corresponding to several segments or sub-segments of memory bank 102 discussed above. For example, multiplexer 242 may select the input port corresponding to the segment address or sub-segment address of the target memory cell based on column address 180. Alternatively or additionally, instead of receiving column address 180, or in addition to receiving column address 180, multiplexer 242 may receive segment address or sub-segment address. In some embodiments, first voltage adjustment circuit 240 (and / or multiplexer 242) may include a lookup table to select input ports coupled to resistor string 244 based on segment address, sub-segment address, and / or column address 180. The first amplifier 248 may receive a reference voltage 246 and a first feedback signal 250. The first amplifier 248 may generate a gate voltage for an output switch 252. The output switch 252 may include a pMOS transistor, an n-channel metal-oxide-semiconductor (nMOS) transistor, and other possibilities.

[0081] Output switch 252 may be coupled to a voltage source on one side and to a ground terminal on the other side via one or more first feedback resistors 254. First amplifier 248 may receive a first feedback signal 250 from the first feedback resistors 254. The voltage source may include a first supply voltage 182 or... Figure 1The memory device 100 may use any other feasible voltage source. Output switch 252 may output a second supply voltage 184. Therefore, the first voltage adjustment circuit 240 may provide a second supply voltage 184 having a voltage level based on the column address 180 and / or segment address or block address of the target memory cell. Therefore, the first voltage adjustment circuit 240 may adjust the voltage level difference (ΔV) between the voltage levels of the first supply voltage 182 and the second supply voltage 184. It should be understood that in different embodiments, the first voltage adjustment circuit 240 may include different circuitry to provide the second supply voltage 184 based on the column address 180 and / or segment address or block address of the target memory cell.

[0082] Figures 11 to 17 Some embodiments relate to a column driver 176 for generating a column select signal 168 having three voltage steps and a logic high bit. The column driver 176 can generate a column select signal 168 with a logic high bit to access a target memory cell coupled to a corresponding column select line 178. The logic high bit with three voltage steps may include a first portion followed by a second portion and a third portion. The first portion may have a second voltage level based on a second supply voltage 184. The voltage level of the first supply voltage 182 may be higher than ground. The second portion may have a first voltage level based on the voltage level of the first supply voltage 182. The voltage level of the second supply voltage 184 may be higher than the voltage level of the first supply voltage 182. The third portion may have a third voltage level based on a third supply voltage 260. The voltage level of the third supply voltage 260 may be lower than ground (e.g., a negative voltage level). In some embodiments, the column driver 176 can increase the slope of the rising edge of the logic high bit received by the target memory cell by outputting a column select signal 168 with three voltage steps. Therefore, in some cases, the target memory cell can receive the logic high bit with a shorter time (e.g., faster) and / or higher voltage level based on the logic high bit with three voltage steps.

[0083] Figure 11 This is a block diagram of a second column driver group 166-2 that generates a three-level column select signal 168 coupled to memory bank 102 via column select line 178, according to embodiments of the present disclosure. As mentioned above, each column driver group 166 may include a plurality of column drivers 176. In the depicted embodiment, the second column driver group 166-2 may include a plurality of top column drivers 176-1 and a plurality of bottom column drivers 176-2. It should be understood that in different embodiments, the second column driver group 166-2 may include different circuit components.

[0084] As discussed above, each of the column drivers 176 may include a first inverter 192 and a second inverter 194. It should be understood that in different embodiments, the column driver 176 may have different circuit systems. The positive supply voltage input of the first inverter 192 may be coupled to a first supply voltage 182. The negative supply voltage input of the first inverter 192 of the top column driver 176-1 may be coupled to first control logic 196. The negative supply voltage input of the first inverter 192 of the bottom column driver 176-2 may be coupled to second control logic 198. The supply voltage inputs of the first control logic 196 and the second control logic may be coupled to (or may be coupled to) the first supply voltage 182 or switch between being coupled to the first supply voltage 182 and the second supply voltage 184, as described above regarding... Figures 5 to 7 As discussed above. It should be understood that, in alternative or additional embodiments, the second column driver group 166-2 may include a different number of column drivers 176 and / or control logic.

[0085] The first inverter 192 of the top column driver 176-1 can each input a corresponding bit of the first column address 180 (CA). The first control logic 196 can activate (e.g., enable) the first inverter 192 of the top column driver 176-1 based on the received high portion of the clock signal 204 and the high bit of the first column address 180. The high bit of the first column address 180 can indicate a memory cell coupled to at least one of the top column drivers 176-1. The first control logic 196 can deactivate (e.g., disable) the first inverter 192 of the top column driver 176-1 based on the absence of the clock signal 204 or the receipt of the low portion of the clock signal 204. Alternatively or additionally, the first control logic 196 can deactivate (e.g., disable) the first inverter 192 of the top column driver 176-1 based on the indication from the first column address 180 that a memory cell coupled to the top column driver 176-1 is not targeted.

[0086] The first inverter 192 of the bottom column driver 176-2 can each input corresponding bits of the second column address 180. The second control logic 198 can activate (e.g., enable) the first inverter 192 of the bottom column driver 176-2 based on the received high portion of the clock signal 204 and the high bit of the second column address 180. The high bit of the second column address 180 can indicate a memory cell coupled to at least one of the bottom column drivers 176-2. The second control logic 198 can deactivate (e.g., disable) the first inverter 192 of the bottom column driver 176-2 based on the absence of the clock signal 204 or the receipt of the low portion of the clock signal 204. Alternatively or additionally, the first control logic 196 can deactivate (e.g., disable) the first inverter 192 of the bottom column driver 176-2 based on the indication from the second column address 180 that a memory cell coupled to the bottom column driver 176-2 is not targeted.

[0087] As mentioned above, the positive supply voltage input of the first inverter 192 can receive a first supply voltage 182. The first inverter 192 can become activated upon receiving the first supply voltage 182 to invert the input signal. Furthermore, the first inverter 192, coupled to the column driver 176 of the target memory cell, can input the logic high bit of column address 180. In some cases, the top column driver 176-1 and / or the bottom column driver 176-2 can each receive a portion (e.g., one bit) of column address 180 in parallel. In some embodiments, the logic high bit can have a voltage level equal to (or nearly equal to) the voltage level of the first supply voltage 182. The activated first inverter 192 can output a logic low bit (CAB) to the second inverter 194 coupled thereto based on the logic high bit of the input column address 180.

[0088] The positive supply voltage input of each second inverter 194 can be coupled to a first switch 210 and a second switch 212. The positive supply voltage input of the second inverter 194 can be coupled to a first supply voltage 182 via the first switch 210 and to a second supply voltage 184 via the second switch 212. In the depicted embodiment, the negative supply voltage input of each second inverter 194 can be coupled to a corresponding third switch 262 and a corresponding fourth switch 264. The negative supply voltage input of each second inverter 194 can be coupled to (e.g., individually coupled to) a third supply voltage 260 via the corresponding third switch 262 and to (e.g., individually coupled to) a first ground terminal 186 via the corresponding fourth switch 264.

[0089] A second inverter 194 coupled to the target memory cell can receive the low-order logic bit generated by the first inverter 192. The positive supply voltage input of the second inverter 194 can receive a common supply voltage 206 (VCS) by being coupled to the first supply voltage 182 and / or the second supply voltage 184. The second inverter 194 can become activated upon receiving the common supply voltage 206 to invert the input signal. Therefore, the second inverter 194 can generate a column select signal 168 with a high-order logic bit based on the input low-order logic bit and the received common supply voltage 204.

[0090] The second inverter 194 can generate a column select signal 168 with a voltage level based on the voltage level of the common supply voltage 206. The activated second inverter 194, with its input logic low bits active, can output the column select signal 168 to the corresponding column select line 178 for accessing the target memory cell of memory bank 102. Therefore, the column driver circuitry 162 can output the column select signal 168 to the selected column select line 178 based on the column address 180.

[0091] As mentioned above, the second inverter 194 can generate a column select signal 168 with a voltage level based on the voltage level of the common supply voltage 206. Specifically, the second inverter 194 can generate the column select signal 168 based on the voltage level of the common supply voltage 206 received at the corresponding positive supply voltage input. In the depicted embodiment, the common supply voltage 206 can have a high voltage level with a single voltage step, two voltage steps, or three voltage steps. A single voltage step can have a voltage level of either a first supply voltage 182 or a second supply voltage 184. Furthermore, two voltage steps can include a first voltage step with a voltage level of the second supply voltage 184 followed by a second voltage step with a voltage level of the first supply voltage 182.

[0092] The three voltage steps may include a first voltage step followed by a second voltage step having a voltage level of a first supply voltage 182 and a third voltage step having a voltage level of a third supply voltage 260. In some embodiments, the memory controller 108 discussed above may generate control signals to open and close the first switch 210, the second switch 212, the third switch 262, and the fourth switch 264. Alternatively or additionally, any other feasible circuitry may generate control signals, for example, based on the received column address 180.

[0093] During the first voltage step of the three voltage steps, the second switch 212 can couple the second supply voltage 184 to the positive supply voltage input of the second inverter 194 of the second column driver group 166-2. Therefore, during any first voltage step of the second column driver group 166-2 that activates the second inverter 194, the second switch 212 can couple the second supply voltage 184 to the positive supply voltage input of the second inverter 194.

[0094] For example, in response to the rising edge of column address 180 (e.g., any of column addresses 180) (e.g., CA<15:0>) of the second column driver group 166-2, the second switch 212 may remain closed during the first duration (ΔT1) of the first voltage step. Furthermore, during the first voltage step, the fourth switch 264, which activates the second inverter 194 (e.g., each of the second inverters 194), may couple the first ground terminal 186 to the negative supply voltage input of the activated second inverter 194. For example, in response to the rising edge of column address 180 (e.g., CA<15:0>) of the selected column driver 176, the second switch 212 may remain closed during the first duration (ΔT1) of the first voltage step. <0> CA <1> On the rising edge of the voltage step (ΔT1), the fourth switch 264 and the second switch 212 of the second inverter 194, which are activated, can remain closed during the first duration (ΔT1). During the first voltage step, the third switch 262 and the first switch 210 of the second inverter 194, which are activated, can (e.g., remain open).

[0095] Activating the second inverter 194 allows input from the first inverter 192 based on the corresponding column address 180 (e.g., CA). <0> CA <1> The logic low bit is generated from the logic high bit (etc.). Therefore, activating the second inverter 194 can output a first portion of the column select signal 168 having a voltage level based on the voltage level of the second supply voltage 184. For example, activating the second inverter 194 can couple the corresponding column select line 178 to the second supply voltage 184. In some cases, the selected column driver 176 can output a positive voltage level higher than ground based on the voltage level of the second supply voltage 184.

[0096] During the second voltage step of the three voltage steps, the first switch 210 may couple a first supply voltage 182 to the positive supply voltage input of the second inverter 194 of the second column driver group 166-2. As mentioned above, the first switch 210 may be coupled to the positive supply voltage input of the second inverter 194 of the second column driver group 166-2. Therefore, during any second voltage step of the second inverter 194 of the second column driver group 166-2, the first switch 210 may couple the first supply voltage 182 to the positive supply voltage input of the second inverter 194. Furthermore, during the second voltage step, the third switch 262, which activates the second inverter 194 (e.g., each of the second inverters 194), may couple a third supply voltage 260 to the negative supply voltage input of the activated second inverter 194. During the second voltage step, the fourth switch 264 and the second switch 212, which activate the second inverter 194, may (e.g., remain) open.

[0097] Activating the second inverter 194 allows input from the first inverter 192 based on the corresponding column address 180 (e.g., CA). <0> CA <1> The logic low bit is generated from the logic high bit (etc.). Therefore, activating the second inverter 194 can output a second portion of the column select signal 168 having a voltage level based on the voltage level of the first supply voltage 182. For example, activating the second inverter 194 can couple the corresponding column select line 178 to the first supply voltage 182. In some cases, the selected column driver 176 can output a positive voltage level lower than the voltage level of the first portion of the column select signal 168 discussed above, based on the fact that the voltage level of the first supply voltage 182 is lower than the voltage level of the second supply voltage 184.

[0098] During the third voltage step of the three voltage steps, the first switch 210 may remain closed during any third voltage step of the second column driver group 166-2 with the second inverter 194 activated. For example, in response to or after a falling edge of column address 180 (e.g., any of column addresses 180, all column addresses 180, CA<15:0>), the first switch 210 may remain closed for a second duration (ΔT2) of the third voltage step. Furthermore, during the third voltage step, the third switch 262 with each of the second inverters 194 activated may remain closed. For example, in response to a falling edge of column address 180 of the selected column driver 176 (e.g., any of column addresses 180, all column addresses 180, CA<15:0>), the third switch 262 with the second inverter 194 activated and the first switch 210 may remain closed for a second duration (ΔT2). During the third voltage step, the fourth switch 264 and the second switch 212, which are activated by the second inverter 194, can (e.g., remain) open.

[0099] Activating the second inverter 194 allows input from the first inverter 192 based on the corresponding column address 180 (e.g., CA). <0> CA <1> The logic high bit is generated from the low bit of the logic (etc.). Therefore, activating the second inverter 194 can output a third portion of the column select signal 168 having a voltage level based on the voltage level of the third supply voltage 260. For example, activating the second inverter 194 can couple the corresponding column select line 178 to the third supply voltage 260. In some cases, the selected column driver 176 can output a negative voltage level below ground based on the voltage level of the third supply voltage 260. Therefore, the second inverter 194 can output three voltage steps of the column select signal 168 based on receiving three different voltage levels (e.g., differential voltage levels) at the corresponding supply voltage input. In some cases, the second inverter 194 can output ground after outputting the third portion of the column select signal 168.

[0100] As mentioned above, the second supply voltage 184 may have a higher voltage level than the first supply voltage 182, which is higher than the ground voltage. The third supply voltage 260 may have a voltage level lower than the ground voltage. Furthermore, as discussed above, the column driver 176 may generate a column select signal 168 with a second voltage level based on the voltage level of the second supply voltage 184, and then generate a column select signal 168 with a first voltage level based on the voltage level of the first supply voltage 182, and a column select signal 168 with a third voltage level based on the voltage level of the third supply voltage 260. In some cases, the column driver 176 may improve (e.g., increase) the slope of the rising and falling edges of the column select signal 168 based on generating a common supply voltage 206 with three voltage steps. For example, compared to receiving a logic high bit (or column select signal 168) with a single voltage step, the target memory cell may receive a logic high bit (or column select signal 168) with three voltage steps in a shorter time (e.g., faster) and / or at a higher voltage level.

[0101] As mentioned above, when column address 180 does not select the corresponding column driver 176, the first inverter 192 can input the low-order logic bit of column address 180. Each of the first inverters 192 can output a logic high signal to the corresponding second inverter 194 based on the low-order logic bit of the input column address 180. Each of the second inverters 194 that inputs the logic high signal can couple the column select line 178 to the first ground terminal 186 via the corresponding fourth switch 264. Therefore, the column driver circuitry 162 can ground the corresponding column select line 178. For example, such column select lines 178 may not be coupled to the target memory cell.

[0102] Figure 12The column driver 176 is the second column driver group 166-2 described above according to embodiments of this disclosure. The column driver 176 may include a first inverter 192 and a second inverter 194 coupled to the memory bank 102 via a column select line 178. The negative supply voltage input of the first inverter 192 may be coupled to a first control logic 196 or a second control logic 198. In the depicted embodiment, the positive supply voltage input of the first inverter 192 may be coupled to a first supply voltage 182. Furthermore, the supply voltage input of the first control logic 196 or the second control logic 198 may be coupled to the first supply voltage 182. In alternative or additional embodiments, the positive supply voltage input of the first inverter 192 and / or the supply voltage input of the first control logic 196 or the second control logic 198 may be coupled to a common supply voltage 206. For example, the second column driver group 166-2 may include the components described above. Figure 6 The pull-up switch 214 is described.

[0103] First switch 210 couples a first supply voltage 182 to the positive supply voltage input of the second inverter 194. Second switch 212 couples a second supply voltage 184 to the positive supply voltage input of the second inverter 194. Third switch 262 couples a third supply voltage 260 to the negative supply voltage input of the second inverter 194. Fourth switch 264 couples a first ground terminal 186 to the negative supply voltage input of the second inverter 194.

[0104] The first inverter 192 can generate a logic low bit based on the logic high bit of the column address 180 of the input select column driver 176. The second inverter 194 can generate a column select signal 168 with a logic high bit. In some cases, the logic high bit of the column select signal 168 can have three voltage steps. The column select signal 168 can have a first voltage step followed by a second voltage step and a third voltage step. The first voltage step can have a voltage level based on the voltage level of the second supply voltage 184. The second voltage step can have a voltage level based on the voltage level of the first supply voltage 182. The third voltage step can have a voltage level based on the voltage level of the third supply voltage 260. The voltage level of the first voltage step can be higher than the voltage levels of the second and third voltage steps. The voltage level of the third voltage step can be lower than the voltage levels of the first and second voltage steps.

[0105] Figure 13 This describes an embodiment of the present disclosure for use as discussed above. Figure 12The column driver 176 provides a timing diagram of control signals 220, 222, 280, and 282 for a common supply voltage 206 with two voltage steps. First switch 210, second switch 212, third switch 262, and fourth switch 264 can receive the first control signal 220, the second control signal 222, the third control signal 280, and the fourth control signal 282, respectively. For example, first switch 210 and second switch 212 may each include a pMOS transistor, and third switch 262 and fourth switch 264 may each include an nMOS transistor. The column driver 176 (e.g., first inverter 192) can receive the rising edge of the logic high bit of column address 180 at time T1.

[0106] During the time interval between T1 and T2, the first control signal 220 and the fourth control signal 282 may have a high voltage level. The second control signal 222 and the third control signal 280 may have a low voltage level. The first switch 210 may be open, the second switch 212 may be closed, the third switch 262 may be open, and the fourth switch 264 may be closed. The second inverter 194 of the column driver 176 may be coupled to the second supply voltage 184 and the first ground terminal 186 during the time interval between T1 and T2. Furthermore, the column driver 176 (e.g., the first inverter 192, the second inverter 194) may receive a portion of the logic high bits of the column address 180. Therefore, the second inverter 194 may generate a column select signal 168 with a second voltage level based on the voltage level of the second supply voltage 184 during the time interval between T1 and T2. For example, the second inverter 194 may couple the column select line 178 to the second supply voltage 184. The time interval between T1 and T2 can correspond to the first voltage step of the three voltage steps.

[0107] During the time period between T2 and T3, the first control signal 220 may have a low voltage level, the second control signal 222 may have a high voltage level, the third control signal 280 may have a high voltage level, and the fourth control signal 282 may have a low voltage level. Therefore, the first switch 210 may be closed, the second switch 212 may be open, the third switch 262 may be closed, and the fourth switch 264 may be open. The second inverter 194 of the column driver 176 may be coupled to the first supply voltage 182 and the third supply voltage 260 during the time period between T2 and T3. Furthermore, the column driver 176 (e.g., the first inverter 192, the second inverter 194) may receive the remaining high-order bits of the column address 180. Therefore, the second inverter 194 may generate a column select signal 168 with a first voltage level based on the voltage level of the first supply voltage 182 during the time period between T2 and T3. For example, the second inverter 194 may couple the column select line 178 to the first supply voltage 182. The time interval between T2 and T3 can correspond to the second voltage step among the three voltage steps.

[0108] During the time interval between T3 and T4, the first control signal 220 may have a low voltage level, the second control signal 222 may have a high voltage level, the third control signal 280 may have a high voltage level, and the fourth control signal 282 may have a low voltage level. Therefore, the first switch 210 may be closed, the second switch 212 may be open, the third switch 262 may be closed, and the fourth switch 264 may be open. The second inverter 194 of the column driver 176 may be coupled to the first supply voltage 182 and the third supply voltage 260 during the time interval between T2 and T3. Furthermore, the column driver 176 (e.g., the first inverter 192, the second inverter 194) may receive a logic low voltage. Therefore, the second inverter 194 may generate a column select signal 168 with a third voltage level based on the voltage level of the third supply voltage 260 during the time interval between T3 and T4. For example, the second inverter 194 may couple the column select line 178 to the third supply voltage 260. The time interval between T3 and T4 corresponds to the third voltage step among the three voltage steps.

[0109] It should be understood that the time periods between T1 and T2, T2 and T3, and T3 and T4 may differ in different embodiments. Furthermore, it should be understood that in alternative or additional embodiments, the first switch 210, the second switch 212, the third switch 262, and the fourth switch 264 of the column driver 176 may each comprise different switching circuits and / or transistor types. In such alternative or additional embodiments, the first control signal 220 and the second control signal 222 may differ based on the switching circuits and / or transistor types of the first switch 210 and the second switch 212. For example, the first control signal 220 and the second control signal 222 may each be inverted, delayed, or have different voltage levels and / or relative timing.

[0110] Figure 14 This describes an embodiment of the present disclosure where the selected column driver 176 is based on the foregoing description of... Figures 11 to 13 The graph illustrates the column selection signal 168 generated by the three voltage steps discussed. In some embodiments, the column selection signal 168 may initially have a voltage level (V2) based on the second supply voltage 184 coupled to the second supply voltage 184 by the second inverter 194. The common supply voltage 206 may then have a voltage level (V1) based on the first supply voltage 182 coupled to the first supply voltage 182 by the second inverter 194. The common supply voltage 206 may then have a voltage level (V3) based on the third supply voltage 260 coupled to the third supply voltage 260 by the second inverter 194. The first voltage level difference (ΔV1) between the voltage levels of the first supply voltage 182 and the second supply voltage 184, and the second voltage level difference (ΔV2) between the ground voltage and the third supply voltage 260, may be adjusted by a second voltage adjustment circuit. The first duration (ΔT1) for providing the voltage level of the second supply voltage and the second duration (ΔT2) for providing the voltage level of the third supply voltage may be adjusted by a delay circuit.

[0111] Figure 15 This describes the embodiments according to the present disclosure. Figure 12 The column driver 176 (e.g., the second inverter 194) is based on the proximal and distal sides of the column select line 178. Figure 13The control signals 220, 222, 280, and 282 are used to generate a graph of the voltage level of the column select signal 168. Specifically, the graph illustrates three voltage steps of the column select signal 168 at or near the near side of the memory bank 102 and at or near the far side of the memory bank 102. The column select signal 168 may have a first voltage step 224 with a voltage level based on the second supply voltage 184. Subsequently, the column select signal 168 may have a second voltage step 290 with a voltage level based on the first supply voltage 182 and a third voltage step 292 with a voltage level based on the third supply voltage 260.

[0112] Near or on the proximal side of column select line 178, the voltage level of the first voltage step 224 may be higher than the voltage level of the second voltage step 290. In some cases, the resistance and / or parasitic capacitance of column select line 178 may reduce the voltage level of column select signal 168 along column select line 178. For example, column select line 178 may have higher resistance and / or parasitic capacitance for accessing target memory cells located near the proximal side of memory bank 102 compared to accessing target memory cells located near the proximal side of memory bank 102. Thus, the voltage level of the first voltage step 224 may be reduced across column select line 178. For example, near or on the distal side of column select line 178, the voltage level of the first voltage step 224 may be lower than the voltage level of the second voltage step 290.

[0113] The higher voltage level of the first voltage step 224 of the column select signal 168 can compensate for at least a portion of the resistance and / or parasitic capacitance of the target memory cell located near the distal side of memory bank 102 (or coupled to column select line 178). In some cases, the higher voltage level of the first voltage step 224 can increase the rising edge slope or time of the column select signal 168 at or near the distal side of memory bank 102. Thus, the target memory cell coupled to column select line 178 at or near the distal side of memory bank 102 can receive the column select signal 168 with a voltage level equal to or higher than the voltage threshold 228 for a period of time equal to or higher than the desired time 230.

[0114] Near or on the side of column select line 178, the voltage level of the third voltage step 292 may be lower than the voltage levels of the first voltage step 224 and the second voltage step 290. As mentioned above, the resistance and / or parasitic capacitance of column select line 178 can reduce the voltage level of column select signal 168 along column select line 178. Therefore, the voltage level of the third voltage step 292 can be reduced across column select line 178.

[0115] The lower voltage level of the third voltage step 292, which is below ground, can compensate for at least a portion of the resistance and / or parasitic capacitance of the target memory cell located near the distal side of memory bank 102 (or coupled to column select line 178). In some cases, the voltage level of the third voltage step 292 can increase the falling edge slope or time of the column select signal 168 at or near the distal side of memory bank 102. For example, based on the lower voltage level of the third voltage step 292 being below ground, the target memory cell coupled to column select line 178 at or near the distal side of memory bank 102 can have reduced delay, residual voltage, and / or other undesirable effects.

[0116] In some embodiments, the column select line 178 may be coupled to an additional memory cell to increase the capacity of the memory bank 102 based on three voltage steps of the logic high bit of the column select signal 168. In a particular embodiment, the second voltage adjustment circuit may adjust the voltage levels of the second supply voltage 184 and / or the third supply voltage 260 based on the length of the column select line 178 or the placement of the target memory cell along the column select line 178. In alternative or additional embodiments, the delay circuit may adjust the first duration (ΔT1) for providing the voltage level of the second supply voltage 184 and / or the second duration (ΔT2) for providing the voltage level of the third supply voltage 260, or both, based on the length of the column select line 178 or the placement of the target memory cell along the column select line 178. For example, the second voltage adjustment circuit and / or the delay circuit may adjust the voltage levels and / or durations based on the column address 180 of the target memory cell, the segment address or block address of the target memory cell, and other possibilities.

[0117] Figure 16 This is a second voltage adjustment circuit 310 according to embodiments of the present disclosure for adjusting the voltage levels of a second supply voltage 184 and a third supply voltage 260 based on column address 180. The second voltage adjustment circuit 310 may include a multiplexer 242, a resistor string 244, a first amplifier 248, an output switch 252, a first feedback resistor 254, a second amplifier 312, an oscillator 314, a negative charge pump, and a second feedback resistor 318. The multiplexer 242 may receive a column address 180 associated with a second column driver group 166-2. As mentioned above, the input ports of the multiplexer 242 may each be coupled to different resistors or coupled between different resistors in the resistor string 244.

[0118] The resistor string 244 can be coupled to a voltage source on one side and to a ground terminal on the other side. The voltage source may include a first supply voltage 182 or... Figure 1The memory device 100 may be any other feasible voltage source. As discussed above, the multiplexer 242 may generate a reference voltage 246 by selecting an input port based on column address 180. In certain non-limiting cases, column address 180 may indicate one or more memory cells for a single memory cell or a single memory segment or memory partition. In some embodiments, the multiplexer 242 may have several input ports corresponding to several segments or partitions of the memory bank 102 discussed above. For example, the multiplexer 242 may select an input port corresponding to a segment address or partition address of a target memory cell based on column address 180. Alternatively or additionally, instead of receiving column address 180 or other than receiving column address 180, the multiplexer 242 may receive segment address or partition address. In some embodiments, the second voltage adjustment circuit 310 (and / or multiplexer 242) may include a lookup table to select the input port coupled to the resistor string 244 based on the segment address, section address, and / or column address 180.

[0119] The first amplifier 248 can generate the gate voltage of the output switch 252 based on a received reference voltage 246 and a first feedback signal 250. The output switch 252 can be coupled to a voltage source on one side and to a ground terminal via a first feedback resistor 254 on the other side. The first amplifier 248 can receive the first feedback signal 250 from the first feedback resistor 254. The voltage source can include a first supply voltage 182 or... Figure 1 The memory device 100 may use any other feasible voltage source. The output switch 252 may output a second supply voltage 184.

[0120] The second amplifier 312 can generate an input signal for the oscillator 314 based on the received reference voltage 246 and the second feedback signal 316. The second amplifier 312 can receive the second feedback signal 316 from a second feedback resistor 318 coupled to the output of the negative charge pump 320. The oscillator 314 can generate an oscillation signal based on the input signal received from the second amplifier 312. The negative charge pump 320 can input the oscillation signal. The negative charge pump 320 can output a third supply voltage 260 based on the received oscillation signal.

[0121] Considering the above, the voltage level of the reference voltage 246 can correspond to the voltage levels of the second supply voltage 184 and the third supply voltage 260. For example, adjusting the voltage level of the reference voltage 246 can correspond to adjusting the voltage levels of the second supply voltage 184 and the third supply voltage 260. As mentioned above, the multiplexer 242 can select the appropriate input port based on the column address, segment address, or section address of the target memory cell to output a reference voltage with a voltage level.

[0122] Therefore, the second voltage adjustment circuit 310 can provide a second supply voltage 184 and a third supply voltage 260 with voltage levels based on the column address 180 and / or segment address or block address of the target memory cell. Thus, the second voltage adjustment circuit 310 can adjust the first voltage level difference (ΔV1) between the second supply voltage 184 and the voltage level of the first supply voltage 182. Furthermore, the second voltage adjustment circuit 310 can adjust the second voltage level difference (ΔV2) between the third supply voltage 260 and the voltage level of the ground voltage and the voltage level of the third supply voltage 260. It should be understood that in different embodiments, the second voltage adjustment circuit 310 may include different circuit systems to provide the second supply voltage 184 and / or the third supply voltage 260 based on the column address 180 and / or segment address or block address of the target memory cell.

[0123] Figure 17 According to embodiments of the present disclosure, a delay circuit 330 is used to adjust a first duration (ΔT1) of the voltage level for providing a second supply voltage 184 and a second duration (ΔT2) of the voltage level for providing a third supply voltage 260 based on the column address 180 of the target memory cell during the duration of the column select signal 168. The delay circuit 330 may include an OR logic circuit 332, a first delay component 334, a second delay component 336, a first buffer 338 (e.g., a first amplifier), and a second buffer 340 (e.g., a second amplifier).

[0124] OR logic circuit 332 can receive column address 180 (e.g., CA<15:0>) of a target memory cell associated with the second column driver group 166-2. OR logic circuit 332 can output a logic high bit in response to any bit of column address 180 having a logic high voltage. OR logic circuit 332 can output the logic high bit to a first delay component 334. First delay component 344 can delay the logic high bit. First delay component 334 can output the delayed logic high bit to a first buffer 338. First buffer 338 can output a first control signal 220 and a second control signal 222 in response to receiving the logic high bit. As discussed above, the first switch 210 and the second switch 212 of the second column driver group 166-2 can receive the first control signal 220 and the second control signal 222.

[0125] The second delay component 336 may receive a portion (e.g., CA) of the column address 180 associated with a memory cell coupled to the column select line 178 (e.g., first column select line 178, second column select line 178, etc.) of the second column driver group 166-2. <0> CA <1> CA <2> (etc.). The second delay component 336 may output a delayed logic high bit to the second buffer 340 in response to receiving a logic high bit. Alternatively, in some cases, the second delay component 336 may output a logic low bit to the second buffer 340 in response to receiving a logic low bit.

[0126] The second buffer 340 can output a third control signal 280 and a fourth control signal 282 in response to receiving a logic high bit. This is related to the portion of column address 180 (e.g., CA). <0> CA <1> CA <2> The third switch 262 and the fourth switch 264 associated with the column selection line 178 (etc.) can receive the first control signal 220, the third control signal 280, and the fourth control signal 282. Therefore, the delay circuit 330 can adjust the first duration (ΔT1) for providing the voltage level of the second supply voltage 184 and / or the second duration (ΔT2) for providing the voltage level of the third supply voltage 260.

[0127] In some embodiments, the first buffer 338 and the second buffer 340 may be based on Figure 13 The timing diagram is used to output control signals 220, 222, 280, and 282. Although the first delay component 334, the second delay component 336, the first buffer 338 (e.g., the first amplifier), and the second buffer 340 are shown, it should be understood that the delay circuit 330 may include additional delay circuitry and buffers, for example, for coupling to the aforementioned... Figure 11 and 12 Each of the remaining column selection lines 178 in the second column driver group 166-2 discussed herein. Furthermore, it should be understood that in additional or different embodiments, the delay circuit 330 may include different circuit systems to generate control signals 220, 222, 280, and 282.

[0128] Figure 18 This is a block diagram of a third column driver group 166-3 having a column driver circuit system 162 with separate column select line drivers for near and far memory cells of memory bank 102 according to an embodiment of the present disclosure. The third column driver group 166-3 may include a top column driver 176-1, a bottom column driver 176-2, first control logic 196, and second control logic 198. Each column driver 176 may include a first inverter 192, a second inverter 194, and a third inverter 350.

[0129] The positive supply voltage inputs of the first inverter 192 and the second inverter 350 can be coupled to the first supply voltage 182. The negative supply voltage input of the first inverter 192 of the top column driver 176-1 can be coupled to the first control logic 196. The negative supply voltage input of the first inverter 192 of the bottom column driver 176-2 can be coupled to the second control logic 198. The supply voltage inputs of the first control logic 196 and the second control logic can be coupled to (or may be coupled to) the first supply voltage 182 or switch between being coupled to the first supply voltage 182 and the second supply voltage 184, as described above. Figures 5 to 7 As discussed above, the negative supply voltage input of the third inverter 350 of each column driver 176 can be coupled to the output port of the first inverter 192 of the corresponding column driver 176.

[0130] The input port of the second inverter 194 of each column driver 176 can be coupled to the negative supply voltage input of the third inverter 350 of the corresponding column driver 176 and the output port of the first inverter 192. The positive supply voltage input of the second inverter 194 can be coupled to the first supply voltage 182 and the second supply voltage 184 via the first switch 210 and the second switch 212, respectively. The negative supply voltage input of the second inverter 194 can be coupled to the third supply voltage 260 and the first ground terminal 186 via the third switch 262 and the fourth switch 264, respectively.

[0131] The third column driver group 166-3 can generate a column select signal 168 based on the received column address 180 (e.g., CA<15:0>) and clock signal 204. When column address 180 is for a near memory cell, the third inverter 350 can output the column select signal 168. When column address 180 is for a far memory cell, the second inverter 194 can output the column select signal 168. In some cases, the third inverter 350 can provide the column select signal 168 based on the voltage level of a first supply voltage 182 coupled to the corresponding positive supply voltage input. Furthermore, the second inverter 194 can provide the column select signal 168 based on the voltage levels of the first supply voltage 182, the second supply voltage 184, and / or the third supply voltage. For example, the second inverter 194 can be based on the voltage levels described above regarding... Figures 4 to 10 The operation of the first column drive group 166-1 described above or based on the above... Figures 11 to 17 The operation of the second column driver group 166-2 is described to provide column selection signal 168.

[0132] As mentioned above, in some cases, the column select line 178 may have higher resistance and / or parasitic capacitance for accessing target memory cells located near the proximal side of the memory bank 102 compared to accessing target memory cells located far from the proximal side of the memory bank 102. Furthermore, the resistance and / or parasitic capacitance of the column select line 178 may reduce the voltage level of the column select signal 168 along the column select line 178. Therefore, the third inverter 350 may provide the column select signal 168 to the proximal memory cell, and the second inverter 194 may provide the column select signal 168 to the far memory cell.

[0133] In different embodiments, distant memory cells and near memory cells may be associated with different column addresses 180, different groups of segments 172, and / or different groups of sub-segments 170 of memory bank 102. (The above refers to...) Figure 2 The different sections 172 and segments 170 of the memory bank 102 are described. For example, a third inverter 350 may provide a column select signal 168 to memory cells located in the first section 172 and / or the first segment 170 (e.g., or a first number of sections 172 and / or segments 170) closest to the corresponding column driver 176. Furthermore, a second inverter 194 may provide column select signals 168 to memory cells in the remaining sections 172 and / or segments 170.

[0134] In some embodiments, the memory controller 108 described above may enable and disable the second inverter 194 and the third inverter 350 of the third column driver group 166-3 based on the column address 180 of the target memory cell. Alternatively or additionally, the memory device 100 or the third column driver group 166-3 described above may include additional circuitry. Additional circuitry may include combinations of logic circuitry and other possibilities. Additional circuitry may enable and disable the second inverter 194 and the third inverter 350 of the third column driver group 166-3 based on the column address 180 of the target memory cell. For example, the memory controller 108 and / or the additional circuitry and other possibilities may generate control signals to enable and disable switches 210, 212, 262, and 264. In some embodiments, the positive supply voltage input of the third inverter 350 may be coupled to the first supply voltage 182 via a fifth switch (not shown for simplicity). The fifth switch may receive control signals to enable and disable the third inverter 350.

[0135] The specific embodiments described above have been illustrated by examples, and it should be understood that various modifications and alternatives are permissible. It should be further understood that the claims are not intended to limit the specific forms disclosed, but rather to cover all modifications, equivalents, and alternatives falling within the spirit and scope of this disclosure.

[0136] The techniques proposed and claimed herein are referenced and applied to practical objects and concrete examples that clearly improve the field of technology and are therefore not abstract, intangible, or purely theoretical. Furthermore, if any claim appended to this specification contains one or more elements expressed as “a component for [performing…function]” or “a step for [performing…function]”, then such elements are intended to be interpreted according to 35U.SC112(f). However, for any claim containing elements expressed in any other way, such elements are not intended to be interpreted according to 35U.SC112(f).

[0137] As is widely known, the use of personally identifiable information should comply with privacy policies and practices, which are generally considered to meet or exceed industry or government requirements for protecting user privacy. Specifically, personally identifiable information data should be managed and processed to minimize the risk of unintentional or unauthorized access or use, and users should be clearly informed of the nature of authorized use.

Claims

1. A memory device, comprising: a plurality of memory cells coupled to a number of column select lines; a column driver coupled to a column select line of the number of column select lines, wherein the column driver is configured to generate a single column select signal having at least two voltage levels to access a target memory cell of the plurality of memory cells coupled to the column select line.

2. The memory device of claim 1, wherein the column driver is configured to generate a first portion of the column select signal having a first voltage level of the at least two voltage levels and to generate a subsequent portion of the column select signal having a second voltage level of the at least two voltage levels that is lower than the first voltage level, wherein the first voltage level and the second voltage level are higher than a threshold voltage level associated with accessing the target memory cell.

3. The memory device of claim 2, wherein the column driver is coupled to a first supply voltage via a first switch and to a second supply voltage via a second switch.

4. The memory device of claim 3, wherein the column driver is configured to be coupled to the first supply voltage via the first switch to generate the first portion of the column select signal having the first voltage level and to be coupled to the second supply voltage via the second switch to generate the subsequent portion of the column select signal having the second voltage level.

5. The memory device of claim 2, wherein the column driver is configured to generate a second subsequent portion of the column select signal having a third voltage level of the at least two voltage levels that is lower than a ground voltage level of the memory device.

6. The memory device of claim 1, comprising a ground terminal coupled to a distal side of the column select line, the distal side being opposite a side of the column select line coupled to the column driver via a ground switch.

7. The memory device of claim 6, wherein the memory device is configured to couple the distal side of the column select line to the ground terminal based on a falling edge of the column select signal.

8. The memory device of claim 1, comprising a voltage adjustment circuit coupled to the column driver, wherein the voltage adjustment circuit is configured to adjust a voltage level of the at least two voltage levels based on a column address of the target memory cell.

9. A memory device, comprising: a plurality of memory cells coupled to a number of column select lines; a first supply voltage; a second supply voltage; a column driver coupled to a column select line of the number of column select lines, wherein the column driver is configured to generate a single column select signal having at least two voltage levels based on being coupled to the first supply voltage and the second supply voltage.

10. The memory device of claim 9, comprising a voltage adjustment circuit coupled to the column driver, wherein the voltage adjustment circuit is configured to adjust a voltage level difference between the first supply voltage and the second supply voltage based on a column address of a first target memory cell in the plurality of memory cells.

11. The memory device of claim 10, wherein the voltage adjustment circuit is configured to increase the voltage level difference for accessing a second target memory cell in the plurality of memory cells further than the voltage level difference for accessing the first target memory cell, wherein the second target memory cell is disposed further along the column select line relative to the first target memory cell.

12. The memory device of claim 9, comprising a first switch coupled to the first supply voltage and the column driver and a second switch coupled to the second supply voltage and the column driver.

13. The memory device of claim 12, wherein the column driver is configured to generate a first portion of the column select signal based on being coupled to the first supply voltage via the first switch and generate a subsequent portion of the column select signal based on being coupled to the second supply voltage via the second switch.

14. The memory device of claim 9, wherein the at least two voltage levels are higher than a threshold voltage level associated with accessing a target memory cell in the plurality of memory cells.

15. A memory device, comprising: a plurality of memory cells coupled to a number of column select lines; a first supply voltage; a voltage adjustment circuit configured to provide a second supply voltage based on a column address of a first target memory cell in the plurality of memory cells; and a column driver coupled to the first supply voltage, the second supply voltage, and a column select line in the number of column select lines, wherein the column driver is configured to generate a single column select signal having a first voltage level based on being coupled to the first supply voltage and generate the single column select signal having a second voltage level based on being coupled to the second supply voltage.

16. The memory device of claim 15, wherein the voltage adjustment circuit is configured to adjust a voltage level difference between the first supply voltage and the second supply voltage based on the column address of the first target memory cell.

17. The memory device of claim 16, wherein the voltage adjustment circuit is configured to increase the voltage level difference for accessing a second target memory cell in the plurality of memory cells further than the voltage level difference for accessing the first target memory cell, wherein the second target memory cell is disposed further along the column select line relative to the first target memory cell.

18. The memory device of claim 15, wherein the column driver is configured to be coupled to the first supply voltage via a first switch to generate a first portion of the column select signal having the first voltage level and to be coupled to the second supply voltage via a second switch to generate a subsequent portion of the column select signal having the second voltage level.

19. The memory device of claim 15, comprising a third supply voltage, wherein the column driver is configured to generate a second subsequent portion of the column select signal having a third voltage level lower than a ground voltage level of the memory device based on being coupled to the third supply voltage.

20. The memory device of claim 15, wherein the voltage adjustment circuit is coupled to the first supply voltage, wherein the voltage adjustment circuit is configured to generate the second supply voltage based on a voltage level of the first supply voltage.

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