Passivation layer forming process and semiconductor device

Abstract

The invention discloses a passivation layer forming process and a semiconductor device, and the passivation layer forming process comprises the steps: providing a semiconductor device which comprises a device core layer and a plurality of top layer metals located at the top of the device core layer; depositing a silicon-rich oxide layer, wherein the silicon-rich oxide layer covers the surface of the liner oxide layer; depositing a high-density plasma layer, wherein the high-density plasma layer covers the surface of the silicon-rich oxide layer; depositing a top oxide layer, wherein the top oxide layer covers the high-density plasma layer; the top oxide layer is thinned to the target thickness through a chemical mechanical polishing technology, so that the high-density plasma layer located above the top layer metal is exposed; and depositing a silicon nitride layer, wherein the silicon nitride layer covers the residual top oxide layer and the exposed top of the high-density plasma layer. According to the scheme, the reliability of the passivation layer can be improved.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor manufacturing, specifically to a passivation layer formation process and a semiconductor device. Background Technology

[0002] In semiconductor manufacturing, the passivation layer is a protective dielectric film deposited at the end of the chip manufacturing process, forming the top layer of the device. Its core function is to isolate the chip's internal structure from external environmental influences, while protecting the device from physical and chemical damage, ensuring long-term stable operation. Under asymmetric stress cycling, materials will experience a cyclic accumulation of inelastic deformation, a phenomenon known as the ratchet effect. During temperature cycling tests, the passivation layer accumulates stress at corners. When the metal wires undergo plastic deformation induced by the ratchet effect, the accumulated stress makes the passivation layer highly susceptible to cracking. This causes the passivation layer to lose its protective function for the internal circuitry and interconnects of the chip, ultimately leading to chip reliability failure. Summary of the Invention

[0003] This application provides a passivation layer formation process and a semiconductor device, which can solve the problem of cracks in the passivation layer during temperature cycling tests in related technologies and improve the reliability of the passivation layer.

[0004] In a first aspect, embodiments of this application provide a passivation layer formation process, including: A semiconductor device is provided, the semiconductor device including a device core layer and a plurality of top layer metals located on top of the device core layer; A deposited pad oxide layer is formed, which covers the surface of the top metal and the device core layer; A silicon-rich oxide layer is deposited, which covers the surface of the pad oxide layer; A high-density plasma layer is deposited, which covers the surface of the silicon-rich oxide layer; A top oxide layer is deposited, which covers the high-density plasma layer; The top oxide layer is thinned to the target thickness using a chemical mechanical polishing process, exposing the high-density plasma layer located above the top metal layer. A silicon nitride layer is deposited, which covers the remaining top oxide layer and the top of the exposed high-density plasma layer.

[0005] In some embodiments, the material of the liner oxide layer is plasma-enhanced oxide.

[0006] In some embodiments, the top oxide layer is made of plasma-enhanced oxide.

[0007] In some embodiments, the thickness of the top layer metal is ≤ 25000 angstroms, and the spacing between adjacent top layer metals is ≥ 1500 angstroms.

[0008] In some embodiments, the thickness of the liner oxide layer is 1500-2000 angstroms.

[0009] In some embodiments, the thickness of the silicon-rich oxide layer is 300-400 angstroms.

[0010] In some embodiments, the thickness of the high-density plasma layer is 10,000-15,000 angstroms.

[0011] In some embodiments, the thickness of the silicon nitride layer is 5000-6000 angstroms.

[0012] Secondly, embodiments of this application provide a semiconductor device, wherein the passivation layer in the semiconductor device is manufactured by the passivation layer forming process described in the first aspect, and the semiconductor device further includes a device core layer and a plurality of top metals located on top of the device core layer. The passivation layer covers the top of the device core layer and the top metals, and the passivation layer includes, from bottom to top, a pad oxide layer, a silicon-rich oxide layer, a high-density plasma layer, a top oxide layer, and a silicon nitride layer.

[0013] The technical solution of this application has at least the following advantages: 1. By sequentially depositing a pad oxide layer, a silicon-rich oxide layer, a high-density plasma layer, a top oxide layer, and a silicon nitride layer on a semiconductor device, a passivation layer covering the device's core layer and top metal is obtained. This process can achieve a fully filled, void-free passivation layer while reducing the use of the high-density plasma layer. Simultaneously, the balance of thermal expansion coefficients and Young's moduli among the different film materials in this passivation layer effectively mitigates spike-induced cracking in the top metal during temperature cycling, preventing crack formation in the passivation layer and improving the reliability of the semiconductor device. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the specific embodiments of this application or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0015] Figure 1 This is a flowchart of a passivation layer formation process provided in an exemplary embodiment of this application; Figures 2-7This is a schematic diagram of a device structure provided in an exemplary embodiment of the present application to illustrate the implementation process of the passivation layer formation process; Figure 8 This is a schematic diagram of the structure of a semiconductor device provided in an exemplary embodiment of this application.

[0016] Explanation of reference numerals in the attached figures: 1. Device core layer; 2. Top metal layer; 3. Pad oxide layer; 4. Silicon-rich oxide layer; 5. High-density plasma layer; 6. Top oxide layer; 7. Silicon nitride layer. Detailed Implementation

[0017] The technical solutions of this application will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0019] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0020] Furthermore, the technical features involved in the different embodiments of this application described below can be combined with each other as long as they do not conflict with each other.

[0021] This application provides a passivation layer formation process, referring to... Figure 1 The passivation layer formation process includes the following steps: S1: A semiconductor device is provided, the semiconductor device including a device core layer and a plurality of top layer metals located on top of the device core layer.

[0022] For example, refer to Figure 2 A semiconductor device is provided, which includes a device core layer 1 and a plurality of top metal layers 2 located on top of the device core layer 1. The device core layer 1 may include the main structure of the semiconductor device (not shown in the figure), such as a substrate, an epitaxial layer, an active region, and a bottom metal interconnect. The material of the top metal layers 2 may be aluminum, etc.

[0023] S2: Deposit pad oxide layer, which covers the surface of the top metal and the device core layer.

[0024] For example, refer to Figure 3 A pad oxide layer 3 is deposited on the surface of the top metal 2 and the surface of the device core layer 1. The pad oxide layer 3 is used to isolate the top metal 2 and the subsequently deposited upper material to prevent chemical reaction between the top metal 2 and the upper material.

[0025] Furthermore, the material of the pad oxide layer 3 can be plasma-enhanced oxide (PEOX), which can be obtained by depositing silicon oxide through plasma-enhanced chemical vapor deposition (PECVD) process.

[0026] Furthermore, the thickness of the liner oxide layer 3 can be 1500-2000 angstroms.

[0027] S3: Deposit a silicon-rich oxide layer, which covers the surface of the pad oxide layer.

[0028] For example, refer to Figure 3 A silicon-rich oxide (SRO) layer is deposited to obtain a silicon-rich oxide layer 4, which covers the surface of the pad oxide layer 3. Due to the silicon-rich properties of the silicon-rich oxide, the silicon-rich oxide layer 4 can act as a diffusion barrier layer to suppress the influence of ion bombardment on the top metal 2 in subsequent processes and improve the interfacial adhesion with the layers formed in subsequent processes.

[0029] Furthermore, a silicon-rich oxide layer 4 can be deposited using a PECVD process.

[0030] Furthermore, the thickness of the silicon-rich oxide layer 4 can be 300-400 angstroms.

[0031] S4: Deposit a high-density plasma layer, which covers the surface of the silicon-rich oxide layer.

[0032] For example, refer to Figure 4A high-density plasma (HDP) layer 5 can be formed using a high-density plasma chemical vapor deposition process, and the HDP layer 5 covers the surface of the silicon-rich oxide layer 4. The HDP layer 5 has the characteristics of high density and excellent step coverage, thus ensuring the quality of the final passivation layer.

[0033] Furthermore, the thickness of the deposited high-density plasma layer 5 can be 10,000-15,000 angstroms.

[0034] S5: Deposit a top oxide layer, which covers a high-density plasma layer.

[0035] For example, refer to Figure 5 A top oxide layer 6 is deposited on top of the high-density plasma layer 5. By depositing the top oxide layer 6, the use of the high-density plasma layer 5 can be reduced, the process time cost can be reduced, and the surface can be ensured to be relatively smooth.

[0036] The top oxide layer 6 can be made of plasma-enhanced oxide.

[0037] S6: The top oxide layer is thinned to the target thickness through a chemical mechanical polishing process, exposing the high-density plasma layer above the top metal layer.

[0038] For example, refer to Figure 6 The top oxide layer 6 is flattened by chemical mechanical polishing (CMP) to reduce it to the target thickness, thereby exposing the high-density plasma layer 5 above the top metal layer 2.

[0039] S7: Deposit a silicon nitride layer, which covers the remaining top oxide layer and the exposed top of the high-density plasma layer.

[0040] For example, refer to Figure 7 A silicon nitride layer 7 is deposited, which covers the remaining top oxide layer 6 and the top of the exposed high-density plasma layer 5. The silicon nitride layer 7 serves as the top layer of the passivation layer, preventing moisture and ion intrusion while providing mechanical protection.

[0041] Furthermore, in this step, a silicon nitride layer 7 can be deposited using a PECVD process.

[0042] Furthermore, the thickness of the silicon nitride layer 7 can be 5000-6000 angstroms.

[0043] Furthermore, the passivation layer formation process described above is applicable to semiconductor devices where the thickness of the top metal 2 is ≤ 25000 angstroms and the spacing between adjacent top metals 2 is ≥ 1500 angstroms.

[0044] This application provides a passivation layer formation process that sequentially deposits a pad oxide layer 3, a silicon-rich oxide layer 4, a high-density plasma layer 5, a top oxide layer 6, and a silicon nitride layer 7 on a semiconductor device, thereby obtaining a passivation layer covering the core layer 1 and the top metal layer 2. This process can achieve a fully filled, void-free passivation layer while reducing the use of the high-density plasma layer. Furthermore, the balance of thermal expansion coefficients and Young's moduli among the different film materials in this passivation layer effectively mitigates spike induction in the top metal during temperature cycling testing, preventing crack formation in the passivation layer and improving the reliability of the semiconductor device.

[0045] Furthermore, embodiments of this application also provide a semiconductor device in which the passivation layer is manufactured using the passivation layer formation process described above. (Refer to...) Figure 8 The semiconductor device also includes a device core layer 1 and several top metal layers 2 located on top of the device core layer 1. The passivation layer covers the top of the device core layer 1 and the top metal layers 2, and the passivation layer includes, from bottom to top, a pad oxide layer 3, a silicon-rich oxide layer 4, a high-density plasma layer 5, a top oxide layer 6, and a silicon nitride layer 7.

[0046] Obviously, the above embodiments are merely illustrative examples for clear explanation and are not intended to limit the implementation. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. However, obvious variations or modifications derived therefrom are still within the scope of protection of this application.

Claims

1. A passivation layer forming process, characterized by, The application provides a semiconductor device manufacturing method, which comprises the following steps: providing a semiconductor device, which comprises a device core layer and a plurality of top metal layers on the top of the device core layer; depositing a liner oxide layer, which covers the top metal layers and the surface of the device core layer; depositing a silicon-rich oxide layer, which covers the surface of the liner oxide layer; depositing a high-density plasma layer, which covers the surface of the silicon-rich oxide layer; depositing a top oxide layer, which covers the high-density plasma layer; thinning the top oxide layer to a target thickness by a chemical mechanical polishing process, so that the high-density plasma layer above the top metal layers is exposed; depositing a silicon nitride layer, which covers the remaining top oxide layer and the top of the exposed high-density plasma layer.

2. The passivation layer forming process according to claim 1, wherein The liner oxide layer is made of plasma-enhanced oxide.

3. The passivation layer formation process of claim 1, wherein, The top oxide layer is made of plasma-enhanced oxide.

4. The passivation layer formation process of claim 1, wherein, The thickness of the top metal layers is less than or equal to 25000 angstroms, and the distance between adjacent top metal layers is greater than or equal to 1500 angstroms.

5. The passivation layer formation process of claim 2, wherein, The thickness of the liner oxide layer is 1500-2000 angstroms.

6. The passivation layer formation process of claim 1, wherein, The thickness of the silicon-rich oxide layer is 300-400 angstroms.

7. The passivation layer formation process of claim 1, wherein, The thickness of the high-density plasma layer is 10000-15000 angstroms.

8. The passivation layer formation process of claim 1, wherein, The thickness of the silicon nitride layer is 5000-6000 angstroms.

9. A semiconductor device, characterized by comprising: The passivation layer in the semiconductor device is manufactured by the passivation layer forming process in any one of claims 1-8, the semiconductor device further comprises a device core layer and a plurality of top metal layers on the top of the device core layer, the passivation layer covers the top of the device core layer and the top metal layers, and the passivation layer comprises, from bottom to top, a liner oxide layer, a silicon-rich oxide layer, a high-density plasma layer, a top oxide layer and a silicon nitride layer.

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