Pollution-free copper interconnects on aluminum pads

Abstract

Embodiments disclosed herein include an apparatus that includes a pad, and the pad includes aluminum. In an embodiment, the liner is on a sidewall of the pad, and the liner extends beyond a surface of the pad. In an embodiment, the first layer is over the pad, and the first layer includes copper. In an embodiment, the second layer is over the first layer, and the second layer is a dielectric material. In an embodiment, a via passes through the second layer and contacts the first layer.

Description

Background Technology

[0001] In advanced packaging, hybrid bonding is a key enabler of higher bandwidth, increased power, and improved signal integrity. In addition to dielectric-to-dielectric bonding adjacent to the pads, hybrid bonding also includes direct metal-to-metal bonding of the pads. Due to process complexity, this hybrid bonding is typically limited to the fabrication of copper-to-copper bonding and / or copper interconnects. In some cases, the incoming wafer may include aluminum pads and / or interconnects.

[0002] However, the bonding of aluminum pads presents several challenges. One issue is that the handling of aluminum can lead to contamination of dry etching tools used in subsequent copper-based processes. Wet cleaning processes used to remove organometallic polymers from dry etching may also involve aluminum. Consequently, it is difficult to integrate systems with incoming aluminum pads into existing process flows. Furthermore, reliable direct bonding between copper and aluminum does not produce interconnects with the same reliability and performance as copper-to-copper interconnects. Attached Figure Description

[0003] Figure 1A This is a cross-sectional view of a die including aluminum pads according to an embodiment.

[0004] Figure 1B This is a cross-sectional view of a die including an aluminum pad with an aluminum via, according to an embodiment.

[0005] Figure 2A This is a cross-sectional view of a die with aluminum pads according to an embodiment, the aluminum pads including a cap between copper pads and aluminum pads.

[0006] Figure 2B This is an enlarged view of the aluminum pads, caps, vias, and copper pads according to the embodiment.

[0007] Figure 2C This is an enlarged view of the aluminum pad, cap, via, and copper pad according to an embodiment, wherein there is a non-flat interface between the aluminum pad and the cap.

[0008] Figures 3A to 3I This is a cross-sectional view depicting a process for forming a cap layer on an aluminum pad according to an embodiment.

[0009] Figure 4A and Figure 4B This is a cross-sectional view depicting the hybrid bonding process between a die with aluminum pads and a packaging substrate according to an embodiment.

[0010] Figure 5 This is a flowchart of a process for forming a cap layer on an aluminum pad according to an embodiment.

[0011] Figure 6This is a cross-sectional view of an electronic system having a die with hybrid bonding to a packaging substrate according to an embodiment, wherein the die has aluminum pads and a cap layer.

[0012] Figure 7 This is a schematic diagram of a computing device constructed according to an embodiment. Detailed Implementation

[0013] This document describes copper-to-aluminum hybrid bonding interconnects according to various embodiments. In the following description, terms commonly used by those skilled in the art will be used to describe various aspects of the illustrative embodiments to convey the essence of their work to those skilled in the art. However, it will be apparent to those skilled in the art that this disclosure may be practiced using only some of the described aspects. Specific quantities, materials, and configurations are set forth for purposes of explanation to provide a thorough understanding of the illustrative embodiments. However, it will be apparent to those skilled in the art that this disclosure may be practiced without specific details. In other instances, well-known features have been omitted or simplified to avoid obscuring the illustrative embodiments.

[0014] Various operations will be described as multiple discrete operations, and then described in a manner most conducive to understanding this disclosure; however, the order of description should not be construed as implying that these operations necessarily depend on the order. In particular, these operations do not need to be performed in the order presented.

[0015] This document describes various embodiments or aspects of this disclosure. In some implementations, different embodiments are implemented independently. However, the embodiments are not limited to individually implemented embodiments. For example, two or more different embodiments may be combined together to be implemented as a single device, process, structure, etc. In some cases, the entirety of the various embodiments may be combined together. In other cases, a portion of a first embodiment may be combined with portions of one or more different embodiments. For example, a portion of a first embodiment may be combined with a portion of a second embodiment, or a portion of a first embodiment may be combined with portions of a second embodiment and portions of a third embodiment.

[0016] As mentioned above, some dies have aluminum pads. When hybrid bonding is desired, these aluminum pads introduce complexity in subsequent processes. For example, the presence of aluminum during dry etching processes can contaminate etching tools used in other copper-based processes. Therefore, integrating such incoming dies into existing hybrid bonding processes is currently not feasible. Furthermore, aluminum-to-copper hybrid bonding may not offer the same reliability and / or performance as copper-to-copper hybrid bonding.

[0017] Therefore, the embodiments disclosed herein may include fabricating an additional layer on top of the aluminum pad to prevent subsequent exposure to aluminum. The subsequent layer may also include copper for copper-to-copper interconnect bonding to improve performance and / or reliability. In embodiments, the structure covering the aluminum pad may include a cap comprising copper. In such embodiments, the aluminum pad may be recessed below the top surface of a passivation layer for the aluminum pad. The cap may then be deposited into the recess above the aluminum pad. In embodiments, subsequent vias and pads (which may also comprise copper) may be formed on top of the cap.

[0018] In one embodiment, the interface between the aluminum pad and the cap can be substantially flat. In other embodiments, the interface between the aluminum pad and the cap can be non-flat. This non-flat interface can increase the strength of the interface and allow for improved reliability.

[0019] Now for reference Figure 1A The diagram illustrates a cross-sectional view of a die 100 according to an embodiment. In this embodiment, the die 100 may include a substrate 101. The substrate 101 may be a semiconductor substrate, such as a silicon substrate. During some or all of the manufacturing processes described herein, the die 100 may be part of a complete wafer. That is, during some or all of the manufacturing processes described herein, the substrate 101 may not be singled out as a separate die 100. In this embodiment, a front-end process (FEOL) layer 102 may be provided on the substrate 101. The FEOL layer 102 may include transistor devices, etc. (not shown separately). In this embodiment, one or more back-end process (BEOL) layers and / or packaging layers may be provided above the FEOL layer 102. For example, the BEOL layer and / or packaging layer may include dielectric layers 103, 104, and 105 that may be separated from each other using etch stop layers 106 and 107. Dielectric layers 103, 104, and 105 (and other dielectric layers described herein) may comprise any suitable dielectric material, such as oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride), oxide oxynitrides (e.g., silicon oxynitride), etc. Some dielectric layers described herein may also comprise organic dielectric materials, such as organic deposited films, etc. In embodiments, electrical wiring (e.g., trace 110, via 111, pad 112, etc.) may be embedded in the BEOL layer and / or encapsulation layer.

[0020] In one embodiment, pad 120 may be disposed on one of traces 110. Figure 1AIn the illustrated embodiment, pad 120 can be directly disposed above trace 110 without intermediate vias. Pad 120 can be separated from trace 110 by a substrate 121. Substrate 121 may include one or more of titanium, nitrogen, tantalum, etc. In embodiments, pad 120 may include aluminum. In some cases, pad 120 may consist substantially of aluminum. For example, pad 120 may include 75% or more, 90% or more, or 99% or more aluminum by weight. In some cases, pad 120 may be approximately 100% aluminum by weight (which may include trace amounts of other elements).

[0021] Because aluminum oxidizes rapidly in the atmosphere, a passivation layer 125 can be formed on the surface of the pad 120. The passivation layer 125 may comprise silicon and nitrogen (e.g., SiN). Due to the passivation layer 125, an etching process is used to subsequently expose the pad 120 for bonding. Specifically, a dry etching process is typically used to remove the passivation layer 125. However, because the etching process exposes the aluminum beneath the pad 120, dry etching cannot be performed in the same processing line used to process the layer that will expose copper. Otherwise, the etching chamber would be contaminated with aluminum, which would significantly hinder the progress of the process.

[0022] Now for reference Figure 1B The diagram shows a cross-sectional view of another die 100 according to an additional embodiment. Figure 1B The die 100 in the middle is similar to Figure 1A The die 100 in the embodiment includes a via 123 added between the pad 120 and the trace 110. For example, an additional dielectric layer 109 may be provided above the etch stop layer 108. The via 123, from the pad 120 to the trace 110, extends through the thickness of the dielectric layer 109. In embodiments, the via 123 may also comprise aluminum. For example, the amount of aluminum in the via 123 may be substantially similar to the amount of aluminum in the pad 120. In some embodiments, the via 123 may comprise substantially 100% aluminum (with only trace amounts of other elements). In embodiments, the via 123 may be separated from the dielectric layer 109 and the trace 110 by a liner 121. The liner 121 may comprise one or more of titanium, nitrogen, tantalum, etc.

[0023] To make die 100 more compatible with existing process flows, the embodiments disclosed herein may include forming an additional copper layer on aluminum pad 120. The additional copper layer may include caps, vias, and pads. After the aluminum pads are recessed, caps can be formed directly on the aluminum pads 120. Vias and pads can then be formed using conventional patterning and plating processes. Figure 2A-2C Different examples of the resulting structures are provided.

[0024] Now for reference Figure 2AThe diagram illustrates a cross-sectional view of a die 200 according to an embodiment. In this embodiment, the die 200 may include a substrate 201. The substrate 201 may be a semiconductor substrate, such as a silicon substrate. During some or all of the manufacturing processes described herein, the die 200 may be part of a complete wafer. That is, during some or all of the manufacturing processes described herein, the substrate 201 may not be singled out as a separate die 200. In this embodiment, a FEOL layer 202 may be disposed on the substrate 201. The FEOL layer 202 may include transistor devices, etc. (not shown separately). In this embodiment, one or more BEOL layers and / or encapsulation layers may be disposed above the FEOL layer 202. For example, the BEOL layers and / or encapsulation layers may include dielectric layers 203, 204, and 205 that may be spaced apart from each other using etch stop layers 206, 207, and 208. In this embodiment, electrical wiring (e.g., traces 210, vias 211, pads 212, etc.) may be embedded in the BEOL layers and / or encapsulation layers.

[0025] In an embodiment, pad 220 may be disposed above one of traces 210. Pad 220 may be electrically coupled to trace 210 via one or more vias 223 through dielectric layer 209. Although not shown, a liner (similar to liner 121) may be formed along the surface of via 223. Such a liner may include one or more of titanium, nitrogen, tantalum, etc. In an embodiment, pad 220 and via 223 may include aluminum. In some cases, pad 220 and via 223 may substantially comprise aluminum. For example, pad 220 and via 223 may comprise 75% or more, 90% or more, or 99% or more aluminum by weight. In some cases, pad 220 and via 223 may be approximately 100% aluminum by weight (which may include trace amounts of other elements). Although an example with via 223 is shown, it should be understood that die 200 may also include pads 220 electrically coupled to trace 210 without any intermediate vias 223 (e.g., similar to...). Figure 1A (The structure shown). In another embodiment, via 223 may include one or more of aluminum, copper, cobalt, or tungsten.

[0026] Because aluminum oxidizes rapidly in the atmosphere, a passivation layer 225 can be formed on some surfaces of the pad 220. The passivation layer 225 may include silicon and nitrogen (e.g., SiN). As shown, the passivation layer 225 has been removed from the top surface of the pad 220 to allow contact with the cap 230 above it. The cap 230 may include copper. For example, the cap 230 may include 75% or more, 90% or more, or 99% or more copper by weight. In some cases, the cap 230 may be approximately 100% copper by weight (which may include trace amounts of other elements). In some embodiments, the cap 230 may also include a seed layer and / or a barrier layer 231. The seed layer and / or barrier layer 231 may include one or more of tantalum, nitrogen, copper, etc. As shown, the top surface of the pad 220 may be recessed below the top surface of the passivation layer 225. Therefore, at least a portion of the cap 230 may also be covered by the passivation layer 225.

[0027] In an embodiment, an etch stop layer 214 may be disposed above a dielectric layer 213 surrounding at least some portions of the pads 220 and the cap 230. A via 235 may pass through the etch stop layer 214 and the dielectric layer 215 situated above the etch stop layer 214. The via 235 may also comprise copper. For example, the percentage of copper in the via 235 may be similar to the percentage of copper in the cap 230. The via 235 may also include a seed layer and / or a barrier layer 236 having a composition similar to that of the seed layer and / or barrier layer 231. In an embodiment, a pad 238 may be disposed above the via 235. The pad 238 may also comprise a high percentage of copper or substantially all copper.

[0028] Now for reference Figure 2B An enlarged view of the interconnects within the die 200 according to an embodiment is shown. As shown, the pad 220 may have a first width W1. The sidewall 224 of the pad 220 may contact the passivation layer 225. The cap 230 covering the pad 220 may have a non-uniform width extending through the thickness of the cap 230. For example, the cap 230 may have a second width W2 at the interface 239 between the cap 230 and the pad 220. In an embodiment, the second width W2 may be substantially equal to the first width W1. Furthermore, the cap 230 may have a third width W3 near the top of the cap 230. The third width W3 may be greater than the second width W2. In an embodiment, a portion of the cap 230 having the second width W2 may be backed by the passivation layer 225. In an embodiment, the interface 239 may be substantially flat.

[0029] In an embodiment, the cap 230 may have sidewalls 233 that do not extend perpendicularly through the entire thickness of the cap 230. For example, a first portion of the sidewall 233 may be substantially orthogonal to the interface 239, and a second portion of the sidewall 233 may be sloped. The slope of the sidewall 233 may be a result of an etching process used to recess the top surface of the pad 220, as will be described in more detail below. In an embodiment, the top surface of the passivation layer 225 may also be sloped at the same angle as the second portion of the sidewall 233 due to the etching process used to recess the top surface of the pad 220.

[0030] Now for reference Figure 2C An enlarged cross-sectional view of the interconnects of the die 200 according to an additional embodiment is shown. In the embodiment, Figure 2C The 200 core in the middle is similar to Figure 2B In the die 200, except for interface 239, interface 239 is non-planar instead of being flat. The non-planar interface 239 can be the result of an etching process used to recess the top surface of the pad 220. Figure 2C In the example shown, interface 239 has a wavy pattern. However, other non-flat interfaces 239 may also exist, such as a sawtooth interface 239, an interface 239 with high surface roughness, or any other interface 239 with regular or irregular patterns. Using such a non-flat interface 239 can provide enhanced reliability because the adhesion strength between the cap 230 and the pad 220 will be increased due to the larger surface area of ​​the interface 239.

[0031] Now for reference Figure 3A-3I The image shows a series of cross-sectional views depicting a process for forming a die 300 with interconnects according to an embodiment, the interconnects comprising aluminum pads with copper caps above the aluminum pads. Figure 3A-3I In the illustrated embodiment, the aluminum pad 320 is coupled to the underlying trace 310 via a via 323. However, in other embodiments, the aluminum pad 320 may be directly on top of the underlying trace 310, similar to... Figure 1A The example shown.

[0032] Now for reference Figure 3A The diagram shows a cross-sectional view of a portion of a die 300 according to an embodiment. The shown portion of die 300 includes an upper dielectric layer (e.g., dielectric layers 305, 309, and 313) and an etch stop layer 308. However, it should be understood that the lower layer may include other BEOL layers, FEOL layers, semiconductor substrates, etc. For example, the lower layer structure of die 300 may be similar to any of the dies described in more detail herein. In embodiments, conductive features such as traces 310, vias, pads, etc., may be embedded and / or disposed on any layer of die 300.

[0033] In an embodiment, pad 320 may be disposed within dielectric layer 313. Pad 320 may comprise aluminum. Pad 320 may comprise 75% or more, 90% or more, or 99% or more aluminum by weight. In some cases, pad 320 may be approximately 100% aluminum by weight (which may include trace amounts of other elements). If exposed, the aluminum within pad 320 may oxidize rapidly. Therefore, a passivation layer 325 may be disposed above the surface of pad 320. Passivation layer 325 may comprise silicon and nitrogen (e.g., SiN), etc. In an embodiment, passivation layer 325 is deposited using a blanket deposition process. Therefore, passivation layer 325 may be disposed above dielectric layer 309, along the sidewalls of pad 320, and above the top surface of pad 320.

[0034] In one embodiment, one or more vias 323 can electrically couple pad 320 to the underlying trace 310. The vias 323 can pass through the dielectric layer 309 and the etch stop layer 308. In another embodiment, the vias 323 may also comprise aluminum. For example, the composition of the vias 323 may be substantially similar to that of the pads 320. In the illustrated embodiment, there is no liner between the vias 323 and the trace 310. However, in other embodiments, a liner (not shown) similar to the liner 121 described in more detail herein may be provided along the sidewalls and bottom surface of the vias 323. In yet another embodiment, the vias 323 may comprise one or more of aluminum, copper, cobalt, or tungsten.

[0035] Now for reference Figure 3B The diagram shows a cross-sectional view of a portion of the die 300 after the passivation layer 325 has been removed from the top surface of the pad 320, according to an embodiment. In this embodiment, the portion with the passivation layer 325 removed exposes the top surface 327 of the pad 320. In this embodiment, the top surface 327 of the pad 320 is substantially coplanar with the top surface of the passivation layer 325 extending upward along the sidewall of the pad 320. In this embodiment, the passivation layer 325 can be removed using any suitable etching process (e.g., dry etching). During the etching process, the aluminum of the pad 320 can be exposed. Therefore, the etching process can be performed in an etching chamber outside of a conventional copper-compatible etching process flow.

[0036] Now for reference Figure 3CThe diagram shows a cross-sectional view of a portion of the die 300 after the pad 320 is recessed, according to an embodiment. In this embodiment, the recessed surface 339 of the pad 320 may lie below the top surface of the passivation layer 325 along the sidewall of the pad 320. That is, a portion of the passivation layer 325 may extend beyond the recessed surface 339 of the pad 320. In the illustrated embodiment, the recessed surface 339 is substantially flat. However, in other embodiments, the etching process may result in a non-flat recessed surface 339, such as other non-flat surfaces described in more detail herein.

[0037] The etching process used to recess pad 320 can also partially remove portions of dielectric layer 313 and passivation layer 325. For example, passivation layer 325 and dielectric layer 313 may have tapered portions. In embodiments, a dry etching process can be used to etch pad 320. After the dry etching process, wet cleaning can be used to remove polymer residues (e.g., organometallic polymers, etc.) and / or any other residues. The wet cleaning process can be used to improve the cleanliness of the recessed surface 339 of pad 320 to provide improved electrical connection with the subsequently formed cap 330.

[0038] Now for reference Figure 3D The diagram shows a cross-sectional view of a portion of the die 300 after a cap 330 layer is formed over the pad 320 according to an embodiment. In this embodiment, a seed layer and / or barrier layer 331 may be blanket-deposited over the pad 320, passivation layer 325, and dielectric layer 313. The seed layer and / or barrier layer 331 may include one or more of tantalum, nitrogen, copper, etc. The seed layer and / or barrier layer 331 may be deposited using any suitable deposition process (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, etc.).

[0039] After depositing the seed layer and / or barrier layer 331, a cap 330 may be formed. The cap 330 may be formed using any suitable plating process, such as electroplating. The cap 330 may include copper. For example, the cap 330 may include 75% or more, 90% or more, or 99% or more copper by weight. In some cases, the cap 330 may be approximately 100% copper by weight (which may include trace amounts of other elements). The cap 330 may fill openings in the dielectric layer 313 above the pad 320 and cover the top surface of the dielectric layer 313. In embodiments, reference to the cap 330 may also refer to the seed layer and / or barrier layer 331. That is, when the cap 330 is described as directly contacting the pad 320, it should be understood that the cap 330 may include a seed layer and / or barrier layer 331 disposed between the bulk copper of the cap 330 and the aluminum pad 320.

[0040] Now for reference Figure 3E The diagram shows a cross-sectional view of a portion of the die 300 after the cap 330 is recessed and an etch stop layer 314 is deposited over the cap 330 and the dielectric layer 313, according to an embodiment. In the embodiment, the cap 330 (and portions of the seed layer and / or barrier layer 331) may be recessed using a chemical mechanical planarization (CMP) process or the like. Recessing may result in the removal of the cap 330 from the opening in the dielectric layer 313 over the pad 320. As shown, the resulting cap 330 may also be at least partially backed by a passivation layer 325. That is, the passivation layer 325 may extend upward along a portion of the sidewall of the cap 330. The sidewall portion of the cap 330 contacted by the passivation layer 325 may be substantially vertical (i.e., substantially orthogonal to the top surface of the pad 320). In some embodiments, the sidewall portion of the cap 330 above the passivation layer 325 (which contacts the dielectric layer 313) may be tapered. For example, the width of the cap 330 at the bottom of the cap 330 can be smaller than the width of the cap 330 at the top of the cap 330.

[0041] In this embodiment, the etch stop layer 314 may comprise any suitable dielectric material. For example, the etch stop layer 314 may comprise one or more of silicon, carbon, and nitrogen (e.g., SiCN). The etch stop layer 314 may be deposited using any suitable deposition process (e.g., CVD process, etc.).

[0042] Now for reference Figure 3F The diagram shows a cross-sectional view of a portion of the die 300 after an additional dielectric layer 315 has been applied and a via opening 340 has been formed, according to an embodiment. In this embodiment, the dielectric layer 315 can be applied using a CVD process, a PVD process, a lamination process, or the like. The via opening 340 can be positioned to pass through the dielectric layer 315 and the etch stop layer 314. In this case, the etching process will only expose the copper of the cap 330. That is, the aluminum of the pads 320 is protected by the cap 330. Therefore, the dry etching process used to form the via opening 340 can be performed in a processing chamber used for other copper-based processes. In this embodiment, the via opening 340 is positioned to expose a portion of the cap 330.

[0043] Now for reference Figure 3G The diagram shows a cross-sectional view of a portion of the die 300 after the formation of the via 335, according to an embodiment. In this embodiment, a seed layer and / or barrier layer 336 may be blanket-deposited over the cap 330, the sidewalls of the via opening 340, and the dielectric layer 315. The seed layer and / or barrier layer 336 may include one or more of tantalum, nitrogen, copper, etc. The seed layer and / or barrier layer 336 may be deposited using any suitable deposition process (e.g., PVD, CVD, ALD, chemical plating, etc.).

[0044] After depositing the seed layer and / or barrier layer 336, a via 335 can be formed. The via 335 can be formed using any suitable plating process (e.g., electroplating). The via 335 may include copper. For example, the composition of the via 335 may have a similar composition to that of the cap 330. Plating the via 335 can fill the via opening 340 and cover the top surface of the dielectric layer 315. In embodiments, reference to via 335 may also refer to the seed layer and / or barrier layer 336. That is, when the via 335 is described as directly contacting the cap 330, it should be understood that the via 335 may include the seed layer and / or barrier layer 336 disposed between the bulk copper of the cap 330 and the bulk copper of the via 335.

[0045] Now for reference Figure 3H The diagram shows a cross-sectional view of a portion of die 300 after the removal of the capping layer from the copper deposited on the via 335, according to an embodiment. For example, the capping layer can be removed using a CMP process, etc. The CMP process can also remove portions of the seed layer and / or barrier layer 336 above the dielectric layer 315. Thus, portions of the dielectric layer 315 are exposed again.

[0046] Now for reference Figure 3I This illustration shows a cross-sectional view of a portion of a die 300 after a pad 338 has been formed over a via 335, according to an embodiment. In this embodiment, the pad 338 may comprise copper. For example, the composition of the pad 338 may be similar to that of the via 335 and / or the cap 330. The pad 338 may be formed using any suitable plating and / or patterning process. In this embodiment, a dielectric layer 345 may also be disposed over a dielectric layer 315. The dielectric layer 345 may cover the sidewalls of the pad 338. In this embodiment, the dielectric layer 345 may be a dielectric-to-dielectric portion material suitable for a hybrid bonding process, as will be described in more detail herein. For example, the dielectric layer 345 may comprise silicon, carbon, and nitrogen (e.g., SiCN).

[0047] Now for reference Figure 4A and Figure 4BA pair of enlarged cross-sectional views depicting a die 400 hybrid-bonded to a package substrate 450 according to an embodiment are shown. The die 400 may be similar to any of the dies 400 described in more detail herein. For example, the die 400 may include interconnects including a first pad 420, a cap 430, a via 435, and a second pad 438, the first pad 420 comprising aluminum, the cap 430 comprising copper on the first pad 420, the via 435 comprising copper connected to the cap 430, and the second pad 438 comprising copper connected to the via 435. In an embodiment, a passivation layer 425 may be provided along at least a portion of the sidewalls of the pad 420 and the sidewalls of the cap 430. A dielectric layer 445 may be provided adjacent to the second pad 438. In an embodiment, the package substrate 450 may include a dielectric layer 451, such as an organic deposited film, etc. A via 454 may electrically couple the pad 452 to an underlying trace (not shown). In this embodiment, a dielectric layer 453 may be disposed adjacent to the pad 452. As indicated by the arrow, the die 400 and the package substrate 450 may be bonded together.

[0048] like Figure 4B As shown, the second pad 438 is directly bonded to pad 452 to provide copper-to-copper bonding. Additionally, the dielectric layer 445 is directly bonded to the dielectric layer 453 to form dielectric-to-dielectric bonding. Therefore, the die 400 is bonded to the package substrate 450 without solder or other intermediate interconnect structures.

[0049] Now for reference Figure 5 The diagram illustrates a flowchart depicting a process 560 for forming a die with interconnects according to an embodiment, the interconnects including aluminum pads and copper caps. In an embodiment, process 560 may begin with operation 561, which includes removing a passivation layer from the aluminum-containing pads. In some embodiments, the pads may comprise substantially all aluminum. In some embodiments, the passivation layer may comprise silicon and nitrogen (e.g., SiN). The passivation layer may be disposed over the sidewalls and top surface of the pads. Removing the passivation layer may expose the top surface of the pads while the sidewalls of the pads remain covered by the passivation layer.

[0050] In an embodiment, process 560 may be followed by operation 562, which includes recessing the pads using an etching process. In an embodiment, the etching process may be a dry etching process. Wet cleaning may be performed after dry etching to remove any residue from the surface of the pads. The recessing process can result in a substantially flat surface or a non-flat surface. Additionally, the etching process can result in the top surface of the pads being recessed below the top surface of the passivation layer.

[0051] In an embodiment, process 560 may be followed by operation 563, which includes forming a first layer over the pads. In an embodiment, the first layer comprises copper. In some embodiments, the first layer may resemble a structure described herein as a cap. The first layer may include a first width substantially equal to the width of the pads and a second width wider than the width of the pads. In an embodiment, at least a portion of the sidewalls of the first layer is covered by a passivation layer.

[0052] In one embodiment, process 560 may then proceed to operation 564, which includes forming a second layer over the first layer. In another embodiment, the second layer comprises a dielectric material, such as an oxide, nitride, oxynitride, etc. In yet another embodiment, process 560 may then proceed to operation 565, which includes forming a via through the second layer. In this embodiment, the via contacts the first layer. In some embodiments, the via may also comprise copper.

[0053] Now for reference Figure 6 The diagram illustrates a cross-sectional view of an electronic system 690 according to an embodiment. In this embodiment, the electronic system 690 may include a board 691. The board 691 may be a printed circuit board (PCB), a motherboard, etc. In this embodiment, the board 691 is coupled to a package substrate 650 via interconnects 692. Interconnects 692 may include any suitable second-level interconnect (SLI) architecture. For example, interconnects 692 may include solder balls, sockets, pins, etc.

[0054] In an embodiment, the package substrate 650 may include one or more dielectric layers 651 having integrated electrical wiring (e.g., pads 652, traces, vias, etc.). The package substrate 650 may be cored or coreless. In the case of a cored package substrate, the core (not shown) may be an organic core or a glass core.

[0055] In an embodiment, electronic system 690 may also include die 600. Die 600 may be similar to any die described in more detail herein. For example, die 600 may include trace 610 coupled to pad 620 via via 623. In an embodiment, pad 620 and via 623 may include aluminum. More specifically, pad 620 and via 623 may comprise substantially all aluminum. In another embodiment, via 623 may include one or more of aluminum, copper, cobalt, or tungsten. In an embodiment, cap 630 is disposed on pad 620. Cap 630 may include copper. In an embodiment, via 635 may electrically couple cap 630 to a second pad 638.

[0056] In this embodiment, die 600 can be hybrid-bonded to package substrate 650. The hybrid bonding interface can be similar to that described above. Figure 4A and Figure 4BA more detailed description of the hybrid bonding interface is provided. For example, the second pad 638 of the die 600 can be directly bonded to the pad 652 of the package substrate 650. The dielectric layers of the die 600 and the package substrate 650 can also be directly bonded to each other. Therefore, in some embodiments, there may be no solder or other interconnect structures between the pads of the die 600 and the package substrate 650.

[0057] Figure 7 A computing device 700 according to one implementation of the present disclosure is shown. The computing device 700 houses a board 702. The board 702 may include multiple components, including but not limited to a processor 704 and at least one communication chip 706. The processor 704 is physically and electrically coupled to the board 702. In some implementations, at least one communication chip 706 is also physically and electrically coupled to the board 702. In other implementations, the communication chip 706 is part of the processor 704.

[0058] These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touchscreen displays, touchscreen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (e.g., hard disk drives, optical discs (CDs), digital multifunction discs (DVDs), etc.).

[0059] Communication chip 706 implements wireless communication for the transmission of data to and from computing device 700. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data using modulated electromagnetic radiation via a non-solid-state medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain any wires. Communication chip 706 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, and derivatives thereof, as well as any other wireless protocols designated as 3G, 4G, 5G, and above. Computing device 700 may include multiple communication chips 706. For example, the first communication chip 706 can be dedicated to short-range wireless communication, such as Wi-Fi and Bluetooth, and the second communication chip 706 can be dedicated to long-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0060] The processor 704 of the computing device 700 includes an integrated circuit die packaged within the processor 704. In some embodiments of this disclosure, according to the embodiments described herein, the integrated circuit die of the processor may be part of an electronic package including dies with interconnects, said interconnects including aluminum pads with copper caps. The term "processor" may refer to any device or part of a device that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory.

[0061] The communication chip 706 also includes an integrated circuit die packaged within the communication chip 706. According to another embodiment of this disclosure, and according to the embodiments described herein, the integrated circuit die of the communication chip may be part of an electronic package including dies with interconnects, said interconnects including aluminum pads with copper caps.

[0062] In this embodiment, computing device 700 can be part of any device. For example, computing device can be part of a personal computer, server, mobile device, tablet computer, automobile, etc. That is, computing device 700 is not limited to use in any particular type of system, and computing device 700 can be included in any device that can benefit from computing functionality.

[0063] The foregoing description of the implementations shown in this disclosure includes the content described in the abstract and is not intended to be exhaustive or to limit this disclosure to its precise form. While specific implementations and examples of this disclosure have been described herein for illustrative purposes, various equivalent modifications are possible within the scope of this disclosure, as will be recognized by those skilled in the art.

[0064] Based on the above detailed description, these modifications can be made to this disclosure. The terminology used in the appended claims should not be construed as limiting this disclosure to the specific implementations disclosed in the specification and claims. Rather, the scope of this disclosure will be determined entirely by the appended claims, which will be interpreted in accordance with the established principles of claim interpretation.

[0065] Example 1: An apparatus comprising: a pad comprising aluminum; a liner on a sidewall of the pad extending beyond the surface of the pad; a first layer above the pad comprising copper; a second layer above the first layer, wherein the second layer is a dielectric material; and a via through the second layer and in contact with the first layer.

[0066] Example 2: The apparatus according to Example 1, wherein the surface of the first layer is in contact with the liner.

[0067] Example 3: The apparatus according to Example 1 or Example 2, wherein the first layer has a first width at a first surface and a second width at a second surface opposite to the first surface, wherein the first width is greater than the second width.

[0068] Example 4: The apparatus according to Examples 1-3, wherein the liner comprises silicon and nitrogen.

[0069] Example 5: The apparatus according to Examples 1-4, wherein the second layer comprises silicon, carbon, and nitrogen.

[0070] Example 6: The apparatus according to Examples 1-5, wherein the interface between the first layer and the pads is substantially flat.

[0071] Example 7: The apparatus according to Examples 1-5, wherein the interface between the first layer and the pads is non-flat.

[0072] Example 8: The apparatus according to Examples 1-7 further includes: a second via that contacts the pad, wherein the second via comprises one or more of aluminum, copper, cobalt, or tungsten.

[0073] Example 9: The apparatus according to Examples 1-8, wherein the first layer comprises a barrier layer and a bulk layer, wherein the barrier layer comprises one or more of tantalum, nitrogen, or a refractory metal.

[0074] Example 10: The apparatus according to Examples 1-9, wherein the pads are on a semiconductor substrate.

[0075] Example 11: An apparatus comprising: a package substrate having a first pad; and a die having an interconnect, wherein the interconnect directly contacts the first pad, and wherein the interconnect includes: a second pad comprising aluminum; a cap on the second pad comprising copper; a via on the cap; and a third pad on the via, wherein the third pad contacts the first pad.

[0076] Example 12: The apparatus according to Example 11 further includes: a liner along the sidewall of the second pad and the cap.

[0077] Example 13: The apparatus according to Example 11 or Example 12, wherein the cap includes a first width at the interface with the second pad and a second width at the surface in contact with the via, wherein the second width is greater than the first width.

[0078] Example 14: The apparatus according to Example 13, wherein the second pad includes a third width, and wherein the first width is substantially equal to the third width.

[0079] Example 15: The apparatus according to Examples 11-14 further includes: a layer on top of the cap, wherein the layer comprises silicon, carbon, and nitrogen.

[0080] Example 16: The apparatus according to Examples 11-15, wherein the die is mixed-bonded to the packaging substrate.

[0081] Example 17: The apparatus according to Examples 11-16 further includes: a plate coupled to a packaging substrate.

[0082] Example 18: An apparatus comprising: a first layer, wherein the first layer includes a first dielectric material; pads in the first layer, wherein the pads include aluminum; a cap above the pads and within the first layer, wherein the cap includes copper; a second layer above the first layer, wherein the second layer includes a second dielectric material different from the first dielectric material; a third layer above the second layer, wherein the third layer includes the first dielectric material; and a via through the third layer and the second layer, wherein the via contacts the cap.

[0083] Example 19: The apparatus according to Example 18, wherein the pads have a first width and the caps have a second width, and wherein the second width is greater than the first width.

[0084] Example 20: The apparatus according to Example 18 or Example 19 further includes: a liner along at least a portion of the sidewall of the pad and the sidewall of the cap.

Claims

1. An apparatus comprising: a pad, wherein the pad comprises aluminum; a liner on a sidewall of the pad, wherein the liner extends beyond a surface of the pad; a first layer over the pad, wherein the first layer comprises copper; a second layer over the first layer, wherein the second layer is a dielectric material; and a via through the second layer and contacting the first layer.

2. The apparatus of claim 1, wherein, a surface of the first layer contacts the liner.

3. The apparatus of claim 1 or 2, wherein, the first layer has a first width at a first surface and a second width at a second surface opposite the first surface, wherein the first width is greater than the second width.

4. The apparatus of claim 1 or 2, wherein, the liner comprises silicon and nitrogen.

5. The apparatus of claim 1 or 2, wherein, the second layer comprises silicon, carbon, and nitrogen.

6. The apparatus of claim 1 or 2, wherein, an interface between the first layer and the pad is substantially planar.

7. The apparatus of claim 1 or 2, wherein, an interface between the first layer and the pad is non-planar.

8. The apparatus of claim 1 or 2, further comprising: a second via contacting the pad, wherein the second via comprises one or more of aluminum, copper, cobalt, or tungsten.

9. The apparatus of claim 1 or 2, wherein, the first layer comprises a barrier layer and a bulk layer, wherein the barrier layer comprises one or more of tantalum, nitrogen, or refractory metal.

10. The apparatus of claim 1 or 2, wherein, the pad is on a semiconductor substrate.

11. An apparatus comprising: a package substrate having a first pad; and a die having an interconnect, wherein the interconnect directly contacts the first pad, and wherein the interconnect comprises: a second pad, wherein the second pad comprises aluminum; a cap over the second pad, wherein the cap comprises copper; a via on the cap; and a third pad on the via, wherein the third pad contacts the first pad.

12. The apparatus of claim 11, further comprising: a liner along a sidewall of the second pad and the cap.

13. The apparatus of claim 11 or 12, wherein, the cap comprises a first width at an interface with the second pad and a second width at a surface contacted by the via, wherein the second width is greater than the first width.

14. The apparatus of claim 13, wherein, the second pad comprises a third width, and wherein the first width is substantially equal to the third width.

15. The apparatus of claim 11 or 12, further comprising: a layer over the cap, wherein the layer comprises silicon, carbon, and nitrogen.

16. The apparatus of claim 11 or 12, wherein, the die is hybrid bonded to the package substrate.

17. The apparatus of claim 11 or 12, further comprising: a board coupled to the package substrate.

18. An apparatus comprising: a first layer, wherein the first layer comprises a first dielectric material; a pad in the first layer, wherein the pad comprises aluminum; a cap over the pad and within the first layer, wherein the cap comprises copper; a second layer over the first layer, wherein the second layer comprises a second dielectric material different from the first dielectric material; a third layer over the second layer, wherein the third layer comprises the first dielectric material; and a via through the third layer and contacting the pad. a via through the third layer and the second layer, wherein the via contacts the cap.

19. The apparatus of claim 18, wherein, the pad has a first width and the cap has a second width, and wherein the second width is greater than the first width.

20. The apparatus of claim 18 or 19, further comprising: a liner along at least a portion of a sidewall of the pad and a sidewall of the cap.

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