Packaging structure and method of power device and electronic equipment

Abstract

The invention relates to the technical field of power devices, and discloses a packaging structure and method of a power device and electronic equipment, and the packaging structure of the power device comprises a lead frame and a semiconductor chip; the semiconductor chip comprises a first surface and a second surface which are oppositely arranged; the first surface of the semiconductor chip is provided with a rewiring layer, the rewiring layer comprises a first bonding pad and a second bonding pad which are correspondingly and electrically connected with a first pin and a second pin of the semiconductor chip respectively, and the second surface of the semiconductor chip is provided with a third pin; the lead frame comprises a base island area and a pin area, the pin area is provided with at least one pin bonding pad, and a third pin of the semiconductor chip is connected with the base island area through a bonding layer. The rewiring layer is arranged on the first surface of the semiconductor chip to realize flexible electric connection of the front pins, so that the stray inductance influence caused by bonding wires is reduced, and the switching speed is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power devices, in particular to a packaging structure and method of a power device and an electronic device. BACKGROUND

[0002] With the rapid development of power electronics technology, power devices are increasingly widely used in new energy power generation, electric vehicles, industrial control and other fields. In the prior art, a common packaging structure of a power device usually realizes electrical connection between a chip and external pins in a wire bonding manner, which needs to reserve sufficient bonding space, resulting in a large packaging volume. Meanwhile, the bonding wire itself introduces additional parasitic inductance and resistance, affecting the high-frequency characteristics of the device. SUMMARY

[0003] Therefore, the packaging structure and method of a power device and the electronic device provided in the embodiments of the present application can effectively solve the problems of a large packaging volume of a power device in the prior art and the influence of a bonding wire on the characteristics of the device.

[0004] In a first aspect, the embodiments of the present application provide a packaging structure of a power device, comprising: a lead frame and a semiconductor chip; the semiconductor chip comprises a first surface and a second surface arranged oppositely; The first surface of the semiconductor chip is provided with a redistribution layer, the redistribution layer comprises a first pad and a second pad electrically connected with a first pin and a second pin of the semiconductor chip respectively, and the second surface of the semiconductor chip is provided with a third pin; The lead frame comprises a base island region and a pin region, the pin region is provided with at least one pin pad, and the third pin of the semiconductor chip is connected to the base island region through a bonding layer.

[0005] In some embodiments, the pin pad and the semiconductor chip are arranged on the same surface of the lead frame, and the pin pad and the first pad and the second pad of the semiconductor chip are respectively located on opposite sides of the lead frame.

[0006] In some embodiments, an edge region of the base island region is provided with a first groove.

[0007] In some embodiments, the first surface of the semiconductor chip is provided with a second groove, and the second groove is arranged close to the first pad and the second pad.

[0008] In a second aspect, the embodiments of the present application provide a packaging method of a power device, comprising: A wafer including a plurality of dies is provided, the wafer including a first surface and a second surface arranged oppositely, the first surface of the wafer being provided with a first pin and a second pin of each of the dies, and the second surface of the wafer being provided with a third pin of each of the dies; A first pad and a second pad are prepared on the first surface of the wafer by using a redistribution manner, the first pad and the second pad being electrically connected to the first pin and the second pin of each of the dies respectively, to obtain a wafer with a prepared redistribution layer; The wafer with the prepared redistribution layer is cut to obtain a semiconductor chip; A lead frame is provided, the lead frame including a base island region and a pin region, and the pin region being provided with at least one pin pad; The second surface of the semiconductor chip is attached to the base island region by using a bonding layer, so that the third pin of the semiconductor chip is electrically connected to the pin pad, to obtain the power device.

[0009] In some embodiments, the packaging method further includes, before the cutting of the wafer with the prepared redistribution layer, performing a thinning process on the second surface of the wafer with the prepared redistribution layer.

[0010] In some embodiments, the packaging method further includes, after the thinning process on the second surface of the wafer with the prepared redistribution layer and before the cutting of the wafer with the prepared redistribution layer, preparing a metallization layer on the second surface of the wafer after the thinning process.

[0011] In some embodiments, the preparation of the metallization layer on the second surface of the wafer after the thinning process includes: A titanium layer, a nickel layer and a silver layer are sequentially prepared on the second surface of the wafer after the thinning process to form the metallization layer.

[0012] In some embodiments, after the attachment of the semiconductor chip to the base island region by using the bonding layer and the electrical connection of the third pin of the semiconductor chip to the pin pad, the packaging method further includes: A protective layer is prepared on the surface of the lead frame and each of the pads.

[0013] In a third aspect, an electronic device is provided, the electronic device including the packaging structure of at least one power device according to the first aspect.

[0014] The embodiments of the present application have the following beneficial effects: The power device packaging structure of this application includes a lead frame and a semiconductor chip. The semiconductor chip includes a first side and a second side disposed opposite to each other. A redistribution layer is disposed on the first side of the semiconductor chip, and the redistribution layer includes a first pad and a second pad electrically connected to the first pin and the second pin of the semiconductor chip, respectively. A third pin is disposed on the second side of the semiconductor chip. The lead frame includes a base island region and a pin region. The pin region is provided with at least one pin pad. The third pin of the semiconductor chip is connected to the base island region through a bonding layer. By disposing of a redistribution layer on the first side of the semiconductor chip, this application allows the first pin and the second pin to be electrically connected through the first pad and the second pad in the redistribution layer. This enables flexible reconfiguration of the pin layout on the front side of the chip, improves the freedom of electrical connection and integration density, reduces the stray inductance caused by bonding wires, and improves switching speed. At the same time, the third pin is connected to the base island region of the lead frame through the bonding layer, making the third pin of the semiconductor chip electrically connected to the pin pad. Heat dissipation is achieved using the lead frame. The overall packaging structure not only enhances the electrical performance and thermal management capabilities of the device, but also supports a more compact package size, improving the reliability, power density, and manufacturing yield of the power device. Attached Figure Description

[0015] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A first structural schematic diagram of the packaging structure of the power device according to an embodiment of this application is shown; Figure 2 A schematic diagram of the lead frame structure according to an embodiment of this application is shown; Figure 3 A second structural schematic diagram of the packaging structure of the power device according to an embodiment of this application is shown; Figure 4 A schematic flowchart of the packaging method for power devices according to an embodiment of this application is shown; Figure 5 A schematic diagram of the structure of a wafer according to an embodiment of this application is shown.

[0017] Explanation of key component symbols: 10: Lead frame; 11: Pin pad; 12: First groove; 20: Semiconductor chip; 21: First pad; 22: Second pad; 23: Second groove; 30: Wafer; 31: Die; 311: First pin; 312: Second pin. Detailed Implementation

[0018] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0019] The components of the embodiments of this application described and illustrated in the accompanying drawings can be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of this application provided in the drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0020] In the following text, the terms "comprising," "having," and their cognates, which may be used in various embodiments of this application, are intended only to indicate a particular feature, number, step, operation, element, component, or combination thereof, and should not be construed as primarily excluding the presence of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, or adding the possibility of one or more combinations thereof. Furthermore, the terms "first," "second," "third," etc., are used only for distinguishing descriptions and should not be construed as indicating or implying relative importance.

[0021] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which the various embodiments of this application pertain. Terms (such as those defined in commonly used dictionaries) shall be interpreted as having the same meaning as in their contextual meaning in the relevant technical field and shall not be construed as having an idealized or overly formal meaning, unless clearly defined in the various embodiments of this application.

[0022] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0023] Power devices are widely used in power electronic systems. In recent years, leadless packages have become one of the mainstream packaging forms for power devices due to their miniaturization, high integration, and excellent electrical performance. However, such packages typically mount the leads side-down on the printed circuit board, and the upper surface opposite the leads is completely covered by resin materials such as epoxy molding compound with low thermal conductivity, resulting in a limited heat dissipation path. Most of the heat generated during operation is conducted downwards to the printed circuit board through the metal leads and the bottom. The heat dissipation channel is singular and has a large thermal resistance, resulting in low overall heat dissipation efficiency, which is difficult to meet the heat dissipation requirements under high power density or high heat generation conditions.

[0024] Furthermore, in terms of electrical interconnection, traditional leadless packages rely on bonding wires such as aluminum ribbon, gold wire, or copper wire to connect the chip to external pins. This process not only increases the complexity of the manufacturing process but also requires compatibility with various bonding materials and equipment, increasing production costs and package size. More importantly, bonding wires introduce non-negligible parasitic parameters, such as parasitic resistance and stray inductance. This not only limits the switching speed of the device but also increases energy loss during switching, affecting the overall system efficiency and reliability.

[0025] The power device of this application adopts a leadframe base island structure with the back facing upwards when mounted onto a circuit board, so that the heat transfer direction is opposite to the circuit board, effectively overcoming the limitation of low thermal conductivity of the circuit board material and improving heat dissipation efficiency; at the same time, it eliminates the bonding wire soldering process, simplifying the packaging process. By setting a redistribution layer on the first surface of the semiconductor chip and using the first and second pads on it to achieve electrical connection between the first and second pins, the pin layout can be flexibly reconfigured on the front side of the chip, significantly reducing parasitic inductance and improving switching speed and integration density; the third pin is connected to the leadframe base island area through a bonding layer to achieve electrical conduction and efficient heat dissipation with the help of the leadframe. The overall packaging structure improves electrical performance, thermal management capabilities and reliability, while supporting a more compact size design, improving power density and manufacturing yield.

[0026] The packaging structure of this power device will be described below with reference to some specific embodiments.

[0027] Figure 1 A schematic diagram of a power device package structure according to an embodiment of this application is shown. Exemplarily, the package structure includes a lead frame 10 and a semiconductor chip 20. The semiconductor chip 20 includes a first surface and a second surface disposed opposite to each other. A redistribution layer is provided on the first surface of the semiconductor chip 20. The redistribution layer includes a first pad 21 and a second pad 22 electrically connected to the first pin and the second pin of the semiconductor chip 20, respectively. Specifically, a redistribution layer is provided on the first surface of the semiconductor chip 20 using a redistribution method, electrically connecting the first pin of the semiconductor chip 20 to the first pad 21 and the second pin of the semiconductor chip 20 to the second pad 22.

[0028] The second side of the semiconductor chip 20 has a third pin. Exemplarily, the semiconductor chip 20 is a MOS chip, with the first pin being the gate pin, the second pin being the source pin, and the third pin being the drain pin.

[0029] The lead frame 10 includes a base island region and a pin region. The base island region is used to connect the semiconductor chip 20, and the pin region is used to set the pads for power devices. Understandably, the pin pads 11 and the semiconductor chip 20 are located on the same side of the lead frame 10, so that the source pads, gate pads, and drain pads required for external device connections are coplanarly distributed, thereby achieving a planar layout of all electrodes of the power device on the bottom of the package, compatible with standard mounting processes. The lead frame 10 can be configured according to the actual application; exemplaryly, the lead frame 10 is a copper structure.

[0030] The third pin of semiconductor chip 20 is connected to the base island region via a bonding layer, electrically connecting the third pin of semiconductor chip 20 to the lead pad 11. Exemplarily, the bonding layer is solder paste, which is used to mount semiconductor chip 20 onto the base island region. By directly mounting the drain pin of semiconductor chip 20 to the base island region of lead frame 10 via the solder paste bonding layer, low-resistance, high-reliability electrical connection and efficient heat conduction of the high-current electrode on the back side are achieved, significantly reducing contact resistance and thermal resistance, and improving device power density and heat dissipation performance.

[0031] Furthermore, Figure 2 A schematic diagram of the lead frame 10 according to an embodiment of this application is shown, in which a first groove 12 is provided at the edge of the base island region. The first groove 12 can be provided by etching or stamping processes depending on the actual application. It is understood that the depth of the groove should be less than the thickness of the base island region. For example, considering the heat dissipation performance and cost of the power device, the thickness of the base island region is 0.25 mm, and the depth of the groove is 0.05 mm. By providing the first groove 12 at the edge of the base island region, the lateral overflow of solder paste during chip mounting can be effectively limited, preventing it from flowing to the pin area and causing short circuits or contamination, significantly improving packaging yield and electrical reliability, while maintaining the mechanical stability and thermal conductivity efficiency of the base island structure. Furthermore, the 0.05 mm depth provides effective barrier without excessively weakening the overall thickness of the base island, ensuring thermal resistance performance.

[0032] The lead frame 10 has at least one pin pad 11 in its pin area, corresponding to the pins of the semiconductor chip 20. The first pad 21 of the power device is the gate pad, the second pad 22 is the source pad, and the pin pad 11 is the drain pad. The number and position of the first pad 21, the second pad 22, and the pin pad 11 can be set according to the actual application. For example, as shown... Figure 1 As shown, a gate pad and three source pads are set on the semiconductor chip 20 by rewiring. Multiple source pads can disperse the current path, reduce parasitic inductance and resistance, improve the current carrying capacity and switching performance of the device, and at the same time improve heat distribution, enhance the reliability and power density of the power device.

[0033] Furthermore, a second groove 23 is provided on the first surface of the semiconductor chip 20, and the second groove 23 is located close to the first pad 21 and the second pad 22. Depending on the actual application, when fabricating the first pad 21 and the second pad 22 using a redistribution method, the second groove 23 can be provided on the encapsulation material near the first pad 21 and the second pad 22. For example, a groove structure can be formed on the surface of the encapsulation body corresponding to the pad area by using a mold with a raised structure during molding. By providing the second groove 23, the surface creepage distance between pads and between pads and external conductors can be significantly increased, effectively suppressing the risk of failure such as leakage current and arc discharge along the surface of the package under high voltage transients or humid environments, and improving the electrical insulation performance and long-term operational reliability of the device. At the same time, this groove structure can achieve higher withstand voltage without increasing the package size. Using molding compound with CTI>600V, the creepage distance is 1.16mm, meeting the safe operation requirements of the device at a 220V operating voltage.

[0034] The lead pads 11 in the lead area are composed of metal pillars. It is understood that the height of the metal pillars should be equal to or greater than the thickness of the semiconductor chip 20; exemplary, the height of the metal pillars is 0.3 mm. In this embodiment, four metal pillars are equidistantly arranged on one side of the lead frame 10 as drain pads. Correspondingly, one gate pad and three source pads are equidistantly distributed on the other side of the power device. Thus, the lead pads 11 and the gate and source pads of the semiconductor chip 20 are located on opposite sides of the lead frame 10, forming a symmetrical double-sided electrode lead structure. All external electrical connections are located in different areas of the bottom of the package, achieving bond-free, low parasitic parameters, and high current dispersion planar interconnection, significantly improving power density, electrical performance, and thermal management efficiency.

[0035] It is understood that the embodiments of this application are illustrated using a dual in-line flat no-lead package (DLP) structure as an example. The proposed package structure and pin layout are pin compatible with existing DLP structures, facilitating direct replacement applications. In practical applications, the package structure of the power devices in this application can also be applied to other no-lead or array-mount package forms, such as quad no-lead flat packages, pad grid array packages, etc. The package shape and pad distribution can be adaptively adjusted according to specific requirements and are not limited here.

[0036] Furthermore, the packaging structure proposed in this application embodiment has good size compatibility and can be adapted to semiconductor chips 20 of different areas. For example... Figure 3As shown, when the size of the semiconductor chip 20 is small, the source and gate can still be accurately aligned with the corresponding pin pads 11 by adjusting the layout position of the pads in the redistribution layer and the mounting position of the chip on the lead frame 10. This achieves an external size and pin arrangement that is completely consistent with the corresponding package shape, ensuring that the packaged device meets the pin replacement requirements.

[0037] Figure 4 A schematic flowchart of a power device packaging method according to an embodiment of this application is shown. Exemplarily, the packaging method includes steps S101-S105: S101: Provides a wafer including multiple dies, the wafer including a first side and a second side disposed opposite to each other, the first side of the wafer being provided with a first pin and a second pin of each die, and the second side of the wafer being provided with a third pin of each die.

[0038] Understandably, the die can be a gallium nitride power device die, but it could also be a silicon carbide power device die, etc. The number of dies in the wafer can be set according to the actual application. For example, Figure 5 As shown, wafer 30 includes four identical dies 31, each die 31 including three pins, wherein the first pin 311 is the gate pin, which is disposed on the first side of wafer 30; the second pin 312 is the source pin, which is disposed on the first side of wafer 30; and the third pin is the sink pin, which is disposed on the second side of wafer 30.

[0039] This application does not limit the specific process type of wafer 30, and can be applied to various die structures 31 such as planar, trench, or superjunction types. As long as it has a basic electrode configuration with a source and a gate on the first side and a drain on the second side, it can be included in the application scope of this packaging method. Exemplarily, wafer 30 is planar and has a thickness of 750 μm.

[0040] This structure lays the physical foundation for subsequent redistribution methods. In particular, the drain is a large-area conductor, which helps reduce contact resistance and thermal resistance, improving the overall performance of the device. Furthermore, the 30-wafer structure supports batch processing such as full-wafer redistribution, full-wafer molding, and full-wafer grinding, significantly improving production efficiency and reducing unit costs, which is in line with the trend of advanced power packaging moving towards 30-wafer-level packaging.

[0041] S102: Using a redistribution method, first pads 21 and second pads 22 are prepared on the first side of wafer 30, which are electrically connected to the first pins 311 and second pins 312 of each die 31, respectively, to obtain wafer 30 with a redistribution layer prepared.

[0042] Specifically, an insulating dielectric material is coated across the entire first side of wafer 30 as a support substrate. This insulating material can be polybenzoxazole, benzocyclobutene, etc., which protects the underlying sensitive device structure and provides a smooth surface for subsequent photolithography and metal wiring. New wire patterns are defined through exposure and development, followed by the fabrication of new metal lines using DC or pulse electroplating techniques. Exemplarily, the thickness of the electroplated copper layer is 0.2 mm. The source and gate of each die 31 are led to the peripheral area of ​​the chip, forming a first pad 21 and a second pad 22 for external electrical connection. The gate pin of the semiconductor chip 20 is connected to the first pad 21, and the source pin of the semiconductor chip 20 is connected to the second pad 22. The source and gate of all dies 31 are extended to designated locations via copper wires. The first pad 21 and the second pad 22 are located on the chip periphery or in a package-compatible area.

[0043] The electroplated wafer 30 is encapsulated, and the first side of the encapsulated wafer 30 is ground to expose the first pad 21 and the second pad 22. It is understood that the thickness of the encapsulation layer should be greater than the thickness of the electroplated copper layer to cover it. Furthermore, the encapsulation mold can form a second groove 23 near the first pad 21 and the second pad 22 to increase the creepage distance between the pads.

[0044] Rewiring brings the source and gate to the periphery, breaking through the space limitations of traditional wire bonding and allowing the use of larger chips. For example, a traditional dual in-line flat 5x6 chip... The packaging efficiency of the packaging structure is 0.3~0.4, and the semiconductor area of ​​this application is 4.6 x 5.1 = 23.5. The packaging efficiency reaches 0.8, which is higher than that of traditional dual in-line flat leadless 5x6 packages. The packaging structure is improved by over 100%. The redistribution method can directly provide external connection pads without the need for aluminum strips or gold wires, significantly reducing stray inductance and resistance, improving switching speed, and reducing EMI.

[0045] Furthermore, after obtaining the wafer 30 with the redistribution layer prepared, before cutting the wafer 30, the second side of the wafer 30 with the redistribution layer prepared can be thinned.

[0046] Specifically, wafer 30 is fixed onto a carrier film, and a portion of the silicon material is removed from the back side using mechanical grinding and / or chemical mechanical polishing, demonstratively reducing its thickness from an initial approximately 750 μm to 250 μm. This step not only reduces the chip's thermal resistance and improves heat dissipation performance, but also provides a good foundation for subsequent metallization layer formation on the back side to improve drain contact characteristics, while avoiding stress damage caused by excessive thickness during dicing.

[0047] Furthermore, after thinning the second side of the wafer 30 with the redistribution layer prepared, a metal oxide layer can be prepared on the second side of the thinned wafer 30. Specifically, a titanium layer, a nickel layer, and a silver layer are prepared sequentially on the second side of the thinned wafer 30 to form a metallization layer.

[0048] After thinning the second side of the wafer 30 with the prepared redistribution layer, titanium, nickel, and silver layers can be sequentially formed on its back side using evaporation, sputtering, or physical vapor deposition processes to form a metallization layer. The titanium layer acts as an adhesion layer to enhance the bonding between the metal and the silicon substrate, the nickel layer acts as a diffusion barrier to inhibit the diffusion of silver atoms into the silicon, and the silver layer provides excellent electrical and thermal conductivity. The continuous deposition of each metal layer, supplemented by annealing to optimize interface characteristics, results in a stable and reliable metallization structure on the back side of the thinned wafer 30, meeting the electrical connection and heat dissipation requirements of subsequent packaging.

[0049] S103: The wafer 30 with the prepared redistribution layer is cut to obtain the semiconductor chip 20.

[0050] The wafer 30 is cut using a precision dicing machine or laser cutting equipment, and the wafer 30 is separated into individual semiconductor chips 20 along the preset cutting path.

[0051] S104: A lead frame 10 is provided, the lead frame 10 includes a base island area and a pin area, the pin area being provided with at least one pin pad 11.

[0052] The lead frame 10 can be made by etching or stamping metal materials, and can be precisely shaped by photolithography and wet or dry etching to ensure the positional accuracy and surface flatness of the base island area and the pin pad 11.

[0053] S105: The second side of the semiconductor chip 20 is mounted on the base island area using the bonding layer, so that the third pin of the semiconductor chip 20 is electrically connected to the pin pad 11 to obtain a power device.

[0054] Solder paste is printed in the base island area, with an exemplary thickness of 0.05 mm. A strong bond is achieved through heat curing or reflow soldering. This mounting method achieves good thermal conductivity and mechanical fixation between the chip and the base island. Combined with the electrical connection of the lead pads 11, it improves the heat dissipation performance and structural reliability of the power device, while simplifying the packaging process. Furthermore, product information such as product model and production date can be laser-engraved on the opposite side of the lead frame 10 to the semiconductor chip 20.

[0055] By forming a redistribution layer on the first side of wafer 30, the first pins 311 and second pins 312 of each die 31 are electrically connected to the rearranged first pads 21 and second pads 22, achieving optimized arrangement of input and output ports. After dicing, the second side of the chip is mounted to the base island area of ​​the lead frame 10 through a bonding layer, making the third pin of the chip conductive with the pin pads 11 of the pin area, thus forming a three-dimensional electrically connected power device. Compared to the traditional 5X6X1.1=33 With this packaging structure, the thickness of the power device can be reduced to 0.55 mm, and the package volume can be reduced to 16.5 mm. This reduces weight by 50%, significantly achieving a lighter and smaller design.

[0056] Furthermore, this packaging method significantly improves the versatility of the packaging platform. By flexibly adjusting the pad positions with the help of redistribution technology and combining it with the adjustable offset of the chip mounting position, the lead frame 10 and package shape of the same specification can be adapted to multiple chip versions, such as field-effect transistors with different current capacities or process iterations. There is no need to change the mold or modify the circuit board design, which effectively reduces development costs and cycle time, facilitates the construction of standardized product series, and improves product compatibility, market response speed and customer replacement convenience.

[0057] Furthermore, a protective layer can be prepared on the surface of the lead frame 10 and each pad.

[0058] Specifically, a metal plating layer can be deposited on the copper surface of the lead frame 10 and the chip source and gate through an electroplating process. For example, pure tin that meets the standards is selected as the plating material. DC electroplating or pulse electroplating technology is used to uniformly cover the exposed copper conductor surface under strict control of current density, temperature and electrolyte composition, forming a dense and firmly bonded protective film.

[0059] By performing pure tin plating on the lead frame 10 and the source and gate pads of the chip, not only is the copper conductor effectively isolated from the outside air, preventing the risk of open circuits or poor contact caused by oxidation and corrosion, but the tin layer itself also has good conductivity, which can reduce the interface contact resistance and improve the signal and power transmission efficiency. In addition, the tin plating layer can quickly wet and fuse with the external solder during the surface mount process, promoting the formation of reliable solder joints, significantly reducing welding defects such as cold solder joints and poor solder joints, ensuring the yield of surface mount process and the reliability of devices, and meeting environmental protection requirements while taking into account performance and manufacturing stability.

[0060] It is understood that the options in the above embodiments also apply to this embodiment, so they will not be described again here.

[0061] This application also provides an electronic device, exemplary of which includes the aforementioned power device packaging structure. Specifically, the electronic device can be any type of electronic device, such as a smartphone, wearable device, power adapter, drive power supply, power tool, new energy vehicle electronic control unit, charging pile module, server power system, or industrial control equipment, etc.

[0062] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that, in alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and combinations of blocks in the block diagram and / or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0063] In addition, the functional modules or units in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0064] If the aforementioned functions are implemented as software functional modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a smartphone, personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application.

[0065] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.

Claims

1. A packaging structure of a power device, characterized by comprising: The package structure comprises: a lead frame and a semiconductor chip; the semiconductor chip comprises a first surface and a second surface arranged oppositely; the first surface of the semiconductor chip is provided with a redistribution layer, the redistribution layer comprises a first pad and a second pad electrically connected with a first pin and a second pin of the semiconductor chip respectively, and the second surface of the semiconductor chip is provided with a third pin; the lead frame comprises a base island region and a pin region, the pin region is provided with at least one pin pad, and the third pin of the semiconductor chip is connected with the base island region through a bonding layer.

2. The packaging structure of a power device according to claim 1, wherein The pin pad and the semiconductor chip are arranged on the same surface of the lead frame, and the pin pad and the first pad and the second pad of the semiconductor chip are respectively located on opposite sides of the lead frame.

3. The packaging structure of a power device according to claim 1, wherein An edge region of the base island region is provided with a first groove.

4. The packaging structure of a power device according to claim 1, wherein The first surface of the semiconductor chip is provided with a second groove, and the second groove is arranged close to the first pad and the second pad.

5. A packaging method of a power device, characterized by, The package structure comprises: a wafer comprising a plurality of dies, the wafer comprising a first surface and a second surface arranged oppositely, the first surface of the wafer being provided with a first pin and a second pin of each of the dies, and the second surface of the wafer being provided with a third pin of each of the dies; a redistribution layer is prepared on the first surface of the wafer to form a wafer with a prepared redistribution layer, the redistribution layer comprising a first pad and a second pad electrically connected with the first pin and the second pin of each of the dies respectively; the wafer with the prepared redistribution layer is cut to obtain semiconductor chips; a lead frame is provided, the lead frame comprising a base island region and a pin region, and the pin region being provided with at least one pin pad; a bonding layer is used to mount the second surface of the semiconductor chip on the base island region, so that the third pin of the semiconductor chip is electrically connected with the pin pad, thereby obtaining the power device.

6. The packaging method of a power device according to claim 5, wherein The package method further comprises: before the wafer with the prepared redistribution layer is cut, a thinning process is performed on the second surface of the wafer with the prepared redistribution layer.

7. The packaging method of a power device according to claim 6, wherein The package method further comprises: after the thinning process is performed on the second surface of the wafer with the prepared redistribution layer and before the wafer with the prepared redistribution layer is cut, a metallization layer is prepared on the second surface of the wafer after the thinning process.

8. The packaging method of a power device according to claim 7, wherein The preparation of the metallization layer on the second surface of the wafer after the thinning process comprises: a titanium layer, a nickel layer and a silver layer are sequentially prepared on the second surface of the wafer after the thinning process to form the metallization layer.

9. The packaging method of a power device according to claim 6, wherein After the bonding layer is used to mount the semiconductor chip on the base island region, so that the third pin of the semiconductor chip is electrically connected with the pin pad, the package method further comprises: a protective layer is prepared on the surface of the lead frame and each of the pads.

10. An electronic device, comprising: The electronic device comprises the package structure of the power device according to any one of claims 1-4.

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