Power amplifier and radio frequency chip

Abstract

The application relates to the field of wireless communication technology and provides a power amplifier and a radio frequency chip, which comprise input matching circuit, power amplifier tube, output matching circuit, sampling amplifier tube, first mirror circuit, second mirror circuit, first resistor, first current source and second current source which are electrically connected in sequence; the first current source is used for generating bias current, and the second current source is used for generating reference current; the input end of the sampling amplifier tube is connected with the input end of the power amplifier tube and is used for sampling the current of the power amplifier tube; if it is detected that the current outputted from the output end of the first mirror circuit is greater than the reference current, the bias current of the first current source is reduced; and if it is detected that the current outputted from the output end of the first mirror circuit is less than or equal to the reference current, the bias current of the first current source is outputted to the first end of the first resistor. The application can protect the power amplifier when the power amplifier outputs high power and avoid failure.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and more particularly to a power amplifier and a radio frequency chip. Background Technology

[0002] In wireless communication systems, power amplifiers are key components for realizing the wireless transmission of radio frequency signals. With the continuous development of wireless communication technology, higher demands are placed on the power consumption of communication systems. As a core component in electronic devices that amplifies signal power, power amplifiers... Figure 1 As shown, its architecture typically includes, in sequence, a control circuit, a power amplifier (PA), an output matching network, a directional coupler, back-end components, and an antenna. The control circuit is responsible for regulating the PA's operating state, while the output matching network optimizes impedance matching to improve power transmission efficiency. The directional coupler is a four-port network containing an input port, a through port, a coupling port, and an isolation port. When a signal is input from the input port, most of the signal is output from the through port to the back-end components, and then from the back-end components to the antenna. A small portion of the signal is output from the coupling port, while the isolation port should theoretically have no signal output. VCOUP is the voltage across the coupling port, reflecting the signal strength coupled from the input port to that port; VISO is the voltage across the isolation port, where a certain voltage exists, and the magnitude of VISO reflects the isolation performance of the directional coupler.

[0003] In practical applications, when a power amplifier outputs high power, its internal components often face a harsh working environment and are prone to failure due to problems such as overvoltage, overcurrent, or load mismatch, which seriously affects the reliability and service life of the equipment.

[0004] To address this issue, existing technologies generally employ two approaches: one is to reduce the operating stress on the power amplifier (PA) by limiting the range of input power, operating voltage, and load impedance variations. The other is to add an overvoltage protection circuit to promptly disconnect the circuit when an abnormal voltage is detected.

[0005] However, application limitations will sacrifice the output performance of the power amplifier, and overvoltage protection circuits can only deal with a single type of fault, making it difficult to fully avoid multiple failure risks under high power output, resulting in poor reliability. Summary of the Invention

[0006] In view of the shortcomings of the prior art, the present invention proposes a power amplifier to solve the problem of poor reliability of existing power amplifiers.

[0007] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0008] In a first aspect, the embodiments of the present application provide a power amplifier, comprising an input matching circuit, a power amplifier tube and an output matching circuit connected in sequence; the power amplifier further comprises a sampling amplifier tube, a first mirror circuit, a second mirror circuit, a first resistor, a first current source and a second current source; the first current source is configured to generate a bias current, and the second current source is configured to generate a reference current.

[0009] An input end of the sampling amplifier tube is connected to an input end of the power amplifier tube, and is configured to sample a current of the power amplifier tube.

[0010] An output end of the sampling amplifier tube is connected to a first input end of the first mirror circuit, a second input end of the first mirror circuit is configured to be connected to an external DC power supply, and a ground end of the sampling amplifier tube is grounded.

[0011] An output end of the first mirror circuit is connected to a positive electrode end of the second current source and an input end of the second mirror circuit respectively, a negative electrode end of the second current source is grounded, a positive electrode end of the first current source is configured to be connected to the external DC power supply, and an output end of the second mirror circuit is connected to a negative electrode end of the first current source; the output end of the second mirror circuit is further connected to a first end of the first resistor, and a second end of the first resistor is connected to an input end of the sampling amplifier tube.

[0012] If it is detected that a current output by the output end of the first mirror circuit is greater than the reference current, the bias current of the first current source is reduced.

[0013] If it is detected that the current output by the output end of the first mirror circuit is less than or equal to the reference current, the bias current of the first current source is output to the first end of the first resistor.

[0014] Preferably, the first mirror circuit comprises a first mirror tube and a second mirror tube; a drain electrode of the first mirror tube is connected to a gate electrode of the first mirror tube and serves as a first input end of the first mirror circuit; a source electrode of the first mirror tube is connected to a source electrode of the second mirror tube and serves as a second input end of the first mirror circuit; the gate electrode of the first mirror tube is connected to a gate electrode of the second mirror tube, and a drain electrode of the second mirror tube serves as an output end of the first mirror circuit.

[0015] Preferably, the second mirror circuit comprises a third mirror tube and a fourth mirror tube; a drain electrode of the third mirror tube is connected to a gate electrode of the third mirror tube and serves as an input end of the second mirror circuit; the gate electrode of the third mirror tube is connected to a gate electrode of the fourth mirror tube, and a drain electrode of the fourth mirror tube serves as an output end of the second mirror circuit; a source electrode of the third mirror tube is connected to a source electrode of the fourth mirror tube and is grounded.

[0016] Preferably, the first mirror tube and the second mirror tube are both PMOS tubes; the third mirror tube and the fourth mirror tube are both NMOS tubes.

[0017] Preferably, the bias current of the first current source is defined as Ibias1, the reference current of the second current source is defined as Iref, the current of the drain of the second mirror tube is defined as Ip2, the current of the source of the third mirror tube is defined as In1, the current of the source of the fourth mirror tube is defined as In2, and the current connected to the first end of the first resistor is defined as Ibias2.

[0018] If Ip2>Iref, then In1=Ip2-Iref, In2=k*In1, and Ibias2=Ibias1-In2; wherein k is a proportional coefficient.

[0019] If Ip2≤Iref, then In1=0 and Ibias2=Ibias1.

[0020] Preferably, the power amplifier further comprises a first inductor, a first end of the first inductor is connected to the output end of the power amplifier tube, and a second end of the first inductor is used for connecting a power supply.

[0021] Preferably, the input matching circuit comprises a first capacitor, a first end of the first capacitor is used for connecting a radio frequency signal, and a second end of the first capacitor is connected to the input end of the power amplifier tube.

[0022] Preferably, the power amplifier tube is a first triode, a base of the first triode is used as the input end of the power amplifier tube, a collector of the first triode is used as the output end of the power amplifier tube, and an emitter of the first triode is used as the ground end of the power amplifier tube.

[0023] Preferably, the sampling amplifier tube is a second triode, a base of the second triode is used as the input end of the sampling amplifier tube, a collector of the second triode is used as the output end of the sampling amplifier tube, and an emitter of the second triode is used as the ground end of the sampling amplifier tube.

[0024] In a second aspect, an embodiment of the present application further provides a radio frequency chip comprising the power amplifier as described above.

[0025] Compared with related technologies, in the embodiments of the present invention, the input terminal of the sampling amplifier tube is connected to the input terminal of the power amplifier tube for current sampling of the power amplifier tube; the output terminal of the sampling amplifier tube is connected to the first input terminal of the first mirror circuit, and the second input terminal of the first mirror circuit is used to connect to an external DC power supply; the ground terminal of the sampling amplifier tube is grounded; the output terminal of the first mirror circuit is connected to the positive terminal of the second current source and the input terminal of the second mirror circuit, respectively, the negative terminal of the second current source is grounded, the positive terminal of the first current source is used to connect to the external DC power supply, and the output terminal of the second mirror circuit is connected to the negative terminal of the first current source; the output terminal of the second mirror circuit is also connected to the first terminal of the first resistor, and the second terminal of the first resistor is connected to the input terminal of the sampling amplifier tube; if the current output by the first mirror circuit is detected to be greater than the reference current, the bias current of the first current source is reduced; in this way, the current of the power amplifier tube is detected by the sampling amplifier tube, and when the current is greater than the preset reference current, the DC bias of the first current source is reduced, thereby reducing the current of the power amplifier tube, which can protect the power amplifier tube and avoid failure under high power output, resulting in high circuit reliability. Attached Figure Description

[0026] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings:

[0027] Figure 1 A circuit block diagram of a power amplifier provided for the prior art;

[0028] Figure 2 A circuit block diagram of a power amplifier provided in an embodiment of the present invention;

[0029] Figure 3 A comparison graph showing the output power versus input power curves of the power amplifier provided in this embodiment of the invention and those of the prior art.

[0030] Among them, 100 is a power amplifier, 1 is an input matching circuit, 2 is a power amplifier tube, 3 is an output matching circuit, 4 is a sampling amplifier tube, 5 is a first mirror circuit, 6 is a second mirror circuit, 7 is a first current source, and 8 is a second current source. Detailed Implementation

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein in the specification of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings of this application, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings of this application are used to distinguish different objects, not to describe a particular order.

[0032] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0033] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] Example 1

[0035] Please see Figure 2 As shown, this embodiment of the invention provides a power amplifier 100, including an input matching circuit 1, a power amplifier transistor 2, and an output matching circuit 3 connected in sequence. The power amplifier 100 also includes a sampling amplifier transistor 4, a first mirror circuit 5, a second mirror circuit 6, a first resistor R1, a first current source 7, and a second current source 8; the first current source 7 generates a bias current Ibias1, and the second current source 8 generates a reference current Iref. The input matching circuit 1 receives radio frequency (RF) signals, and the power amplifier transistor 2 amplifies the RF signals before impedance matching by the output matching circuit 3 before output.

[0036] The input terminal of the sampling amplifier tube 4 is connected to the input terminal of the power amplifier tube 2, and is used to sample the current of the power amplifier tube 2. The base of the sampling amplifier tube 4 is connected to the base of the power amplifier tube 2, and their base voltages are the same. Therefore, the collector current of the sampling amplifier tube 4 is in a fixed ratio to the collector current of the power amplifier tube 2, which facilitates real-time sampling of the current of the power amplifier tube 2.

[0037] The output terminal of the sampling amplifier tube 4 is connected to the first input terminal of the first mirror circuit 5, and the second input terminal of the first mirror circuit 5 is connected to an external DC power supply VBATT; the ground terminal of the sampling amplifier tube 4 is grounded. The external DC power supply VBATT can be the battery voltage, used to provide the operating voltage for the first mirror circuit 5.

[0038] The output terminal of the first mirror circuit 5 is connected to the positive terminal of the second current source 8 and the input terminal of the second mirror circuit 6, respectively. The negative terminal of the second current source 8 is connected to the ground terminal of the second mirror circuit 6. The positive terminal of the first current source 7 is used to connect to the external DC power supply VBATT, and the output terminal of the second mirror circuit 6 is connected to the negative terminal of the first current source 7. The output terminal of the second mirror circuit 6 is also connected to the first end of the first resistor R1, and the second end of the first resistor R1 is connected to the input terminal of the sampling amplifier tube 4. The sampling amplifier tube 4 collects the current of the power amplifier tube 2 and outputs it to the first mirror circuit 5. The first mirror circuit 5 adjusts the current and outputs it to the second mirror circuit 6 and the second current source 8. By comparing the current output by the first mirror circuit 5 with the reference current Iref of the second current source 8, the bias current Ibias1 of the first current source 7 is controlled according to the comparison result, thereby achieving the protection effect of the power amplifier tube 2. The first resistor R1 can reduce the current in the circuit, limit the current in the bias circuit, avoid damage to the sampling amplifier tube 4 or other components due to sudden large current, and stabilize the base voltage, thereby improving the reliability of the protection circuit. Meanwhile, the loop current is limited by the first resistor R1, and the first mirror circuit 5 and the second mirror circuit 6 ensure the accuracy of current replication, thus ensuring that the protection mechanism is stable and reliable and is not significantly affected by power supply voltage fluctuations or temperature changes.

[0039] The current output from the first mirror circuit 5 can be detected by a current meter to obtain its value. A current comparator can be used to compare the current output from the first mirror circuit 5 with a reference current Iref, and the output of the bias current Ibias1 from the first current source 7 can be controlled based on the comparison result.

[0040] Specifically, if the current output from the first mirror circuit 5 is greater than the reference current Iref, the bias current Ibias1 of the first current source 7 is reduced. If the current output from the first mirror circuit 5 is less than or equal to the reference current Iref, the bias current Ibias1 of the first current source 7 is output to the first terminal of the first resistor R1. In this way, the current of the power amplifier tube 2 is detected by the sampling amplifier tube 4. When the current exceeds the preset reference current Iref, the DC bias of the first current source 7 is reduced, thereby reducing the current of the power amplifier tube 2. The sampling amplifier tube 4 and the mirror circuit monitor the current of the power amplifier tube 2 in real time, protecting the power amplifier tube 2 and preventing failure during high-power output. When the current exceeds the threshold reference current Iref, the bias current Ibias1 is rapidly reduced to prevent damage to the device due to overcurrent, resulting in a fast response speed. Simultaneously, the overcurrent protection threshold can be flexibly set by adjusting the reference current Iref of the second current source 8, adapting to the needs of amplifier tubes with different power levels, demonstrating strong versatility.

[0041] In this embodiment, the first mirror circuit 5 includes a first mirror transistor P1 and a second mirror transistor P2. The drain of the first mirror transistor P1 is connected to its gate and serves as the first input terminal of the first mirror circuit 5. The source of the first mirror transistor P1 is connected to the source of the second mirror transistor P2 and serves as the second input terminal of the first mirror circuit 5. The gate of the first mirror transistor P1 is connected to the gate of the second mirror transistor P2, and the drain of the second mirror transistor P2 serves as the output terminal of the first mirror circuit 5. The output current of the sampling amplifier transistor 4 is input to the first input terminal of the first mirror circuit 5, such as the drain of the first mirror transistor P1. Since the first mirror transistor P1 and the second mirror transistor P2 form a current mirror, the drain of the second mirror transistor P2 will output a mirror current proportional to the sampling current. The current output by the first mirror circuit 5 is divided into two paths: one path flows into the input terminal of the second mirror circuit 6, and the other path is compared with the reference current Iref provided by the second current source 8.

[0042] In this embodiment, the second mirror circuit 6 includes a third mirror transistor N1 and a fourth mirror transistor N2. The drain of the third mirror transistor N1 is connected to its gate and serves as the input terminal of the second mirror circuit 6. The gate of the third mirror transistor N1 is connected to the gate of the fourth mirror transistor N2, and the drain of the fourth mirror transistor N2 serves as the output terminal of the second mirror circuit 6. The source of the third mirror transistor N1 is connected to the source of the fourth mirror transistor N2 and grounded. By mirroring the bias current Ibias1 through the third mirror transistor N1 and the fourth mirror transistor N2, the protection effect of the output current is improved.

[0043] In this embodiment, the first mirror transistor P1 and the second mirror transistor P2 are both PMOS transistors; the third mirror transistor N1 and the fourth mirror transistor N2 are both NMOS transistors.

[0044] In this embodiment, the power amplifier 100 further includes a first inductor L1. The first end of the first inductor L1 is connected to the output terminal of the power amplifier transistor 2, and the second end of the first inductor L1 is connected to the power supply VCC. The first inductor L1 provides a DC bias path, blocking radio frequency signals from entering the power supply. This ensures that the power amplifier transistor 2 obtains a stable DC bias, prevents radio frequency signals from interfering with the power supply or causing leakage, and simultaneously assists in optimizing output matching and suppressing interference.

[0045] In this embodiment, the input matching circuit 1 includes a first capacitor C1, the first end of which is used to receive a radio frequency signal, and the second end of which is connected to the input terminal of the power amplifier tube 2.

[0046] Optionally, the output matching circuit 3 can be a series capacitor or inductor, or a parallel capacitor and inductor connected together to achieve the output impedance matching effect.

[0047] In this embodiment, the power amplifier tube 2 is a first transistor T1, the base of the first transistor T1 serves as the input terminal of the power amplifier tube 2, the collector of the first transistor T1 serves as the output terminal of the power amplifier tube 2, and the emitter of the first transistor T1 serves as the ground terminal of the power amplifier tube 2.

[0048] In this embodiment, the sampling amplifier transistor 4 is a second transistor T2. The base of the second transistor T2 serves as the input terminal of the sampling amplifier transistor 4, the collector of the second transistor T2 serves as the output terminal of the sampling amplifier transistor 4, and the emitter of the second transistor T2 serves as the ground terminal of the sampling amplifier transistor 4. Using the second transistor T2 and a mirror transistor (PMOS / NMOS) to form a protection circuit eliminates the need for complex logic control modules, making it easy to integrate into RF integrated circuits and reducing design costs.

[0049] In this embodiment, the bias current of the first current source 7 is defined as Ibias1, the reference current of the second current source 8 is defined as Iref, the drain current of the second image transistor P2 is defined as Ip2, the source current of the third image transistor N1 is defined as In1, the source current of the fourth image transistor N2 is defined as In2, and the current connected to the first terminal of the first resistor R1 is defined as Ibias2. The ground current of the power amplifier transistor 2 is I... T1 The grounding current of sampling amplifier tube 4 is I. T2 After grounding, I T1 and I T2 It is 0.

[0050] If Ip2 > Iref, then In1 = Ip2 - Iref, In2 = k * In1, Ibias2 = Ibias1 - In2; where k is a proportionality coefficient. Optionally, k can be an integer such as 1 or 2.

[0051] If Ip2≤Iref, then In1=0, Ibias2=Ibias1.

[0052] Specifically, when the current of power amplifier transistor 2 is normal (Ip2≤Iref), Ip2 is entirely absorbed by the reference current Iref of the second current source 8, the third mirror transistor N1 has no current (In1=0), and the second mirror circuit 6 has no output (In2=0). At this time, the bias current Ibias1 provided by the first current source 7 is directly applied to the base of the sampling amplifier transistor 4 and the power amplifier transistor 2 through the first resistor R1, ensuring their normal operation (Ibias2=Ibias1).

[0053] When the current of power amplifier transistor 2 is too large (Ip2 > Iref), the portion exceeding the reference current forms a current In1 (In1 = Ip2 - Iref) which flows into the third image transistor N1. Since the third image transistor N1 and the fourth image transistor N2 form an NMOS current mirror, the fourth image transistor N2 will output a current In2 proportional to In1 (In2 = k * In1, where k is the proportionality coefficient). At this time, the bias current Ibias1 provided by the first current source 7 will be shunted by In2, and the actual current applied to the base Ibias2 = Ibias1 - In2, which causes the operating current of power amplifier transistor 2 to decrease, thus achieving overcurrent protection.

[0054] In this embodiment, please refer to Figure 3 As shown, Figure 3 The curves showing the output power of the power amplifier 100 versus the input power are shown. In the prior art, at high power, the output power of the power amplifier 100 increases with increasing input power, which can easily damage the power amplifier transistor 2. However, the curves of the present invention show that at high power, the present invention can significantly reduce the output power of the power amplifier 100, thereby protecting the power amplifier 100 from damage during high-power output and ensuring good circuit reliability.

[0055] Example 2

[0056] This invention also provides an RF chip, including the power amplifier 100 as described above.

[0057] It should be noted that the various embodiments described above with reference to the accompanying drawings are merely illustrative of the present invention and not intended to limit its scope. Those skilled in the art should understand that any modifications or equivalent substitutions made to the present invention without departing from its spirit and scope should be included within the scope of the present invention. Furthermore, unless the context otherwise requires, words appearing in the singular include those in the plural, and vice versa. Additionally, unless specifically stated otherwise, all or part of any embodiment may be used in conjunction with all or part of any other embodiment.

Claims

1. A power amplifier, comprising an input matching circuit, a power amplifier transistor, and an output matching circuit connected in sequence; characterized in that, The power amplifier further includes a sampling amplifier tube, a first mirror circuit, a second mirror circuit, a first resistor, a first current source, and a second current source; the first current source is used to generate a bias current, and the second current source is used to generate a reference current. The input terminal of the sampling amplifier tube is connected to the input terminal of the power amplifier tube, and is used to sample the current of the power amplifier tube; The output terminal of the sampling amplifier tube is connected to the first input terminal of the first mirror circuit, and the second input terminal of the first mirror circuit is used to connect to an external DC power supply; the ground terminal of the sampling amplifier tube is grounded. The output terminal of the first mirror circuit is connected to the positive terminal of the second current source and the input terminal of the second mirror circuit, respectively. The negative terminal of the second current source is grounded. The positive terminal of the first current source is used to connect to the external DC power supply. The output terminal of the second mirror circuit is connected to the negative terminal of the first current source. The output terminal of the second mirror circuit is also connected to the first terminal of the first resistor. The second terminal of the first resistor is connected to the input terminal of the sampling amplifier tube. If the current output from the first mirror circuit is detected to be greater than the reference current, the bias current of the first current source is reduced. If the current output from the first mirror circuit is less than or equal to the reference current, the bias current of the first current source is output to the first terminal of the first resistor. The first mirror circuit includes a first mirror transistor and a second mirror transistor; the drain of the first mirror transistor is connected to the gate of the first mirror transistor and serves as the first input terminal of the first mirror circuit; the source of the first mirror transistor is connected to the source of the second mirror transistor and serves as the second input terminal of the first mirror circuit; the gate of the first mirror transistor is connected to the gate of the second mirror transistor, and the drain of the second mirror transistor serves as the output terminal of the first mirror circuit. The second mirror circuit includes a third mirror transistor and a fourth mirror transistor; The drain of the third mirror transistor is connected to the gate of the third mirror transistor and serves as the input terminal of the second mirror circuit; the gate of the third mirror transistor is connected to the gate of the fourth mirror transistor, and the drain of the fourth mirror transistor serves as the output terminal of the second mirror circuit; the source of the third mirror transistor is connected to the source of the fourth mirror transistor and grounded. The bias current of the first current source is defined as Ibias1, the reference current of the second current source is Iref, the drain current of the second image transistor is Ip2, the source current of the third image transistor is In1, the source current of the fourth image transistor is In2, and the current connected to the first terminal of the first resistor is Ibias2. If Ip2 > Iref, then In1 = Ip2 - Iref, In2 = k In1, Ibias2 = Ibias1 - In2; where k is the proportionality coefficient; If Ip2≤Iref, then In1=0, Ibias2=Ibias1.

2. The power amplifier according to claim 1, characterized in that, The first and second image transistors are both PMOS transistors; the third and fourth image transistors are both NMOS transistors.

3. The power amplifier according to claim 1, characterized in that, The power amplifier further includes a first inductor, the first end of which is connected to the output terminal of the power amplifier tube, and the second end of which is used to connect to the power supply.

4. The power amplifier according to claim 1, characterized in that, The input matching circuit includes a first capacitor, the first end of which is used to receive an radio frequency signal, and the second end of which is connected to the input terminal of the power amplifier tube.

5. The power amplifier according to claim 1, characterized in that, The power amplifier transistor is a first transistor, with its base serving as the input terminal, its collector serving as the output terminal, and its emitter serving as the ground terminal.

6. The power amplifier according to claim 1, characterized in that, The sampling amplifier tube is a second transistor, with its base serving as the input terminal, its collector serving as the output terminal, and its emitter serving as the ground terminal.

7. A radio frequency chip, characterized in that, Including the power amplifier as described in any one of claims 1-6.

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