Method, system, device and storage medium for large bandwidth multi-rate real-time signal processing

Abstract

The application relates to the technical field of filtering, and particularly provides a large-bandwidth multi-rate real-time signal processing method, system, device and storage medium, which comprises the following steps: acquiring a high-speed data stream output by an analog-to-digital converter (ADC); processing the high-speed data stream by using a dynamically configured multi-stage decimation filtering link, wherein the multi-stage decimation filtering link at least comprises a cascade integrated comb (CIC) filter, a half-band (HBF) filter and a coefficient-configurable finite impulse response (FIR) filter; in a signal processing process, the configuration state of the multi-stage decimation filtering link is dynamically switched in response to the change of a target signal bandwidth demand; the dynamic switching comprises changing the enabling states of the CIC filter and the HBF filter, and loading the FIR filter coefficients matched with the changed bandwidth; and the processed sampling data is cached. By using the dynamically configurable multi-stage decimation filtering link, adaptive processing of different bandwidth signals is realized.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of filtering, and particularly relates to a large-bandwidth multi-rate real-time signal processing method, system, device and storage medium. BACKGROUND

[0002] With the rapid development of 5G / 6G, satellite communication and electromagnetic spectrum monitoring, the demand for real-time acquisition and processing of large-bandwidth and multi-rate signals is increasingly urgent. The existing technology generally adopts a hardware architecture of "high-speed ADC+FPGA", and processes through a fixed digital down-conversion process. However, this scheme has significant limitations: first, its processing real-time is mostly limited to data stream communication, rather than true analysis real-time, and it is difficult to meet the demand for microsecond-level response; second, the system often uses a filter with fixed parameters, which cannot dynamically optimize performance and resources when collecting narrowband and wideband signals, resulting in insufficient out-of-band suppression of narrowband signals or excessive consumption of resources of wideband signals; finally, in order to realize large multiple decimation from high rate to low rate, a filter with extremely high order is needed, which seriously occupies FPGA logic resources and restricts the multi-channel expansion capability of the system. Therefore, there is an urgent need for a new real-time signal processing method that can flexibly adapt to changing signal bandwidth and achieve efficient use of resources. SUMMARY

[0003] In view of the above problems of the prior art, the application provides a large-bandwidth multi-rate real-time signal processing method, system, device and storage medium to solve the above technical problems.

[0004] In a first aspect, the application provides a large-bandwidth multi-rate real-time signal processing method, comprising:

[0005] obtaining a high-speed data stream output by an analog-to-digital converter ADC;

[0006] processing the high-speed data stream by using a dynamically configured multi-stage decimation filter link, the multi-stage decimation filter link at least including a cascaded integration comb CIC filter, a half-band HBF filter and a finite impulse response FIR filter with configurable coefficients;

[0007] In the signal processing process, in response to changes in the bandwidth demand of a target signal, the configuration state of the multi-stage decimation filter link is dynamically switched; the dynamic switching includes changing the enable state of the CIC filter and the HBF filter, and loading the FIR filter coefficients matched with the changed bandwidth;

[0008] storing the processed sampling data.

[0009] In an optional embodiment, after obtaining the high-speed data stream output by the analog-to-digital converter ADC, the method further comprises:

[0010] The high-speed data stream is inputted to a main signal processing path and a light spectrum sensing engine in parallel through a data stream distributor;

[0011] The main signal processing path is configured to perform down-sampling and filtering processing by using a multi-stage down-sampling filter link;

[0012] The light spectrum sensing engine acquires real-time bandwidth parameters of the signal by periodically extracting data frames and performing fast Fourier transform (FFT) analysis.

[0013] In an optional embodiment, the multi-stage down-sampling filter link is dynamically configured, including:

[0014] When the target signal bandwidth is greater than or equal to a first threshold, the filter link is configured to enable only the coefficient-configurable FIR filter;

[0015] When the target signal bandwidth is less than the first threshold and greater than or equal to a second threshold, the filter link is configured to enable the HBF filter and the coefficient-configurable FIR filter;

[0016] When the target signal bandwidth is less than the second threshold, the filter link is configured to enable the CIC filter, the HBF filter and the coefficient-configurable FIR filter;

[0017] The multi-stage down-sampling filter link is connected in a cascading manner, and the processing sequence is, in order, a cascading integral comb (CIC) filter, a half-band (HBF) filter and a coefficient-configurable finite impulse response (FIR) filter.

[0018] In an optional embodiment, a coefficient configuration method of the finite impulse response (FIR) filter includes:

[0019] A plurality of groups of FIR filter coefficients are pre-stored, each group of coefficients being matched with a specific signal bandwidth and out-of-band suppression requirement;

[0020] According to real-time bandwidth parameters obtained by the real-time spectrum analysis, a corresponding group of coefficients is automatically selected from the plurality of groups of coefficients and loaded to the FIR filter.

[0021] In an optional embodiment, during signal processing, in response to a change in a target signal bandwidth requirement, a configuration state of the multi-stage down-sampling filter link is dynamically switched, including:

[0022] Writing of new data to a target filter that needs to be removed in the multi-stage down-sampling filter link is suspended;

[0023] Residual data in a processing pipeline of the target filter is emptied;

[0024] switching an input of a downstream filter originally connected to an output of a target filter to a data node further upstream;

[0025] continuing to process a subsequent data stream in the new configuration state.

[0026] In an optional embodiment, the switching timing point is a non-continuous point of the data stream, and the non-continuous point includes a guard interval between data frames, a switching window predicted according to a signal change trend, or a preset periodic synchronization point.

[0027] In an optional embodiment, the switching of the input of the downstream filter to the data node further upstream is implemented by a multiplexer.

[0028] The first input of the multiplexer is connected to the output of the target filter, the second input is connected to the data node further upstream, and the output is connected to the input of the downstream filter.

[0029] The selection control signal of the multiplexer is switched to select between the output of the target filter and the data node further upstream.

[0030] In a second aspect, the present application provides a large-bandwidth multi-rate real-time signal processing system, comprising:

[0031] a data acquisition module configured to acquire a high-speed data stream output by an analog-to-digital converter (ADC);

[0032] a dynamic filtering module configured to process the high-speed data stream by using a dynamically configured multi-stage decimation filtering link, wherein the multi-stage decimation filtering link at least includes a cascaded integration comb (CIC) filter, a half-band (HBF) filter, and a finite impulse response (FIR) filter with configurable coefficients;

[0033] a dynamic switching module configured to dynamically switch a configuration state of the multi-stage decimation filtering link in response to a change in a target signal bandwidth requirement during a signal processing process, wherein the dynamic switching includes changing an enabling state of the CIC filter and the HBF filter, and loading FIR filter coefficients matching the changed bandwidth;

[0034] a data caching module configured to cache the processed sampling data.

[0035] In a third aspect, the present application provides a device, comprising:

[0036] a memory configured to store a large-bandwidth multi-rate real-time signal processing program;

[0037] A processor is configured to implement the steps of the large bandwidth multi-rate real-time signal processing method according to the first aspect when executing the large bandwidth multi-rate real-time signal processing program.

[0038] In a fourth aspect, a computer readable storage medium is provided, and the large bandwidth multi-rate real-time signal processing program is stored on the computer readable storage medium. The large bandwidth multi-rate real-time signal processing program is configured to implement the steps of the large bandwidth multi-rate real-time signal processing method according to the first aspect when executed by a processor.

[0039] The large bandwidth multi-rate real-time signal processing method, system, device and storage medium provided by the present application have the following beneficial effects. The large bandwidth multi-rate real-time signal processing method, system, device and storage medium provided by the present application realize adaptive processing of different bandwidth signals by using a multi-stage down-sampling filter link that can be dynamically configured. The system can intelligently switch the combination state and coefficients of CIC, HBF and FIR filters according to the characteristics of real-time signals, thereby ensuring the signal quality under each bandwidth and significantly optimizing the FPGA resource utilization. The scheme breaks through the limitations of the traditional fixed architecture, can maintain excellent out-of-band suppression performance in narrowband, midband and wideband signal acquisition scenarios, and ensures data integrity through a seamless switching mechanism, thereby providing an efficient and flexible solution for multi-rate real-time signal acquisition in a complex electromagnetic environment. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments or prior art description will be briefly introduced as follows. Obviously, for those skilled in the art, other drawings can also be obtained based on these drawings without creative labor.

[0041] Figure 1 is a schematic flowchart of the method of one embodiment of the present application.

[0042] Figure 2 is a schematic principle diagram of the method of one embodiment of the present application.

[0043] Figure 3 is a schematic block diagram of the system of one embodiment of the present application.

[0044] Figure 4 is a structural schematic diagram of a device provided by the embodiment of the present application. DETAILED DESCRIPTION

[0045] In order to make the person skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by the person skilled in the art without creative labor should belong to the protection scope of the present application.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description herein is for describing specific embodiments only and is not intended to be limiting of the application.

[0047] The large-bandwidth multi-rate real-time signal processing method provided by the embodiments of the present application is executed by a computer device, and accordingly, the large-bandwidth multi-rate real-time signal processing system runs in the computer device.

[0048] Figure 1 is a schematic flowchart of the method of an embodiment of the present application. In which, Figure 1 The execution subject can be a large-bandwidth multi-rate real-time signal processing system. According to different needs, the order of the steps in the flowchart can be changed, and some can be omitted.

[0049] As Figure 1 indicated, the method comprises:

[0050] S1. Obtain a high-speed data stream output by an analog-to-digital converter (ADC);

[0051] S2. Process the high-speed data stream by using a dynamically configured multi-stage down-sampling filter link, wherein the multi-stage down-sampling filter link at least comprises a cascaded integration comb (CIC) filter, a half-band (HBF) filter, and a finite impulse response (FIR) filter with configurable coefficients;

[0052] S3. In the signal processing process, in response to a change in a target signal bandwidth requirement, dynamically switch the configuration state of the multi-stage down-sampling filter link; the dynamic switching comprises changing the enable states of the CIC filter and the HBF filter, and loading the FIR filter coefficients matching the changed bandwidth;

[0053] S4. Cache the processed sampling data.

[0054] In an embodiment of the present application, based on step S1, a possible embodiment will be given below to non-restrictively describe the specific implementation thereof.

[0055] In this embodiment, the core of the system is implemented by a large-scale field programmable gate array (FPGA). As shown in the attached Figure 2 The high-speed data stream outputted by the ADC is first sent into a data stream distributor. The distributor is usually embodied as a multi-channel data duplication unit or multiple read ports of a first-in-first-out (FIFO) memory in the FPGA, and its function is to duplicate the same original data into two identical data streams without any delay.

[0056] One of the data streams enters the main signal processing path. The path contains the dynamically configurable multi-stage decimation filter link (CIC, HBF, FIR) as described above. These filters are cascaded in a pipeline manner, and are enabled and processed according to the default configuration in the initial state.

[0057] Meanwhile, the duplicated other data stream is sent into a parallel lightweight spectrum sensing engine. The engine is the key to the intelligence of the present application. In the FPGA logic, it is composed of a data frame buffer, a low-precision FFT IP core, and a simple spectrum analysis module. The implementation process is as follows: the engine does not process every sampling point, but extracts a frame of data from the data stream at a lower rate (for example, every 1024 points). Then, the frame of data is sent to the FFT IP core for low-precision (such as 16-point or 32-point) fast Fourier transform, which aims to quickly estimate the signal spectrum with the least logic resources. The spectrum analysis module then analyzes the FFT operation results, calculates the power spectral density of the signal, and applies methods such as power percentage method (such as calculating the bandwidth occupying 99% of the signal energy) or threshold detection method to calculate the key parameters of the signal such as instantaneous bandwidth, center frequency, and out-of-band noise power in real time.

[0058] In one embodiment of the present application, based on step S2, a possible embodiment will be given below to non-limitingly illustrate the specific implementation scheme.

[0059] S201. Hardware architecture and configuration logic of multi-stage filter link

[0060] Inside the FPGA, the multi-stage decimation filter link is connected in a fixed cascade order, and its data stream processing order is: cascaded integral comb (CIC) filter, half-band (HBF) filter, and coefficient-configurable finite-length unit impulse response (FIR) filter. This fixed physical connection ensures the determinacy of the data path.

[0061] The core of the "dynamic configuration" is to control the enable signals of the filters at each stage and the selection of the data path. The specific implementation is as follows:

[0062] Wideband mode (only enable FIR):

[0063] When the target signal bandwidth (e.g. > 100MHz) is greater than or equal to the first threshold, the system configuration logic will generate the following control signals:

[0064] Send a clock enable disable signal or put it in bypass mode to the CIC filter to stop its operation to save power and resources.

[0065] Send similar disable / bypass signals to the HBF filter.

[0066] At the same time, control a multiplexer at the input of the HBF to select the ADC raw data stream directly to the input of the FIR filter.

[0067] In this mode, the FIR filter undertakes the main anti-aliasing and out-of-band suppression task.

[0068] Mid-band mode (enable HBF + FIR):

[0069] When the target signal bandwidth (e.g. 20MHz to 100MHz) is less than the first threshold but greater than or equal to the second threshold, the system is configured: the CIC filter is disabled / bypassed. The HBF filter is enabled to perform preliminary 2 times decimation. The output of the HBF is directly sent to the FIR filter for final filtering and possible further decimation.

[0070] Narrowband mode (enable CIC + HBF + FIR):

[0071] When the target signal bandwidth (e.g. < 20MHz) is less than the second threshold, all three filters are enabled. The CIC filter first realizes a large decimation factor, the HBF performs secondary decimation, and finally the FIR filter performs precise matched filtering.

[0072] S202. Dynamic loading method of FIR filter coefficients

[0073] The coefficient configurable FIR filter is usually composed of a multiply-accumulate (MAC) unit and a coefficient memory (such as Block RAM) in hardware.

[0074] The specific implementation of the coefficient configuration method is: at system initialization, load the pre-designed multiple sets of FIR filter coefficients (e.g. coefficient sets corresponding to different signal bandwidths such as 180K, 1.4M, 5M, 20M, 100M) from an external non-volatile memory to a dedicated coefficient ROM or dual-port RAM inside the FPGA. Each set of coefficients is precisely designed to meet the passband ripple, transition bandwidth and out-of-band suppression requirements under its corresponding signal bandwidth.

[0075] When the system is running, the intelligent switching scheduler (based on the output of the spectrum sensing engine) decides to switch mode or update coefficients, and sends a coefficient selection instruction to the FIR filter module. The instruction contains the starting address of the target coefficient set in the coefficient memory. The controller inside the FIR filter reads the new coefficient set from the specified address and loads it into the coefficient registers of its operation unit within a clock cycle (or several cycles according to the coefficient length), so that it takes effect immediately, achieving accurate matching filtering of the changed signal bandwidth.

[0076] Through the cooperation of the above hardware architecture and control logic, the present application realizes joint dynamic optimization of filter link configuration and filter parameters, achieving the best balance between resource efficiency and processing performance.

[0077] In an embodiment of the present application, based on step S3, a possible embodiment will be given below to illustrate the specific implementation thereof.

[0078] S301. Determination of switching timing (synchronization point)

[0079] To achieve seamless switching, the switching action must be initiated at a non-continuous point of the data stream. In this embodiment, this function is realized by a switching timing detection module. The module continuously monitors the data stream and determines the switching timing according to the preset strategy:

[0080] For framed signals (such as communication signals): The module accurately identifies the guard interval between data frames by detecting the frame synchronization header or frame end identifier, and initiates switching within this time window.

[0081] For continuous signals: The system establishes a preset periodic synchronization point, for example, a fixed time interval (such as every 1 ms) or the moment when a certain data buffer completes a read / write pointer exchange as the switching window.

[0082] Predictive switching: The intelligent switching scheduler predicts that the signal bandwidth will soon exceed the tolerance of the current configuration according to the bandwidth change trend provided by the spectrum sensing engine, and issues an instruction in advance, waiting for the next available synchronization point to execute immediately.

[0083] S302. Execution flow of seamless switching

[0084] Taking switching from "narrowband mode (CIC+HBF+FIR)" to "midband mode (HBF+FIR)" as an example, the execution steps of switching are described in detail. This process is precisely controlled by a state machine inside a switching controller.

[0085] Decision and preparation: The intelligent switching scheduler makes the switching decision according to the real-time bandwidth parameters, and sends the new configuration parameters (including the target filter to be removed, in this case, the CIC filter) to the switching controller.

[0086] Pause and empty: At the selected inter-frame synchronization point, the switching controller immediately sends a "data valid disable" signal to the data input end of the CIC filter to pause writing new ADC sample data to it. At the same time, the system keeps the clock running, allowing the processing pipeline inside the CIC filter to continue working until all the residual data is calculated and output. This ensures that all the data that has entered the CIC is processed completely, avoiding data loss.

[0087] Path switching (through the multiplexer):

[0088] After the emptying is completed, the switching controller changes the selection control signal of the multiplexer. The hardware connection relationship of the multiplexer is: the first input end is connected to the output end of the CIC filter, the second input end is directly connected to the data node upstream, that is, the ADC original data stream (or the output of the distributor). The output end is always connected to the input end of the downstream filter, that is, the HBF filter.

[0089] Through the switching control signal, the output of the multiplexer is instantaneously switched from the "first input end (CIC output)" to the "second input end (ADC original data stream)". At this time, the CIC filter is successfully removed from the signal chain, and the input source of the HBF becomes the original data.

[0090] Restoration processing: After the path switching is completed, the switching controller releases the data flow control of the HBF and the FIR filter, and the system resumes the processing of the subsequent ADC data stream in the new "HBF+FIR" configuration state. The entire switching process is completed within the natural pause of the data stream, ensuring the continuity and integrity of the output IQ data.

[0091] Through the above precise timing control and hardware cooperation, the seamless switching in the filter link reconstruction process is successfully realized, meeting the stringent requirements of high-end real-time signal acquisition systems for data integrity.

[0092] In an embodiment of the present application, based on step S4, a possible embodiment will be given below to illustrate the specific implementation scheme.

[0093] S401. Buffer hardware architecture

[0094] The final output data after multi-stage down-sampling filter link processing is usually a moderate rate, continuous in-phase / quadrature (IQ) data stream. In the present application, the "buffering" function is mainly implemented by a large-capacity, high-bandwidth DDR SDRAM located outside the FPGA. A DDR memory controller IP core and a dedicated data write control module are provided inside the FPGA, which jointly write IQ data into the DDR memory efficiently.

[0095] S402. Buffering data stream and management

[0096] The IQ data from the output end of the FIR filter is first sent to an asynchronous FIFO (first-in first-out queue) for clock domain conversion and rate buffering. Subsequently, the data write control module packages the data in the FIFO into data bursts conforming to the AXI bus protocol in a direct memory access (DMA) manner, and continuously writes the data into a ring-shaped data buffer area previously opened in the DDR through the DDR memory controller.

[0097] In order to ensure uninterrupted real-time acquisition, the data write control module maintains a write address pointer to cyclically overwrite old data or allocate new space in the ring-shaped buffer area. At the same time, the module notifies the central processing unit (CPU) or subsequent service analysis unit (such as a digital signal processor DSP) in the system through an interrupt or a status register that there is a new data block available for reading. The subsequent unit reads the IQ data from the specified address of the DDR through memory mapping or DMA reading of the operating system for demodulation, analysis and subsequent processing.

[0098] Through this architecture, the present application realizes the "acquisition-processing-buffering-analysis" pipeline operation of high-speed data stream. The DDR buffer as a key link effectively solves the contradiction between data processing rate and subsequent analysis rate, provides sufficient data basis and flexible time window for deep data analysis, and thus realizes the leap from "data stream real-time" to "service analysis real-time".

[0099] In some embodiments, the large-bandwidth multi-rate real-time signal processing system can include a plurality of functional modules composed of computer program segments. The computer programs of each program segment in the large-bandwidth multi-rate real-time signal processing system can be stored in the memory of a computer device and executed by at least one processor to perform (see Figure 1 Description) the functions of large-bandwidth multi-rate real-time signal processing.

[0100] In the present embodiment, the large-bandwidth multi-rate real-time signal processing system can be divided into a plurality of functional modules according to the functions it performs, such as Figure 3The modules referred to in the present application refer to a series of computer program segments capable of being executed by at least one processor and capable of completing fixed functions, which are stored in a memory. In the present embodiment, the functions of the modules will be described in detail in subsequent embodiments.

[0101] a data acquisition module, configured to acquire a high-speed data stream output by an analog-to-digital converter (ADC);

[0102] a dynamic filtering module, configured to process the high-speed data stream by using a dynamically configured multi-stage decimation filtering link, the multi-stage decimation filtering link at least including a cascaded integration comb (CIC) filter, a half-band (HBF) filter, and a finite impulse response (FIR) filter with configurable coefficients;

[0103] a dynamic switching module, configured to dynamically switch a configuration state of the multi-stage decimation filtering link in response to a change in a target signal bandwidth requirement during a signal processing process; the dynamic switching includes changing an enabling state of the CIC filter and the HBF filter, and loading FIR filter coefficients matching the changed bandwidth;

[0104] a data acquisition module, configured to cache the processed sampling data.

[0105] Figure 4 The large-bandwidth multi-rate real-time signal processing method provided by the present application can be applied to a device. Those skilled in the art can understand that the device structure involved in the embodiments of the present application does not constitute a limitation on the device, and the device can include more or fewer components than those shown, or combine certain components, or different component arrangements. In the embodiments of the present application, the device includes but is not limited to a laptop computer, a desktop computer, a workstation, a personal digital assistant, a server, a blade server, a mainframe computer, and other suitable computers. The device can also represent various forms of mobile devices, such as a personal digital processor, a cellular phone, a smart phone, a wearable device, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the embodiments of the present application described herein and / or claimed.

[0106] The present application also provides a computer storage medium, wherein the computer storage medium can store a program, and the program can include some or all steps in the embodiments provided by the present application when executed. The storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

Claims

1. A high-bandwidth, multi-rate real-time signal processing method, characterized in that, include: Acquire the high-speed data stream output by the analog-to-digital converter (ADC); The high-speed data stream is processed using a dynamically configured multi-stage downsampling filter link, which includes at least a cascaded integrator comb (CIC) filter, a half-band HBF filter, and a finite-length unit impulse response (FIR) filter with configurable coefficients. During signal processing, in response to changes in the target signal bandwidth requirements, the configuration state of the multi-stage downsampling filter links is dynamically switched; the dynamic switching includes changing the enable state of the CIC filter and the HBF filter, and loading FIR filter coefficients that match the changed bandwidth. The processed sampled data is cached; Dynamically configure multi-stage downsampling filtering links, including: When the target signal bandwidth is greater than or equal to the first threshold, the filtering link is configured to enable only the FIR filter. When the target signal bandwidth is less than the first threshold and greater than or equal to the second threshold, the filtering link is configured to enable the HBF filter and the coefficient-configurable FIR filter. When the target signal bandwidth is less than the second threshold, the filtering link is configured to enable the CIC filter, the HBF filter, and the coefficient-configurable FIR filter; The multi-stage downsampling filter links are connected in a cascaded manner, and the processing order is as follows: cascaded integral comb CIC filter, half-band HBF filter, and finite-length unit impulse response FIR filter with configurable coefficients. Methods for configuring the coefficients of a finite-length unit impulse response (FIR) filter include: Multiple sets of FIR filter coefficients are pre-stored, and each set of coefficients is matched with a specific signal bandwidth and out-of-band rejection requirement; Based on the real-time bandwidth parameters obtained from real-time spectrum analysis, a corresponding set of coefficients is automatically selected from the multiple sets of coefficients and loaded into the FIR filter.

2. The method according to claim 1, characterized in that, After acquiring the high-speed data stream output by the analog-to-digital converter (ADC), the method further includes: The high-speed data stream is input in parallel to the main signal processing path and a lightweight spectrum sensing engine via a data stream distributor. The main signal processing path is used to perform downsampling and filtering processing using a multi-stage downsampling and filtering link; The lightweight spectrum sensing engine obtains the real-time bandwidth parameters of the signal by periodically extracting data frames and performing Fast Fourier Transform (FFT) analysis.

3. The method according to claim 2, characterized in that, During signal processing, in response to changes in the target signal bandwidth requirements, the configuration state of the multi-stage downsampling filter links is dynamically switched, including: Pause writing new data to the target filter that needs to be removed in the multi-stage downsampling filter link; Drain residual data from the processing pipeline of the target filter; The input of the downstream filter, which was originally connected to the output of the target filter, is directly switched to the upstream data node; Continue processing subsequent data streams with the new configuration state.

4. The method according to claim 3, characterized in that, The switching point is a point of discontinuity in the data stream, which includes: a guard interval between data frames, a switching window predicted based on signal change trends, or a preset periodic synchronization point.

5. The method according to claim 3, characterized in that, Switching the input of the downstream filter directly to the upstream data node is achieved through a multiplexer; The first input of the multiplexer is connected to the output of the target filter, the second input is connected to the upstream data node, and the output is connected to the input of the downstream filter. By switching the selection control signal of the multiplexer, its output is selected between the output of the target filter and the upstream data node.

6. A high-bandwidth, multi-rate real-time signal processing system, characterized in that, include: The data acquisition module is used to acquire the high-speed data stream output by the analog-to-digital converter (ADC). The dynamic filtering module is used to process the high-speed data stream using a dynamically configured multi-stage downsampling filtering link. The multi-stage downsampling filtering link includes at least a cascaded integrator comb (CIC) filter, a half-band HBF filter, and a finite-length unit impulse response (FIR) filter with configurable coefficients. The dynamic switching module is used to dynamically switch the configuration state of the multi-stage downsampling filter link in response to changes in the bandwidth requirements of the target signal during signal processing; the dynamic switching includes changing the enable state of the CIC filter and the HBF filter, and loading FIR filter coefficients that match the changed bandwidth. The data caching module is used to cache the processed sampled data; Dynamically configure multi-stage downsampling filtering links, including: When the target signal bandwidth is greater than or equal to the first threshold, the filtering link is configured to enable only the FIR filter. When the target signal bandwidth is less than the first threshold and greater than or equal to the second threshold, the filtering link is configured to enable the HBF filter and the coefficient-configurable FIR filter. When the target signal bandwidth is less than the second threshold, the filtering link is configured to enable the CIC filter, the HBF filter, and the coefficient-configurable FIR filter; The multi-stage downsampling filter links are connected in a cascaded manner, and the processing order is as follows: cascaded integral comb CIC filter, half-band HBF filter, and finite-length unit impulse response FIR filter with configurable coefficients. Methods for configuring the coefficients of a finite-length unit impulse response (FIR) filter include: Multiple sets of FIR filter coefficients are pre-stored, and each set of coefficients is matched with a specific signal bandwidth and out-of-band rejection requirement; Based on the real-time bandwidth parameters obtained from real-time spectrum analysis, a corresponding set of coefficients is automatically selected from the multiple sets of coefficients and loaded into the FIR filter.

7. A high-bandwidth, multi-rate real-time signal processing device, characterized in that, include: Memory, used to store high-bandwidth, high-rate real-time signal processing programs; A processor, configured to implement the steps of the high bandwidth multi-rate real-time signal processing method as described in any one of claims 1-5 when executing the high bandwidth multi-rate real-time signal processing program.

8. A computer-readable storage medium storing a computer program, characterized in that, The readable storage medium stores a high-bandwidth, high-rate real-time signal processing program, which, when executed by a processor, implements the steps of the high-bandwidth, high-rate real-time signal processing method as described in any one of claims 1-5.

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