Storage array, memory and electronic equipment

Abstract

The invention provides a storage array, a memory, electronic equipment and a preparation method. Relates to the technical field of data storage. A storage unit in the storage array can be a 6T storage unit, for example, the storage array comprises a substrate, a plurality of storage units, a first power line and a second power line, and the first power line and the second power line are electrically connected with the storage units; the plurality of memory cells are located on the front side of the substrate, and the first power line and the second power line are located on the back side of the substrate, that is, the power lines and the memory cells are located on different sides of the substrate. Therefore, interconnection wiring on the front surface of the substrate can be simplified, and the power line is arranged in the back space of the substrate, so that the storage density of the storage unit on the front surface of the substrate can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor storage, in particular to a storage array, a memory comprising the storage array, an electronic device comprising the memory, and a preparation method of the storage array. BACKGROUND

[0002] With the development of integrated circuits, the size of transistors is continuously reduced. For example, in a two-dimensional planar structure, the size of structures such as a gate (GT), a contact hole, a spacer between a gate and a source and a drain (SD) has basically reached the process limit, and the contacted poly pitch (CPP) / contacted gate pitch (CGP) of different transistors is difficult to further reduce. Based on this, the architecture of the transistor has gradually evolved from a two-dimensional planar structure (as shown in (a), (b), and (c) in FIG. 1) to a three-dimensional structure (as shown in (d) in FIG. 1), that is, the gate GT, the source S, and the drain D of the transistor are changed from a lateral arrangement to a vertical arrangement, so that the gate, the spacer, and other structures no longer occupy the space in the CPP direction, providing the possibility for further reduction of the CPP. Figure 1 Figure 1

[0003] Static random access memory (SRAM) has the highest data storage speed among various types of memories and can directly interact with a processor for data exchange, and therefore is widely used. The vertical transistor with a three-dimensional structure is beneficial to reducing the area of a storage unit in the SRAM and improving the storage density of the SRAM.

[0004] However, as shown in FIG. 2, the gate GT, the source S, and the drain D of the vertical transistor are located in different planes, and the leads of the gate GT, the source S, and the drain D are also located in different planes, which makes it difficult and complex to connect different storage units in the SRAM and to interconnect the internal components of the storage unit. Therefore, it is difficult to compress the area of the SRAM comprising the vertical channel transistor, and the further improvement of the storage density is limited. Figure 2 SUMMARY

[0005] The present application provides a storage array, a memory comprising the storage array, a preparation method of the storage array, and an electronic device comprising the memory. The main purpose is to provide a storage array structure that can simplify the interconnection and improve the storage density.

[0006] To achieve the above purpose, the embodiments of the present application adopt the following technical solutions: ​​​

[0007] In a first aspect, the present application provides a storage array, which can be a static random access memory (SRAM) for example.

[0008] The storage array comprises a substrate, a plurality of storage units, a first power line and a second power line; the substrate has opposite first and second sides, the plurality of storage units are located on the first side, and the first and second power lines are located on the second side, that is, the power lines and the storage units are located on different sides of the substrate; each storage unit comprises a plurality of transistors, the transistors comprise a first pole, a second pole and a gate, the first and second poles are arranged in a direction perpendicular to the surface of the substrate, and the first pole is located in the substrate, that is, the transistor is a vertical transistor, the plurality of transistors comprise first and second transistors and third and fourth transistors, the first and second transistors are coupled in series between the first and second power lines, and the third and fourth transistors are coupled in series between the first and second power lines; the first pole of the first transistor is provided with the first power line on the side away from the second pole, and the first pole of the second transistor is provided with the second power line on the side away from the second pole; the first pole of the third transistor is provided with the first power line on the side away from the second pole, and the first pole of the fourth transistor is provided with the second power line on the side away from the second pole.

[0009] In the storage array provided by the present application, the storage units are arranged on the front surface (such as the first side) of the substrate; since the first and second transistors coupled in series need to be connected with the first and second power lines, and the third and fourth transistors coupled in series need to be connected with the first and second power lines, the present application arranges the power lines on the back surface (such as the second side) of the substrate, so that the interconnection wiring on the front surface of the substrate can be simplified, the power lines can be arranged in the space on the back surface of the substrate, and thus the storage density of the storage units on the front surface of the substrate can be improved.

[0010] In an implementable manner, the arrangement direction of the first and third transistors is parallel to the extension direction of the first power line; the first and third transistors are electrically connected with the same first power line.

[0011] Since the first and third transistors are both connected with the first power line, the extension direction of the first power line can be consistent with the arrangement direction of the two transistors, so that the two transistors are electrically connected with the same power line. For example, the first and third transistors are arranged along the first direction, and the first power line extends along the first direction, so that the problem of high resistance and voltage drop of the plurality of storage units in the first direction can be weakened, and thus the storage performance can be improved.

[0012] In an implementable manner, the arrangement direction of the second transistor and the fourth transistor is parallel to the extension direction of the second power supply line; the second transistor and the fourth transistor are electrically connected to the same second power supply line; the first power supply line and the second power supply line are parallel; and the arrangement direction of the first power supply line and the second power supply line is perpendicular to the arrangement direction of the second transistor and the fourth transistor.

[0013] Since the second transistor and the fourth transistor are both connected to the second power supply line, the extension direction of the second power supply line can be consistent with the arrangement direction of the two transistors, so that the two transistors are electrically connected to the same power supply line. In this way, the problem of high resistance and voltage drop of the plurality of storage units can be weakened, and the storage performance can be improved.

[0014] In an implementable manner, the storage unit further includes a fifth transistor and a sixth transistor; the series coupling point of the first transistor and the second transistor is electrically connected to the fifth transistor; the series coupling point of the third transistor and the fourth transistor is electrically connected to the sixth transistor; and the storage array further includes a first signal line and a second signal line; the fifth transistor is electrically connected to the first signal line, and the sixth transistor is electrically connected to the second signal line.

[0015] For example, the first signal line is electrically connected to the first electrode of the fifth transistor, the series coupling point of the first transistor and the second transistor is electrically connected to the second electrode of the fifth transistor, the second signal line is electrically connected to the first electrode of the sixth transistor, and the series coupling point of the third transistor and the fourth transistor is electrically connected to the second electrode of the sixth transistor. The storage unit formed in this way can be referred to as a 6T storage unit, the first transistor and the second transistor connected in series form an inverter, the third transistor and the fourth transistor connected in series form another inverter, and the fifth transistor and the sixth transistor respectively serve as a gate-on transistor. The storage unit with such a structure has a large storage capacity and a fast response speed.

[0016] In one possible implementation, the first terminal of a first transistor is electrically connected to a first power line; the first terminal of a second transistor is electrically connected to a second power line; the second terminal of a first transistor is electrically connected to the second terminal of a second transistor; and the gate of a first transistor is electrically connected to the gate of a second transistor. The first terminal of a third transistor is electrically connected to the first power line; the first terminal of a fourth transistor is electrically connected to the second power line; the second terminal of a third transistor is electrically connected to the second terminal of a fourth transistor; and the gate of a third transistor is electrically connected to the gate of a fourth transistor. The coupling point between the second terminals of the first and second transistors is electrically connected to the coupling point between the gates of the third and fourth transistors; the coupling point between the second terminals of the third and fourth transistors is electrically connected to the coupling point between the gates of the first and second transistors. The coupling point between the second terminals of the first and second transistors is electrically connected to the second terminal of a fifth transistor; and the coupling point between the second terminals of the third and fourth transistors is electrically connected to the second terminal of a sixth transistor.

[0017] In one possible implementation, the first signal line and the second signal line are located on the second side of the substrate; the first signal line is located on the side of the first electrode of the fifth transistor opposite to the second electrode; the second signal line is located on the side of the first electrode of the sixth transistor opposite to the second electrode; the first signal line, the second signal line, the first power line, and the second power line are located in the same metal layer.

[0018] In this implementation structure, the first signal line and the second signal line can also be placed on the back side of the substrate, further simplifying the interconnect routing on the front side of the substrate and further improving the storage density.

[0019] In one possible implementation, the memory array further includes: a third signal line, a fifth transistor electrically connected to the third signal line, and a sixth transistor electrically connected to the third signal line; the third signal line is located on a first side of the substrate.

[0020] For example, the gates of the fifth transistor and the sixth transistor are both electrically connected to the third signal line. In this example, the third signal line is positioned on the front side of the substrate.

[0021] In one possible implementation, the first signal line and the second signal line are located on a first side of the substrate; the memory array further includes: a third signal line, a fifth transistor electrically connected to the third signal line, a sixth transistor electrically connected to the third signal line, the third signal line being located on a first side of the substrate; the first signal line and the second signal line being located on a first front metal layer; the third signal line being located on a second front metal layer; the first front metal layer and the second front metal layer are stacked along a direction perpendicular to the substrate surface.

[0022] In this implementation structure, the first signal line, the second signal line, and the third signal line are all disposed on the front side of the substrate. The first signal line and the second signal line are located in the same metal layer, while the third signal line is located in another metal layer. For example, the first front-side metal layer is closer to the substrate than the second front-side metal layer.

[0023] In one possible implementation, a fifth transistor, a first transistor, and a second transistor are arranged sequentially in a second direction; a third transistor, a fourth transistor, and a sixth transistor are arranged sequentially in a second direction; a first transistor and a third transistor are arranged in a first direction; a second transistor and a fourth transistor are arranged in a first direction; both the first and second directions are parallel to the substrate surface, and the first direction is perpendicular to the second direction.

[0024] In other words, two inverters are arranged side by side along the first direction, and the two inverters together are called a latch. One of the two selectors is located on one side of the latch, and the other selector is located on the other side of the latch. This simplifies the interconnection routing of the two inverters, as well as the interconnection routing between the selector and the inverter.

[0025] In one possible implementation, the plurality of memory cells include adjacent first memory cells and second memory cells; the first memory cells and second memory cells are arranged in a second direction; the arrangement of the plurality of transistors in the first memory cells and the arrangement of the plurality of transistors in the second memory cells are mirror-symmetrical about a reference plane, the reference plane being perpendicular to the substrate surface.

[0026] In one possible implementation, the plurality of memory cells include adjacent first memory cells and second memory cells; the first memory cells and second memory cells are arranged in a second direction; the arrangement of the plurality of transistors in the first memory cell is the same as the arrangement of the plurality of transistors in the second memory cell.

[0027] The above describes two different deployment methods for storage arrays. Using these two deployment methods will not pose any challenges to the manufacturing process.

[0028] In one possible implementation, the first signal line and the second signal line are located on the second side of the substrate; the first power line and the second power line are located on the first back metal layer; the first signal line and the second signal line are located on the second back metal layer; the first back metal layer and the second back metal layer are stacked in a direction perpendicular to the substrate surface.

[0029] In this embodiment, the first signal line and the second signal line, as well as the first power line and the second power line, are all located on the back side of the substrate. The first power line and the second power line are located within one metal layer, while the first signal line and the second signal line are located within another metal layer. In some implementations, the fifth transistor in one of two adjacent memory cells can be arranged side-by-side with the sixth transistor in the other memory cell. This further reduces the projected area of ​​each memory cell on the substrate, increasing storage density.

[0030] In one possible implementation, the second back metal layer is further away from the substrate than the first back metal layer; the first electrode of the fifth transistor has a first trace on the first side away from the second electrode, and the first trace is connected to a first signal line located on the second back metal layer through a conductive via through the dielectric layer, and the first trace is located on the first back metal layer; the first electrode of the sixth transistor has a second trace on the first side away from the second electrode, and the first trace is connected to a second signal line located on the second back metal layer through a conductive via through the dielectric layer, and the second trace is located on the first back metal layer.

[0031] The first trace located in the first back metal layer may not extend in a direction parallel to the substrate, and may be connected to the first signal line located in the second back metal layer through a conductive via. Similarly, the second trace located in the first back metal layer may not extend in a direction parallel to the substrate, and may be connected to the second signal line located in the second back metal layer through a conductive via.

[0032] In one possible implementation, the memory array further includes: a third signal line, a fifth transistor electrically connected to the third signal line, and a sixth transistor electrically connected to the third signal line; the third signal line is located on a first side of the substrate.

[0033] For example, the gates of the fifth transistor and the sixth transistor are both electrically connected to the third signal line. In this example, the third signal line is positioned on the front side of the substrate.

[0034] In one possible implementation, the extension direction of the third signal line is perpendicular to the extension direction of the first signal line.

[0035] In one possible implementation, a fifth transistor, a first transistor, and a second transistor are arranged sequentially in a second direction; a third transistor, a fourth transistor, and a sixth transistor are arranged sequentially in a second direction; a first transistor and a third transistor are arranged in a first direction; a second transistor and a fourth transistor are arranged in a first direction; both the first and second directions are parallel to the substrate surface, and the first direction is perpendicular to the second direction.

[0036] In this example, two inverters are arranged side-by-side along a first direction, and the two inverters are collectively referred to as a latch. One of the two selectors is located on one side of the latch, and the other selector is located on the other side of the latch. This simplifies the interconnection routing of the two inverters, as well as the interconnection routing between the selector and the inverter.

[0037] In one possible implementation, a plurality of memory cells include a first memory cell and a second memory cell; the first memory cell and the second memory cell are arranged in a second direction; a fifth transistor in the first memory cell and a sixth transistor in the second memory cell are arranged in the first direction.

[0038] The fifth transistor in the first memory cell and the sixth transistor in the second memory cell are arranged in the first direction, which can further compress the projected area of ​​each memory cell on the substrate and increase the storage density.

[0039] In one possible configuration, the first signal line, the second signal line, the first power line, and the second power line are parallel.

[0040] In one possible implementation, a first power line and a second power line extend along a first direction parallel to the substrate surface; the first electrode of a first transistor of a plurality of memory cells arranged along the first direction is electrically connected to the first power line; and the first electrode of a third transistor of a plurality of memory cells arranged along the first direction is electrically connected to the first power line.

[0041] Since the first electrode of the first transistor of the plurality of memory cells arranged along the first direction is electrically connected to the same first power line, and since the first electrode of the third transistor of the plurality of memory cells arranged along the first direction is electrically connected to the same second power line, the problems of high resistance and voltage drop of the plurality of memory cells in the first direction can be reduced, thereby improving memory performance.

[0042] In one possible implementation, a first signal line and a second signal line extend along a first direction parallel to the substrate surface; the first electrode of a fifth transistor of a plurality of memory cells arranged along the first direction is electrically connected to the first signal line; the first electrode of a fifth transistor of a plurality of memory cells arranged along the first direction is electrically connected to the first signal line.

[0043] Since the first electrode of the fifth transistor of the plurality of memory cells arranged along the first direction is electrically connected to the same first signal line, and since the first electrode of the sixth transistor of the plurality of memory cells arranged along the first direction is electrically connected to the same second signal line, the problem of high resistance and voltage drop of the plurality of memory cells in the first direction can be reduced, thereby improving memory performance.

[0044] Secondly, this application provides a memory including a controller and a memory array as described in any of the above implementations, wherein the controller is used to control the reading and writing of the memory array.

[0045] In the memory provided in this application, multiple memory cells are disposed on the front side of the substrate. Since the first power line and the second power line of the memory array are disposed on the back side of the substrate, the interconnection routing on the front side of the substrate can be simplified and the memory density can be increased.

[0046] Thirdly, this application provides an electronic device including a processor and a memory in any of the above implementations, wherein the processor is electrically connected to the memory and the memory is used to store data generated by the processor.

[0047] The electronic device provided in this application includes the memory in any of the above implementations. Therefore, the electronic device provided in this application and the memory of the above technical solutions can solve the same technical problems and achieve the same expected results.

[0048] Fourthly, this application provides a method for fabricating a memory array, the method comprising:

[0049] Multiple memory cells are formed on the first side of the substrate. Each memory cell includes multiple transistors. The transistors include a first electrode, a second electrode, and a gate. The first electrode and the second electrode are arranged in a direction perpendicular to the substrate surface. The first electrode is located inside the substrate. The multiple transistors include a first transistor, a second transistor, a third transistor, and a fourth transistor.

[0050] A first power line is provided on the side of the first electrode of the first transistor away from the second electrode, a second power line is provided on the side of the first electrode of the second transistor away from the second electrode, a first power line is provided on the side of the first electrode of the third transistor away from the second electrode, and a second power line is provided on the side of the first electrode of the fourth transistor away from the second electrode; wherein, the first transistor and the second transistor are coupled in series between the first power line and the second power line, and the third transistor and the fourth transistor are coupled in series between the first power line and the second power line.

[0051] When fabricating a memory array using this method, the first power line and the second power line are placed on the back side of the substrate (the side of the substrate where the memory cells are located is the front side), and not on the front side of the substrate. This simplifies the interconnect routing on the front side of the substrate, thereby increasing the integration density of the memory cells on the front side of the substrate and improving the storage capacity.

[0052] In one feasible embodiment, a plurality of memory cells are formed on a first side of the substrate, and the method further includes:

[0053] The fifth and sixth transistors are formed, and the series coupling point of the first and second transistors is electrically connected to the fifth transistor, and the series coupling point of the third and fourth transistors is electrically connected to the sixth transistor.

[0054] The preparation method also includes:

[0055] The first signal line is formed on the side of the first electrode of the fifth transistor that is away from the second electrode, and the second signal line is formed on the side of the first electrode of the sixth transistor that is away from the second electrode. The fifth transistor is electrically connected to the first signal line, and the sixth transistor is electrically connected to the second signal line. The first signal line, the second signal line, the first power line, and the second power line are located on the same metal layer.

[0056] In this fabrication method, the first signal line and the second signal line can be placed on the back side of the substrate, which can further improve the storage density and storage capacity.

[0057] In one feasible embodiment, a plurality of memory cells are formed on a first side of the substrate, and the method further includes:

[0058] The fifth and sixth transistors are formed, and the series coupling point of the first and second transistors is electrically connected to the fifth transistor, and the series coupling point of the third and fourth transistors is electrically connected to the sixth transistor.

[0059] The preparation method also includes:

[0060] A first signal line and a second signal line are formed on the first side of the substrate. A fifth transistor is electrically connected to the first signal line, and a sixth transistor is electrically connected to the second signal line.

[0061] In one feasible manner, a third signal line is formed on a first side of the substrate, a fifth transistor is electrically connected to the third signal line, a sixth transistor is electrically connected to the third signal line, a first signal line and a second signal line are located on a first front metal layer, and a third signal line is located on a second front metal layer. The first front metal layer and the second front metal layer are stacked in a direction perpendicular to the substrate surface.

[0062] In this fabrication method, the first signal line and the second signal line are integrated on the front side of the substrate, the first signal line and the second signal line are located in the same metal layer, and the third signal line is located in another metal layer.

[0063] In one feasible embodiment, a plurality of memory cells are formed on a first side of the substrate, and the method further includes:

[0064] The fifth and sixth transistors are formed, and the series coupling point of the first and second transistors is electrically connected to the fifth transistor, and the series coupling point of the third and fourth transistors is electrically connected to the sixth transistor.

[0065] The preparation method also includes:

[0066] A second back metal layer is formed on the side of the first back metal layer away from the substrate. The second back metal layer includes a first signal line and a second signal line. The first back metal layer includes a first power line and a second power line.

[0067] In this fabrication method, not only are the first signal line and the second signal line disposed on the back side of the substrate, but the first signal line and the second signal line are located in one metal layer, and the first power line and the second power line are located in another metal layer, in some implementation structures, the fifth transistor in one of two adjacent memory cells can be arranged side by side with the sixth transistor in the other memory cell, which can further compress the projected area of ​​each memory cell on the substrate and improve the storage density. Attached Figure Description

[0068] Figure 1 A schematic diagram illustrating the evolution of transistor architecture from a two-dimensional planar structure to a three-dimensional solid structure;

[0069] Figure 2 This is a schematic diagram of a vertical transistor structure.

[0070] Figure 3 This is a circuit diagram of an electronic device.

[0071] Figure 4 This is a circuit diagram of a memory.

[0072] Figure 5A This is a diagram showing the packaging structure of a storage array and a controller;

[0073] Figure 5B This is a diagram showing the packaging structure of a storage array and a controller;

[0074] Figure 5C This is a diagram showing the packaging structure of a storage array and a controller;

[0075] Figure 6 This is a simplified circuit diagram of a memory.

[0076] Figure 7 A circuit diagram of a 6T storage cell provided for an embodiment of this application;

[0077] Figure 8 A circuit diagram of a storage array containing 6T storage cells provided for an embodiment of this application;

[0078] Figure 9 A layout of a 6T storage cell is provided in an embodiment of this application;

[0079] Figure 10 for Figure 9A cross-sectional view along section AA;

[0080] Figure 11 for Figure 9 A cross-sectional view along BB section;

[0081] Figure 12 A layout comprising four 6T memory cells is provided for an embodiment of this application;

[0082] Figure 13 A layout of the transistors of four 6T memory cells provided for an embodiment of this application;

[0083] Figure 14 This application provides an embodiment of an interconnection routing diagram for four 6T memory cells.

[0084] Figure 15 A layout comprising four 6T memory cells is provided for an embodiment of this application;

[0085] Figure 16 A layout of the transistors of four 6T memory cells provided for an embodiment of this application;

[0086] Figure 17 This application provides an embodiment of an interconnection routing diagram for four 6T memory cells.

[0087] Figure 18 A layout of a 6T storage cell is provided in an embodiment of this application;

[0088] Figure 19 for Figure 18 A cross-sectional view along the CC section;

[0089] Figure 20 A layout comprising four 6T memory cells is provided for an embodiment of this application;

[0090] Figure 21 A layout of the transistors of four 6T memory cells provided for an embodiment of this application;

[0091] Figure 22 This application provides an embodiment of an interconnection routing diagram for four 6T memory cells.

[0092] Figure 23 This application provides an embodiment of an interconnection routing diagram for four 6T memory cells.

[0093] Figure 24 A layout of a 6T storage cell is provided in an embodiment of this application;

[0094] Figure 25 for Figure 24A cross-sectional view along DD;

[0095] Figure 26 A layout comprising four 6T memory cells is provided for an embodiment of this application;

[0096] Figure 27 A layout of the transistors of four 6T memory cells provided for an embodiment of this application;

[0097] Figure 28 This application provides an embodiment of an interconnection routing diagram for four 6T memory cells.

[0098] Figure 29 A flowchart illustrating a method for fabricating a storage array, as provided in an embodiment of this application;

[0099] Figures 30A-30F This is a process structure diagram showing some steps in the fabrication process of a storage array provided in an embodiment of this application. Detailed Implementation

[0100] The following embodiments of this application will be described in conjunction with the accompanying drawings.

[0101] The technical solutions of this application can be applied to various electronic devices that employ memory. For example, the electronic devices in the embodiments of this application can be mobile phones, tablets, laptops, smart home devices, smart wearable devices (e.g., smartwatches, smart bracelets, smart glasses, smart helmets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, etc. The electronic devices can also be handheld devices with wireless communication capabilities, computing devices or other processing devices connected to a wireless modem, in-vehicle devices, electronic devices in 5G networks, or electronic devices in future evolved public land mobile networks (PLMNs), etc. The embodiments of this application are not limited in this regard.

[0102] like Figure 3The electronic device 100 may include a bus 205 and a system-on-chip (SOC) 210 connected to the bus 205. The SOC 210 can be used to process data, such as processing application data, processing image data, and caching temporary data. In one embodiment, the SOC 210 may include an application processor (AP) 211 for processing applications, a graphics processing unit (GPU) 212 for processing image data, and a first random access memory (RAM) 213 for caching high-speed data. The first RAM 213 may be static random access memory (SRAM) or embedded flash memory (EF Flash), etc. The AP 211, GPU 212, and first RAM 213 may be integrated into a single die or disposed in multiple dies.

[0103] For example Figure 3 As shown, the electronic device 100 may further include a second RAM 220 connected to the SOC 210 via a bus 205. This second RAM 220 may be dynamic random access memory (DRAM). The second RAM 220 can be used to store volatile data, such as temporary data generated by the SOC 210. The storage capacity of the second RAM 220 is typically larger than that of the first RAM 213, but its read speed is typically slower than that of the first RAM 213.

[0104] In addition, the electronic device 100 may also include a communication chip 230 and a power management chip 240 connected to the SOC 210 via a bus 205. The communication chip 230 can be used for protocol stack processing, or for amplifying, filtering, or performing other processing on analog radio frequency signals, or simultaneously performing the above functions. The power management chip 240 can be used to supply power to other chips. In one embodiment, the SOC 210 and the second RAM 220 can be packaged in a single package structure, such as using 2.5D (dimensional) or 3D packaging, to achieve faster inter-chip data transfer rates and reduce chip footprint.

[0105] like Figure 4 As shown, the memory 300 includes a memory array 31 and a controller 32 for accessing the memory array 31, wherein the controller 32 is used to control the read and write operations of the memory array 31.

[0106] in,Figure 4 The storage array 31 and controller 32 shown have a variety of implementable packaging structures, for example, several implementable packaging structures are given below.

[0107] Figure 5A This is one of the packaging structures for the memory array 31 and controller 32 provided in the embodiments of this application. Specifically, the memory array 31 and controller 32 are two independent chips, each integrated on a substrate 33. For example, the memory array 31 and controller 32 can be electrically connected via metal traces laid on the substrate 33. In this structure, since the memory array 31 and controller 32 are two independent chips, the memory array 31 can be referred to as a stand-a-lone memory.

[0108] Figure 5B This is another packaging structure for the storage array 31 and controller 32 provided in the embodiments of this application. In this structure, and the above... Figure 5A Similarly, the memory array 31 and the controller 32 are two independent chips, therefore the memory array 31 can also be referred to as an independent memory. And as described above... Figure 5A The difference is that, in Figure 5B In this configuration, the storage array 31 and the controller 32 are stacked together. For example, the storage array 31 and the controller 32 can be connected through a through-silicon via (TSV) or a redistribution layer (RDL).

[0109] Figure 5C This is yet another packaging structure for the storage array 31 and controller 32 provided in the embodiments of this application. In this example structure, the storage array 31 and controller 32 are integrated into the same chip 3, which is integrated on the substrate 33. Therefore, the storage array 31 can be referred to as an embedded memory.

[0110] In the above Figure 5C In the structure shown, the controller 32 can be integrated on the substrate via a front-end of line (FEOL) process, while the interconnects and memory array are integrated onto the controller 32 via a back-end of line (BEOL) process. The controller can generate control signals, which can be read / write control signals used to control read / write operations on data in the memory array. Alternatively, the controller may include analog circuitry, such as a sensitive amplifier.

[0111] In one embodiment, the storage array 31 in the memory may include Figure 6The diagram shows multiple arrays of storage cells 400, each capable of storing 1 bit or more bits of data. The storage array 31 may also include word lines (WL) and bit lines (BL). Each storage cell 400 is electrically connected to a corresponding word line (WL) and bit line (BL). Different storage cells 400 can be electrically connected via word lines (WL) and bit lines (BL). One or more of the aforementioned word lines (WL) and bit lines (BL) are used to select the storage cell 400 to be read or written in the storage array by receiving a control level output from a control circuit, thereby realizing data read and write operations.

[0112] The controller 32 in the memory may include Figure 6 The circuit structure shown includes one or more of the following: decoder 320, driver 330, timing controller 340, buffer 350, or input / output driver 360.

[0113] exist Figure 6 In the memory 300 structure shown, decoder 320 decodes the received address to determine the memory cell 400 to be accessed. Driver 330 controls the level of signal lines based on the decoding result generated by decoder 320, thereby enabling access to the specified memory cell 400. Buffer 350 buffers read data, for example, using first-in-first-out (FIFO). Timing controller 340 controls the timing of buffer 350 and controls driver 330 to drive the signal lines in memory array 31. Input / output driver 360 drives transmission signals, such as driven received data signals and driven data signals to be sent, enabling long-distance transmission of data signals.

[0114] The aforementioned memory array 31, decoder 320, driver 330, timing controller 340, buffer 350 and input / output driver 360 can be integrated into one chip or into multiple chips respectively.

[0115] In some examples, memory 300 may be electrically connected to the processor, and the memory is used to store data generated by the processor.

[0116] In some examples, the memory involved in the embodiments of this application may include static random access memory or dynamic random access memory.

[0117] Static Random Access Memory (SRAM) is an important component of logic devices and uses transistor latches to store data. Compared to other types of memory, SRAM has a smaller capacity in the same area but is significantly faster. Therefore, SRAM is often used in L1 and L2 caches.

[0118] For example, see Figure 7 As shown, a memory cell in a static random access memory array can include 6 field-effect transistors (Oxide semiconductor based Field-Effect Transistor, OS-FET), which can be referred to as a 6T memory cell.

[0119] In other examples, a memory cell can be a 4T memory cell, a 5T memory cell, a 7T memory cell, an 8T memory cell, a 9T memory cell, or a 10T memory cell, or a memory cell that includes more field-effect transistors.

[0120] See you later Figure 7 At least two of the plurality of transistors are used to form a pass gate (PG) transistor, and the remaining transistors are used to form at least two inverters, which together form the transistor latch. Each inverter includes a pull-up (PU) transistor and a pull-down (PU) transistor.

[0121] In a memory cell, each transistor T includes a first terminal, a second terminal, and a gate. One of the first and second terminals is, for example, the drain, and the other is, for example, the source. The specific configuration depends on the type of transistor T.

[0122] In some examples, such as Figure 8 As shown, the memory array includes multiple word lines WL, multiple first bit lines BL, multiple second bit lines BLB, multiple first power lines VDD, and multiple second power lines VSS. The first voltage signal transmitted by the first power line VDD is, for example, a DC high-level signal, and the second voltage signal transmitted by the second power line VSS is, for example, a DC low-level signal.

[0123] Continue reading Figure 8Each memory cell may contain multiple transistors T, including a first pull-up transistor PU1, a first pull-down transistor PD1, a second pull-up transistor PU2, a second pull-down transistor PD2, a first gating transistor PG1, and a second gating transistor PG2. For example, the first pull-up transistor PU1 and the second pull-up transistor PU2 are both P-type transistors, and the first pull-down transistor PD1, the second pull-down transistor PD2, the first gating transistor PG1, and the second gating transistor PG2 are all N-type transistors.

[0124] The first pull-up transistor PU1 and the first pull-down transistor PD1 form an inverter, and the second pull-up transistor PU2 and the second pull-down transistor PD2 form another inverter.

[0125] Figure 7 and Figure 8 In the example, word line WL, first bit line BL, and second bit line BLB can be called signal lines. For example, first bit line BL can be called the first signal line, second bit line BLB can be called the second signal line, and word line WL can be called the third signal line.

[0126] Figure 7 and Figure 8 In the example, the first pull-up transistor PU1 can be referred to as the first transistor, the first pull-down transistor PD1 can be referred to as the second transistor, the second pull-up transistor PU2 can be referred to as the third transistor, the second pull-down transistor PD2 can be referred to as the fourth transistor, the first gating transistor PG1 can be referred to as the fifth transistor, and the second gating transistor PG2 can be referred to as the sixth transistor.

[0127] The first transistor and the second transistor are coupled in series between the first power line and the second power line; the third transistor and the fourth transistor are coupled in series between the first power line and the second power line.

[0128] The series coupling point of the first transistor and the second transistor is connected to the fifth transistor. The fifth transistor is also connected to the first signal line and the third signal line. The series coupling point of the third transistor and the fourth transistor is connected to the sixth transistor. The sixth transistor is also connected to the second signal line and the third signal line.

[0129] like Figure 7 and Figure 8 As shown, the gates of the first select transistor PG1 and the second select transistor PG2 are both electrically connected to the word line WL. The gates of the first select transistor PG1 and the second select transistor PG2 can receive the same electrical signal.

[0130] The first terminal of the first selector transistor PG1 is electrically connected to the first bit line BL, and the first terminal of the second selector transistor PG2 is electrically connected to the second bit line BLB.

[0131] The second terminal of the first gate transistor PG1 is electrically connected to the second terminal of the first pull-up transistor PU1 and the second terminal of the first pull-down transistor PD1 to form the first data storage node Q.

[0132] The second terminal of the second gate transistor PG2 is electrically connected to the second terminal of the second pull-up transistor PU2 and the second terminal of the second pull-down transistor PD2 to form the second data storage node QB.

[0133] The first terminal of the first pull-up transistor PU1 and the first terminal of the second pull-up transistor PU2 are both electrically connected to the first power line VDD, and the first terminal of the first pull-down transistor PD1 and the first terminal of the second pull-down transistor PD2 are both electrically connected to the second power line VSS.

[0134] The first data storage node Q is also electrically connected to the gate of the second pull-up transistor PU2 and the gate of the second pull-down transistor PD2, and the second data storage node QB is also electrically connected to the gate of the first pull-up transistor PU1 and the gate of the first pull-down transistor PD1, so that the two inverters are cross-coupled.

[0135] by Figure 7 Using the equivalent circuit diagram shown as an example, the reading and writing processes of the above-mentioned memory unit are illustrated.

[0136] For example, when the voltage of the first data storage node Q is high and the voltage of the second data storage node QB is low, the corresponding stored data is "1"; when the voltage of the first data storage node Q is low and the voltage of the second data storage node QB is high, the corresponding stored data is "0".

[0137] Reading Process: Taking the data stored in the memory cell as "0" as an example, a high voltage is applied to the word line WL, and the first bit line BL and the second bit line BLB are pre-charged, both with a high voltage applied. The first selection transistor PG1 and the second selection transistor PG2 are turned on under the control of the electrical signal transmitted through the word line WL. The first pull-up transistor PU1 is turned off under the control of the second data storage node QB, the first pull-down transistor PD1 is turned on under the control of the second data storage node QB, the second pull-up transistor PU2 is turned on under the control of the first data storage node QB, and the second pull-down transistor PD2 is turned off under the control of the first data storage node QB. At this time, the voltage of the second bit line BLB remains unchanged, while the voltage of the first bit line BL drops, creating a voltage difference between the first bit line BL and the second bit line BLB. This voltage difference can be output through a differential amplifier or similar structure to complete the data reading.

[0138] Write process: Taking the current data stored in the memory cell as "0" as an example, a high voltage is applied to the word line WL, and the first bit line BL and the second bit line BLB are pre-charged. A high voltage is applied to the first bit line BL, and a low voltage is applied to the second bit line BLB. The first select transistor PG1 and the second select transistor PG2 are turned on under the control of the electrical signal transmitted through the word line WL. The first pull-up transistor PU1 is turned off under the control of the second data storage node QB, and the first pull-down transistor PD1 is turned on under the control of the second data storage node QB. Due to the low voltage signal on the second bit line BLB, the voltage of the second data storage node QB drops, which in turn causes the first pull-up transistor PU1 to turn on and the first pull-down transistor PD1 to turn off. At this time, the voltage of the first data storage node QB rises, the second pull-up transistor PU2 turns off, and the second pull-down transistor PD2 turns on. The voltages of the two data storage nodes reverse, completing the data writing process.

[0139] like Figure 7 and Figure 8 As shown, when a memory cell contains at least four transistors, the interconnection routing inside the memory cell becomes more complex, as do the interconnection routing between different memory cells, thus making the interconnection routing of the entire memory array even more complex.

[0140] Based on this, embodiments of this application provide some feasible process structures to simplify memory array routing and improve memory density.

[0141] like Figure 9 , Figure 10 and Figure 11 As shown, Figure 9 An example layout of a 6T storage cell is shown. Figure 10 yes Figure 9 AA section view, Figure 11 yes Figure 9 BB cross-section.

[0142] like Figure 10 and Figure 11 In the memory cell, each transistor includes a first electrode and a second electrode. For example, one of the first electrode and the other can be a drain and the other can be a source. The first electrode and the second electrode are arranged in a direction perpendicular to the substrate surface, that is, the transistor in the example of this application is a vertical transistor.

[0143] Each transistor also includes a channel layer and a gate. The channel layer is located between the first and second electrodes, and the gate is located on at least one side of the channel layer.

[0144] The relative positional relationship between the gate and the channel layer can vary. For example, if the gate is located on one side of the channel layer, the transistor is a single-gate vertical transistor. Alternatively, if the gate is located on three sides of the channel layer, the transistor is a triple-gate vertical transistor. And so on... Figure 10 and Figure 11 With the gate surrounding the channel layer, this transistor is a gate-all-around field-effect transistor (GAA FET). When the gate surrounds the channel layer, it is beneficial to improve the gate's control over the channel layer and improve the transistor's performance.

[0145] like Figure 10 and Figure 11 The individual transistors in the memory cell are located on the front side of the substrate (which can be referred to as the first side of the substrate). The first electrode of the transistor is formed by heavy doping in the substrate, and the second electrode is located above the first electrode.

[0146] Return to Figure 7 and Figure 8 In this example, the first terminal of the first pull-up transistor PU1 and the first terminal of the second pull-up transistor PU2 are both electrically connected to the first power supply line VDD. The first terminal of the first pull-down transistor PD1 and the first terminal of the second pull-down transistor PD2 are both electrically connected to the second power supply line VSS.

[0147] like Figure 10 In this application example, the first power line VDD, which is electrically connected to the first electrode of the first pull-up transistor PU1, is disposed on the back side of the substrate (which may be referred to as the second side of the substrate), and the second power line VSS, which is electrically connected to the first electrode of the first pull-down transistor PD1, is disposed on the back side of the substrate.

[0148] For example, a first power line VDD is provided on the side of the first pole of the first pull-up transistor PU1 that is away from the second pole, and a second power line VSS is provided on the side of the first pole of the first pull-down transistor PD1 that is away from the second pole.

[0149] like Figure 11 In this application example, the first power line VDD, which is electrically connected to the first electrode of the second pull-up transistor PU2, is disposed on the back side of the substrate (which may be referred to as the second side of the substrate), and the second power line VSS, which is electrically connected to the first electrode of the second pull-down transistor PD2, is disposed on the back side of the substrate.

[0150] For example, a first power line VDD is provided on the side of the first terminal of the second pull-up transistor PU2 that is away from the second terminal, and a second power line VSS is provided on the side of the first terminal of the second pull-down transistor PD2 that is away from the second terminal.

[0151] Combination Figure 10 and Figure 11In the memory array provided in this application, the power lines are not located on the front side of the substrate along with the memory cells; instead, they are located on the back side of the substrate. This simplifies the structure of the interconnects on the front side of the substrate. For example, it eliminates the need to lay metal traces around the memory cells to connect to the heavily doped first electrode. Therefore, the memory array provided in this application utilizes the space on the back side of the substrate to lay the power lines, thereby simplifying the interconnects on the front side of the substrate, increasing the integration density of the memory cells on the front side of the substrate, and increasing the memory capacity.

[0152] like Figure 10 and Figure 11 The power line is located on the side of the first electrode opposite to the second electrode. The arrangement of the power line is relatively simple; for example, it can be fabricated by depositing metal on one side of the first electrode, without posing any challenges to the fabrication process.

[0153] Return to Figure 9 , Figure 9 In the layout shown, the first pull-down transistor PD1 and the second pull-down transistor PD2 are arranged in a first direction (e.g., the X direction), and the second power line VSS can extend along the first direction. The first pull-down transistor PD1 and the second pull-down transistor PD2 can be electrically connected to the same second power line VSS.

[0154] The first pull-up transistor PU1 and the second pull-up transistor PU2 are arranged in a first direction (e.g., the X direction), and the first power line VDD can extend along the first direction. The first pull-up transistor PU1 and the second pull-up transistor PU2 can be electrically connected to the same first power line VDD.

[0155] In some examples, such as Figure 9 The first power line VDD and the second power line VSS are arranged along a second direction (e.g., the Y direction), and the first power line VDD and the second power line VSS can be parallel.

[0156] In this example, the first direction can be perpendicular to the second direction, and both the first and second directions are parallel to the surface of the substrate.

[0157] The second terminal of the first pull-up transistor PU1 is electrically connected to the second terminal of the first pull-down transistor PD1, forming a series coupling point between the first pull-up transistor PU1 and the first pull-down transistor PD1. The second terminal of the first select transistor PG1 is electrically connected to this series coupling point. Figure 10 The second terminal of the first pull-up transistor PU1, the second terminal of the first pull-down transistor PD1, and the second terminal of the first gating transistor PG1 can be electrically connected through the top contact (TCT) to form a data storage node Node Q.

[0158] The second terminal of the second pull-up transistor PU2 is electrically connected to the second terminal of the second pull-down transistor PD2, forming a series coupling point between the second pull-up transistor PU2 and the second pull-down transistor PD2. The second terminal of the second select transistor PG2 is electrically connected to this series coupling point. Figure 11 The second terminal of the second pull-up transistor PU2, the second terminal of the second pull-down transistor PD2, and the second terminal of the second gating transistor PG2 can be electrically connected through the top contact (TCT) to form a data storage node Node QB.

[0159] like Figure 10 Since the gate of the first pull-up transistor PU1 is electrically connected to the gate of the first pull-down transistor PD1, in some processes, the gate can be arranged to surround the channel layer of the first pull-up transistor PU1 and the channel layer of the first pull-down transistor PD1, thereby making the gate of the first pull-up transistor PU1 electrically connected to the gate of the first pull-down transistor PD1.

[0160] like Figure 11 Since the gate of the second pull-up transistor PU2 is electrically connected to the gate of the second pull-down transistor PD2, in some processes, the gate can be arranged to surround the channel layer of the second pull-up transistor PU2 and the channel layer of the second pull-down transistor PD2, thereby making the gate of the second pull-up transistor PU2 electrically connected to the gate of the second pull-down transistor PD2.

[0161] Because the gate coupling point of the first pull-up transistor PU1 and the gate coupling point of the first pull-down transistor PD1 are electrically connected to the series coupling point of the second pull-up transistor PU2 and the second pull-down transistor PD2, as follows: Figure 10 The gates surrounding the first pull-up transistor PU1 and the first pull-down transistor PD1 can be interconnected with the series coupling point of the second pull-up transistor PU2 and the second pull-down transistor PD2 through node contact (NCT) holes.

[0162] Because the gate coupling point of the second pull-up transistor PU2 and the gate coupling point of the second pull-down transistor PD2 are electrically connected to the series coupling point of the first pull-up transistor PU1 and the first pull-down transistor PD1, as follows: Figure 11 The gates surrounding the second pull-up transistor PU2 and the second pull-down transistor PD2 can be interconnected with the series coupling points of the first pull-up transistor PU1 and the first pull-down transistor PD1 through node contact (NCT) holes.

[0163] Return to Figure 9In this example, the first gate transistor PG1, the first pull-down transistor PD1, and the first pull-up transistor PU1 are arranged in sequence in the Y direction, the second pull-down transistor PD2, the second pull-up transistor PU2, and the second gate transistor PG2 are arranged in sequence in the Y direction, and the two inverters are arranged side by side. The first gate transistor PG1 is located on one side of the two inverters, and the second gate transistor PG2 is located on the other side of the two inverters.

[0164] The first terminal of the first selector transistor PG1 is electrically connected to the first bit line BL, and the first terminal of the second selector transistor PG2 is electrically connected to the second bit line BLB.

[0165] Figure 10 and Figure 11 An implementation structure for the first bit line BL and the second bit line BLB is given. In this example, both the first bit line BL and the second bit line BLB are disposed on the back side of the substrate, for example, see [link to example]. Figure 10 The first line BL is located on the side of the first terminal of the first select transistor PG1 that is away from the second terminal, see... Figure 11 The second bit line BLB is located on the side of the first terminal of the second gating transistor PG2 away from the second terminal.

[0166] In some examples, such as Figure 10 and Figure 11 The first power line VDD, the second power line VSS, the first bit line BL, and the second bit line BLB are all located on the back side of the substrate, and the first power line VDD, the second power line VSS, the first bit line BL, and the second bit line BLB are located in the same metal layer, such as the BM1 layer located on the back side of the substrate.

[0167] In some configurations, the first bit line BL and the second bit line BLB extend in parallel directions. The extension directions of the first bit line BL and the second bit line BLB are parallel to the extension directions of the first power line VDD and the second power line VSS. For example, they can both extend along the X-direction, allowing electrical connection of multiple memory cells located in the X-direction.

[0168] See you later Figure 10 and Figure 11 As shown, the gates of the first select transistor PG1 and the second select transistor PG2 are connected to the word line WL, which can be disposed on the front side of the substrate. For example, the word line WL can be disposed on the M1 layer on the front side of the substrate.

[0169] The word line WL can extend along the second direction (Y direction) so as to connect the gate of the first gating transistor PG1 and the gate of the second gating transistor PG2.

[0170] like Figure 10The gate of the first select transistor PG1 can be connected to the word line WL through a gate contact (GCT). For example... Figure 11 The gate of the second gate transistor PG2 can be connected to the word line WL through a gate contact (GCT).

[0171] Figure 12 An exemplary demonstration Figure 9 A 2x2 mosaic layout, Figure 13 What is being shown is Figure 12 The arrangement of multiple electrodes in a transistor. Figure 14 What is being shown is Figure 12 The interconnection method of different transistors.

[0172] like Figure 12 The 2×2 tiled layout includes a first storage unit, a second storage unit, a third storage unit, and a fourth storage unit. The first and second storage units are arranged along a second direction (Y direction), the third and fourth storage units are arranged along a second direction (Y direction), the first and third storage units are arranged along a first direction (X direction), and the second and fourth storage units are arranged along a first direction (X direction).

[0173] The arrangement of the transistors in the first memory cell and the arrangement of the transistors in the second memory cell are mirror-symmetrical about the first reference plane, which is perpendicular to the substrate surface. The first reference plane is as follows: Figure 12 The reference plane MM is shown.

[0174] The arrangement of multiple transistors in the third memory cell and the arrangement of multiple transistors in the fourth memory cell are mirror-symmetrical about the first reference plane MM.

[0175] The arrangement of the transistors in the first memory cell and the arrangement of the transistors in the third memory cell are mirror-symmetrical about the second reference plane, which is perpendicular to the substrate surface. The second reference plane is as follows: Figure 12 The reference plane NN is shown. The reference plane MM is perpendicular to the reference plane NN.

[0176] The arrangement of multiple transistors in the second memory cell and the arrangement of multiple transistors in the fourth memory cell are mirror-symmetric about the reference plane NN.

[0177] The first power line VDD, the second power line VSS, the first bit line BL, and the second bit line BLB all extend along the first direction (X direction) and are electrically connected to multiple memory cells arranged along the first direction (X direction). For example, the first power line VDD is electrically connected to the first terminal of the first pull-up transistor PU1 and the first terminal of the second pull-up transistor PU2 of the multiple memory cells arranged along the first direction (X direction).

[0178] This can mitigate the high resistance and voltage drop issues of multiple memory cells in the first direction, thereby improving memory performance.

[0179] See Figure 13 The first pull-down transistor PD1 and the first pull-up transistor PU1 are arranged in the second direction (Y direction), and their gates can extend along the second direction (Y direction), so that the gates of the first pull-down transistor PD1 and the first pull-up transistor PU1 are electrically connected. The second pull-down transistor PD2 and the second pull-up transistor PU2 are arranged in the second direction (Y direction), and their gates can extend along the second direction (Y direction), so that the gates of the second pull-down transistor PD2 and the second pull-up transistor PU2 are electrically connected.

[0180] Because the arrangement of the transistors in the first memory cell and the arrangement of the transistors in the second memory cell are mirror-symmetrical about the first reference plane, the second selection transistor PG2 in the first memory cell and the second selection transistor PG2 in the second memory cell are close to each other. The gates of the second selection transistor PG2 in both the first and second memory cells need to be electrically connected to the word line WL. Thus, as... Figure 13 The gate of the second gate transistor PG2 and the gate of the second gate transistor PG2 in the second memory cell can be connected together, as shown in the example. Figure 14 The gate contact (GCT) shown is connected to the word line WL.

[0181] The above Figures 9-14 An example is given of one arrangement of the first bit line BL and the second bit line BLB, that is, the first bit line BL and the second bit line BLB are disposed on the back side of the substrate. In some examples, the first power line VDD, the second power line VSS, the first bit line BL and the second bit line BLB are located in the same metal layer, such as the BM1 layer located on the back side of the substrate.

[0182] Figure 15 An exemplary demonstration Figure 9 A 2x2 mosaic layout, Figure 16 What is being shown is Figure 15 The arrangement of multiple electrodes in a transistor. Figure 17 What is being shown is Figure 15The interconnection method of different transistors.

[0183] Figure 15 The 2x2 mosaic layout, and Figure 12 The differences between the 2x2 tiled layout include: Figures 15-17 In the example, the arrangement of the transistors in the first memory cell is the same as that in the second memory cell. The arrangement of the transistors in the third memory cell is the same as that in the fourth memory cell.

[0184] exist Figure 12 In the example, the arrangement of the transistors in the first memory cell and the arrangement of the transistors in the second memory cell are mirror-symmetrical about the reference plane MM, which is perpendicular to the substrate surface. The arrangement of the transistors in the third memory cell and the arrangement of the transistors in the fourth memory cell are also mirror-symmetrical about the reference plane MM.

[0185] exist Figure 15 In the example, since the arrangement of the transistors in the first memory cell is the same as that in the second memory cell, the second selection transistor PG2 in the first memory cell and the first selection transistor PG1 in the second memory cell are close to each other. The gates of both the second selection transistor PG2 in the first memory cell and the first selection transistor PG1 in the second memory cell need to be electrically connected to the word line WL. Thus, as... Figure 17 The gate of the second gate transistor PG2 in the first memory cell and the gate of the first gate transistor PG1 in the second memory cell can be connected to the word line WL through a gate contact (GCT).

[0186] Figure 18 An example is given of another arrangement of the first bit line BL and the second bit line BLB. Figure 19 yes Figure 18 The CC cross-sectional view is shown above. In this example, the process structure of the six transistors and the interconnection structure between the different transistors can be referenced above. Figure 9 Examples will not be repeated here.

[0187] Figure 18 In the example, the first power line VDD and the second power line VSS are located on the back side of the substrate. For example, the first power line VDD and the second power line VSS can be located on the BM1 layer on the back side of the substrate.

[0188] exist Figure 18 and Figure 19In the example, the first bit line BL and the second bit line BLB are located on the front side of the substrate. For example, the first bit line BL and the second bit line BLB can be located in the same metal layer.

[0189] See Figure 19 In this example, the word line WL is located on the front side of the substrate, and the first bit line BL and the second bit line BLB are also located on the front side of the substrate. In some implementations, the first bit line BL and the second bit line BLB can be located on the same metal layer, while the word line WL is located on another metal layer. For example, the first bit line BL and the second bit line BLB are located on the front side of layer M1, and the word line WL is located on the front side of layer M2. Layers M1 and M2 can be stacked in a direction perpendicular to the substrate surface.

[0190] This can be understood as follows: the first bit line BL and the second bit line BLB are located in the first front metal layer, and the word line WL is located in the second front metal layer. The first front metal layer and the second front metal layer are stacked in a direction perpendicular to the substrate surface.

[0191] In some examples, the first bit line BL and the second bit line BLB are set in parallel. The extension direction of the first bit line BL and the second bit line BLB is parallel to the extension direction of the first power line VDD and the second power line VSS.

[0192] See Figure 19 The first terminal of the second select transistor PG2 can be connected to the second bit line BLB in the M1 layer through a conductive via, and the first terminal of the first select transistor PG1 can be connected to the first bit line BL in the M1 layer through a conductive via.

[0193] See Figure 19 A metal trace WL1 can be set in the M1 layer. The gate of the first select transistor PG1 can be connected to the metal trace WL1 in the M1 layer through a gate contact (GCT). The metal trace WL1 is connected to the word line WL in the M2 layer through a conductive via.

[0194] like Figure 19 Metal trace 1 can be provided on the side of the first terminal of the first select transistor PG1 away from the second terminal, or metal trace 2 can be provided on the side of the first terminal of the second select transistor PG2 away from the second terminal. However, metal trace 1 located on the back side of the substrate does not extend in one direction and does not electrically connect different memory cells, thus it cannot have the function of the first bit line (BL). Similarly, metal trace 2 located on the back side of the substrate does not extend in one direction and does not electrically connect different memory cells, thus it cannot have the function of the second bit line (BLB).

[0195] For example, in a plurality of memory cells arranged along the first direction, a metal trace 1 is provided on the side of the first pole of the first gate transistor PG1 of each memory cell that is away from the second pole, and these plurality of metal traces 1 are electrically isolated from each other.

[0196] Figure 20 An exemplary demonstration Figure 18 A 2x2 mosaic layout, Figure 21 What is being shown is Figure 20 The arrangement of multiple electrodes in a transistor. Figure 22 and Figure 23 What is being shown is Figure 20 Interconnection traces of different transistors.

[0197] like Figure 20 The 2×2 tiled layout includes a first storage unit, a second storage unit, a third storage unit, and a fourth storage unit. The first and second storage units are arranged along a second direction (Y direction), the third and fourth storage units are arranged along a second direction (Y direction), the first and third storage units are arranged along a first direction (X direction), and the second and fourth storage units are arranged along a first direction (X direction).

[0198] The arrangement of the transistors in the first memory cell and the arrangement of the transistors in the second memory cell are mirror-symmetrical about the first reference plane, which is perpendicular to the substrate surface. The first reference plane is as follows: Figure 20 The reference plane MM is shown.

[0199] The arrangement of the transistors in the first memory cell and the arrangement of the transistors in the third memory cell are mirror-symmetrical about the second reference plane, which is perpendicular to the substrate surface. The second reference plane is as follows: Figure 20 The reference plane NN is shown. The second reference plane is perpendicular to the first reference plane.

[0200] In this application example, the first bit line BL and the second bit line BLB are located on the front side of the substrate.

[0201] like Figure 21 The first terminal of the first select transistor PG1 can extend to a location where no transistor is present, such as extending to the Q1 region. Figure 22 The bottom contact (BCT) can extend to the Q1 region, thereby bringing out the first electrode of the first select transistor PG1 to connect with the first line BL located on the front side of the substrate.

[0202] For example, see Figure 21 The first terminal of the second gate transistor PG2 can extend to a location where no transistor is present, such as extending to the Q2 region. Figure 22The bottom contact (BCT) can extend to the Q2 region, thereby bringing out the first electrode of the second select transistor PG2 to connect with the second bit line BLB located on the front side of the substrate.

[0203] Figure 24 The example provides another way to arrange the first bit line BL and the second bit line BLB. Figure 25 yes Figure 24 DD cross-sectional view.

[0204] In this example, such as Figure 24 In a memory cell, the first gate transistor PG1, the first pull-down transistor PD1, and the first pull-up transistor PU1 are arranged in sequence in the Y direction, the second pull-down transistor PD2, the second pull-up transistor PU2, and the second gate transistor PG2 are arranged in sequence in the Y direction, the first pull-down transistor PD1 and the second pull-down transistor PD2 are arranged in the X direction, and the first pull-up transistor PU1 and the second pull-up transistor PU2 are arranged in the X direction.

[0205] This can be understood as follows: two inverters are set up side by side, with the first select transistor PG1 set on one side of the two inverters and the second select transistor PG2 set on the other side of the two inverters.

[0206] In this example, the first power line VDD and the second power line VSS are located on the back side of the substrate, and the first bit line BL and the second bit line BLB are also located on the back side of the substrate. For example, see... Figure 25 The first power line VDD and the second power line VSS are located on the back side of the substrate in the BM1 layer, and the first bit line BL and the second bit line BLB are located on the back side of the substrate in the BM2 layer. The BM1 layer and the BM2 layer are stacked in a direction perpendicular to the substrate surface.

[0207] This can be understood as follows: the first power line VDD and the second power line VSS are located in the first back metal layer, and the first bit line BL and the second bit line BLB are located in the second back metal layer. The first back metal layer and the second back metal layer are stacked in a direction perpendicular to the substrate surface.

[0208] In some examples, such as Figure 25 The first back metal layer where the first power line VDD and the second power line VSS are located is closer to the substrate than the second back metal layer where the first bit line BL and the second bit line BLB are located.

[0209] See Figure 25The first power line VDD is located on the side of the first terminal of the first pull-up transistor PU1 that is away from the second terminal, and the second power line VSS is located on the side of the first terminal of the first pull-down transistor PD1 that is away from the second terminal. The first power line VDD and the second power line VSS can extend along a first direction (X direction).

[0210] See Figure 25 The first power line VDD and the second power line VSS are located on the back side of the substrate, M1 layer. The first bit line BL and the second bit line BLB are located on the back side of the substrate, BM2 layer. In some structures, the first terminal of the first select transistor PG1 has a first trace on the side opposite to the second terminal. The first trace can be electrically connected to the first bit line BL through a conductive via. The first terminal of the second select transistor PG2 has a second trace on the side opposite to the second terminal. The second trace can be electrically connected to the second bit line BLB through a conductive via. The first trace and the second trace can be located on the back side of the substrate, BM1 layer.

[0211] See Figure 25 The word line WL is located on the front side of the substrate. For example, the word line WL can be located on the M1 layer on the front side of the substrate.

[0212] Figure 26 An exemplary demonstration Figure 24 A 2x2 mosaic layout, Figure 27 What is being shown is Figure 26 The arrangement of multiple electrodes in a transistor. Figure 28 What is being shown is Figure 26 Interconnection traces of different transistors.

[0213] like Figure 26 The 2×2 tiled layout includes a first storage unit, a second storage unit, a third storage unit, and a fourth storage unit. The first and second storage units are arranged along a second direction (Y direction), the third and fourth storage units are arranged along a second direction (Y direction), the first and third storage units are arranged along a first direction (X direction), and the second and fourth storage units are arranged along a first direction (X direction).

[0214] See Figure 26 Because the second gate transistor PG2 of the first memory cell and the first gate transistor PG1 of the second memory cell are arranged along the first direction (X direction), it is possible to... Figure 25 As shown, the first bit line BL, which is electrically connected to the first gating transistor PG1, and the second bit line BLB, which is electrically connected to the second gating transistor PG2, are disposed on the BM2 layer on the back side of the substrate.

[0215] Storage array adopts Figure 26 and Figure 27 When arranged as shown, the area of ​​each storage unit can be compressed, for example, asFigure 26 This can compress the size of the storage unit in the Y direction, thereby increasing the storage array density and storage capacity.

[0216] Since the gates of the first select transistor PG1 and the second select transistor PG2 are both electrically connected to the word line WL, as Figure 27 and Figure 28 This allows the gate to surround the channel layer of the first gate transistor PG1 and the channel layer of the second gate transistor PG2, and the gate is connected to the word line WL through a gate contact (GCT).

[0217] In the memory cells provided by the above embodiments, the materials that can be selected for each functional layer of transistor Tr, as well as each signal line and each power line, are various. Some of the materials that can be selected are given below.

[0218] Among the optional materials, the second electrode, gate, word line WL, first bit line BL, second bit line BLB, first power line VDD, and second power line VSS of transistor Tr are all conductive materials, such as metallic materials. In optional embodiments, one or more conductive materials selected from TiN (titanium nitride), Ti (titanium), Au (gold), W (tungsten), Mo (molybdenum), In-Ti-O (ITO, indium tin oxide), Al (aluminum), Cu (copper), Ru (ruthenium), and Ag (silver) can be used.

[0219] Among the available materials, the channel layer of the transistor Tr can be selected from one or more semiconductor materials such as Si (silicon), poly-Si (p-Si, polycrystalline silicon), amorphous-Si (a-Si, amorphous silicon), In-Ga-Zn-O (IGZO, zinc gallium oxide), ZnO (zinc oxide), ITO (indium tin oxide), TiO2 (titanium dioxide), MoS2 (molybdenum disulfide), WS2 (tungsten disulfide), graphene, and black phosphorus.

[0220] This application also provides a method for fabricating a storage array, such as... Figure 29 , Figure 29 An exemplary flowchart of a method for fabricating a memory array is shown, the method comprising:

[0221] Step S1: A plurality of memory cells are formed on the first side of the substrate. Each memory cell includes a plurality of transistors. The transistors include a first electrode, a second electrode, and a gate. The first electrode and the second electrode are arranged in a direction perpendicular to the surface of the substrate. The first electrode is located inside the substrate. The plurality of transistors include a first transistor, a second transistor, a third transistor, and a fourth transistor.

[0222] In other words, this application can place the memory cell on the front side of the substrate, and the transistor in the memory cell is a vertical transistor. The first electrode of the vertical transistor can be fabricated by the front-end process, for example, it can be formed in the substrate by a high doping process.

[0223] Step S2: A first power line is provided on the side of the first electrode of the first transistor away from the second electrode, a second power line is provided on the side of the first electrode of the second transistor away from the second electrode, a first power line is provided on the side of the first electrode of the third transistor away from the second electrode, and a second power line is provided on the side of the first electrode of the fourth transistor away from the second electrode; wherein, the first transistor and the second transistor are coupled in series between the first power line and the second power line, and the third transistor and the fourth transistor are coupled in series between the first power line and the second power line.

[0224] This can be understood as follows: some interconnects in a memory cell are located on the back side of the substrate, such as the first power line and the second power line. This simplifies the interconnects on the front side of the substrate, makes full use of the space on the back side of the substrate, and thus increases the integration density of memory cells on the front side of the substrate and increases the storage capacity.

[0225] When a memory array is fabricated using the method described in this application, a memory cell may include four transistors or more transistors, such as a 6T memory cell, an 8T memory cell, or a 10T memory cell. In memory cells with more transistors, power lines may also be disposed on the back side of the substrate.

[0226] In the process flow for obtaining the storage array structure involved in the above embodiments, the following process method can be adopted:

[0227] like Figure 30A Devices are fabricated on the front side of the substrate.

[0228] For example, memory cells are fabricated on the front side of the substrate, each memory cell including at least four transistors; this application uses a 6T memory cell as an example. Figure 30A The image shows a first gating transistor PG1, a first pull-down transistor PD1, and a first pull-up transistor PU1 in a memory cell.

[0229] When fabricating devices on the front side of a substrate, interconnect traces within the memory cells can also be obtained, for example, such as... Figure 30A As shown, word lines WL can be fabricated. For example, word lines WL can be located on the front side of the substrate M1 layer.

[0230] See you later Figure 30A In the memory cell, the first electrode of the transistor is formed by heavy doping in the substrate.

[0231] The first poles of two adjacent transistors can be isolated by a shallow trench isolation layer (STI).

[0232] like Figure 30B The obtained Figure 30A The structure shown is inverted, and the back side of the substrate is thinned.

[0233] For example, the selectivity ratio of silicon substrate and STI can be used to stop at STI.

[0234] like Figure 30C The substrate is etched to expose the first electrode of the transistor.

[0235] For example, by using the selectivity ratio of undoped and heavily doped silicon, undoped silicon is etched into the cross section of heavily doped silicon, exposing the heavily doped silicon and forming a self-aligned trench.

[0236] like Figure 30D Metal silicides were created within the trenches. The metal silicides did not completely fill the trenches.

[0237] like Figure 30E The metal is deposited, causing the trench to be filled with metal.

[0238] like Figure 30F The metal is mechanically ground and then placed on the STI. In this way, the metal layer electrically connected to the first pull-down transistor PD1 and the first pull-up transistor PU1 can serve as a power line.

[0239] use Figures 30A-30F The storage array fabricated by the method shown has power lines located on the back side of the substrate, making full use of the space on the back side of the substrate.

[0240] In addition, the fabrication of power lines located on the back side of the substrate is relatively simple and does not pose any challenges to the process.

[0241] In execution Figure 30F During the process, both the first power line VDD and the second power line VSS extend in a direction parallel to the substrate surface, and the first bit line BL and the second bit line BLB can also extend in a direction parallel to the substrate surface. In this way, in the memory array, not only are the first power line VDD and the second power line VSS located on the back side of the substrate, but the first bit line BL and the second bit line BLB are also located on the back side of the substrate, further simplifying the interconnect routing on the front side of the substrate and further improving the storage density.

[0242] In this example, the first power line VDD and the second power line VSS, as well as the first bit line BL and the second bit line BLB, are located in the same metal layer.

[0243] In other examples, during execution Figure 30AAt that time, the first bit line BL and the second bit line BLB can be produced.

[0244] In this configuration, the first bit line BL and the second bit line BLB can be located in the first front-side metal layer, and the word line WL can be located in the second front-side metal layer. The first and second front-side metal layers are stacked in a direction perpendicular to the substrate surface. For example, the first bit line BL and the second bit line BLB can be located in the M1 layer on the front side of the substrate, and the word line WL can be located in the M2 layer on the front side of the substrate.

[0245] In some other examples, during execution Figure 30F In this configuration, the first power line VDD and the second power line VSS are located in the first back metal layer, and the first bit line BL and the second bit line BLB can be located in the second back metal layer. For example, the first power line VDD and the second power line VSS are located in the BM1 layer on the back side of the substrate, and the first bit line BL and the second bit line BLB can be located in the BM2 layer on the back side of the substrate.

[0246] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0247] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory array comprising: The application relates to a memory array, comprising: a substrate having opposite first and second sides; a plurality of memory cells on the first side of the substrate; a first power line and a second power line on the second side of the substrate; each of the memory cells comprises a plurality of transistors, each of the transistors comprising a first electrode and a second electrode arranged in a direction perpendicular to the surface of the substrate, and a gate electrode, the first electrode being arranged in the substrate; the plurality of transistors comprises a first transistor and a second transistor, and a third transistor and a fourth transistor; the first transistor and the second transistor are coupled in series between the first power line and the second power line; the third transistor and the fourth transistor are coupled in series between the first power line and the second power line; the first electrode of the first transistor is arranged on a side of the first electrode facing away from the second electrode of the first transistor, and the first electrode of the second transistor is arranged on a side of the first electrode facing away from the second electrode of the second transistor; the first electrode of the third transistor is arranged on a side of the first electrode facing away from the second electrode of the third transistor, and the first electrode of the fourth transistor is arranged on a side of the first electrode facing away from the second electrode of the fourth transistor.

2. The storage array of claim 1, wherein, the first transistor and the third transistor are arranged in a direction parallel to the extension direction of the first power line; the first transistor and the third transistor are electrically connected to the same first power line.

3. The storage array of claim 1 or 2, wherein, the second transistor and the fourth transistor are arranged in a direction parallel to the extension direction of the second power line; the second transistor and the fourth transistor are electrically connected to the same second power line; the first power line and the second power line are parallel to each other; the first power line and the second power line are arranged in a direction perpendicular to the arrangement direction of the second transistor and the fourth transistor.

4. The storage array of any of claims 1-3, wherein, the memory array further comprises a fifth transistor and a sixth transistor; the fifth transistor is electrically connected to the coupling point of the first transistor and the second transistor; the sixth transistor is electrically connected to the coupling point of the third transistor and the fourth transistor; the memory array further comprises a first signal line and a second signal line; the fifth transistor is electrically connected to the first signal line, and the sixth transistor is electrically connected to the second signal line.

5. The storage array of claim 4, wherein, the first signal line and the second signal line are arranged on the second side of the substrate; the first signal line is arranged on a side of the first electrode of the fifth transistor facing away from the second electrode of the fifth transistor; the second signal line is arranged on a side of the first electrode of the sixth transistor facing away from the second electrode of the sixth transistor; the first signal line, the second signal line, the first power line and the second power line are arranged on the same metal layer.

6. The memory array of claim 4 or 5, wherein, the memory array further comprises a third signal line, the fifth transistor is electrically connected to the third signal line, and the sixth transistor is electrically connected to the third signal line; the third signal line is arranged on the first side of the substrate.

7. The storage array of claim 4, wherein, the first signal line and the second signal line are arranged on the first side of the substrate; The storage array further comprises a third signal line, the fifth transistor is electrically connected with the third signal line, the sixth transistor is electrically connected with the third signal line, and the third signal line is located at the first side of the substrate. The first signal line and the second signal line are located at a first front metal layer; The third signal line is located at a second front metal layer; The first front metal layer and the second front metal layer are stacked in a direction perpendicular to the surface of the substrate.

8. The storage array of any one of claims 4-7, wherein, The fifth transistor, the first transistor and the second transistor are arranged in a second direction in sequence; The third transistor, the fourth transistor and the sixth transistor are arranged in the second direction in sequence; The first transistor and the third transistor are arranged in a first direction; The second transistor and the fourth transistor are arranged in the first direction; The first direction and the second direction are both parallel to the surface of the substrate, and the first direction is perpendicular to the second direction.

9. The storage array of claim 8, wherein, The plurality of storage units comprise adjacent first and second storage units; The first and second storage units are arranged in the second direction; The arrangement of the plurality of transistors in the first storage unit and the arrangement of the plurality of transistors in the second storage unit are mirror-symmetrically arranged about a reference surface, the reference surface being perpendicular to the surface of the substrate.

10. The storage array of claim 8, wherein, The plurality of storage units comprise adjacent first and second storage units; The first and second storage units are arranged in the second direction; The arrangement of the plurality of transistors in the first storage unit and the arrangement of the plurality of transistors in the second storage unit are the same.

11. The storage array of claim 4, wherein, The first signal line and the second signal line are located at a second side of the substrate; The first power supply line and the second power supply line are located at a first back metal layer; The first signal line and the second signal line are located at a second back metal layer; The first back metal layer and the second back metal layer are stacked in a direction perpendicular to the surface of the substrate.

12. The storage array of claim 11, wherein, The second back metal layer is farther away from the substrate than the first back metal layer; The first pole of the fifth transistor away from the second pole has a first trace, the first trace is connected with the first signal line located at the second back metal layer through a conductive via hole penetrating through a dielectric layer, and the first trace is located at the first back metal layer; The first pole of the sixth transistor away from the second pole has a second trace, the first trace is connected with the second signal line located at the second back metal layer through a conductive via hole penetrating through a dielectric layer, and the second trace is located at the first back metal layer.

13. The storage array of claim 11 or 12, wherein, The storage array further comprises a third signal line, the fifth transistor is electrically connected with the third signal line, the sixth transistor is electrically connected with the third signal line; The third signal line is located at the first side of the substrate.

14. The storage array of any one of claims 11-13, wherein, The fifth transistor, the first transistor and the second transistor are arranged in a second direction in sequence. The third transistor, the fourth transistor and the sixth transistor are arranged in the second direction in sequence. The first transistor and the third transistor are arranged in a first direction. The second transistor and the fourth transistor are arranged in the first direction. The first direction and the second direction are parallel to the substrate surface, and the first direction is perpendicular to the second direction.

15. The storage array of claim 14, wherein, The plurality of storage units comprises a first storage unit and a second storage unit. The first storage unit and the second storage unit are arranged in the second direction. The fifth transistor in the first storage unit and the sixth transistor in the second storage unit are arranged in the first direction.

16. The storage array of any of claims 4-15, wherein, The first signal line, the second signal line, the first power line and the second power line are parallel.

17. A memory, comprising: Comprising: The storage array according to any one of claims 1-16; A controller electrically connected with the storage array, the controller being configured to control reading and writing of the storage array.

18. An electronic device, comprising: Comprising: A processor; The memory according to claim 17, the processor being electrically connected with the memory, the memory being configured to store data generated by the processor.

19. A method of fabricating a memory array, comprising: The preparation method comprises: forming a plurality of storage units on a first side of a substrate, each of the storage units comprising a plurality of transistors, the transistors comprising a first electrode, a second electrode and a gate electrode, the first electrode and the second electrode being arranged in a direction perpendicular to the substrate surface, the first electrode being located in the substrate; the plurality of transistors comprising a first transistor and a second transistor, and a third transistor and a fourth transistor; a first power line is arranged on a side of the first electrode of the first transistor away from the second electrode, a second power line is arranged on a side of the first electrode of the second transistor away from the second electrode, a first power line is arranged on a side of the first electrode of the third transistor away from the second electrode, and a second power line is arranged on a side of the first electrode of the fourth transistor away from the second electrode; wherein the first transistor and the second transistor are coupled in series between the first power line and the second power line, and the third transistor and the fourth transistor are coupled in series between the first power line and the second power line.

20. The preparation method of the storage array according to claim 19, wherein, forming a plurality of storage units on a first side of a substrate, each of the storage units comprising a plurality of transistors, the transistors comprising a first electrode, a second electrode and a gate electrode, the first electrode and the second electrode being arranged in a direction perpendicular to the substrate surface, the first electrode being located in the substrate; the plurality of transistors comprising a first transistor and a second transistor, and a third transistor and a fourth transistor; forming a fifth transistor and a sixth transistor, the series coupling point of the first transistor and the second transistor being electrically connected with the fifth transistor, and the series coupling point of the third transistor and the fourth transistor being electrically connected with the sixth transistor; the preparation method further comprises: A first side of a first electrode of the fifth transistor away from a second electrode forms a first signal line, a first side of a first electrode of the sixth transistor away from a second electrode forms a second signal line, the fifth transistor is electrically connected with the first signal line, the sixth transistor is electrically connected with the second signal line, and the first signal line, the second signal line, the first power supply line and the second power supply line are located in the same metal layer.

21. The method of claim 19, wherein, forming a plurality of memory cells on the first side of the substrate, further comprising: forming a fifth transistor and a sixth transistor, a series coupling point of the first transistor and the second transistor is electrically connected with the fifth transistor, and a series coupling point of the third transistor and the fourth transistor is electrically connected with the sixth transistor; the method further comprises: forming a first signal line and a second signal line on the first side of the substrate, the fifth transistor is electrically connected with the first signal line, and the sixth transistor is electrically connected with the second signal line.

22. The method of claim 21, wherein the method further comprises: the method further comprises: forming a third signal line on the first side of the substrate, the fifth transistor is electrically connected with the third signal line, and the sixth transistor is electrically connected with the third signal line, the first signal line and the second signal line are located in a first front metal layer, the third signal line is located in a second front metal layer, and the first front metal layer and the second front metal layer are stacked in a direction perpendicular to a surface of the substrate.

23. The method of claim 19, wherein, forming a plurality of memory cells on the first side of the substrate, further comprising: forming a fifth transistor and a sixth transistor, a series coupling point of the first transistor and the second transistor is electrically connected with the fifth transistor, and a series coupling point of the third transistor and the fourth transistor is electrically connected with the sixth transistor; the method further comprises: forming a second back metal layer on a side of a first back metal layer away from the substrate, the second back metal layer comprising a first signal line and a second signal line, and the first back metal layer comprising the first power supply line and the second power supply line.

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