Backside illumination image sensor fabrication method and backside illumination image sensor

Abstract

The present disclosure relates to a back-illuminated image sensor preparation method and a back-illuminated image sensor, and relates to the technical field of integrated circuits, which comprises the following steps: providing a substrate, forming, on the back surface of the substrate, first semiconductor layers and first initial photosensitive layers which are arranged alternately along a first direction parallel to the back surface and have opposite conductive types; etching the first initial photosensitive layers to obtain first photosensitive layers in the process of forming second semiconductor layers and second photosensitive layers which are arranged alternately along the first direction and have opposite conductive types; the second semiconductor layers are located on the top surfaces of the first semiconductor layers; the second photosensitive layers cover the top surfaces of the first photosensitive layers; and forming third semiconductor layers and third photosensitive layers which are arranged alternately along the first direction and have opposite conductive types. At least the electronic concentration of the photosensitive area can be increased, and the photosensitive performance of the BSI image sensor can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a method for fabricating a back-illuminated image sensor and the back-illuminated image sensor itself. Background Technology

[0002] Back-side illumination (BSI) image sensors are a type of image sensor that offers better performance than front-side illumination image sensors in low-light conditions.

[0003] However, the photosensitivity of BSI image sensors manufactured using existing BSI image sensor fabrication methods cannot meet practical needs. Therefore, improving the photosensitivity of BSI image sensors has become one of the urgent technical problems to be solved. Summary of the Invention

[0004] Therefore, it is necessary to address the technical problem of insufficient light sensitivity of existing BSI image sensors by providing a back-illuminated image sensor fabrication method and a back-illuminated image sensor.

[0005] In a first aspect, this disclosure provides a method for fabricating a back-illuminated image sensor, comprising:

[0006] A substrate is provided, and a first semiconductor layer and a first initial photosensitive stack are formed on the back side of the substrate, which are alternately arranged along a first direction parallel to the back side and have opposite conductivity types.

[0007] During the formation of the second semiconductor layer and the second photosensitive layer, which are alternately arranged along the first direction and have opposite conductivity types, the first initial photosensitive stack is etched to obtain the first photosensitive stack; the second semiconductor layer is located on the top surface of the first semiconductor layer; the second photosensitive layer covers the top surface of the first photosensitive stack.

[0008] A third semiconductor layer and a third photosensitive layer are formed, which are alternately arranged along the first direction and have opposite conductivity types; the third semiconductor layer is located on the top surface of the second semiconductor layer; the third photosensitive layer covers the top surface of the second photosensitive layer; the stacked first semiconductor layer, second semiconductor layer and third semiconductor layer are used to form an isolation pillar, and the stacked first photosensitive layer, second photosensitive layer and third photosensitive layer are used to form a photosensitive layer, and adjacent isolation pillars and photosensitive layers are isolated from each other through a PN junction.

[0009] In the back-illuminated image sensor fabrication method described above, a first semiconductor layer and a first photosensitive layer, arranged alternately along a first direction and with opposite conductivity types, are fabricated simultaneously in the same process steps, and photoelectric isolation is achieved using a PN junction between the first semiconductor layer and the first photosensitive layer; a second semiconductor layer and a second photosensitive layer, arranged alternately along the first direction and with opposite conductivity types, are fabricated simultaneously in the same process steps, and photoelectric isolation is achieved using a PN junction between the second semiconductor layer and the second photosensitive layer; a third semiconductor layer and a third photosensitive layer, arranged alternately along the first direction and with opposite conductivity types, are fabricated simultaneously in the same process steps, and photoelectric isolation is achieved using a PN junction between the third semiconductor layer and the third photosensitive layer; this avoids the process step of separately fabricating the isolation structure, reducing the complexity and cost of the fabrication process.

[0010] Furthermore, the orthographic projection of the top surface of the first photosensitive layer onto the bottom surface of the second photosensitive layer is located inside the bottom surface of the second photosensitive layer; the orthographic projection of the top surface of the second photosensitive layer onto the bottom surface of the third photosensitive layer is located inside the bottom surface of the third photosensitive layer, so that the size of the light receiving surface of the photosensitive layer gradually increases in the direction away from the substrate, which helps to improve the light receiving efficiency of the photosensitive layer.

[0011] Furthermore, the stacked first, second, and third photosensitive layers can each contain different Group 5 elements. Upon photoexcitation, a concentration gradient is generated within these layers. This difference optimizes the transport path of photogenerated carriers, reducing the recombination rate during diffusion. Through the combined effect of these two factors, the quantum efficiency of the photosensitive stack based on this structure is effectively improved. In addition, since pentavalent elements have higher atomic masses than silicon, their mobility is lower during epitaxial growth, leading to uneven doping concentration in a single doped layer. Growing different pentavalent elements in multiple stages can improve the uniformity of doping concentration in the pixel region.

[0012] In some embodiments, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer all contain elements from a third group; the second photosensitive layer and the first photosensitive stack contain different elements from a fifth group; and the second photosensitive layer and the third photosensitive layer contain different elements from a fifth group.

[0013] In some embodiments, the top surface of the first photosensitive stack is not higher than the bottom surface of the second semiconductor layer; the first photosensitive stack includes a first sub-photosensitive layer and a second sub-photosensitive layer located between the first sub-photosensitive layer and the second photosensitive layer; the second sub-photosensitive layer contains different Group V elements from the first sub-photosensitive layer and the second photosensitive layer, respectively.

[0014] In some embodiments, the first sub-photosensitive layer comprises a SiAs layer; the second sub-photosensitive layer comprises a SiP layer; the second photosensitive layer comprises a SiAs layer; the third photosensitive layer comprises a SiSb layer; the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer all comprise a SiB layer; wherein, the SiAs layer is used to characterize silicon materials containing As; the SiP layer is used to characterize silicon materials containing P; the SiSb layer is used to characterize silicon materials containing Sb; and the SiB layer is used to characterize silicon materials containing B.

[0015] In some embodiments, forming a first semiconductor layer and a first initial photosensitive stack arranged alternately along a first direction and having opposite conductivity types includes:

[0016] A first semiconductor material layer is formed on the back side of the substrate;

[0017] A first dielectric layer is formed on the top surface of the first semiconductor material layer;

[0018] A first groove is formed in the first semiconductor material layer and spaced apart along a first direction; the remaining first semiconductor material layer is used to form the first semiconductor layer.

[0019] A first sub-photosensitive layer with a top surface lower than the top surface of the first semiconductor material layer is selectively epitaxially grown in the first groove;

[0020] On the top surface of the first sub-photosensitive layer in the first groove, a second sub-photosensitive layer is selectively epitaxially grown with its top surface higher than the top surface of the first dielectric layer. The first sub-photosensitive layer and the second sub-photosensitive layer are used together to form the first initial photosensitive stack.

[0021] In some embodiments, forming a second semiconductor layer and a second photosensitive layer that are alternately arranged along a first direction and have opposite conductivity types includes:

[0022] A second semiconductor material layer is formed, covering the second sub-photosensitive layer and the first dielectric layer, with its top surface higher than the second sub-photosensitive layer;

[0023] A second dielectric layer is formed on the top surface of the second semiconductor material layer;

[0024] During the process of forming second grooves spaced apart along the first direction in the second semiconductor material layer, the first initial photosensitive stack is etched to obtain the first photosensitive stack; the bottom surface of the second groove is lower than the bottom surface of the first dielectric layer; the remaining second semiconductor material layer is used to form the second semiconductor layer;

[0025] A second photosensitive layer with a top surface not lower than the top surface of the second semiconductor material layer is selectively epitaxially grown in the second groove.

[0026] In some embodiments, a third semiconductor layer and a third photosensitive layer are formed, which are alternately arranged along a first direction and have opposite conductivity types, including:

[0027] A third semiconductor material layer is formed, covering the second photosensitive layer and the second dielectric layer, with its top surface higher than that of the second photosensitive layer;

[0028] A third dielectric layer is formed on the top surface of the third semiconductor material layer;

[0029] A third groove is formed in the third semiconductor material layer, which is spaced apart along the first direction; the bottom surface of the third groove is lower than the bottom surface of the second dielectric layer; the remaining third semiconductor material layer is used to form the third semiconductor layer.

[0030] A third photosensitive layer with a top surface not lower than the top surface of the third semiconductor material layer is selectively epitaxially grown in the third groove;

[0031] The top surfaces of the third photosensitive layer and the third dielectric layer are planarized to make the top surfaces of the remaining third photosensitive layer and the remaining third dielectric layer flush.

[0032] In some embodiments, after forming the third photosensitive layer, the method further includes:

[0033] Planarize the top surface of the third photosensitive layer until the top surface of the remaining third photosensitive layer is flush with the top surface of the third dielectric layer;

[0034] Multiple grids are formed on the top surface of the third dielectric layer at intervals along the first direction, and the grids and photosensitive stacks are arranged alternately along the first direction.

[0035] In some embodiments, the substrate includes a plurality of trench isolation portions spaced apart along a first direction; a plurality of grids are located directly above the plurality of trench isolation portions.

[0036] Secondly, this disclosure provides a back-illuminated image sensor, fabricated using the back-illuminated image sensor fabrication method of any of the foregoing embodiments. The back-illuminated image sensor includes a substrate, a first semiconductor layer, a first photosensitive stack, a second semiconductor layer, a second photosensitive layer, a third semiconductor layer, and a third photosensitive layer. The first semiconductor layer and the first photosensitive stack are located on the back side of the substrate, alternately arranged along a first direction parallel to the back side and with opposite conductivity types. The second semiconductor layer and the second photosensitive layer are alternately arranged along the first direction and with opposite conductivity types. The second semiconductor layer is located on the top surface of the first semiconductor layer. The second photosensitive layer covers the top surface of the first photosensitive stack. The third semiconductor layer and the third photosensitive layer are alternately arranged along the first direction and with opposite conductivity types. The third semiconductor layer is located on the top surface of the second semiconductor layer. The third photosensitive layer covers the top surface of the second photosensitive layer. The stacked first semiconductor layer, second semiconductor layer, and third semiconductor layer are used to form isolation pillars, and the stacked first photosensitive stack, second photosensitive layer, and third photosensitive layer are used to form a photosensitive stack. Adjacent isolation pillars and photosensitive stacks are isolated via PN junctions.

[0037] The back-illuminated image sensor fabrication method and the back-illuminated image sensor disclosed in this embodiment have the following unexpected technical effects:

[0038] In the same process steps, a first semiconductor layer and a first initial photosensitive layer, arranged alternately along a first direction and with opposite conductivity types, are simultaneously fabricated. The PN junction between the first semiconductor layer and the first initial photosensitive layer achieves opto-isolation and avoids signal crosstalk. Similarly, in the same process steps, a second semiconductor layer and a second photosensitive layer, arranged alternately along a first direction and with opposite conductivity types, are simultaneously fabricated. The PN junction between the second semiconductor layer and the second photosensitive layer achieves opto-isolation and avoids signal crosstalk. Furthermore, in the same process steps, a third semiconductor layer and a third photosensitive layer, arranged alternately along a first direction and with opposite conductivity types, are simultaneously fabricated. The PN junction between the third semiconductor layer and the third photosensitive layer achieves opto-isolation and avoids signal crosstalk. This avoids the need for separate fabrication steps for the isolation structure, reducing the complexity and cost of the fabrication process. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0040] Figure 1 This is a schematic flowchart of a back-illuminated image sensor fabrication method provided in one embodiment;

[0041] Figure 2 This is a schematic diagram of the longitudinal cross-section of the semiconductor structure obtained after forming a first dielectric layer on a substrate in step S10 of the back-illuminated image sensor fabrication method provided in one embodiment.

[0042] Figure 3 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a first groove on the substrate in step S10 of the back-illuminated image sensor fabrication method provided in one embodiment.

[0043] Figure 4 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a second sub-photosensitive layer on the substrate in step S10 of the back-illuminated image sensor fabrication method provided in one embodiment.

[0044] Figure 5 This is a schematic diagram of the longitudinal cross-section of the semiconductor structure obtained after forming the second dielectric layer in step S20 of the back-illuminated image sensor fabrication method provided in one embodiment.

[0045] Figure 6This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming the second groove in step S20 of the back-illuminated image sensor fabrication method provided in one embodiment.

[0046] Figure 7 This is a schematic diagram of the longitudinal cross-section of the semiconductor structure obtained after forming the second photosensitive layer in step S20 of the back-illuminated image sensor fabrication method provided in one embodiment.

[0047] Figure 8 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming the third groove in step S30 of the back-illuminated image sensor fabrication method provided in one embodiment.

[0048] Figure 9 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming the third photosensitive layer in step S30 of the back-illuminated image sensor fabrication method provided in one embodiment.

[0049] Figure 10 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a grid in a back-illuminated image sensor fabrication method provided in one embodiment.

[0050] Figure 11 This is a schematic diagram of the longitudinal section of the semiconductor structure obtained after forming a filter in a back-illuminated image sensor fabrication method provided in one embodiment.

[0051] Explanation of reference numerals in the attached figures:

[0052] 10. Substrate; 10a. Back side; 101. Trench isolation portion; 102. Etch stop layer; 103. Interlayer dielectric layer; 21. First semiconductor layer; 211. First semiconductor material layer; 22. First dielectric layer; 30. First groove; 31. First sub-photosensitive layer; 32. Second sub-photosensitive layer; 300. First photosensitive stack; 411. Second semiconductor material layer; 41. Second semiconductor layer; 42. Second dielectric layer; 50. Second groove; 51. Second photosensitive layer; 61. Third semiconductor layer; 62. Third dielectric layer; 70. Third groove; 71. Third photosensitive layer; 80. Grating; 81. First grating material layer; 82. Second grating material layer; 83. Third grating material layer; 90. Filter. Detailed Implementation

[0053] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0055] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0056] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0057] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0058] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the present disclosure.

[0059] In this embodiment of the disclosure, neglecting the flatness of the substrate surface, the direction parallel to the substrate surface is, for example, a first direction, and the direction away from the substrate surface (the thickness direction of the substrate) is, for example, a second direction. In this embodiment of the disclosure, the first direction can be the ox direction, and the second direction can be the oz direction.

[0060] Please refer to Figure 1 In some embodiments, a method for fabricating a back-illuminated image sensor is provided, comprising:

[0061] Step S10: Provide a substrate, and form on the back side of the substrate a first semiconductor layer and a first initial photosensitive stack, which are alternately arranged along a first direction parallel to the back side and have opposite conductivity types;

[0062] Step S20: During the formation of the second semiconductor layer and the second photosensitive layer, which are alternately arranged along the first direction and have opposite conductivity types, the first initial photosensitive stack is etched to obtain the first photosensitive stack; the second semiconductor layer is located on the top surface of the first semiconductor layer; the second photosensitive layer covers the top surface of the first photosensitive stack;

[0063] Step S30: Form a third semiconductor layer and a third photosensitive layer that are alternately arranged along the first direction and have opposite conductivity types; the third semiconductor layer is located on the top surface of the second semiconductor layer; the third photosensitive layer covers the top surface of the second photosensitive layer; the stacked first semiconductor layer, second semiconductor layer and third semiconductor layer are used to form an isolation pillar, and the stacked first photosensitive layer, second photosensitive layer and third photosensitive layer are used to form a photosensitive layer, and adjacent isolation pillars and photosensitive layers are isolated from each other through a PN junction.

[0064] For example, please continue to refer to Figure 1 In the same process steps, a first semiconductor layer and a first photosensitive layer, arranged alternately along a first direction and with opposite conductivity types, are simultaneously fabricated, and opto-isolation is achieved using a PN junction between the first semiconductor layer and the first photosensitive layer; in the same process steps, a second semiconductor layer and a second photosensitive layer, arranged alternately along a first direction and with opposite conductivity types, are simultaneously fabricated, and opto-isolation is achieved using a PN junction between the second semiconductor layer and the second photosensitive layer; in the same process steps, a third semiconductor layer and a third photosensitive layer, arranged alternately along a first direction and with opposite conductivity types, are simultaneously fabricated, and opto-isolation is achieved using a PN junction between the third semiconductor layer and the third photosensitive layer; this avoids the process steps of separately fabricating the isolation structure, reducing the complexity and cost of the fabrication process.

[0065] Please refer to Figure 2 In some embodiments, the provided substrate 10 includes a plurality of trench isolation portions 101 spaced apart along a first direction, such as the ox direction. The material of the trench isolation portions 101 may include, but is not limited to, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (Si2N2O), or combinations thereof.

[0066] As an example, please continue to refer to Figure 2 The trench isolation portion 101 can be used to isolate electrons and light energy. The shape of the longitudinal section (the section parallel to the Zox plane) of the trench isolation portion 101 may include a regular trapezoid, an inverted trapezoid, a rectangle, etc., or a combination of regular trapezoids, inverted trapezoids, rectangles, etc. This disclosure does not impose specific limitations on the shape, material, or size of the trench isolation portion 101, as long as it can isolate electrons, light energy, doped ions, etc. Furthermore, this embodiment does not impose specific limitations on the spacing between adjacent trench isolation portions 101, and it can be set according to actual needs.

[0067] As an example, please continue to refer to Figure 2The substrate 10 can be made of semiconductor material, insulating material, conductive material, or any combination thereof. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates, or II / VI semiconductor substrates. Alternatively, for example, the substrate 10 can be a layered substrate comprising materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator. Therefore, the type of substrate should not limit the scope of this disclosure.

[0068] As an example, please continue to refer to Figure 2 P-type ions, such as boron ions, can be implanted into the substrate 10 by ion implantation to form a P-type substrate, so that a PN junction of a photodiode can be formed between the P-type substrate and the N-type photosensitive stack.

[0069] Please continue to refer to this. Figure 2 In some embodiments, the front side of the trench isolation portion 101 is the surface facing away from the back side of the substrate 10a, and the front side of the trench isolation portion 101 is covered with an etch stop layer 102. The side of the etch stop layer 102 facing away from the trench isolation portion 101 includes an interlayer dielectric layer 103.

[0070] For example, please continue to refer to Figure 2 After forming the etch stop layer 102, metal is deposited to form a partial interconnect structure, and an interlayer dielectric layer 103 is formed on this basis. When the etch stop layer 102 is multilayered, other process problems caused by cracks in a single layer and / or failure of the metal interconnect structure can be avoided. The interlayer dielectric layer 103 can be silicon oxide or other dielectric material layers. In addition, metal interconnect structures can be formed on the interlayer dielectric layer 103 as metal interconnect portions of the device.

[0071] Of course, this embodiment only illustrates one method. As long as the metal interconnect structure can be formed reasonably, the thickness of the etching stop layer 102 and the interlayer dielectric layer 103 is not limited and can be adjusted according to specific process requirements.

[0072] Please continue to refer to this. Figure 2 In some embodiments, after forming a shallow trench (STI) in the substrate 10 and filling the STI with dielectric material, a trench isolation portion 101 can be formed. Subsequently, the substrate 10 can be flipped over, and the back side of the substrate 10 can be thinned and planarized to expose the back side of the trench isolation portion 101, thereby obtaining the back side 10a of the substrate 10.

[0073] For example, please continue to refer to Figure 2 A first semiconductor material layer 211 is epitaxially grown on the back side 10a of a substrate 10 with a flat top surface. The thickness of the first semiconductor material layer 211 can be 50 nanometers to 60 nanometers. For example, the thickness of the first semiconductor material layer 211 can be 50 nanometers, 55 nanometers, or 60 nanometers, etc. The first semiconductor material layer 211 may include a SiB layer, which is used to characterize silicon material doped with boron (B).

[0074] For example, please continue to refer to Figure 2 After forming a first semiconductor material layer 211 on the back side 10a of the substrate 10 using a selective epitaxial growth process, a first dielectric layer 22 is formed on the top surface of the first semiconductor material layer 211. The first dielectric layer 22 is used to protect the first semiconductor material layer 211 from damage during subsequent etching or polishing processes.

[0075] For example, please continue to refer to Figure 2 The thickness of the first dielectric layer 22 can be 1 nm to 2 nm. For example, the thickness of the first dielectric layer 22 can be 1 nm, 1.5 nm, or 2 nm. The material of the first dielectric layer 22 can include silicon oxide.

[0076] Please refer to Figure 3 In some embodiments, step S10, forming a first semiconductor layer 21 and a first photosensitive stack that are alternately arranged along a first direction and have opposite conductivity types, includes: after forming a first patterned photoresist layer (not shown) on the top surface of the first dielectric layer 22, the first patterned photoresist layer includes an opening pattern for defining the shape, position, and size of the first grooves 30; etching the first dielectric layer 22 and the first semiconductor material layer 211 based on the first patterned photoresist layer; and forming a plurality of first grooves 30 spaced apart along the first direction within the first semiconductor material layer 211. The remaining first semiconductor material layer 211 is used to constitute the first semiconductor layer 21.

[0077] Please refer to Figures 3-4 In some embodiments, step S10 further includes: selectively epitaxially growing a first sub-photosensitive layer 31 with a top surface lower than the top surface of the first semiconductor material layer 211 within the first groove 30; selectively epitaxially growing a second sub-photosensitive layer 32 with a top surface higher than the top surface of the first dielectric layer 22 on the top surface of the first sub-photosensitive layer 31 within the first groove 30, wherein the first sub-photosensitive layer 31 and the second sub-photosensitive layer 32 are used to jointly constitute the first photosensitive stack.

[0078] For example, please continue to refer to Figures 3-4 The first sub-photosensitive layer 31 includes a SiAs layer; the second sub-photosensitive layer 32 includes a SiP layer; wherein, the SiAs layer is used to characterize silicon materials containing As; and the SiP layer is used to characterize silicon materials containing P.

[0079] Please refer to Figures 4-7 In some embodiments, step S20, which involves forming a second semiconductor layer 41 and a second photosensitive layer 51 that are alternately arranged along the first direction and have opposite conductivity types, includes:

[0080] Step S21: Form a second semiconductor material layer 411 that covers the entire top surface of the second sub-photosensitive layer 32 and the first dielectric layer 22, and whose top surface is higher than the second sub-photosensitive layer 32;

[0081] Step S22: Form a second dielectric layer 42 on the top surface of the second semiconductor material layer 411;

[0082] Step S23: A second groove 50 is formed in the second semiconductor material layer 411, which is spaced apart along the first direction; the bottom surface of the second groove 50 is lower than the bottom surface of the first dielectric layer 22; the remaining second semiconductor material layer 411 is used to form the second semiconductor layer 41.

[0083] Step S24: Selectively epitaxially grow a second photosensitive layer 51 with a top surface not lower than the top surface of the second semiconductor material layer 411 within the second groove 50.

[0084] For example, please continue to refer to Figure 5 The thickness of the second dielectric layer 42 is less than the thickness of the second semiconductor material layer 411. The second dielectric layer 42 is used to protect the second semiconductor material layer 411 from damage during subsequent etching or polishing processes. The material of the second dielectric layer 42 may include silicon oxide.

[0085] For example, please continue to refer to Figure 6 The dimension of the second groove 50 along the first direction is greater than the dimension of the second sub-photosensitive layer 32 along the first direction; the second groove 50 can expose the entire top surface of the second sub-photosensitive layer 32.

[0086] For example, please continue to refer to Figures 6-7 After forming the second groove 50, a second sub-photosensitive layer 32 is obtained with its top surface not higher than the bottom surface of the first dielectric layer 22. The second sub-photosensitive layer 32 and the first sub-photosensitive layer 31 constitute the first photosensitive stack 300.

[0087] Please refer to Figures 7-9 In some embodiments, step S30, which involves forming a third semiconductor layer 61 and a third photosensitive layer 71 that are alternately arranged along the first direction and have opposite conductivity types, includes:

[0088] Step S31: Form a third semiconductor material layer (not shown) that covers the second photosensitive layer 51 and the second dielectric layer 42, and whose top surface is higher than the second photosensitive layer 51.

[0089] Step S32: Form a third dielectric layer 62 on the top surface of the third semiconductor material layer;

[0090] Step S33: A third groove 70 is formed in the third semiconductor material layer, which is spaced apart along the first direction; the bottom surface of the third groove 70 is lower than the bottom surface of the second dielectric layer 42; the remaining third semiconductor material layer is used to form the third semiconductor layer 61.

[0091] Step S34: Selectively epitaxially grow a third photosensitive layer 71 with a top surface not lower than the top surface of the third semiconductor material layer in the third groove 70;

[0092] Step S35: Planarize the top surface of the third photosensitive layer 71 and the top surface of the third dielectric layer 62 so that the top surfaces of the remaining third photosensitive layer 71 and the remaining third dielectric layer 62 are flush.

[0093] For example, please continue to refer to Figures 7-8 The dimension of the third groove 70 along the first direction is greater than the dimension of the second photosensitive layer 51 along the first direction.

[0094] For example, please continue to refer to Figure 8 The thickness of the third dielectric layer 62 is less than the thickness of the third semiconductor material layer. The third dielectric layer 62 is used to protect the third semiconductor material layer from damage during subsequent etching or polishing processes.

[0095] For example, please continue to refer to Figures 7-9 The orthographic projection of the top surface of the second sub-photosensitive layer 32 onto the bottom surface of the second photosensitive layer 51 is located inside the bottom surface of the second photosensitive layer 51. The orthographic projection of the top surface of the second photosensitive layer 51 onto the bottom surface of the third photosensitive layer 71 is located inside the bottom surface of the third photosensitive layer 71.

[0096] For example, please continue to refer to Figures 8-9 The first semiconductor layer 21, the second semiconductor layer 41, and the third semiconductor layer 61 all contain elements from Group 3; the second photosensitive layer 51 and the second sub-photosensitive layer 32 contain different elements from Group 5; and the second photosensitive layer 51 and the third photosensitive layer 71 contain different elements from Group 5.

[0097] For example, the third group element contained in the first semiconductor layer 21, the second semiconductor layer 41, and the third semiconductor layer 61 can be at least one of boron (B), aluminum (Al), gallium (Ga), indium (In), and thallium (Tl).

[0098] For example, the second photosensitive layer 51, the second sub-photosensitive layer 32, and the third photosensitive layer 71 may contain at least one of the Group V elements: nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi).

[0099] For example, please continue to refer to Figures 8-9The second photosensitive layer 51 contains a SiAs layer; the third photosensitive layer 71 contains a SiSb layer; the first semiconductor layer 21, the second semiconductor layer 41, and the third semiconductor layer 61 all contain a SiB layer; the SiSb layer is used to characterize silicon materials containing Sb; the SiB layer is used to characterize silicon materials containing B.

[0100] Please refer to Figures 9-10 In some embodiments, after forming the third photosensitive layer 71, the following is also included:

[0101] Step S41: Planarize the top surface of the third photosensitive layer 71 until the top surface of the remaining third photosensitive layer 71 is flush with the top surface of the third dielectric layer 62.

[0102] Step S42: A plurality of grids 80 are formed on the top surface of the third dielectric layer 62 at intervals along the first direction, and the grids 80 and the photosensitive stack are arranged alternately along the first direction.

[0103] For example, please continue to refer to Figure 10 The substrate 10 includes a plurality of trench isolation portions 101 spaced apart along a first direction; a plurality of grids are located directly above the plurality of trench isolation portions 101.

[0104] Please continue to refer to this. Figure 10 In some embodiments, after step S41, a grid material stack (not shown) covering the top surface of the third photosensitive layer 71 and the top surface of the third dielectric layer 62 can be formed. The grid material stack includes a first grid material layer 81, a second grid material layer 82, and a third grid material layer 83 sequentially stacked along a second direction away from the substrate. The material of the first grid material layer 81 may include HfO2. The material of the second grid material layer 82 may include TiN. The material of the third grid material layer 83 may include Al.

[0105] Please continue to refer to this. Figures 10-11 In some embodiments, after forming the grid material stack, a fourth patterned photoresist layer (not shown) may be formed on the top surface of the grid material stack. The fourth patterned photoresist layer includes an opening pattern for defining the shape, position and size of the filter 90. The grid material stack is etched based on the fourth patterned photoresist layer to form a plurality of grids 80, wherein the plurality of grids 80 are located directly above the plurality of trench isolation portions 101.

[0106] Please continue to refer to this. Figures 10-11 In some embodiments, after forming the grid 80, the following steps are also included:

[0107] A filter 90 is formed between adjacent grids 80 along a first direction, such as the ox direction.

[0108] For example, please continue to refer to Figure 11The filter 90 includes, but is not limited to, a red filter, a yellow filter, and a blue filter, and the three filters are arranged adjacent to each other as a pixel group. Among them, the red filter transmits red light waves, the yellow filter transmits yellow light waves, and the blue filter transmits blue light waves.

[0109] Please refer to Figure 11 In some embodiments, a back-illuminated image sensor is provided, fabricated using the back-illuminated image sensor fabrication method described in any of the foregoing embodiments. The back-illuminated image sensor includes a substrate 10, a first semiconductor layer 21, a first photosensitive stack 300, a second semiconductor layer 41, a second photosensitive layer 51, a third semiconductor layer 61, and a third photosensitive layer 71. The first semiconductor layer 21 and the first photosensitive stack 300 are located on the back surface 10a of the substrate 10, alternately arranged along a first direction parallel to the back surface 10a, and have opposite conductivity types. The second semiconductor layer 41 and the second photosensitive layer 51 are alternately arranged along the first direction and have opposite conductivity types. Layer 41 is located on the top surface of the first semiconductor layer 21; the second photosensitive layer 51 covers the entire top surface of the first photosensitive stack 300; the third semiconductor layer 61 and the third photosensitive layer 71 are arranged alternately along the first direction and have opposite conductivity types; the third semiconductor layer 61 is located on the top surface of the second semiconductor layer 41; the third photosensitive layer 71 covers the entire top surface of the second photosensitive layer 51; the stacked first semiconductor layer 21, second semiconductor layer 41, and third semiconductor layer 61 are used to form isolation pillars, and the stacked first photosensitive stack 300, second photosensitive layer 51, and third photosensitive layer 71 are used to form photosensitive stacks, and adjacent isolation pillars and photosensitive stacks are isolated by PN junctions.

[0110] Please continue to refer to this. Figures 1-11 The back-illuminated image sensor fabrication method and back-illuminated image sensor in this disclosure embodiment have the following unexpected technical effects:

[0111] In the same process steps, a first semiconductor layer 21 and a first initial photosensitive layer, arranged alternately along the first direction and with opposite conductivity types, are simultaneously fabricated, and opto-isolation is achieved by the PN junction between the first semiconductor layer 21 and the first initial photosensitive layer; in the same process steps, a second semiconductor layer 41 and a second photosensitive layer 51, arranged alternately along the first direction and with opposite conductivity types, are simultaneously fabricated, and opto-isolation is achieved by the PN junction between the second semiconductor layer 41 and the second photosensitive layer 51; in the same process steps, a third semiconductor layer 61 and a third photosensitive layer 71, arranged alternately along the first direction and with opposite conductivity types, are simultaneously fabricated, and opto-isolation is achieved by the PN junction between the third semiconductor layer 61 and the third photosensitive layer 71; this avoids the process steps of separately fabricating the isolation structure, reducing the complexity and cost of the fabrication process.

[0112] Furthermore, the orthographic projection of the top surface of the first photosensitive stack 300 onto the bottom surface of the second photosensitive layer 51 is located within the bottom surface of the second photosensitive layer 51; the orthographic projection of the top surface of the second photosensitive layer 51 onto the bottom surface of the third photosensitive layer 71 is located within the bottom surface of the third photosensitive layer 71, so that the size of the light receiving surface of the photosensitive stack gradually increases in the direction away from the substrate 10, which helps to improve the light receiving efficiency of the photosensitive stack.

[0113] Furthermore, the stacked first photosensitive layer 300, second photosensitive layer 51, and third photosensitive layer 71 can each contain different Group 5 elements. Upon photoexcitation, a concentration gradient is generated within these layers. This difference optimizes the transport path of photogenerated carriers, reducing the recombination rate during diffusion. Under the combined effect of these two factors, the quantum efficiency of the photosensitive stack based on this structure is effectively improved. In addition, since pentavalent elements have higher atomic masses than silicon, their mobility is lower during epitaxial growth, leading to uneven doping concentration in a single doped layer. Growing pentavalent elements with different dopants multiple times can improve the uniformity of doping concentration in the pixel region.

[0114] It should be understood that, although Figure 1 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0115] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0116] The embodiments described above are merely illustrative of several implementation methods of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these modifications and improvements all fall within the scope of protection of this disclosure.

Claims

1. A method for fabricating a back-illuminated image sensor, characterized in that, include: P-type substrates are provided; A first semiconductor layer and a first initial photosensitive stack are formed on the back side of the substrate, which are alternately arranged and have opposite conductivity types along a first direction parallel to the back side; During the formation of the second semiconductor layer and the second photosensitive layer, which are alternately arranged along the first direction and have opposite conductivity types, the first initial photosensitive stack is etched to obtain the first photosensitive stack. The second semiconductor layer is located on the top surface of the first semiconductor layer; The second photosensitive layer covers the top surface of the first photosensitive stack; A third semiconductor layer and a third photosensitive layer are formed, which are alternately arranged along the first direction and have opposite conductivity types; the third semiconductor layer is located on the top surface of the second semiconductor layer; the third photosensitive layer covers the top surface of the second photosensitive layer; the stacked first semiconductor layer, second semiconductor layer and third semiconductor layer are all P-type and are used to form isolation pillars; the stacked first photosensitive layer, second photosensitive layer and third photosensitive layer are all N-type and are used to form photosensitive layers; the adjacent isolation pillars and photosensitive layers are used to jointly form a PN junction for isolation.

2. The method for fabricating a back-illuminated image sensor according to claim 1, characterized in that, The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer all contain elements from a third main group. The second photosensitive layer and the first photosensitive stack contain different Group 5 elements; The second photosensitive layer and the third photosensitive layer contain different Group 5 elements.

3. The method for fabricating a back-illuminated image sensor according to claim 1, characterized in that, The top surface of the first photosensitive layer is not higher than the bottom surface of the second semiconductor layer; The first photosensitive stack includes a first sub-photosensitive layer and a second sub-photosensitive layer located between the first sub-photosensitive layer and the second photosensitive layer; The second sub-photosensitive layer contains different Group 5 elements from the first sub-photosensitive layer and the second photosensitive layer, respectively.

4. The method for fabricating a back-illuminated image sensor according to claim 3, characterized in that, The first sub-photosensitive layer comprises a SiAs layer; the second sub-photosensitive layer comprises a SiP layer; the second photosensitive layer comprises a SiAs layer; the third photosensitive layer comprises a SiSb layer; the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer all comprise a SiB layer; The SiAs layer is used to characterize silicon materials containing As; the SiP layer is used to characterize silicon materials containing P; the SiSb layer is used to characterize silicon materials containing Sb; and the SiB layer is used to characterize silicon materials containing B.

5. The method for fabricating a back-illuminated image sensor according to any one of claims 1-4, characterized in that, Forming a first semiconductor layer and a first initial photosensitive stack with alternating arrangements of opposite conductivity types along the first direction includes: A first semiconductor material layer is formed on the back side of the substrate; A first dielectric layer is formed on the top surface of the first semiconductor material layer; A first groove is formed in the first semiconductor material layer and spaced apart along the first direction; the remaining first semiconductor material layer is used to form the first semiconductor layer. A first sub-photosensitive layer with a top surface lower than the top surface of the first semiconductor material layer is selectively epitaxially grown in the first groove; On the top surface of the first sub-photosensitive layer within the first groove, a second sub-photosensitive layer is selectively epitaxially grown with its top surface higher than that of the first dielectric layer. The first sub-photosensitive layer and the second sub-photosensitive layer together constitute the first initial photosensitive stack.

6. The method for fabricating a back-illuminated image sensor according to claim 5, characterized in that, Forming a second semiconductor layer and a second photosensitive layer that are alternately arranged along the first direction and have opposite conductivity types includes: A second semiconductor material layer is formed that covers the second sub-photosensitive layer and the first dielectric layer, and whose top surface is higher than the second sub-photosensitive layer; A second dielectric layer is formed on the top surface of the second semiconductor material layer; During the process of forming second grooves spaced apart along the first direction in the second semiconductor material layer, the first initial photosensitive stack is etched to obtain the first photosensitive stack; the bottom surface of the second groove is lower than the bottom surface of the first dielectric layer; the remaining second semiconductor material layer is used to form the second semiconductor layer; A second photosensitive layer with a top surface not lower than the top surface of the second semiconductor material layer is selectively epitaxially grown in the second groove.

7. The method for fabricating a back-illuminated image sensor according to claim 6, characterized in that, Forming a third semiconductor layer and a third photosensitive layer that are alternately arranged along the first direction and have opposite conductivity types includes: A third semiconductor material layer is formed that covers the second photosensitive layer and the second dielectric layer, and whose top surface is higher than the second photosensitive layer; A third dielectric layer is formed on the top surface of the third semiconductor material layer; A third groove is formed in the third semiconductor material layer, which is spaced apart along the first direction; the bottom surface of the third groove is lower than the bottom surface of the second dielectric layer; the remaining third semiconductor material layer is used to form the third semiconductor layer. A third photosensitive layer with a top surface not lower than the top surface of the third semiconductor material layer is selectively epitaxially grown within the third groove; The top surfaces of the third photosensitive layer and the third dielectric layer are planarized to make the top surfaces of the remaining third photosensitive layer and the remaining third dielectric layer flush.

8. The method for fabricating a back-illuminated image sensor according to claim 7, characterized in that, After forming the third photosensitive layer, the method further includes: The top surface of the third photosensitive layer is planarized until the top surface of the remaining third photosensitive layer is flush with the top surface of the third dielectric layer. A plurality of grids are formed on the top surface of the third dielectric layer at intervals along the first direction, and the grids and the photosensitive stack are arranged alternately along the first direction.

9. The method for fabricating a back-illuminated image sensor according to claim 8, characterized in that, The substrate includes a plurality of trench isolation portions spaced apart along the first direction; The plurality of grilles are located directly above the plurality of trench isolation sections.

10. A back-illuminated image sensor, characterized in that, The back-illuminated image sensor is fabricated using the method described in any one of claims 1-9. The back-illuminated image sensor includes a P-type substrate, a first semiconductor layer, a first photosensitive stack, a second semiconductor layer, a second photosensitive layer, a third semiconductor layer, and a third photosensitive layer. The first semiconductor layer and the first photosensitive stack are located on the back side of the substrate, and are arranged alternately along a first direction parallel to the back side and have opposite conductivity types; The second semiconductor layer and the second photosensitive layer are arranged alternately along the first direction and have opposite conductivity types; the second semiconductor layer is located on the top surface of the first semiconductor layer; The second photosensitive layer covers the top surface of the first photosensitive stack; The third semiconductor layer and the third photosensitive layer are arranged alternately along the first direction and have opposite conductivity types; the third semiconductor layer is located on the top surface of the second semiconductor layer; the third photosensitive layer covers the top surface of the second photosensitive layer; the stacked first semiconductor layer, second semiconductor layer, and third semiconductor layer are all P-type and are used to form isolation pillars; the stacked first photosensitive layer, second photosensitive layer, and third photosensitive layer are all N-type and are used to form photosensitive layers; the adjacent isolation pillars and photosensitive layers are used to jointly form a PN junction for isolation.

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