Semiconductor device and manufacturing method thereof

Abstract

Semiconductor devices and methods of manufacture are provided. In some embodiments, the disclosed semiconductor device includes a memory array structure and a peripheral circuit structure connected to the memory array structure. The memory array structure includes: a transistor layer including a plurality of arrays of vertical transistors; a storage layer including a plurality of arrays of capacitors coupled with the vertical transistors; a plurality of bit lines coupled to the vertical transistors; and a first interconnect layer including a first interconnect structure connected to the plurality of bit lines and a second interconnect structure separated from the plurality of bit lines and connected to a common electrical node. The peripheral circuit structure includes a second interconnect layer including a third interconnect structure connected to the first interconnect structure, and a sense amplifier circuit connected to the third interconnect structure.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor technology, and more specifically to semiconductor devices and methods of manufacturing the same. Background Technology

[0002] Through improvements in process technology, circuit design, programming algorithms, and manufacturing processes, planar memory cells have been shrunk to even smaller sizes. However, as the feature size of memory cells approaches its lower limit, planar processes and manufacturing technologies become challenging and costly. As a result, the memory density of planar memory cells is approaching its upper limit.

[0003] Three-dimensional (3D) storage architectures can address the density limitations of planar storage cells. A 3D storage architecture includes a storage array and peripheral circuitry to facilitate the operation of the storage array. Summary of the Invention

[0004] One aspect of this disclosure provides a semiconductor device comprising: a memory array structure including: a transistor layer including a plurality of arrays of vertical transistors; a storage layer including a plurality of arrays of capacitors coupled to the vertical transistors; a plurality of bit lines coupled to the vertical transistors; and a first interconnect layer including a first interconnect structure connected to the plurality of bit lines and a second interconnect structure separated from the plurality of bit lines and connected to a common electrical node; and a peripheral circuit structure connected to the memory array structure, including: a second interconnect layer including a third interconnect structure connected to the first interconnect structure; and a sense amplifier circuit connected to the third interconnect structure.

[0005] In some embodiments, the second interconnect layer further includes a fourth interconnect structure, separate from the sense amplifier circuit and the first interconnect structure, and connected to the common electrical node.

[0006] In some implementations, the first interconnect structure is connected between bit lines of adjacent arrays of vertical transistors.

[0007] In some embodiments, the first interconnect structure includes: a plurality of first conductive lines arranged along a first lateral direction, each first conductive line extending along a second lateral direction and coupled to a corresponding bit line among the bit lines through a bit line contact structure.

[0008] In some embodiments, adjacent first conductive lines have different first lengths along the second transverse direction.

[0009] In some embodiments, the second interconnect structure includes: a plurality of second conductive lines arranged along the first lateral direction and connected to a common conductive line extending along the first lateral direction, wherein each second conductive line extends along the second lateral direction and is aligned with a corresponding first conductive line among the first conductive lines.

[0010] In some embodiments, adjacent second conductive lines have different second lengths along the second transverse direction.

[0011] In some embodiments, the first interconnect layer includes at least two layers of conductive lines; and the first interconnect structure and the second interconnect structure are portions of the at least two layers of conductive lines.

[0012] In some embodiments, the second interconnect layer includes at least two layers of conductive lines; and the third interconnect structure and the fourth interconnect structure are portions of the at least two layers of conductive lines.

[0013] In some embodiments, the memory array structure further includes: a first bit line contact structure located on a first side of the corresponding array of vertical transistors and in contact with the odd-numbered bit lines of the corresponding array of vertical transistors; and a second bit line contact structure located on a second side of the corresponding array of vertical transistors opposite to the first side and in contact with the even-numbered bit lines of the corresponding array of vertical transistors.

[0014] Another aspect of this disclosure provides a semiconductor device comprising: a vertical transistor; bit lines coupled to the vertical transistor; a first interconnect structure including: first conductive lines arranged along a first lateral direction, each first conductive line extending along a second lateral direction and connected to a corresponding bit line among the bit lines; and second conductive lines arranged along the first lateral direction, each second conductive line extending along the second lateral direction and connected to a common electrical node and separated from the bit lines; and a sense amplifier circuit connected to the plurality of bit lines via the first conductive lines.

[0015] In some embodiments, the semiconductor device further includes a second interconnect structure comprising: a third conductive line connected between the first conductive line and the sense amplifier circuit; and a fourth conductive line connected to the common electrical node and separate from the sense amplifier circuit and the first interconnect structure.

[0016] In some implementations, the first interconnect structure is connected between bit lines of adjacent arrays of vertical transistors.

[0017] In some embodiments, each first conductive line is aligned with a corresponding second conductive line in the second conductive line along the second lateral direction.

[0018] In some embodiments, adjacent first conductive lines have different first lengths along the second transverse direction.

[0019] In some embodiments, the second conductive line is connected to a common conductive line extending along the first transverse direction.

[0020] In some embodiments, adjacent second conductive lines have different second lengths along the second transverse direction.

[0021] In some embodiments, the first conductive line and the second conductive line are distributed in at least two conductive wiring layers along a vertical direction.

[0022] In some embodiments, the third conductive line and the fourth conductive line are distributed in at least two conductive wiring layers along a vertical direction.

[0023] In some embodiments, the semiconductor device further includes: a first bit line contact structure located on a first side of a corresponding array of vertical transistors and in contact with the odd-numbered bit lines of the corresponding array of vertical transistors; and a second bit line contact structure located on a second side of the corresponding array of vertical transistors opposite to the first side and in contact with the even-numbered bit lines of the corresponding array of vertical transistors.

[0024] Another aspect of this disclosure provides a method for forming a semiconductor device, the method comprising: forming a memory array structure, including: forming a transistor layer including a plurality of arrays of vertical transistors; forming a memory layer including a plurality of arrays of capacitors coupled to the vertical transistors; forming a plurality of bit lines coupled to the vertical transistors; and forming a first interconnect layer including a first interconnect structure connected to the plurality of bit lines and a second interconnect structure separated from the plurality of bit lines and coupled to a first common electrical node; forming a peripheral circuit structure, including: forming a second interconnect layer including a third interconnect structure; and forming a sense amplifier circuit connected to the third interconnect structure; and connecting the peripheral circuit structure to the memory array structure such that the third interconnect structure is coupled to the first interconnect structure.

[0025] In some embodiments, forming the second interconnect layer further includes forming a fourth interconnect structure, the fourth interconnect structure being separate from the sense amplifier circuit and the first interconnect structure and connected to a second common electrical node; and connecting the peripheral circuit structure to the memory array structure includes connecting the first common electrical node to the second common electrical node.

[0026] In some implementations, forming the first interconnect layer includes connecting the first interconnect structure between bit lines of adjacent arrays of vertical transistors.

[0027] In some embodiments, forming the first interconnect layer includes forming a plurality of first conductive lines arranged along a first lateral direction, each first conductive line extending along a second lateral direction and coupled to a corresponding bit line among the bit lines through a bit line contact structure.

[0028] In some embodiments, forming the plurality of first conductive lines includes forming adjacent first conductive lines having different first lengths along the second transverse direction.

[0029] In some embodiments, forming the second interconnect structure includes forming a plurality of second conductive lines arranged along the first lateral direction and connected to a common conductive line extending along the first lateral direction, wherein each second conductive line extends along the second lateral direction and is aligned with a corresponding first conductive line among the first conductive lines.

[0030] In some embodiments, forming the plurality of second conductive lines includes forming adjacent second conductive lines having different second lengths along the second transverse direction.

[0031] In some embodiments, forming the first interconnect layer includes forming at least two layers of conductive lines, wherein the first interconnect structure and the second interconnect structure are portions of the at least two layers of conductive lines.

[0032] In some embodiments, forming the second interconnect layer includes forming at least two layers of conductive lines, wherein the third interconnect structure and the fourth interconnect structure are portions of the at least two layers of conductive lines.

[0033] In some embodiments, forming the memory array structure further includes: forming a first bit line contact structure located on a first side of the corresponding array of vertical transistors and in contact with the odd-numbered bit lines of the corresponding array of vertical transistors; and forming a second bit line contact structure located on a second side of the corresponding array of vertical transistors opposite to the first side and in contact with the even-numbered bit lines of the corresponding array of vertical transistors. Attached Figure Description

[0034] The accompanying drawings, which are incorporated herein and form part of this specification, illustrate embodiments of the present disclosure and, together with the specification, further serve to explain the principles of the present disclosure and enable those skilled in the art to make and use the present disclosure.

[0035] Figure 1A schematic circuit diagram of a memory device including an array of memory cells according to some embodiments of the present disclosure is shown, each memory cell having a vertical transistor.

[0036] Figure 2 A schematic layout diagram of a memory chip according to some embodiments of the present disclosure is shown.

[0037] Figure 3A A schematic top view of a portion of a repository according to some embodiments of this disclosure is shown.

[0038] Figure 3B A schematic top view of a portion of a repository according to some embodiments of this disclosure is shown.

[0039] Figure 4 A schematic top view of a portion of a repository according to some embodiments of this disclosure is shown.

[0040] Figure 5 A schematic side cross-sectional view of a portion of a repository according to some embodiments of this disclosure is shown.

[0041] Figure 6 A schematic side cross-sectional view of a portion of a repository according to some embodiments of this disclosure is shown.

[0042] Figure 7 A schematic side cross-sectional view of a portion of a repository according to some embodiments of this disclosure is shown.

[0043] Figure 8 A schematic top view of a portion of a repository according to some embodiments of this disclosure is shown.

[0044] Figure 9 A block diagram of a system having a storage device according to some embodiments of the present disclosure is shown.

[0045] Figure 10 A flowchart of a manufacturing method for forming a semiconductor device according to some embodiments of the present disclosure is shown.

[0046] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0047] Although specific configurations and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Thus, other configurations and arrangements can be used without departing from the scope of this disclosure. Furthermore, this disclosure can be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified with each other, and can be combined, adjusted, and modified in ways not specifically depicted in the accompanying drawings, such combinations, adjustments, and modifications being within the scope of this disclosure.

[0048] Generally, terms can be understood at least in part from their use in context. For example, the term "one or more" as used herein, depending at least in part on the context, can be used to describe any feature, structure, or characteristic in a singular sense, or a combination of features, structures, and characteristics in a plural sense. Similarly, terms such as "a," "one," or "described" can be understood to convey either singular or plural usage, depending at least in part on the context. Furthermore, "based on" can be understood not necessarily to convey an exclusive set of factors, but rather, on the contrary, to allow for the presence of other factors that are not necessarily explicitly described, again, depending at least in part on the context.

[0049] It will be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” means not only “directly on” but also “on” with an intermediate feature or layer, and that “above” or “on top of” means not only “above” or “on top of” but also “above” or “on top of” without an intermediate feature or layer (i.e., directly on).

[0050] Furthermore, spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” are used for ease of description to depict the relationship of one element or feature to other elements (single or multiple) or features (single or multiple) as shown in the figures. In addition to the orientations depicted in the figures, spatially relative terms are also intended to cover different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or in other orientations) and the spatially relative descriptors used herein can be interpreted accordingly.

[0051] As used herein, the term "substrate" refers to a material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned, or the material added on top of the substrate may remain unpatterned. Furthermore, the substrate may comprise a broad series of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0052] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entire undercoat or overcoat structure, or may have a width smaller than that of the undercoat or overcoat structure. Furthermore, a layer may be a region of a continuous structure whose thickness is less than the thickness of a homogeneous or heterogeneous continuous structure. For example, a layer may lie between any pair of horizontal planes between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (where interconnect lines, and / or vertical interconnect vias (vias) are formed) and one or more dielectric layers.

[0053] Transistors are used as switches or selection devices in memory cells of some memory devices, such as Dynamic Random Access Memory (DRAM). In a transistor-capacitor (1T1C) DRAM structure, data is stored in a capacitor. A sense amplifier (SA) circuit can be connected between two bit lines (BLs), one BL connected to the capacitor storing the data to be read, and the other BL used as a reference voltage. The function of the SA circuit is to amplify the voltage across these two BLs, thereby allowing the correct data to be read. Sensing margin refers to the voltage difference between the two BLs. A larger voltage difference increases the probability that the SA circuit will operate correctly. If the voltage difference between the two BLs is relatively small, there is a risk that the SA circuit may cause data flipping during operation, resulting in incorrect data readout. Therefore, ensuring sufficient sensing margin to maintain the reliability of data readout is crucial.

[0054] With the iterative development of DRAM products, the reduction in capacitor capacitance due to manufacturing process factors has led to a decrease in sensing margin. In some 4F2 DRAM architectures, the SA circuitry and word line driver (WLD) circuitry are located directly below the memory array to improve area efficiency. Furthermore, to improve the BL pickup window, some 4F2 DRAM architectures use BL interconnect structures to pick up the odd and even BLs on opposite sides of the memory array separately. Compared to the traditional 6F2 DRAM architecture, the total coupling capacitance of the capacitors and BLs is much smaller because the BLs and word lines (WLs) are led out at both ends of the transistor layer, and coupling capacitance is introduced between the BLs. These factors combined result in insufficient sensing margin. Therefore, effectively improving sensing margin is a pressing issue in DRAM architecture design.

[0055] To address one or more of the aforementioned problems, this disclosure introduces a DRAM architecture in which portions of the interconnect layer used to connect the buffer lines (BLs) and circuitry are used as a metal shielding structure. Specifically, odd and even BLs are routed to opposite sides of the memory array to connect to the standard interconnect (SA) circuitry via a metal interconnect located at the bottom of the memory array. The metal interconnect layer for BL pickup has additional metal lines on each side, which can be connected to a fixed voltage potential to serve as shielding lines. The shielding lines effectively increase the total coupling capacitance of the BLs, thereby optimizing the sensing margin to ensure reliable data read operations. The shielding lines can be formed in the same front-end-of-line (FEOL) or back-end-of-line (BOEL) process that forms the BL interconnect structure. The disclosed solution significantly reduces BL-BL parasitic capacitance, thereby reducing capacitor requirements, enhancing sensing margin, simplifying capacitor manufacturing, improving DRAM performance and reliability, and paving the way for further scaling as DRAM continues to scale.

[0056] Consistent with the scope of this disclosure, according to some embodiments of this disclosure, the memory cell array has vertical transistors, each vertical transistor including a semiconductor layer extending in a vertical direction, and a gate structure adjacent to or surrounded by the semiconductor layer. In some embodiments, WL and BL connected to the vertical transistors are arranged along a first lateral direction and a second lateral direction, respectively. Each semiconductor body of the array of vertical transistors extends in a vertical direction. By using such an arrangement, memory area efficiency can be improved. Furthermore, the memory cell array and peripheral circuitry can be formed separately on different wafers, so that the manufacturing processes of the memory cell array and peripheral circuitry do not affect each other, and memory area efficiency can be further improved.

[0057] Figure 1 A schematic diagram of a memory device 100 having an array of memory cells according to some embodiments of the present disclosure is shown, each memory cell having a vertical transistor. The memory device 100 may include an array of memory cells, wherein each memory cell 110 includes a vertical transistor 120 and a storage element coupled to the vertical transistor 120. In such... Figure 1 In some embodiments shown, the memory cell array is a DRAM cell array, and the storage element is a capacitor 130 for storing charge as binary information stored by the respective DRAM cell. In some other embodiments not shown in the figures, the memory cell array is a PCM cell array, and the storage element may be a PCM element (e.g., including a chalcogenide alloy) for storing the binary information of the respective PCM cell based on the different resistivities of the PCM element in the amorphous and crystalline phases.

[0058] like Figure 1As shown, memory cells 110 can be arranged in a two-dimensional (2D) memory cell array 180 having rows and columns. The memory device 100 may include word lines 150 that couple the memory cell array 180 to peripheral circuitry 190 to control the switching of vertical transistors 120 in the memory cells 110 located in a row, and bit lines 160 that couple the memory cell array 180 to peripheral circuitry 190 to send data to and / or receive data from memory cells 110 located in a column. That is, each word line 150 is coupled to a corresponding row of memory cells 110, and each bit line 160 is coupled to one or more corresponding logical columns of memory cells 110. In some embodiments, the gate of a vertical transistor 120 is coupled to word line 150, one of the source and drain of vertical transistor 120 is coupled to bit line 160, the other of the source and drain of vertical transistor 120 is coupled to one electrode of capacitor 130, and the other electrode of capacitor 130 is coupled to ground. Consistent with the scope of this disclosure, vertical transistors 120, such as vertical metal-oxide-semiconductor field-effect transistors (MOSFETs), can replace conventional planar transistors as pass transistors for memory cells 110 to reduce the area occupied by pass transistors, coupling capacitance, and the complexity of interconnect wiring.

[0059] Figure 2 A schematic layout diagram of a memory chip 200 according to some embodiments of the present disclosure is shown. In some embodiments, the memory chip 200 may include a die 210 having a square or rectangular shape. The die 210 may include a plurality of (e.g., 16 or any other suitable number) memory repositories 220. Each repository 220 may include a plurality of memory cell arrays (e.g., combined with the above). Figure 1 The described storage cell array 180 is arranged in rows along the x-direction and / or in columns along the y-direction. Spacing regions 230 may be located between adjacent rows of the storage cell 220.

[0060] Figure 3A A schematic layout diagram of a portion of a repository 300A according to some embodiments of the present disclosure is shown. Figure 3AAs shown, the WLD circuit 330 can be located on both sides of the memory cell array 310, while the SA circuit 320 can be located at a position overlapping the memory cell array 320 along the vertical direction. That is, the projection of the SA circuit 320 onto the lateral plane lies within the projection of the memory cell array 310 onto the lateral plane. Note that the memory cell array 310 can be formed on a first wafer, while the SA circuit 320 and WLD circuit 330 can be parts of peripheral circuitry formed on a second wafer. The memory bank 300A can be formed by bonding a first wafer including the memory cell array 310 to a second wafer including the SA circuit 320 and WLD circuit 330. Therefore, the SA circuit 320 and WLD circuit 330 are not located on the same lateral plane where the memory cell array 310 is located. Figure 3A Only a partial top view of repository 300A is shown.

[0061] Figure 3B A schematic layout diagram of a portion of a repository 300B according to some embodiments of this disclosure is shown. Figure 3B As shown, the WLD circuit 330 and SA circuit 320 can be located at positions overlapping with the memory cell array 310 along the vertical direction. That is, the projections of the WLD circuit 330 and SA circuit 320 onto the lateral plane lie within the projection of the memory cell array 310 onto the lateral plane. In some embodiments, the WLD circuit 330 can be located at positions overlapping with two corners along the first diagonal of the memory cell array 310, and the SA circuit 320 can be located at positions overlapping with two corners along the second diagonal of the memory cell array 310. Note that the memory cell array 310 can be formed on a first wafer, while the SA circuit 320 and WLD circuit 330 can be portions of peripheral circuitry formed on a second wafer. The memory bank 300A can be formed by bonding a first wafer including the memory cell array 310 to a second wafer including the SA circuit 320 and WLD circuit 330. Therefore, the SA circuit 320 and WLD circuit 330 are not located on the same lateral plane where the memory cell array 310 is located. Figure 3A Only a top view of a portion of repository 300A is shown.

[0062] Figure 4 A schematic layout diagram of a portion of a repository 400 according to some embodiments of this disclosure is shown. Figure 4 As shown, the word lines (WL) 450 of the memory cell array 410 can extend parallel to a first lateral direction (i.e., the x-direction, referred to as the WL direction), while the bit lines (BL) 460 of the memory cell array can extend parallel to a second lateral direction orthogonal to the first lateral direction (i.e., the y-direction, referred to as the BL direction). For ease of routing, the word lines 450 and bit lines 460 can be formed in different lateral planes.

[0063] In some implementations, the WL interconnect structure 455 may be located on both sides of each memory array 410 along the WL direction (x-direction). WL 450 may be interconnected to the WL interconnect structure 455 in an interleaved manner on both sides of each memory array 410 along the WL direction (x-direction). For example, located on the first side of the memory array 410 (e.g., Figure 4 The first group of WL interconnect structures 455 (on the left side of the array) can be connected to the odd number of WLs 450 and is located on the second side of the storage array 410 (e.g., Figure 4 The second WL interconnect structure 455 (on the right side of the diagram) can be connected to an even number of WL 450.

[0064] In some implementations, the BL interconnect structure 465 is located on both sides of each memory array 410 along the BL direction (y-direction). The BLs 460 may be interconnected to the BL interconnect structure 465 in an interleaved manner at both sides of each memory array 410 along the BL direction (y-direction). For example, located on the first side of the memory array 410 (e.g., Figure 4 The first set of BL interconnect structures 465 (on the lower side of the array) can be connected to the odd number of BLs 460 and is located on the second side of the storage array 410 (e.g., Figure 4 The second group of BL interconnect structures 465 (on the upper middle side) can be connected to an even number of BLs 460. In some embodiments, the BL interconnect structure 465 can be connected to the SA circuit 420. Note that the memory cell array 410, WL 450, BL 460, WL interconnect structure 455, BL interconnect structure 465, and SA circuit 420 can be formed on different lateral planes; Figure 4 Only a top view of a portion of repository 400 is shown.

[0065] Figure 5 A schematic side cross-sectional view of a portion of a storage repository 500 in the yz plane according to some embodiments of the present disclosure is shown. In some embodiments, the storage repository 500 may include a peripheral circuitry structure 590 stacked on a storage array structure 510 in the vertical direction (z direction).

[0066] The memory array structure 510 may include multiple arrays of memory cells 530 on a substrate 520. Each memory cell 530 includes a vertical transistor 550 and a storage element 540. In some embodiments, according to some embodiments of this disclosure, the vertical transistor 550 may have any suitable arrangement of components, such as a channel-all-around (CAA) vertical transistor, a gate-all-around (GAW) vertical transistor, a single-metal-gate (SMG) vertical transistor, a double-metal-gate (DMG) vertical transistor, a triple-metal-gate (TMG) vertical transistor, etc. Each vertical transistor 550 includes a semiconductor layer 553 and a gate electrode 555 at one or more lateral sides of the semiconductor layer 553.

[0067] In some embodiments, the gate electrodes 555 of rows of vertical transistors 550 along a first lateral direction (x-direction) may be interconnected to form word lines extending along the first lateral direction (x-direction). The gate electrodes 555 may comprise any suitable conductive material, such as polysilicon, metals (e.g., tungsten (W), copper (Cu), aluminum (Al), etc.), metal compounds (e.g., titanium nitride (TiN), tantalum nitride (TaN), etc.), or silicides. For example, the gate electrode 555 may comprise doped polysilicon, i.e., gate polysilicon. In some embodiments, the gate electrode 555 comprises multiple conductive layers, such as a W layer over a TiN layer. In some embodiments, a gate dielectric layer may be located between the semiconductor layer 553 and the gate electrode 555. The gate dielectric layer may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric.

[0068] In some embodiments, bit line 565 is at the end of semiconductor layer 553 (e.g., Figure 5 The bit line 565 contacts the upper end of the layer and extends along a second lateral direction (y-direction). In some embodiments, the bit line 565 may comprise any suitable conductive material, such as polysilicon, metal (e.g., W, Cu, Al, etc.), metal compound (e.g., TiN, TaN, etc.), or silicide. In some embodiments, the bit line 565 may comprise multiple conductive layers, such as a W layer over a TiN layer.

[0069] In some embodiments, each memory cell 530 may further include a storage element 540 coupled to a vertical transistor 550. The storage element 540 may include any device capable of storing binary data (e.g., 0s and 1s), including but not limited to capacitors for DRAM cells and PCM elements for PCM cells. In some embodiments, each vertical transistor 550 controls the selection and / or state switching of the corresponding storage element 540 coupled to the vertical transistor 550. In some embodiments, the storage element 540 includes a capacitor. It should be understood that the capacitor may include any suitable structure and configuration, such as a planar capacitor, a stacked capacitor, a multi-fin capacitor, a cylindrical capacitor, a trench capacitor, or a substrate-plate capacitor. In some embodiments, the capacitor may be coupled to a common electrode 548.

[0070] In some embodiments, the storage array structure 510 may include an array interconnect structure 560. For example, the array interconnect structure may include array contact structures, such as WL contacts, BL contacts, capacitor electrode contacts, etc. In some embodiments, the array interconnect structure 560 may further include one or more first interconnect layers connected to the array contact structures. In some embodiments, the array interconnect structure 560 may further include array bonding pads. In some embodiments, the array interconnect structure 560 may include any suitable conductive material, such as polysilicon, metals (e.g., W, Cu, Al, etc.), metal compounds (e.g., TiN, TaN, etc.), or silicides.

[0071] In some embodiments, the peripheral circuit structure 590 may be located vertically on the memory array structure 510. The peripheral circuit structure 590 may include various types of peripheral circuits formed using CMOS technology. In some embodiments, the peripheral circuit structure 590 may include a WLD circuit 330 and an SA circuit 320, which include a transistor 580. The peripheral circuit structure 590 may further include a peripheral interconnect structure 570 coupled to the transistor 580. The peripheral interconnect structure 570 may include any suitable conductive structure, such as various conductive vias, conductive lines, conductive plates, etc., as transistor contacts, peripheral bonding pads, external connection pads 577, and one or more second interconnect layers. In some embodiments, the array interconnect structure 560 may further include array bonding pads. In some embodiments, the peripheral interconnect structure 570 may include any suitable conductive material, such as polysilicon, metals (e.g., W, Cu, Al, etc.), metal compounds (e.g., TiN, TaN, etc.), or silicides.

[0072] In some embodiments, the peripheral circuitry 590 may be bonded to the memory array structure 510 at a bonding interface 575, such that the array bonding pads are coupled to the peripheral bonding pads. Thus, transistors 580 can be coupled to the array of memory cells 530 via peripheral interconnects 570, array interconnects 560, bit lines 565, word lines 555, and any other suitable metal wiring. Note that one or more peripheral circuits may include any suitable circuitry for facilitating the operation of the array of memory cells 530 by applying voltage and / or current signals to each vertical transistor 550 via word lines 555 and bit lines 565 and sensing voltage and / or current signals from each vertical transistor 550.

[0073] Figure 6 A schematic side cross-sectional view of a portion of a storage repository 600 according to some embodiments of the present disclosure is shown in the yz plane. In some embodiments, the storage repository 600 may include a plurality of arrays of storage cells 610, each storage cell 610 including a vertical transistor 630 and a storage element 620. In some embodiments, according to some embodiments of the present disclosure, the vertical transistor 630 may have any suitable arrangement of components, such as a channel full-around (CAA) type vertical transistor, a gate full-around type vertical transistor, a single metal gate (SMG) type vertical transistor, a double metal gate (DMG) type vertical transistor, a triple metal gate (TMG) type vertical transistor, etc. Note that, for simplicity, Figure 6 A vertical transistor 630 is shown.

[0074] In some embodiments, memory cell 610 may further include a storage element 620 coupled to vertical transistor 630. Storage element 620 may include any device capable of storing binary data (e.g., 0s and 1s), including but not limited to capacitors for DRAM cells and PCM elements for PCM cells. In some embodiments, vertical transistor 630 controls the selection and / or state switching of storage element 620 coupled to vertical transistor 630. In some embodiments, storage element 620 is a capacitor. It should be understood that the capacitor may include any suitable structure and configuration, such as planar capacitors, stacked capacitors, multi-fin capacitors, cylindrical capacitors, trench capacitors, or substrate-plate capacitors. Note that, for simplicity, Figure 6 A storage cell 620 is shown.

[0075] In some embodiments, bit line 635 contacts vertical transistor 630 and extends along a second lateral direction (y-direction). In some embodiments, memory cell line 625 contacts memory cell 620. Note that, for simplicity, Figure 6 A bit line 635 and a storage element line 625 are shown.

[0076] In some embodiments, repository 600 may further include a BL interconnect structure 640 connected to bit line 635. In some embodiments, the BL interconnect structure 640 may include one or more conductive layers and via contact structures. In some embodiments, the BL interconnect structure 640 may include any suitable conductive material, such as polysilicon, metals (e.g., W, Cu, Al, etc.), metal compounds (e.g., TiN, TaN, etc.), or silicides. Note that... Figure 6 The two conductive layers of the BL interconnect structure 640 are shown as an example.

[0077] In some embodiments, the repository 600 may further include an SA circuit 690 and an SA circuit interconnect structure 660 coupled to the SA circuit 690. The SA circuit interconnect structure 660 includes one or more conductive layers and via contact structures. In some embodiments, the SA circuit interconnect structure 660 may include any suitable conductive material, such as polysilicon, metals (e.g., W, Cu, Al, etc.), metal compounds (e.g., TiN, TaN, etc.), or silicides. Note that... Figure 6 The three conductive layers of the SA circuit interconnect structure 660 are shown as an example.

[0078] In some implementations, the SA circuit interconnect 660 is coupled to the BL interconnect 640 via pads 650. Thus, each SA circuit 690 is electrically coupled to two BLs 635 via the SA circuit interconnect 660, bonding pads 650, and BL interconnect 640 to amplify the voltage across the two BLs 635.

[0079] Figure 7 A schematic side cross-sectional view of a portion of a storage repository 700 according to some embodiments of the present disclosure is shown in the yz plane. In some embodiments, the storage repository 700 may include two adjacent storage cell arrays 701 and 702. Note that, for simplicity, in Figure 7 The memory cells, including vertical transistors and storage elements, are omitted. For example... Figure 7 As shown, the first memory cell array 701 may include a first bit line 721 and a first SA circuit 791, and the second memory cell array 702 may include a second bit line 722 and a second SA circuit 792.

[0080] In some embodiments, the storage reservoir 700 may further include one or more first conductive layers 740 on the storage array side. Note that... Figure 7Two first conductive layers 740 are shown as an example. In some embodiments, one or more first conductive layers 740 may include a first interconnect structure 741 connected to bit lines 721 and 722 of memory cell arrays 701 and 702. For example, the first interconnect structure 741 may be a combination of Figure 6 The BL interconnect structure 640 is described in part. In some embodiments, a first interconnect structure 741 may be connected between a first bit line 721 of a first memory cell array 701 and a second bit line 722 of a second memory cell array 702. In some embodiments, one or more first conductive layers 740 may further include a second interconnect structure 748 separate from the bit lines 721 and 722 of the memory cell arrays 701 and 702. In some embodiments, the second interconnect structures 748 may be connected to each other via any suitable contact to a common electrical node (not shown) to form a metal shield structure. The formed metal shield structure including the second interconnect structure 748 can effectively increase the total coupling capacitance of the bit lines 721 and 722, thereby optimizing the sensing margin to ensure reliable data read operations of the formed memory device.

[0081] Similarly, the storage unit 700 may further include one or more second conductive layers 760 on the peripheral circuit side. It should be noted that... Figure 7 Three second conductive layers 760 are shown as an example. In some embodiments, one or more second conductive layers 760 may include a third interconnect structure 761 connected to SA circuits 791 and 792 and coupled to the first interconnect structure 741 via bonding pads 750. For example, the third interconnect structure 761 may be a combination Figure 6 The SA circuit interconnect structure 660 described herein. Thus, the first SA circuit 791 and the second SA circuit 792 can be coupled to the first bit line 721 and the second bit line 722 via the third interconnect structure 761, bonding pads 750, and the first interconnect structure 741. In some embodiments, one or more second conductive layers 760 may further include a fourth interconnect structure 768 separate from the SA circuits 791 / 792 and the first interconnect structure 741. In some embodiments, the fourth interconnect structure 768 can be connected to each other via any suitable contact to a common electrical node (not shown) to form a metal shield structure. The formed metal shield structure including the fourth interconnect structure 768 can further increase the total coupling capacitance of the bit lines 721 and 722, thereby optimizing the sensing margin to ensure reliable data read operations of the formed memory device.

[0082] Figure 8 A schematic top view of a portion of a repository 800 according to some embodiments of the present disclosure in the xy plane is shown. In some embodiments, Figure 8 A conductive layer of the repository 800 is shown, such as the one shown above. Figure 7 Described as a first conductive layer 740 or a second conductive layer 760.

[0083] Note that, although in Figure 8 Not shown, but the memory cell array 810 may include multiple bit lines extending parallel along the second lateral direction (y-direction). Figure 8 As shown, multiple bit line contact structures 835, 845 can be located on opposite sides of the memory cell array 810 (e.g., Figure 8 The first bit line contact structure 835 can be located on the upper and lower sides of the memory cell array 810, respectively, to contact the corresponding bit lines. For example, the first bit line contact structure 835 can be located on the first side of the memory cell array 810 and contact the odd-numbered bit lines of the memory cell array 810. The second bit line contact structure 845 can be located on the second side of the memory cell array 810 opposite to the first side and contact the even-numbered bit lines of the memory cell array 810.

[0084] In some embodiments, the first bit contact structure 835 can be connected to the first conductive line 830. The first conductive line 830 can be arranged along a first lateral direction (x-direction). Each first conductive line 830 extends along a second lateral direction (y-direction) and is coupled to one of the odd-numbered bit lines through a corresponding bit contact structure 835. In some embodiments, adjacent first conductive lines 830 have different first lengths along the second lateral direction, such as... Figure 8 As shown. In some embodiments, multiple second conductive lines 870 are arranged along the first transverse direction and connected to a common conductive line 880 extending along the first transverse direction, aligned with the first conductive line 830 along the second transverse direction. Each second conductive line 870 extends along the second transverse direction and is aligned with a corresponding first conductive line among the first conductive lines 830. In some embodiments, adjacent second conductive lines 870 have different second lengths along the second transverse direction. In some embodiments, as... Figure 8 As shown, the total length of each pair of first conductive lines 830 and second conductive lines 870 aligned along the second transverse direction can be equal.

[0085] Similarly, the second bit line contact structure 845 can be connected to the third conductive line 840. The third conductive line 840 can be arranged along a first lateral direction (x direction). Each third conductive line 840 extends along a second lateral direction (y direction) and is coupled to one of the even-numbered bit lines through a corresponding bit line contact structure 845. In some embodiments, adjacent third conductive lines 840 have different first lengths along the second lateral direction, such as... Figure 8As shown. In some embodiments, multiple fourth conductive lines 860 are arranged along a first transverse direction and connected to a common conductive line 880 extending along the first transverse direction, aligned with the third conductive line 840 along the second transverse direction. Each fourth conductive line 860 extends along the second transverse direction and is aligned with a corresponding third conductive line among the third conductive lines 840. In some embodiments, adjacent fourth conductive lines 860 have different second lengths along the second transverse direction. In some embodiments, as... Figure 8 As shown, the total length of each pair of third conductive wires 840 and fourth conductive wires 860 aligned along the second transverse direction can be equal.

[0086] Figure 9 A block diagram of a system 900 having a storage device according to some embodiments of the present disclosure is shown. System 900 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronics, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 9 As shown, system 900 may include a host 908 and a storage system 902 having one or more storage devices 904 and a memory controller 906. The host 908 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-a-chip (SoC), such as an application processor (AP). The host 908 may be configured to send data to or receive data from storage device 904. Storage device 904 may be any storage device disclosed herein, such as storage device 100. In some embodiments, storage device 904 includes the components described above. Figure 2-8 One or more repositories described.

[0087] According to some embodiments, a memory controller 906 is coupled to a storage device 904 and a host 908 and is configured to control the storage device 904. The memory controller 906 can manage data stored in the storage device 904 and communicate with the host 908. The memory controller 906 can be configured to control the operation of the storage device 904, such as read, write, and refresh operations. The memory controller 906 can also be configured to manage various functions regarding data stored or to be stored in the storage device 904, including but not limited to refresh and timing control, command / request translation, buffering and scheduling, and power management. In some embodiments, the memory controller 906 is also configured to determine the maximum storage capacity that the computer system can use, the number of storage repositories, storage type and speed, storage granular data depth and data width, and other important parameters. The memory controller 906 can also perform any other suitable functions. The memory controller 906 can communicate with external devices (e.g., the host 908) according to specific communication protocols. For example, the memory controller 906 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), Fast PCI (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, etc.

[0088] Figure 10 A flowchart of a manufacturing method 1000 for forming a semiconductor device according to some embodiments of the present disclosure is shown. It should be understood that the operations shown in method 1000 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in conjunction with… Figure 10 The different execution sequences are shown.

[0089] like Figure 10 As shown, method 1000 can begin at operation 1010, in which a memory array structure can be formed. In some embodiments, operation 1010 for forming the memory array structure includes the following steps: step 1011: forming a transistor layer including multiple arrays of vertical transistors; step 1013: forming a storage layer including multiple arrays of capacitors coupled to the vertical transistors, forming multiple bit lines coupled to the vertical transistors; and step 1015: forming a first interconnect layer, the first interconnect layer including a first interconnect structure connected to the multiple bit lines, and a second interconnect structure separated from the multiple bit lines and coupled to a first common electrical node.

[0090] In some embodiments, step 1015 of forming the first interconnect layer includes connecting first interconnect structures between bit lines of adjacent arrays of vertical transistors. In some embodiments, step 1015 of forming the first interconnect layer further includes forming a plurality of first conductive lines arranged along a first lateral direction. Each first conductive line extends along a second lateral direction and is coupled to a corresponding bit line in the bit line via a bit line contact structure. In some embodiments, forming the plurality of first conductive lines includes forming adjacent first conductive lines with different first lengths along the second lateral direction. In some embodiments, step 1015 of forming the first interconnect layer includes forming at least two layers of conductive lines, wherein the first interconnect structure and the second interconnect structure are portions of the at least two layers of conductive lines.

[0091] In some embodiments, step 1015 of forming the second interconnect structure includes forming a plurality of second conductive lines arranged along a first lateral direction and connected to a common conductive line extending along the first lateral direction. Each second conductive line extends along a second lateral direction and is aligned with a corresponding first conductive line among the first conductive lines. In some embodiments, forming the plurality of second conductive lines includes forming adjacent second conductive lines with different second lengths along the second lateral direction. In some embodiments, step 1015 of forming the second interconnect layer includes forming at least two layers of conductive lines, wherein the third interconnect structure and the fourth interconnect structure are portions of the at least two layers of conductive lines.

[0092] In some embodiments, the operation 1010 of forming the memory array structure further includes forming a first bit line contact structure located on a first side of the corresponding array of vertical transistors and contacting the odd-numbered bit lines of the corresponding array of vertical transistors. In some embodiments, the operation 1010 of forming the memory array structure further includes forming a second bit line contact structure located on a second side of the corresponding array of vertical transistors opposite to the first side and contacting the even-numbered bit lines of the corresponding array of vertical transistors.

[0093] like Figure 10 As shown, method 1000 can then proceed to operation 1020, in which a peripheral circuit structure can be formed. In some embodiments, operation 1020 of forming the peripheral circuit structure may include the following steps: step 1021: forming a second interconnect layer including a third interconnect structure, and step 1023: forming a sense amplifier circuit connected to the third interconnect structure.

[0094] In some embodiments, step 1021 of forming the second interconnect layer further includes forming a fourth interconnect structure that is separate from the sense amplifier circuitry and the first interconnect structure and connected to the second common electrical node. In some embodiments, step 1021 of forming the second interconnect layer further includes connecting the peripheral circuitry structure to the memory array structure, which includes connecting the first common electrical node to the second common electrical node.

[0095] like Figure 10 As shown, method 1000 can then proceed to operation 1030, wherein the peripheral circuitry structure can be connected to the memory array structure such that the third interconnect structure is coupled to the first interconnect structure. In some embodiments, operation 1030 may include bonding the peripheral circuitry structure to the memory array structure using any suitable bonding technique (such as a hybrid bonding process).

[0096] The foregoing description of the specific embodiments can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance presented herein, such adaptations and modifications are intended to be within the meaning and scope of equivalents of the disclosed embodiments.

[0097] The breadth and scope of this disclosure should not be limited by any of the above-described embodiments, but should be defined solely by the following claims and their equivalents.

Claims

1. A semiconductor device comprising: a memory array structure comprising: a transistor tier comprising a plurality of arrays of vertical transistors, a storage tier comprising a plurality of arrays of capacitors coupled with the vertical transistors, a plurality of bit lines coupled with the vertical transistors, and a first interconnect tier comprising first interconnect structures connected with the plurality of bit lines and second interconnect structures separate from the plurality of bit lines and connected to a common electrical node; and a peripheral circuit structure connected with the memory array structure and comprising: a second interconnect tier comprising third interconnect structures connected with the first interconnect structures, and a sense amplifier circuit connected with the third interconnect structures.

2. The semiconductor device of claim 1, wherein, the second interconnect tier further comprising: a fourth interconnect structure separate from the sense amplifier circuit and the first interconnect structures and connected to the common electrical node.

3. The semiconductor device of claim 1, wherein: the first interconnect structures are connected between bit lines of adjacent arrays of vertical transistors.

4. The semiconductor device of claim 1, wherein, the first interconnect structures comprise: a plurality of first conductive lines arranged along a first lateral direction, each first conductive line extending along a second lateral direction and coupled with a corresponding one of the bit lines through a bit line contact structure.

5. The semiconductor device of claim 4, wherein, adjacent first conductive lines have different first lengths along the second lateral direction.

6. The semiconductor device of claim 5, wherein, the second interconnect structures comprise: a plurality of second conductive lines arranged along the first lateral direction and connected to a common conductive line extending along the first lateral direction, wherein each second conductive line extends along the second lateral direction and is aligned with a corresponding one of the first conductive lines.

7. The semiconductor device of claim 6, wherein, adjacent second conductive lines have different second lengths along the second lateral direction.

8. The semiconductor device of claim 1, wherein: the first interconnect tier comprises at least two tiers of conductive lines; and the first interconnect structures and the second interconnect structures are portions of the at least two tiers of conductive lines.

9. The semiconductor device of claim 2, wherein: the second interconnect tier comprises at least two tiers of conductive lines; and the third interconnect structures and the fourth interconnect structure are portions of the at least two tiers of conductive lines.

10. The semiconductor device of claim 1, wherein, the memory array structure further comprises: a first bit line contact structure located at a first side of a corresponding array of vertical transistors and contacting odd bit lines of the corresponding array of vertical transistors; and a second bit line contact structure located at a second side of the corresponding array of vertical transistors opposite the first side and contacting even bit lines of the corresponding array of vertical transistors.

11. A semiconductor device comprising: a vertical transistor; a bit line coupled with the vertical transistor; a first interconnect structure comprising: first conductive lines arranged along a first lateral direction, each first conductive line extending along a second lateral direction and connected with a corresponding one of the bit lines, and second conductive lines arranged along the first lateral direction, each second conductive line extending along the second lateral direction and connected to a common electrical node and separate from the bit lines; and a sense amplifier circuit connected with the bit lines through the first conductive lines. ​ 12. The semiconductor device of claim 11, further comprising a second interconnect structure, the second interconnect structure comprising: a third conductive line connected between the first conductive lines and the sense amplifier circuit; and a fourth conductive line connected to the common electrical node and separate from the sense amplifier circuit and the first interconnect structure.

13. The semiconductor device of claim 11, wherein: the first interconnect structure is connected between bit lines of adjacent arrays of vertical transistors. each first conductive line is aligned with a corresponding one of the second conductive lines along the second lateral direction.

14. The semiconductor device of claim 11, wherein, adjacent first conductive lines have different first lengths along the second lateral direction.

15. The semiconductor device of claim 14, wherein, 16. The semiconductor device of claim 15, wherein: the second conductive lines are connected to a common conductive line extending along the first lateral direction. adjacent second conductive lines have different second lengths along the second lateral direction.

17. The semiconductor device of claim 16, wherein, 18. The semiconductor device of claim 11, wherein: the first conductive lines and the second conductive lines are distributed in at least two conductive wiring layers along a vertical direction.

19. The semiconductor device of claim 12, wherein: the third conductive line and the fourth conductive line are distributed in at least two conductive wiring layers along a vertical direction.

20. The semiconductor device of claim 11, further comprising: a first bit line contact structure on a first side of a corresponding array of vertical transistors and contacting odd bit lines of the corresponding array of vertical transistors; and a second bit line contact structure on a second side of the corresponding array of vertical transistors opposite the first side and contacting even bit lines of the corresponding array of vertical transistors.

21. A method for forming a semiconductor device, comprising: forming a memory array structure, comprising: forming a transistor layer, the transistor layer comprising a plurality of arrays of vertical transistors, forming a storage layer, the storage layer comprising a plurality of arrays of capacitors coupled with the vertical transistors, forming a plurality of bit lines coupled with the vertical transistors, and forming a first interconnect layer, the first interconnect layer comprising first interconnect structures connected with the plurality of bit lines and second interconnect structures separate from the plurality of bit lines and coupled with a first common electrical node; forming a peripheral circuit structure, comprising: forming a second interconnect layer, the second interconnect layer comprising third interconnect structures, and forming a sense amplifier circuit connected with the third interconnect structures; and connecting the peripheral circuit structure with the memory array structure such that the third interconnect structures are coupled with the first interconnect structures.

22. The method of claim 21, wherein: forming the second interconnect layer further comprises forming fourth interconnect structures separate from the sense amplifier circuit and the first interconnect structures and connected to a second common electrical node; and connecting the peripheral circuit structure with the memory array structure comprises connecting the first common electrical node to the second common electrical node. ​ ​ 23. The method of claim 21, wherein, forming the first interconnect layer includes: connecting the first interconnect structure between bit lines of adjacent arrays of vertical transistors.

24. The method of claim 21, wherein, forming the first interconnect layer includes: forming a plurality of first conductive lines arranged along a first lateral direction, each first conductive line extending along a second lateral direction and coupled with a corresponding one of the bit lines through a bit line contact structure.

25. The method of claim 24, wherein, forming the plurality of first conductive lines includes forming adjacent first conductive lines having different first lengths along the second lateral direction.

26. The method of claim 25, wherein, forming the second interconnect structure includes: forming a plurality of second conductive lines arranged along the first lateral direction and connected to a common conductive line extending along the first lateral direction, wherein each second conductive line extends along the second lateral direction and is aligned with a corresponding one of the first conductive lines.

27. The method of claim 26, wherein, forming the plurality of second conductive lines includes forming adjacent second conductive lines having different second lengths along the second lateral direction.

28. The method of claim 21, wherein, forming the first interconnect layer includes: forming at least two layers of conductive lines, wherein the first interconnect structure and the second interconnect structure are portions of the at least two layers of conductive lines.

29. The method of claim 22, wherein, forming the second interconnect layer includes: forming at least two layers of conductive lines, wherein the third interconnect structure and the fourth interconnect structure are portions of the at least two layers of conductive lines.

30. The method of claim 21, wherein, forming the memory array structure further includes: forming first bit line contact structures on a first side of a corresponding array of vertical transistors and contacting odd bit lines of the corresponding array of vertical transistors; and forming second bit line contact structures on a second side of the corresponding array of vertical transistors opposite the first side and contacting even bit lines of the corresponding array of vertical transistors.

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