Display device

Abstract

Disclosed in an embodiment of the present invention is a display device in which a conductive layer disposed under a semiconductor layer of a driving transistor at least corresponds to a channel region of the semiconductor layer, thereby preventing a disconnection of the semiconductor layer due to a lower step, and improving the reliability of the display device. And the capacitor is formed by a plurality of conductive layers overlapping a channel region of the semiconductor layer and disposed under and on top of the semiconductor layer to ensure a large capacitance. A display device according to one embodiment includes: a first conductive line; a first electrode disposed on and overlapping the first conductive line; a semiconductor layer disposed on the first electrode and overlapping the first electrode; a second electrode disposed on the semiconductor layer and overlapping the first electrode; and a third electrode disposed on the second electrode, the third electrode overlapping the second electrode, and the third electrode being electrically connected to the semiconductor layer and the first electrode, in which a region of the semiconductor layer overlapping the second electrode overlaps the first conductive line.

Description

Technical Field

[0001] One or more embodiments relate to pixels and display devices including pixels. Background Technology

[0002] In recent years, the applications of display devices have diversified. Furthermore, display devices have become thinner and lighter, and therefore, their uses have expanded.

[0003] As display devices are used for a variety of purposes, there are various ways to design the shape of display devices, and the functions that can be connected to or associated with display devices have increased. Summary of the Invention

[0004] Technical issues

[0005] One or more embodiments include a display device with improved display quality. However, this is intended as an example, and the scope of this disclosure is not limited thereto.

[0006] Solution to the problem

[0007] According to one or more embodiments, a display device includes: a first conductive line; a first electrode disposed on and overlapping the first conductive line; a semiconductor layer disposed on and overlapping the first electrode; a second electrode disposed on the semiconductor layer and overlapping the first electrode; and a third electrode disposed on the second electrode, overlapping the second electrode, and electrically connected to the semiconductor layer and the first electrode, wherein a region of the semiconductor layer overlapping the second electrode overlaps with the first conductive line.

[0008] The display device may further include: a fourth electrode electrically connected to the second electrode, the fourth electrode and the third electrode being disposed on the same layer; and a fifth electrode disposed on the fourth electrode, the fifth electrode overlapping the fourth electrode, and the fifth electrode being electrically connected to the third electrode.

[0009] The display device may further include a sixth electrode, wherein the sixth electrode and the first conductive line are arranged on the same layer, wherein the first electrode, the second electrode and the third electrode may overlap with the sixth electrode, and the second electrode may be electrically connected to the sixth electrode.

[0010] An opening overlapping the sixth electrode can be confined within the first electrode, and the second electrode can be electrically connected to the sixth electrode through the opening.

[0011] The display device may further include: a seventh electrode electrically connected to the second electrode, the seventh electrode and the third electrode being disposed on the same layer; and an eighth electrode disposed on the seventh electrode, the eighth electrode overlapping the seventh electrode, and the eighth electrode being electrically connected to the third electrode.

[0012] The display device may further include: a second conductive line spaced apart from the first conductive line, the second conductive line and the first conductive line being disposed on the same layer, wherein the voltage applied to the second conductive line may be different from the voltage applied to the first conductive line.

[0013] The first electrode can overlap with the second conductive line.

[0014] According to one or more embodiments, a display device includes: a first circuit region and a second circuit region, wherein a pixel circuit of a first pixel is disposed in the first circuit region and a pixel circuit of a second pixel is disposed in the second circuit region; a first conductive line is disposed in the first circuit region and the second circuit region; a first electrode is disposed on and overlaps with the first conductive line, the first electrode being disposed in each of the first circuit region and the second circuit region; a semiconductor layer is disposed on and overlaps with the first electrode, the semiconductor layer being disposed in each of the first circuit region and the second circuit region; a second electrode is disposed on the semiconductor layer and overlaps with the first electrode, the second electrode being disposed in each of the first circuit region and the second circuit region; and a third electrode is disposed on the second electrode, the third electrode overlaps with the second electrode, and the third electrode is electrically connected to the semiconductor layer and the first electrode, the third electrode being disposed in each of the first circuit region and the second circuit region, wherein the region of the semiconductor layer overlapping the second electrode overlaps with the first conductive line.

[0015] The display device may further include: a fourth electrode electrically connected to the second electrode, the fourth electrode being disposed in each of the first circuit region and the second circuit region, the fourth electrode and the third electrode being disposed on the same layer; and a fifth electrode disposed on the fourth electrode, the fifth electrode overlapping the fourth electrode and being electrically connected to the third electrode, the fifth electrode being disposed in each of the first circuit region and the second circuit region.

[0016] The display device may further include a sixth electrode, wherein the sixth electrode and the first conductive line are arranged on the same layer in the first circuit region, wherein the first electrode, the second electrode and the third electrode may overlap with the sixth electrode, and the second electrode may be electrically connected to the sixth electrode.

[0017] In the first circuit region, an opening overlapping the sixth electrode can be defined in the first electrode, and the second electrode can be electrically connected to the sixth electrode through the opening.

[0018] The display device may further include: a seventh electrode electrically connected to the second electrode, the seventh electrode being disposed in each of the first circuit region and the second circuit region, the seventh electrode and the third electrode being disposed on the same layer; and an eighth electrode disposed on the seventh electrode, the eighth electrode overlapping the seventh electrode and being electrically connected to the third electrode, the eighth electrode being disposed in each of the first circuit region and the second circuit region.

[0019] According to one or more embodiments, a display device includes: a first circuit region and a second circuit region, wherein a pixel circuit of a first pixel is disposed in the first circuit region and a pixel circuit of a second pixel is disposed in the second circuit region; a first conductive line is disposed in the first circuit region and the second circuit region; a second conductive line is spaced apart from the first conductive line, and the second conductive line and the first conductive line are disposed on the same layer in the first circuit region and the second circuit region; a first electrode is disposed on and overlaps with the first conductive line, and the first electrode is disposed in each of the first circuit region and the second circuit region; a semiconductor layer is disposed on and overlaps with the first electrode, and the semiconductor layer is disposed in each of the first circuit region and the second circuit region; a second electrode is disposed on the semiconductor layer and overlaps with the first electrode, and the second electrode is disposed in each of the first circuit region and the second circuit region; and a third electrode is disposed on the second electrode, overlaps with the second electrode, and is electrically connected to the semiconductor layer and the first electrode, and is disposed in each of the first circuit region and the second circuit region, wherein the region of the semiconductor layer overlapping the second electrode overlaps with the first conductive line.

[0020] The display device may further include: a fourth electrode electrically connected to the second electrode, the fourth electrode being disposed in each of the first circuit region and the second circuit region, the fourth electrode and the third electrode being disposed on the same layer; and a fifth electrode disposed on the fourth electrode, the fifth electrode overlapping the fourth electrode and being electrically connected to the third electrode, the fifth electrode being disposed in each of the first circuit region and the second circuit region.

[0021] The display device may further include a sixth electrode, wherein the sixth electrode and the first conductive line are arranged on the same layer in the first circuit region, wherein the first electrode, the second electrode and the third electrode may overlap with the sixth electrode, and the second electrode may be electrically connected to the sixth electrode.

[0022] In the first circuit region, an opening overlapping the sixth electrode can be defined in the first electrode, and the second electrode can be electrically connected to the sixth electrode through the opening.

[0023] The display device may further include: a seventh electrode electrically connected to the second electrode, the seventh electrode being disposed in each of the first circuit region and the second circuit region, the seventh electrode and the third electrode being disposed on the same layer; and an eighth electrode disposed on the seventh electrode, the eighth electrode overlapping the seventh electrode and being electrically connected to the third electrode, the eighth electrode being disposed in each of the first circuit region and the second circuit region.

[0024] The display device may further include a third circuit region, in which pixel circuitry for a third pixel is disposed. A first conductive line and a second conductive line may extend into the third circuit region. The first conductive line may include multiple sub-conductive lines spaced apart from each other, and the region of the semiconductor layer disposed in the third circuit region that overlaps with the second electrode may be positioned between the sub-conductive lines.

[0025] The first electrode can overlap with the second conductive line.

[0026] The area where the first electrode arranged in the first circuit region overlaps with the second conductive line may be different from the area where the first electrode arranged in the second circuit region overlaps with the second conductive line.

[0027] Beneficial effects of the present invention

[0028] According to one or more of the above embodiments of this disclosure, a display device with improved display quality can be provided. However, the scope of this disclosure is not limited to the effects described above. Attached Figure Description

[0029] Figure 1a and Figure 1b This is a schematic diagram of a display device according to an embodiment.

[0030] Figure 2 This is a schematic diagram of a display device according to an embodiment.

[0031] Figure 3 This is a schematic diagram illustrating the arrangement of the emission regions of pixels according to an embodiment.

[0032] Figure 4 This is a schematic diagram of the equivalent circuit of a pixel according to an embodiment.

[0033] Figure 5 This is a schematic layout diagram showing the positions of the transistors and capacitors of the pixels according to an embodiment.

[0034] Figures 6 to 16 This is a schematic layout diagram showing the elements for each pixel of each layer.

[0035] Figure 17 It is along Figure 5 and Figure 16A schematic cross-sectional view of the pixel elements intercepted by lines Ia-Ia' and IIa-IIa'.

[0036] Figure 18 It is along Figure 5 and Figure 16 A schematic cross-sectional view of the pixel elements intercepted by lines Ib-Ib' and IIb-IIb'.

[0037] Figure 19 It is along Figure 5 and Figure 16 A schematic cross-sectional view of the pixel elements intercepted by lines Ic-Ic' and IIc-IIc'.

[0038] Figure 20 and Figure 21 This is a schematic diagram illustrating the arrangement relationship between the conductive layer and the semiconductor layer according to a comparative example.

[0039] Figure 22 This is a schematic diagram of the equivalent circuit of a pixel according to an embodiment.

[0040] Figure 23 This is a schematic layout diagram showing the positions of the transistors and capacitors of the pixels according to an embodiment.

[0041] Figures 24 to 34 This is a schematic layout diagram showing the elements for each pixel of each layer.

[0042] Figure 35 It is along Figure 23 and Figure 34 A schematic cross-sectional view of the pixel elements intercepted by lines IVa-IVa' and Va-Va'.

[0043] Figure 36 It is along Figure 23 and Figure 34 A schematic cross-sectional view of the pixel elements intercepted by lines IVb-IVb' and Vb-Vb'.

[0044] Figure 37 It is along Figure 23 and Figure 34 A schematic cross-sectional view of the pixel elements intercepted by lines IVc-IVc' and Vc-Vc'.

[0045] Figure 38 This is a schematic diagram of the equivalent circuit of a pixel according to an embodiment.

[0046] Figure 39 This is a schematic layout diagram showing the positions of the transistors and capacitors of the pixels according to an embodiment.

[0047] Figures 40 to 50This is a schematic layout diagram showing the elements for each pixel of each layer.

[0048] Figure 51 It is along Figure 39 and Figure 50 A schematic cross-sectional view of the pixel elements intercepted by lines VI-VI' and VII-VII'.

[0049] Figures 52a to 53b This is a schematic cross-sectional view showing the structure of a display element according to an embodiment.

[0050] Figure 54 This is a schematic cross-sectional view showing the structure of the pixels of a display device according to an embodiment. Detailed Implementation

[0051] The best way to carry out the present invention

[0052] According to one or more embodiments, a display device includes: a first conductive line; a first electrode disposed on and overlapping the first conductive line; a semiconductor layer disposed on and overlapping the first electrode; a second electrode disposed on the semiconductor layer and overlapping the first electrode; and a third electrode disposed on the second electrode, overlapping the second electrode, and electrically connected to the semiconductor layer and the first electrode, wherein a region of the semiconductor layer overlapping the second electrode overlaps with the first conductive line.

[0053] Embodiments of the present invention

[0054] Reference will now be made in detail to embodiments illustrated in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this respect, embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, embodiments are described below only with reference to the accompanying drawings to illustrate aspects of this description.

[0055] The term "and / or" includes all combinations of one or more of the related configurations that may be defined. For example, "A and / or B" can be understood to mean "A, B, or A and B". For the purposes of this disclosure, the phrase "at least one of A and B" can be interpreted as only A, only B, or any combination of A and B. Additionally, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z.

[0056] While this disclosure is capable of various modifications and alternative forms, embodiments thereof are illustrated by way of example in the accompanying drawings and will be described in detail herein. The effects and features of this disclosure, as well as methods for implementing these effects and features, will become apparent from the accompanying drawings and embodiments described in detail below. However, this disclosure is not limited to the embodiments disclosed below and can be implemented in various forms.

[0057] It will be understood that although the terms “first,” “second,” etc., may be used in this document to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0058] Unless the context clearly indicates otherwise, as used herein, singular expressions (e.g., “a” and “one (species / being)”) are also intended to include plural forms.

[0059] It will also be understood that the terms “comprising” and / or “having” as used herein indicate the presence of the stated features or elements, but do not preclude the presence or addition of one or more other features or elements.

[0060] It will be understood that when a layer, area, or element is referred to as being formed "on" another layer, area, or element, the layer, area, or element may be formed directly or indirectly on the other layer, area, or element. That is, for example, an intermediary layer, area, or element may exist.

[0061] In the embodiments described below, when X and Y are referred to as being connected to each other, this can include situations where X and Y are electrically connected, functionally connected, and physically connected. Furthermore, when X and Y are referred to as being connected to each other, this can indicate situations where X and Y are directly connected or indirectly connected. Here, X and Y can be objects (e.g., devices, apparatuses, circuits, wires, electrodes, terminals, conductive layers, layers, etc.). Therefore, X and Y are not limited to a specific connection relationship (e.g., the connection relationship indicated in the drawings or detailed description). Rather, X and Y may include other connection relationships besides those indicated in the drawings or detailed description.

[0062] For example, the situation where X and Y are electrically connected to each other can include the situation where X and Y are electrically grounded and directly connected to each other, and the situation where at least one device (e.g., switch, transistor, capacitor, inductor, resistor, diode, etc.) for the electrical connection between X and Y is connected between X and Y.

[0063] In the embodiments described below, the terms "on" and "off," used in relation to device states, refer to the active and inactive states of the device, respectively. The terms "on" and "off," used in relation to signals received by the device, can refer to signals configured to activate the device and signals configured to deactivate the device, respectively. The device can be activated by a high-level voltage or a low-level voltage. For example, a P-channel transistor (P-type transistor) can be activated by a low-level voltage, and an N-channel transistor (N-type transistor) can be activated by a high-level voltage. Therefore, it should be understood that the "on" voltages for P-type and N-type transistors can have opposite (low to high) voltage levels.

[0064] In the embodiments described below, the x, y, and z directions are not limited to the directions of the three axes in a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x, y, and z directions may be perpendicular to each other, or may refer to different directions that are not perpendicular to each other. Unless otherwise defined or implied herein, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined herein, terms (such as those defined in a general dictionary) should be interpreted as having a meaning consistent with their context in the relevant field and their meaning in this disclosure, and should not be interpreted in an idealized or overly formal sense.

[0065] The display device according to some embodiments of this disclosure can be a device for displaying video or still images. Electronic devices can be used as display screens for various devices such as televisions, laptop computers, monitors, billboards, and Internet of Things (IoT) devices, as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, mobile communication terminals, e-notebooks, e-book readers, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). Additionally, the display device according to embodiments can be used for wearable devices such as smartwatches, watch phones, glasses displays, and head-mounted displays (HMDs). Furthermore, the display device according to embodiments can be used as a central information display (CID) on a vehicle's dashboard or central instrument panel, an interior rearview mirror display replacing the vehicle's side mirrors, or a display mounted on the rear surface of the front seats as an entertainment device for the rear seats of a vehicle. Additionally, the display device can be a flexible device.

[0066] Figure 1a and Figure 1b This is a schematic diagram of a display device according to an embodiment. Figure 2This is a schematic diagram of the display panel 10 according to an embodiment.

[0067] refer to Figure 1a and Figure 1b The display device 1 may include a display area DA for displaying images and a peripheral area PA outside the display area DA. The display area DA may be completely surrounded by the peripheral area PA.

[0068] In a plan view, the display area DA can be rectangular. According to another embodiment, the display area DA can be a polygonal shape such as a triangle, pentagon, or hexagon, a circle, an ellipse, or an amorphous shape. The display area DA can have rounded corners. In an embodiment, such as... Figure 1a As shown, display device 1 may have a display area DA whose length in the x-direction is greater than its length in the y-direction. In another embodiment, as... Figure 1b As shown, display device 1 may have a display area DA whose length in the y direction is greater than its length in the x direction.

[0069] The display device 1 may include a display panel 10, and a cover window (not shown) protecting the display panel 10 may be arranged above the display panel 10.

[0070] Various components included in the display panel 10 can be arranged on the substrate 100. The substrate 100 and / or the display panel 10 may include a display area DA and a peripheral area PA surrounding the display area DA.

[0071] The substrate 100 may include at least one of various materials (e.g., glass, ceramic, metallic, or flexible or bendable materials). The substrate 100 may have a single-layer structure including an organic layer or a multi-layer structure including an organic layer and an inorganic layer. For example, the substrate 100 may have a stacked structure of a first substrate layer / barrier layer / second substrate layer. Each of the first and second substrate layers may be an organic layer comprising a polymer resin. The first and second substrate layers may comprise a transparent polymer resin. The barrier layer may be configured to prevent the penetration of external impurities and may include inorganic materials (such as SiN). x or SiO x (a single layer or multiple layers)

[0072] Pixels PX can be arranged in the display area DA. Gate lines GL, data lines DL, and pixels PX connected to gate lines GL and data lines DL can be arranged in the display area DA. Pixels PX can be arranged in various forms (e.g., stripe pattern, etc.). The pixels (PX) can be arranged in various patterns (such as diamond, mosaic, etc.) to create an image. Each pixel PX may include an organic light-emitting diode (OLED) as a display element (light-emitting device), and the OLED may be connected to a pixel circuit. The pixel circuit may include a transistor and at least one capacitor. Pixel PX can emit light, such as red, green, blue, or white light, through the OLED. Each pixel PX can be connected to the gate line corresponding to that pixel PX in each gate line GL and the data line corresponding to that pixel PX in each data line DL.

[0073] Each gate line GL can extend in the x-direction (row direction) and connect to a pixel PX arranged in the same row. Each gate line GL can be configured to transmit a gate signal to a pixel PX arranged in the same row. Each data line DL can extend in the y-direction (column direction) and connect to a pixel PX arranged in the same column. Each data line DL can be synchronized with the gate signal and can be configured to transmit a data signal to each pixel PX in the same column. Each pixel PX can be connected to a drive voltage line PL and can be supplied with a drive voltage ELVDD. Each drive voltage line PL can extend in the y-direction (column direction) and connect to a pixel PX arranged in the same column.

[0074] Figure 2 An example of a pixel PX connected to a gate line GL is shown. However, embodiments of this disclosure are not limited thereto. Pixel PX may be connected to one or more gate lines GL.

[0075] Each of the pixel circuits configured to drive pixel PX can be electrically connected to external circuitry arranged in the peripheral region PA. In an embodiment, the first gate drive circuit GDRV1, the second gate drive circuit GDRV2, the terminal portion PAD, the drive voltage supply line 11, the common voltage supply line 13, etc., can be arranged in the peripheral region PA.

[0076] In one embodiment, the peripheral region PA can be a non-display area where no pixels PX are arranged. In another embodiment, pixels PX can be arranged in at least one corner of the peripheral region PA to overlap with external circuitry. Therefore, unused space can be reduced, and the display area DA can be expanded.

[0077] The first gate driving circuit GDRV1 can be connected to the gate line GL and can be configured to apply a gate signal to each of the pixel circuits configured to drive the pixel PX via the gate line GL. The second gate driving circuit GDRV2 can be arranged on the opposite side of the first gate driving circuit GDRV1 relative to the display area DA, and can be approximately parallel to the first gate driving circuit GDRV1. In one embodiment, each pixel circuit of each pixel PX in the display area DA can be electrically connected to the first gate driving circuit GDRV1 and the second gate driving circuit GDRV2. In another embodiment, some pixel circuits of each pixel PX in the display area DA can be electrically connected to the first gate driving circuit GDRV1, and the remaining pixel circuits can be electrically connected to the second gate driving circuit GDRV2. The second gate driving circuit GDRV2 can be omitted.

[0078] The terminal portion PAD can be disposed on one side of the substrate 100. The terminal portion PAD can be exposed without being covered by the insulating layer and can be connected to the display circuit board 30. The display driver 32 can be disposed on the display circuit board 30.

[0079] The display driver 32 may include data driving circuitry. This data driving circuitry may be connected to a data line DL and may be configured to generate a data signal. The generated data signal may be transmitted to the pixel circuitry of pixel PX via a fan-out line FW and the data line DL connected to the fan-out line FW.

[0080] The display driver 32 may include a power supply circuit, which may be configured to supply a drive voltage ELVDD to drive voltage supply line 11 and a common voltage ELVSS to common voltage supply line 13. The drive voltage ELVDD may be applied to the pixel circuitry of pixel PX via drive voltage line PL of display area DA connected to drive voltage supply line 11, and the common voltage ELVSS may be applied to the opposite electrode of display element via common voltage supply line 13. In an embodiment, common voltage supply line 13 and / or the opposite electrode may be connected to common voltage line EL of display area DA (see [link to relevant documentation]). Figure 22 Furthermore, the common voltage ELVSS can be applied to the common voltage line EL.

[0081] The display driver 32 may include a controller, and the controller may be configured to generate control signals transmitted to the first gate drive circuit GDRV1, the second gate drive circuit GDRV2, the data drive circuit, and / or the power supply circuit.

[0082] The drive voltage supply line 11 can be connected to the terminal portion PAD and can extend in the x direction at the lower part of the display area DA. The common voltage supply line 13 can be connected to the terminal portion PAD and can have a ring shape with an open side to partially surround the display area DA.

[0083] During the process of forming pixel circuits in the display area DA of substrate 100, part or all of the first gate drive circuit GDRV1 and the second gate drive circuit GDRV2 can be directly formed in the peripheral area PA of substrate 100. Display driver 32 can be formed as an integrated circuit chip and can be disposed on display circuit board 30, which is electrically connected to terminal portion PAD disposed on one side of substrate 100. Display circuit board 30 may include flexible printed circuit board (FPCB). In another embodiment, display driver 32 can be disposed directly on substrate 100 as chip-on-glass (COG) or chip-on-plastic (COP).

[0084] In one embodiment, the transistors included in the pixel circuit of the display area DA and the transistors included in the external circuitry of the peripheral area PA (e.g., the first gate drive circuit GDRV1 and the second gate drive circuit GDRV2) can be N-type oxide thin-film transistors. The transistors included in the external circuitry of the peripheral area PA can be formed simultaneously with the transistors included in the pixel circuitry of the display area DA during the same process. In another embodiment, the transistors included in the pixel circuitry of the display area DA can be N-type oxide thin-film transistors, and the transistors included in the external circuitry of the peripheral area PA can be P-type silicon thin-film transistors.

[0085] Oxide thin-film transistors (TFTs) may include a semiconductor layer comprising an oxide. The oxide semiconductor may include Zn oxide-based materials, such as Zn oxide, In-Zn oxide, Ga-In-Zn oxide, etc. In some embodiments, the oxide semiconductor may include an In-Ga-Zn-O (IGZO) semiconductor in which metals including In and Ga are contained in ZnO. In some embodiments, the oxide semiconductor may include an In-Sn-Ga-Zn-O (ITGZO) semiconductor. In embodiments, the oxide TFT may include a low-temperature polycrystalline oxide (LTPO) TFT. Silicon TFTs may include low-temperature polycrystalline silicon (LTPS) TFTs in which the semiconductor layer comprises amorphous silicon, polycrystalline silicon, etc.

[0086] Figure 3 This is a schematic diagram illustrating the arrangement of the emission regions of pixels according to an embodiment.

[0087] refer to Figure 3The pixels PX arranged in the display area DA may include a first pixel PX1 that emits light of a first color, a second pixel PX2 that emits light of a second color, and a third pixel PX3 that emits light of a third color. For example, the first pixel PX1 may be a red pixel, the second pixel PX2 may be a green pixel, and the third pixel PX3 may be a blue pixel. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may be arranged in a repeating pattern in the x and y directions. Each of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include pixel circuitry and an organic light-emitting diode (OLED) as a display element electrically connected to the pixel circuitry.

[0088] The display area DA defined on the substrate 100 may include intersecting (or overlapping) pixel rows and columns, and may include circuit regions. Pixel rows and columns may intersect each other, and pixel circuits may be arranged in each circuit region. In an embodiment, a unit circuit region PCAu may be defined, comprising two or more circuit regions adjacent to each other in the x-direction. For example, the unit circuit region PCAu may include three circuit regions adjacent to each other in the x-direction (e.g., a first circuit region PCA1, a second circuit region PCA2, and a third circuit region PCA3). The first circuit region PCA1 may be the region where the pixel circuit of a first pixel PX1 is arranged. The second circuit region PCA2 may be the region where the pixel circuit of a second pixel PX2 is arranged. The third circuit region PCA3 may be the region where the pixel circuit of a third pixel PX3 is arranged.

[0089] Each pixel circuit arranged in the first circuit region PCA1 to the third circuit region PCA3 can be electrically connected to a display element that emits light of different colors from each other. Each pixel circuit arranged in the first circuit region PCA1 to the third circuit region PCA3 can be configured to drive the display element electrically connected to that pixel circuit. For example, a display element electrically connected to a pixel circuit arranged in the first circuit region PCA1 can emit red light. A display element electrically connected to a pixel circuit arranged in the second circuit region PCA2 can emit green light. A display element electrically connected to a pixel circuit arranged in the third circuit region PCA3 can emit blue light.

[0090] Figure 3 The pixel electrode PE and emission region EA of each of the first pixel PX1 to the third pixel PX3 are shown. The emission region EA can be a region in which the emission layer of an organic light-emitting diode (OLED) is disposed. The emission region EA can be defined by an opening in the pixel defining layer. Because the emission layer is disposed on the pixel electrode PE, Figure 3 The arrangement of the emission region EA shown can be understood as the arrangement of the pixel electrode PE or the arrangement of the pixel PX.

[0091] The emission area EA can have polygonal shapes such as quadrilateral or octagonal shapes, circular shapes, elliptical shapes, etc., and polygonal shapes can include shapes with rounded corners (vertices).

[0092] The emission region EA of the first pixel PX1 and the emission region EA of the second pixel PX2 can be arranged to be adjacent to each other in the y-direction, and the emission region EA of the third pixel PX3 can be arranged to be adjacent to the emission regions EA of the first pixel PX1 and the second pixel PX2 in the x-direction. Therefore, the emission regions EA of the first pixel PX1 and the second pixel PX2 can be arranged alternately in the y-direction on the virtual line ISL1, and the emission region EA of the third pixel PX3 can be arranged repeatedly in the y-direction on the virtual line ISL2.

[0093] The lengths of the emission regions EA in the x-direction and y-direction of each of the first pixel PX1 to the third pixel PX3 can be the same or different. For example, the emission region EA of the first pixel PX1 can be square, and the emission regions EA of the second pixel PX2 and the third pixel PX3 can be rectangular with a long side in the y-direction. The length of the emission region EA of the third pixel PX3 in the y-direction can be equal to or greater than the sum of the lengths of the emission regions EA of the first pixel PX1 and the second pixel PX2 in the y-direction.

[0094] The emission regions EA of the first pixel PX1, the second pixel PX2, and the third pixel PX3 can have different areas (sizes) than each other. In an embodiment, the emission region EA of the third pixel PX3 can have a larger area than the emission region EA of the first pixel PX1. The emission region EA of the third pixel PX3 can have a larger area than the emission region EA of the second pixel PX2. The emission region EA of the second pixel PX2 can have a larger area than the emission region EA of the first pixel PX1.

[0095] Auxiliary electrodes AE can be further arranged between the emitting regions EA. Auxiliary electrodes AE can be arranged between the emitting regions EA of the third pixel PX3. Auxiliary electrodes AE can contact the opposing electrode and / or common voltage line in the display area DA.

[0096] Figure 4 This is a schematic diagram of the equivalent circuit of a pixel according to an embodiment.

[0097] refer to Figure 4Pixel PXa may include pixel circuit PCa and an organic light-emitting diode (OLED) as a display element connected to pixel circuit PCa.

[0098] Pixel PXa can be connected to a first gate line GWL configured to transmit a first gate signal GW, a second gate line GIL configured to transmit a second gate signal GI, a third gate line GRL configured to transmit a third gate signal GR, a fourth gate line EML configured to transmit a fourth gate signal EM, a fifth gate line EMBL configured to transmit a fifth gate signal EMB, and a data line DL configured to transmit a data signal. The emission of pixel PX can be controlled by the fourth gate signal EM and the fifth gate signal EMB; therefore, the fourth gate signal EM and the fifth gate signal EMB can also be referred to as emission control signals, and the fourth gate line EML and the fifth gate line EMBL can also be referred to as emission control lines. Pixel PX can be connected to a drive voltage line PL configured to transmit a drive voltage ELVDD, a reference voltage line VRL configured to transmit a reference voltage Vref, and an initialization voltage line VL configured to transmit an initialization voltage Vint.

[0099] In an embodiment, the transistors included in the pixel circuit PCa may include N-type oxide thin-film transistors. The oxide thin-film transistors may include LTPO thin-film transistors, which include a semiconductor layer comprising an oxide layer. However, LTPO thin-film transistors are merely examples, and N-type transistors are not limited thereto. For example, the semiconductor layer included in an N-type transistor may include inorganic semiconductors (e.g., amorphous silicon, polycrystalline silicon, etc.) or organic semiconductors.

[0100] The pixel circuit PCa may include first transistors T1 to T6, a first capacitor C1, and a second capacitor C2. First transistor T1 may be a drive transistor configured to output a drive current corresponding to a data signal DATA, and second transistors T2 to T6 may be switching transistors configured to transmit signals. Depending on the voltage at the first and second terminals, the first terminal (first electrode) and the second terminal (second electrode) of each of the first transistors T1 to T6 may be a source (or source electrode) or a drain (or drain electrode). For example, depending on the voltage at the first and second terminals, the first terminal may be a drain and the second terminal may be a source, or vice versa. Hereinafter, the node to which the first gate of the first transistor T1 is connected may be defined as a first node N1, and the node to which the second terminal of the first transistor T1 is connected may be defined as a second node N2.

[0101] The first transistor T1 can be connected to the driving voltage line PL and the organic light-emitting diode (OLED). The first transistor T1 can be connected between the fifth transistor T5 and the sixth transistor T6. The first transistor T1 may include a gate, a first terminal, and a second terminal connected to the second node N2. The first transistor T1 may include a first gate connected to the first node N1. The first transistor T1 may also include a second gate connected to the second terminal of the first transistor T1. The first gate and the second gate may be arranged on different layers facing each other. For example, the first gate and the second gate of the first transistor T1 may be arranged facing each other, with a semiconductor layer between the first gate and the second gate of the first transistor T1. Hereinafter, the gate (or gate electrode) of the first transistor T1 may refer to the first gate relating to the on and off states of the first transistor T1.

[0102] The first gate of the first transistor T1 can be connected to the second terminal of the second transistor T2, the first terminal of the third transistor T3, and the first capacitor C1. The second gate of the first transistor T1 can be connected to the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The first terminal of the first transistor T1 can be connected to the driving voltage line PL through the fifth transistor T5, and the second terminal of the first transistor T1 can be connected to the pixel electrode of the organic light-emitting diode (OLED) through the sixth transistor T6. The first terminal of the first transistor T1 can be connected to the second terminal of the fifth transistor T5. The second terminal of the first transistor T1 can be connected to the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The first transistor T1 can be configured to receive a data signal DATA according to the switching operation of the second transistor T2, and can be configured to control the amount of driving current flowing to the OLED.

[0103] The second transistor T2 (write transistor) can be connected to the data line DL and the first gate of the first transistor T1. The second transistor T2 may include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1. The second terminal of the second transistor T2 can be connected to the first gate of the first transistor T1, the first terminal of the third transistor T3, and the first capacitor C1. The second transistor T2 can be turned on by a first gate signal GW transmitted through the first gate line GWL, and can be configured to electrically connect the data line DL to the first node N1 and transmit the data signal DATA transmitted through the data line DL to the first node N1.

[0104] A third transistor T3 (first initialization transistor) can be connected to the first gate of the first transistor T1 and the reference voltage line VRL. The third transistor T3 may include a gate connected to the third gate line GRL, a first terminal connected to the first node N1, and a second terminal connected to the reference voltage line VRL. The first terminal of the third transistor T3 can be connected to the first gate of the first transistor T1, the second terminal of the second transistor T2, and the first capacitor C1. The third transistor T3 can be turned on by a third gate signal GR transmitted through the third gate line GRL, and can be configured to transmit a reference voltage Vref transmitted through the reference voltage line VRL to the first node N1.

[0105] A fourth transistor T4 (the second initialization transistor) can be connected to the sixth transistor T6 and the initialization voltage line VL. The fourth transistor T4 can be connected between the organic light-emitting diode (OLED) and the initialization voltage line VL. The fourth transistor T4 may include a gate connected to the second gate line GIL, a first terminal connected to the third node N3, and a second terminal connected to the initialization voltage line VL. The first terminal of the fourth transistor T4 can be connected to the second terminal of the sixth transistor T6 and the pixel electrode of the OLED. The fourth transistor T4 can be turned on by a second gate signal GI transmitted through the second gate line GIL and can be configured to transmit the initialization voltage Vint transmitted through the initialization voltage line VL to the third node N3.

[0106] The fifth transistor T5 (the first emitter control transistor) can be connected to the drive voltage line PL and the first transistor T1. The fifth transistor T5 may include a gate connected to the fourth gate line EML, a first terminal connected to the drive voltage line PL, and a second terminal connected to the first terminal of the first transistor T1. The fifth transistor T5 can be turned on or off according to the fourth gate signal EM transmitted through the fourth gate line EML.

[0107] The sixth transistor T6 (the second emitter control transistor) can be connected to the first transistor T1 and the organic light-emitting diode (OLED). The sixth transistor T6 can be connected between the second node N2 and the third node N3. The sixth transistor T6 may include a gate connected to the fifth gate line EMBL, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. The first terminal of the sixth transistor T6 can be connected to the second terminal of the first transistor T1, the first capacitor C1, and the second capacitor C2. The second terminal of the sixth transistor T6 can be connected to the first terminal of the fourth transistor T4 and the pixel electrode of the OLED. The sixth transistor T6 can be turned on or off according to the fifth gate signal EMB transmitted through the fifth gate line EMBL.

[0108] A first capacitor C1 can be connected between the first gate of the first transistor T1 and the second terminal of the first transistor T1. The first electrode of the first capacitor C1 can be connected to the first node N1, and the second electrode of the first capacitor C1 can be connected to the second node N2. The first electrode of the first capacitor C1 can be connected to the first gate of the first transistor T1, the second terminal of the second transistor T2, and the first terminal of the third transistor T3. The second electrode of the first capacitor C1 can be connected to the second terminal and the second gate of the first transistor T1, the second electrode of the second capacitor C2, and the first terminal of the sixth transistor T6. The first capacitor C1 can be a storage capacitor and can be configured to store the threshold voltage of the first transistor T1 and the voltage corresponding to the data signal DATA.

[0109] When the third transistor T3 and the fifth transistor T5 are both turned on, the first transistor T1 can be turned on. When the voltage at the second terminal of the first transistor T1 reaches the value of the difference (Vref-Vth) between the reference voltage Vref and the threshold voltage (Vth) of the first transistor T1, the first transistor T1 can be turned off, and the voltage corresponding to the threshold voltage (Vth) of the first transistor T1 can be stored in the first capacitor C1, so that the threshold voltage (Vth) of the first transistor T1 can be compensated.

[0110] The second capacitor C2 can be connected between the drive voltage line PL and the second node N2. The first electrode of the second capacitor C2 can be connected to the drive voltage line PL. The second electrode of the second capacitor C2 can be connected to the second terminal and second gate of the first transistor T1, the second electrode of the first capacitor C1, and the first terminal of the sixth transistor T6.

[0111] The capacitance of each of the first capacitor C1 and the second capacitor C2 can vary according to the color of the light emitted by the pixel PX.

[0112] An organic light-emitting diode (OLED) can be connected to a first transistor T1 via a sixth transistor T6. The OLED may include a pixel electrode (anode) connected to a third node N3 and a opposite electrode (cathode) facing the pixel electrode, and the opposite electrode may receive a common voltage ELVSS. The opposite electrode may be a common electrode shared by all pixels PX. When the fifth transistor T5 and the sixth transistor T6 are turned on, the first transistor T1 can output a driving current that can flow through the OLED, and the OLED can emit light with a brightness or luminance corresponding to the magnitude of the driving current.

[0113] Figure 5 This is a schematic layout diagram showing the positions of the transistors and capacitors of the pixels according to an embodiment. Figures 6 to 16This is a schematic layout diagram showing the elements for each pixel of each layer. Figure 15 This is a schematic diagram illustrating the arrangement of vertical conductive lines according to an embodiment. Figure 17 It is along Figure 5 and Figure 16 A schematic cross-sectional view of the pixel elements intercepted by lines Ia-Ia' and IIa-IIa'. Figure 18 It is along Figure 5 and Figure 16 A schematic cross-sectional view of the pixel elements intercepted by lines Ib-Ib' and IIb-IIb'. Figure 19 It is along Figure 5 and Figure 16 A schematic cross-sectional view of the pixel elements intercepted by lines Ic-Ic' and IIc-IIc'.

[0114] exist Figure 5 In the first circuit region PCA1a, the second circuit region PCA2a, and the third circuit region PCA3a, the pixel circuits can correspond to Figure 4 The pixel circuit PCa of the pixel is shown in the figure.

[0115] In this embodiment, considering the emission characteristics of the first pixel PX1 to the third pixel PX3, the initialization voltages Vint supplied to the first pixel PX1 to the third pixel PX3 can be different from each other. For example, the pixel circuit PCa of the first pixel PX1 can be connected to the first-1 initialization voltage line VL11, and the pixel circuits PCa of the second pixel PX2 and the third pixel PX3 can be connected to the first-2 initialization voltage line VL12. The initialization voltage supplied to the first-1 initialization voltage line VL11 and the initialization voltage supplied to the first-2 initialization voltage line VL12 can be different from each other.

[0116] Identical devices can be arranged on each layer of the first circuit region PCA1a to the third circuit region PCA3a. In the following description, for ease of illustration and explanation, reference numerals are assigned to devices of the pixel circuit PCa arranged in the first circuit region PCA1a, and the description is given based on the first circuit region PCA1a. However, this description can also be applied to the same elements in the second circuit region PCA2a and the third circuit region PCA3a. Reference will be made below to… Figures 6 to 19 A description is provided. In the following text, the connecting electrode can be an electrode configured to electrically connect and transmit signals to conductive lines or electrodes (conductive patterns) arranged on different layers.

[0117] The first conductive layer can be disposed on the substrate 100. For example... Figure 6As shown, the first conductive layer may include conductive lines 200, a first electrode 210, and repair lines RL. In an embodiment, a barrier layer may be further disposed between the substrate 100 and the first conductive layer.

[0118] The first electrode 210 can be provided in an island shape. The first electrode 210 can be arranged adjacent to the conductive line 200 in the first circuit region PCA1a and the second circuit region PCA2a, and may not be arranged in the third circuit region PCA3a. In an embodiment, the area of ​​the first electrode 210 in the first circuit region PCA1a can be larger than the area of ​​the first electrode 210 in the second circuit region PCA2a.

[0119] Conductive line 200 may extend in the x-direction and may be arranged to pass through the first circuit region PCA1a, the second circuit region PCA2a, and the third circuit region PCA3a. Conductive line 200 may be a driving voltage line PL to which the driving voltage ELVDD is applied. In the following, conductive line 200 and driving voltage line PL may be used interchangeably. Conductive line 200 may include a main line 200m extending in the x-direction in each circuit region and a protrusion 200p1 protruding from the main line 200m in the -y direction. Conductive line 200 may also include protrusions 200p2 and 200p3 protruding in the +y direction in each of the first circuit region PCA1a and the second circuit region PCA2a.

[0120] The area of ​​the conductive line 200 can be different for each circuit region. The area of ​​the conductive line 200 can be adjusted according to the y-direction width of the main line 200m and the x-direction and y-direction widths (lengths) of the protruding portion. In the embodiment, the area of ​​the conductive line 200 in the third circuit region PCA3a can be larger than the area of ​​the conductive line 200 in the first circuit region PCA1a and the second circuit region PCA2a. The area of ​​the conductive line 200 in the second circuit region PCA2a can be larger than the area of ​​the conductive line 200 in the first circuit region PCA1a. The y-direction width w13 of the main line 200m in the third circuit region PCA3a can be larger than the y-direction width w12 of the main line 200m in the second circuit region PCA2a, and the y-direction width w12 of the main line 200m in the second circuit region PCA2a can be larger than the y-direction width w11 of the main line 200m in the first circuit region PCA1a. The y-direction width w13 of the main line 200m in the third circuit region PCA3a can be at least greater than or equal to the y-direction length of the channel region of the first transistor T1.

[0121] In the first circuit region PCA1a and the second circuit region PCA2a, the protrusion 200p2 may overlap with the data line DL. In the first circuit region PCA1a and the second circuit region PCA2a, the protrusion 200p3 may overlap with the channel region of the first transistor T1. The y-direction width w14 of the main line 200m and the protrusion 200p3 in the first circuit region PCA1a and the y-direction width w15 of the main line 200m and the protrusion 200p3 in the second circuit region PCA2a may be equal to each other, and may be at least greater than or equal to the y-direction length of the channel region of the first transistor T1.

[0122] The repair line RL can extend in the x direction and can be arranged to pass through the first circuit region PCA1a, the second circuit region PCA2a and the third circuit region PCA3a.

[0123] The first insulating layer 111 may be disposed on the substrate 100 to cover or overlap the first conductive layer, and the second conductive layer may be disposed on the first insulating layer 111. Figure 7 As shown, the second conductive layer may include a second electrode 220, a lower first gate line GWLb, a reference voltage line VRL, and a first-second initialization voltage line VL12.

[0124] The second electrode 220 can be provided as an island. The second electrode 220 can overlap with the first electrode 210 and the conductive line 200. The second electrode 220 may include the second gate electrode G12 and the source electrode of the first transistor T1. In the first circuit region PCA1a and the second circuit region PCA2a, the opening SOP overlapping with the first electrode 210 can be defined in the second electrode 220. The area of ​​the second electrode 220 can be different for each circuit region. For example, the area of ​​the second electrode 220 in the second circuit region PCA2a and the third circuit region PCA3a can be larger than the area of ​​the second electrode 220 in the first circuit region PCA1a. The area of ​​the second electrode 220 overlapping with the conductive line 200 in the second circuit region PCA2a can be larger than the area of ​​the second electrode 220 overlapping with the conductive line 200 in the first circuit region PCA1a. In the third circuit region PCA3a, the area where the second electrode 220 overlaps with the conductive line 200 can be greater than the area where the second electrode 220 overlaps with the conductive line 200 in the first circuit region PCA1a and the second circuit region PCA2a.

[0125] The lower first gate line GWLb, the reference voltage line VRL, and the first-second initialization voltage line VL12 can extend in the x direction and can be arranged to pass through the first circuit region PCA1a to the third circuit region PCA3a.

[0126] like Figure 8As shown, the second insulating layer 112 may be disposed on the first insulating layer 111 to cover or overlap the second conductive layer, and a semiconductor layer ACT comprising an oxide semiconductor may be disposed on the second insulating layer 112. The semiconductor layer ACT may include a first semiconductor layer ACT1, a second semiconductor layer ACT2, and a third semiconductor layer ACT3. The semiconductor layer ACT may include the source region, drain region, and channel region between the source and drain regions of each of the first transistor T1 to the sixth transistor T6. According to an embodiment, the source region or drain region may also be interpreted as the source electrode or drain electrode of the transistor.

[0127] Figure 10 The transistors in the first circuit region PCA1a are shown. (Reference) Figure 10 The first semiconductor layer ACT1 may include the source region S1 and drain region D1 of the first transistor T1 and the source region S5 and drain region D5 of the fifth transistor T5. The second semiconductor layer ACT2 may include the source region S2 and drain region D2 of the second transistor T2 and the source region S3 and drain region D3 of the third transistor T3. The third semiconductor layer ACT3 may include the source region S4 and drain region D4 of the fourth transistor T4 and the source region S6 and drain region D6 of the sixth transistor T6.

[0128] The third insulating layer 113 may be disposed on the second insulating layer 112 to cover the semiconductor layer ACT or overlap with the semiconductor layer ACT, and the third conductive layer may be disposed on the third insulating layer 113. Figure 9 As shown, the third conductive layer may include a third electrode 230, a fourth electrode 240, a connecting electrode 250, an upper first gate line GWLt, a second gate line GIL, a third gate line GRL, a fourth gate line EML, a fifth gate line EMBL, and / or a first-first initialization voltage line VL11.

[0129] The third electrode 230, the fourth electrode 240, and the connecting electrode 250 can be provided in an island shape. The third electrode 230, the fourth electrode 240, and the connecting electrode 250 can be arranged in each of the first circuit regions PCA1a to the third circuit regions PCA3a.

[0130] The area of ​​the third electrode 230 can be different for each circuit region. For example, the area of ​​the third electrode 230 in the second circuit region PCA2a and the third circuit region PCA3a can be larger than the area of ​​the third electrode 230 in the first circuit region PCA1a. The area where the third electrode 230 overlaps with the second electrode 220 in the second circuit region PCA2a and the third circuit region PCA3a can be larger than the area where the third electrode 230 overlaps with the second electrode 220 in the first circuit region PCA1a.

[0131] In the first circuit region PCA1a and the second circuit region PCA2a, the third electrode 230 can be electrically connected to the first electrode 210 through a contact hole 31a passing through the first insulating layer 111 to the third insulating layer 113. The contact hole 31a can be insulated from the opening SOP of the second electrode 220 and can be arranged in the opening SOP.

[0132] In the first circuit region PCA1a to the third circuit region PCA3a, the connecting electrode 250 can be electrically connected to the protruding portion 200p1 of the conductive wire 200 through the contact hole 33a passing through the first insulating layer 111 to the third insulating layer 113.

[0133] The upper first gate line GWLt, second gate line GIL, third gate line GRL, fourth gate line EML, fifth gate line EMBL and first-1 initialization voltage line VL11 can extend in the x direction and can be arranged to pass through the first circuit region PCA1a to the third circuit region PCA3a.

[0134] The upper first gate line GWLt can overlap with the lower first gate line GWLb, and can be electrically connected to the lower first gate line GWLb through the contact hole 32a passing through the second insulating layer 112 and the third insulating layer 113.

[0135] like Figure 10 As shown, the third conductive layer may include the gate electrodes G1 to G6 of the first transistor T1 to the sixth transistor T6. The gate electrodes G1 to G6 may overlap with the channel region of the semiconductor layer ACT.

[0136] refer to Figure 10 The third electrode 230 may include the first gate electrode G11 of the first transistor T1. The first gate electrode G11 may overlap with the first semiconductor layer ACT1. The fourth electrode 240 may correspond to the gate electrode G2 of the second transistor T2. The fourth electrode 240 may overlap with the second semiconductor layer ACT2. The gate electrode G3 of the third transistor T3 may be the portion of the third gate line GRL that overlaps with the second semiconductor layer ACT2. The gate electrode G4 of the fourth transistor T4 may be the portion of the second gate line GIL that overlaps with the third semiconductor layer ACT3. The gate electrode G5 of the fifth transistor T5 may be the portion of the fourth gate line EML that overlaps with the first semiconductor layer ACT1. The gate electrode G6 of the sixth transistor T6 may be the portion of the fifth gate line EML that overlaps with the third semiconductor layer ACT3.

[0137] The fourth insulating layer 114 may be disposed on the third insulating layer 113 to cover the third conductive layer or overlap the third conductive layer, and the fourth conductive layer may be disposed on the fourth insulating layer 114. For example... Figure 11aAs shown, the fourth conductive layer may include a data line DL and connecting electrodes 270, 271, 272, 273, 274, 275, 276 and 277.

[0138] For each circuit region, the data line DL can be arranged to extend in the y direction. The data line DL can be electrically connected to the drain region D2 of the second transistor T2 through contact holes 43a passing through the third insulating layer 113 and the fourth insulating layer 114.

[0139] The connecting electrode 270 may include a first region 270a overlapping with the first electrode 210 to the third electrode 230 and a second region 270b protruding from the first region 270a in the -y direction. The connecting electrode 270 can electrically connect the source region S1 of the first transistor T1 to the second gate electrode G12 of the first transistor T1 and the sixth transistor T6.

[0140] The first region 270a of the connecting electrode 270 can be electrically connected to the source region S1 of the first transistor T1 through a contact hole 42a passing through the third insulating layer 113 and the fourth insulating layer 114. The first region 270a of the connecting electrode 270 can be electrically connected to the second electrode 220 through a contact hole 41a passing through the second insulating layer 112 to the fourth insulating layer 114. Therefore, the connecting electrode 270 can correspond to the source electrode electrically connected to the source region S1 of the first transistor T1. The second electrode 220 can correspond to the second gate electrode G12 of the first transistor T1, and the second gate electrode G12 can face the first gate electrode G11 of the first transistor T1 and overlap with the channel region of the first transistor T1. When the connecting electrode 270 is connected to the second electrode 220, the second gate electrode G12 of the first transistor T1 can be electrically connected to the source region S1 of the first transistor T1.

[0141] The second region 270b of the connecting electrode 270 can be electrically connected to the drain region D6 of the sixth transistor T6 through the contact hole 50a passing through the third insulating layer 113 and the fourth insulating layer 114.

[0142] The connection electrode 271 can be electrically connected to the gate electrode G2 of the second transistor T2 through the contact hole 45a passing through the fourth insulating layer 114. The connection electrode 271 can be electrically connected to the upper first gate line GWLt through the contact hole 44a passing through the fourth insulating layer 114.

[0143] The connecting electrode 272 can be electrically connected to the source region S3 of the third transistor T3 through the contact hole 46a passing through the third insulating layer 113 and the fourth insulating layer 114, and can be electrically connected to the reference voltage line VRL through the contact hole 47a passing through the second insulating layer 112 to the fourth insulating layer 114.

[0144] The connection electrode 273 can be electrically connected to the source region S2 of the second transistor T2 and the drain region D3 of the third transistor T3 through contact holes 48a passing through the third insulating layer 113 and the fourth insulating layer 114. The connection electrode 273 can be electrically connected to the third electrode 230 through contact holes 49a passing through the fourth insulating layer 114, and can also be electrically connected to the first gate electrode G11 of the first transistor T1. The connection electrode 273 can correspond to... Figure 4 The node electrode corresponding to the first node N1. The connection electrode 273 may correspond to the bridge electrode that electrically connects at least two transistors. For example, the connection electrode 273 may correspond to the bridge electrode that connects the first gate electrode G11 of the first transistor T1, the source region S2 of the second transistor T2, and the drain region D3 of the third transistor T3.

[0145] The connecting electrode 274 can be electrically connected to the protruding portion 200p1 of the conductive line 200 through contact holes 51a passing through the first insulating layer 111 to the fourth insulating layer 114. The connecting electrode 274 can be electrically connected to the drain region D5 of the fifth transistor T5 through contact holes 52a passing through the third insulating layer 113 and the fourth insulating layer 114. Therefore, the drain region D5 of the fifth transistor T5 can be electrically connected to the conductive line 200.

[0146] The connecting electrode 275 can be electrically connected to the source region S6 of the sixth transistor T6 and the drain region D4 of the fourth transistor T4 through contact holes 53a passing through the third insulating layer 113 and the fourth insulating layer 114. The connecting electrode 275 can overlap with a portion of the repair line RL. The connecting electrode 275 can be insulated from the repair line RL, and can be electrically connected to the repair line RL later in the event of a defect in the pixel circuitry arranged in the circuit region.

[0147] In the first circuit region PCA1a, the connection electrode 276 can be electrically connected to the source region S4 of the fourth transistor T4 through a contact hole 54a passing through the third insulating layer 113 and the fourth insulating layer 114. The connection electrode 276 can be connected to the first-1 initialization voltage line VL11 through a contact hole 55a passing through the fourth insulating layer 114.

[0148] In the second circuit region PCA2a and the third circuit region PCA3a, the connecting electrode 276 can be electrically connected to the source region S4 of the fourth transistor T4 through contact holes 54a passing through the third insulating layer 113 and the fourth insulating layer 114. The connecting electrode 276 can be electrically connected to the first-second initialization voltage line VL12 through contact holes 56a passing through the second insulating layer 112 to the fourth insulating layer 114.

[0149] In some of the first circuit regions PCA1a, such as Figure 11bAs shown, the connecting electrode 276 may also have a protrusion 276p. For example, the protrusion 276p of the connecting electrode 276 may be formed only in the first vertical initialization voltage line VL11v in the vertical conductive lines described below (see...). Figure 12 In the first circuit region PCA1a arranged therein.

[0150] In the first circuit region PCA1a, the connecting electrode 277 can be electrically connected to the first-second initialization voltage line VL12 through contact holes 57a passing through the second insulating layer 112 to the fourth insulating layer 114. The connecting electrode 277 can be arranged in some of the first circuit regions PCA1a. For example, the connecting electrode 277 can be arranged only in the second vertical initialization voltage line VL12v (see below) where the vertical conductive lines described below are arranged. Figure 13 In the first circuit region PCA1a of ).

[0151] The fifth insulating layer 115 may be disposed above the fourth insulating layer 114 to cover the fourth conductive layer or overlap with the fourth conductive layer, and the fifth conductive layer may be disposed above the fifth insulating layer 115. For example... Figures 12 to 15 As shown, the fifth conductive layer may include a vertical conductive line VCL and connecting electrodes 281 and 283. For ease of illustration and explanation, Figures 12 to 14 Only a few of the lower conductive lines connected to the fifth conductive layer are shown.

[0152] The connecting electrode 281 can be electrically connected to the connecting electrode 275 through the contact hole 61a passing through the fifth insulating layer 115, and can also be electrically connected to the source region S6 of the sixth transistor T6.

[0153] The connecting electrode 283 can be electrically connected to the connecting electrode 270 through the contact hole 62a passing through the fifth insulating layer 115. The connecting electrode 283 can be arranged to cover and overlap the connecting electrode 273, which serves as a node electrode. The second electrode 220 can be arranged below the connecting electrode 273, and the connecting electrode 283 can be arranged above the connecting electrode 273. The connecting electrode 283 can completely cover the connecting electrode 273, and the second electrode 220 can completely cover the connecting electrode 273. The connecting electrode 283 can serve as an upper shielding layer for the connecting electrode 273, and the second electrode 220 can serve as a lower shielding layer for the connecting electrode 273.

[0154] The vertical conductor line VCL may include a vertical drive voltage line PLv, a first vertical initialization voltage line VL11v, a second vertical initialization voltage line VL12v, a vertical common voltage line ELv, and / or a vertical reference voltage line VRLv. Each of the vertical conductor lines VCL may extend in the y-direction and may be arranged to be spaced apart from each other in the x-direction within the first circuit region PCA1a to the third circuit region PCA3a.

[0155] Four vertical conductive lines are arranged to be spaced apart from each other in the x-direction within the first circuit region PCA1a to the third circuit region PCA3a. For example, four vertical conductive lines among the first vertical initialization voltage line VL11v, the second vertical initialization voltage line VL12v, the vertical drive voltage line PLv, the vertical common voltage line ELv, and the vertical reference voltage line VRLv can be arranged to be spaced apart from each other in the x-direction. The vertical conductive line VCL can be electrically connected to a horizontal conductive line extending in the x-direction. The horizontal conductive line may include conductive line 200 as the drive voltage line PL, the first initialization voltage line VL11, the first initialization voltage line VL12, and the reference voltage line VRL.

[0156] Figure 12 An example is shown where the first vertical initialization voltage line VL11v, a pair of vertical drive voltage lines PLv, and the vertical reference voltage line VRLv are arranged sequentially in the x-direction in the first circuit region PCA1a to the third circuit region PCA3a.

[0157] Figure 13 An example is shown where the second vertical initialization voltage line VL12v, a pair of vertical drive voltage lines PLv, and a vertical reference voltage line VRLv are arranged sequentially in the x-direction in the first circuit region PCA1a to the third circuit region PCA3a.

[0158] Figure 14 An example is shown where the second vertical initialization voltage line VL12v, the vertical drive voltage line PLv, the vertical common voltage line ELv, and the vertical reference voltage line VRLv are arranged sequentially in the x-direction in the first circuit region PCA1a to the third circuit region PCA3a.

[0159] A pair of adjacent vertical drive voltage lines PLv can be connected via a connecting portion BR. The pair of vertical drive voltage lines PLv can be integrated together. In an embodiment, the connecting portion BR can be positioned every two rows. For example, as... Figure 13 As shown, a pair of vertical drive voltage lines PLv can be connected to each other via a connection portion BR in either odd or even rows, and can be spaced apart from each other in either even or odd rows without a connection portion BR.

[0160] In an embodiment, such as Figure 15 As shown, the first vertical conductive line VCL of the unit circuit region PCAu can be either the first vertical initialization voltage line VL11v or the second vertical initialization voltage line VL12v. The fourth vertical conductive line VCL of the unit circuit region PCAu can be the vertical reference voltage line VRLv. The second and third vertical conductive lines VCL of the unit circuit region PCAu can be either a pair of vertical drive voltage lines PLv or a pair of vertical drive voltage lines PLv and a vertical common voltage line ELv.

[0161] like Figure 12 As shown, the first vertical initialization voltage line VL11v can be electrically connected to the connection electrode 276 arranged in the first circuit region PCA1a through the contact hole 63a passing through the fifth insulating layer 115. The connection electrode 276 can be electrically connected to the first initialization voltage line VL11, and the first initialization voltage line VL11 can have a mesh structure in the display region DA.

[0162] like Figure 13 As shown, the second vertical initialization voltage line VL12v can be electrically connected to the connection electrode 277 arranged in the first circuit region PCA1a through the contact hole 66a passing through the fifth insulating layer 115. The connection electrode 277 can be electrically connected to the first-second initialization voltage line VL12, and the first-second initialization voltage line VL12 can have a mesh structure in the display area DA.

[0163] like Figures 12 to 14 As shown, the vertical drive voltage line PLv can be electrically connected to the connection electrode 274 arranged in the second circuit region PCA2a through the contact hole 64a passing through the fifth insulating layer 115. The connection electrode 274 can be electrically connected to the conductive line 200, and the drive voltage line PL can have a mesh structure in the display region DA.

[0164] like Figure 14 As shown, the vertical common voltage line ELv can be electrically connected to the common voltage supply line 13 arranged in the peripheral area PA (see Figure 13). Figure 2 ).

[0165] like Figures 12 to 14 As shown, the vertical reference voltage line VRLv can be electrically connected to the connection electrode 272 arranged in the third circuit region PCA3a through the contact hole 65a passing through the fifth insulating layer 115. The connection electrode 272 can be electrically connected to the reference voltage line VRL, and the reference voltage line VRL can have a mesh structure in the display area DA.

[0166] Although not shown in the accompanying drawings, voltage supply lines electrically connected to the horizontal and / or vertical conductive lines may be further arranged in the peripheral area PA. The voltage supply lines may be arranged on at least one of the upper, lower, left, and right sides of the display area DA.

[0167] The connecting electrodes, which have the same function and correspond to the first circuit region PCA1a to the third circuit region PCA3a, can have different shapes and positions depending on the position of the lines arranged in the first circuit region PCA1a to the third circuit region PCA3a.

[0168] The sixth insulating layer 116 may be disposed above the fifth insulating layer 115 to cover the fifth conductive layer or overlap with the fifth conductive layer, and the organic light-emitting diode (OLED) may be disposed above the sixth insulating layer 116 as a display element. The organic light-emitting diode (OLED) may include a pixel electrode 511, a counter electrode 515, and an intermediate layer (or intermediary layer) between the pixel electrode 511 and the counter electrode 515.

[0169] The pixel electrode 511 can be electrically connected to the connection electrode 281, which is a lower conductive pattern, through the contact hole 71a of the sixth insulating layer 116, and therefore can be electrically connected to the first transistor T1. For example... Figure 16 As shown, the pixel electrode 511 connected to the pixel circuit of the first pixel PX1 can be electrically connected to the connection electrode 281 arranged in the first circuit region PCA1a, and therefore can be electrically connected to the first transistor T1. The pixel electrode 511 connected to the pixel circuit of the second pixel PX2 can be electrically connected to the connection electrode 281 arranged in the second circuit region PCA2a, and therefore can be electrically connected to the first transistor T1. The pixel electrode 511 connected to the pixel circuit of the third pixel PX3 can be electrically connected to the connection electrode 281 arranged in the third circuit region PCA3a, and therefore can be electrically connected to the first transistor T1.

[0170] like Figure 3 As shown, the auxiliary electrode AE ​​can be further arranged on the same layer as the pixel electrode 511. The auxiliary electrode AE ​​can be arranged between the pixel electrodes 511 of the third pixel PX3. The auxiliary electrode AE ​​can contact the opposing electrode 515 in the display area DA. In an embodiment, the auxiliary electrode AE ​​can be electrically connected to the vertical common voltage line ELv in the display area DA.

[0171] like Figures 17 to 19As shown, a seventh insulating layer 117, serving as a pixel defining layer covering the edge of the pixel electrode 511, can be disposed above the pixel electrode 511. An opening 117OP that exposes a portion of the pixel electrode 511 and defines the emission region can be defined in the seventh insulating layer 117. The seventh insulating layer 117 can be a single organic insulating layer or multiple organic insulating layers and / or a single inorganic insulating layer or multiple inorganic insulating layers.

[0172] The intermediate layer may include an emitter layer 513 and a first functional layer below the emitter layer 513 and / or a second functional layer above the emitter layer 513. The first functional layer may be a hole transport layer (HTL). As another example, the first functional layer may include a hole injection layer (HIL) and a hole transport layer (HTL). The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first and second functional layers may be integrated with each other to correspond to an organic light-emitting diode (OLED) included in the display area DA. Either the first or second functional layer may be omitted. Figure 16 The diagram shows an emission layer 513a of an organic light-emitting diode OLED1 electrically connected to a pixel circuit arranged in a first circuit region PCA1a, an emission layer 513b of an organic light-emitting diode OLED2 electrically connected to a pixel circuit arranged in a second circuit region PCA2a, and an emission layer 513c of an organic light-emitting diode OLED3 electrically connected to a pixel circuit arranged in a third circuit region PCA3a.

[0173] The opposing electrodes 515 can be integrated with each other to correspond to the organic light-emitting diodes (OLEDs) arranged in the display area DA.

[0174] refer to Figures 17 to 19 The conductive line 200 may correspond to the entire channel region CH1 of the first transistor T1 in each circuit region, and the entire channel region CH1 of the first transistor T1 may overlap with the conductive line 200.

[0175] Figure 20 and Figure 21 This is a schematic diagram illustrating the arrangement relationship between the conductive layer and the semiconductor layer according to a comparative example. Figure 20 and Figure 21In the comparative example shown, the conductive line 200' may correspond to a portion of the channel region CH1 of the first transistor T1, and said portion of the channel region CH1 of the first transistor T1 may overlap with the conductive line 200'. Due to the step formed between the region where the conductive line 200' is arranged and the region where the conductive line 200' is not arranged, the channel region CH1 of the first transistor T1 included in the first semiconductor layer ACT1 may be completely or partially disconnected in region X. Because the output current of the first transistor T1 varies depending on the degree of disconnection of the channel region CH1 of the first transistor T1, short-range uniformity (SRU) degradation and granular spots or dark spots may occur.

[0176] According to embodiments of this disclosure, since the conductive line 200 is arranged to at least correspond to the channel region CH1 of the first transistor T1, the disconnection of the channel region CH1 of the first transistor T1 can be minimized (prevented).

[0177] According to embodiments of this disclosure, the ratio of the first capacitor C1 to the second capacitor C2 for each pixel can be optimized by adjusting the degree of overlap between the conductive line 200 and the second electrode 220, the separation distance between the conductive line 200 and the first electrode 210, and the size of the conductive line 200 and / or the first electrode 210 and / or the width of the conductive line 200 and / or the first electrode 210 in the y direction.

[0178] Return to reference Figure 17 and Figure 18 The first capacitor C1 of the first pixel PX1 and the second pixel PX2 may include a first electrode C11 and a second electrode C12. The first electrode C11 may include a lower first electrode C11b formed by the first electrode 210, an intermediate first electrode (or intervening first electrode) C11m formed by the third electrode 230, and an upper first electrode C11t formed by the connecting electrode 273. The lower first electrode C11b and the intermediate first electrode C11m may be electrically connected to each other through a contact hole 31a, and the intermediate first electrode C11m and the upper first electrode C11t may be electrically connected to each other through a contact hole 49a. The second electrode C12 may include a lower second electrode C12b formed by the second electrode 220, an intermediate second electrode (or intervening second electrode) C12m formed by the connecting electrode 270, and an upper second electrode C12t formed by the connecting electrode 283. The lower second electrode C12b and the middle second electrode C12m can be electrically connected to each other through the contact hole 41a, and the middle second electrode C12m and the upper second electrode C12t can be electrically connected to each other through the contact hole 62a.

[0179] The capacitance of the first capacitor C1 can be the sum of the capacitance formed by the lower first electrode C11b and the lower second electrode C12b, the capacitance formed by the lower second electrode C12b and the intermediate first electrode C11m, the capacitance formed by the intermediate first electrode C11m and the intermediate second electrode C12m, and the capacitance formed by the upper first electrode C11t and the upper second electrode C12t. The first capacitor C1 can have a structure in which sub-capacitors formed by conductive lines overlapping each other in the z-direction are connected in parallel, and thus can have (obtain) increased capacitance without increasing the area in the x and y directions.

[0180] The y-direction width wc1 of the lower first electrode C11b of the first capacitor C1 of the first pixel PX1 can be greater than the y-direction width wc1 of the lower first electrode C11b of the first capacitor C1 of the second pixel PX2. The overlap area between the lower first electrode C11b and the lower second electrode C12b of the first capacitor C1 of the second pixel PX2 can be greater than the overlap area between the lower first electrode C11b and the lower second electrode C12b of the first capacitor C1 of the first pixel PX1. The sum of the overlap area between the lower second electrode C12b and the middle first electrode C11m of the first capacitor C1 of the second pixel PX2 and the overlap area between the middle first electrode C11m and the middle second electrode C12m of the first capacitor C1 of the second pixel PX2 can be greater than the sum of the overlap area between the lower second electrode C12b and the middle first electrode C11m of the first capacitor C1 of the first pixel PX1 and the overlap area between the middle first electrode C11m and the middle second electrode C12m of the first capacitor C1 of the first pixel PX1.

[0181] The second capacitor C2 of the first pixel PX1 and the second pixel PX2 may include a first electrode C21 formed by conductive line 200 and a second electrode C22 formed by second electrode 220. The area where the second electrode 220 overlaps with the conductive line 200 in the second circuit region PCA2a can be larger than the area where the second electrode 220 overlaps with the conductive line 200 in the first circuit region PCA1a. Therefore, the capacitance of the second capacitor C2 of the second pixel PX2 can be larger than the capacitance of the second capacitor C2 of the first pixel PX1.

[0182] refer to Figure 19The first capacitor C1 of the third pixel PX3 can be formed between the third electrode 230 and the connecting electrode 270, between the second electrode 220 and the third electrode 230, and between the connecting electrode 273 and the connecting electrode 283. The first capacitor C1 of the first pixel PX1 can include a first electrode C11 and a second electrode C12. The first electrode C11 can include an intermediate first electrode C11m formed by the third electrode 230 and an upper first electrode C11t formed by the connecting electrode 273. The intermediate first electrode C11m and the upper first electrode C11t can be electrically connected to each other through a contact hole 49a. The second electrode C12 can include a lower second electrode C12b formed by the second electrode 220, an intermediate second electrode C12m formed by the connecting electrode 270, and an upper second electrode C12t formed by the connecting electrode 283. The lower second electrode C12b and the intermediate second electrode C12m can be electrically connected to each other through a contact hole 41a, and the intermediate second electrode C12m and the upper second electrode C12t can be electrically connected to each other through a contact hole 62a.

[0183] The capacitance of the first capacitor C1 can be the sum of the capacitance formed by the lower second electrode C12b and the intermediate first electrode C11m, the capacitance formed by the intermediate first electrode C11m and the intermediate second electrode C12m, and the capacitance formed by the upper first electrode C11t and the upper second electrode C12t. The first capacitor C1 can have a structure in which sub-capacitors formed by conductive lines overlapping each other in the z-direction are connected in parallel, and thus can have (obtain) increased capacitance without increasing the area in the x and y directions.

[0184] The second capacitor C2 of the third pixel PX3 may include a first electrode C21 formed by conductive line 200 and a second electrode C22 formed by second electrode 220. The area where the second electrode 220 overlaps with the conductive line 200 in the third circuit region PCA3a can be larger than the area where the second electrode 220 overlaps with the conductive line 200 in the first circuit region PCA1a and the second circuit region PCA2a. Therefore, the capacitance of the second capacitor C2 of the third pixel PX3 can be larger than the capacitance of the second capacitor C2 of the first pixel PX1 and the second pixel PX2.

[0185] Figure 22 This is a schematic diagram of the equivalent circuit of a pixel according to an embodiment.

[0186] refer to Figure 22 ,Apart from Figure 4 In addition to the pixel circuit PCa of pixel PXa shown in the diagram, the pixel circuit PCb of pixel PXb may also include a third capacitor C3. Other configurations and operations can be related to... Figure 4 The configuration and operation of the pixel PXa shown are basically the same.

[0187] The third capacitor C3 can be connected between the second node N2 and the common voltage line EL supplied by the common voltage ELVSS. The first electrode of the third capacitor C3 can be connected to the common voltage line EL. The second electrode of the third capacitor C3 can be connected to the second terminal and second gate of the first transistor T1, the second electrode of the first capacitor C1, the second electrode of the second capacitor C2, the first terminal of the fourth transistor T4, and the first terminal of the sixth transistor T6.

[0188] The capacitance of each of the first capacitor C1, the second capacitor C2, and the third capacitor C3 can vary according to the color of the light emitted from the pixel PXb.

[0189] Figure 23 This is a schematic layout diagram showing the positions of the transistors and capacitors of the pixels according to an embodiment. Figures 24 to 34 This is a schematic layout diagram showing the elements for each pixel of each layer. Figure 33 This is a schematic diagram illustrating the arrangement of vertical conductive lines according to an embodiment. Figure 35 It is along Figure 23 and Figure 34 A schematic cross-sectional view of the pixel elements intercepted by lines IVa-IVa' and Va-Va'. Figure 36 It is along Figure 23 and Figure 34 A schematic cross-sectional view of the pixel elements intercepted by lines IVb-IVb' and Vb-Vb'. Figure 37 It is along Figure 23 and Figure 34 A schematic cross-sectional view of the pixel elements intercepted by lines IVc-IVc' and Vc-Vc'.

[0190] exist Figure 23 In the process, the pixel circuits arranged in the first circuit region PCA1b, the second circuit region PCA2b, and the third circuit region PCA3b can correspond to Figure 22 The pixel circuit PCb of the pixel is shown in the figure.

[0191] In this embodiment, the pixel circuit PCb of the first pixel PX1 can be connected to the first-1 initialization voltage line VL11, and the pixel circuit PCb of the second pixel PX2 and the pixel circuit PCb of the third pixel PX3 can be connected to the first-2 initialization voltage line VL12. The initialization voltage supplied to the first-1 initialization voltage line VL11 and the initialization voltage supplied to the first-2 initialization voltage line VL12 can be different from each other.

[0192] In the following description, for ease of illustration and explanation, reference numerals are assigned to devices of the pixel circuit PCb arranged in the first circuit region PCA1b, and the description is given based on the first circuit region PCA1b. However, this description can also be applied to the same elements in the second circuit region PCA2b and the third circuit region PCA3b. Reference will be made below to... Figures 24 to 37 Provide a description.

[0193] The first conductive layer can be disposed on the substrate 100. For example... Figure 24 As shown, the first conductive layer may include a first conductive line 300a, a second conductive line 300b, a first electrode 310, and a repair line RL. In an embodiment, a barrier layer may be further disposed between the substrate 100 and the first conductive layer.

[0194] The first electrode 310 can be provided in an island shape. The first electrode 310 can be arranged in a plan view between the first conductive line 300a and the second conductive line 300b in the first circuit region PCA1b and the second circuit region PCA2b, and may not be arranged in the third circuit region PCA3b. The area of ​​the first electrode 310 in the second circuit region PCA2b may be different from the area of ​​the first electrode 310 in the first circuit region PCA1b. In an embodiment, the area of ​​the first electrode 310 in the second circuit region PCA2b may be larger than the area of ​​the first electrode 310 in the first circuit region PCA1b.

[0195] The first conductive line 300a may extend in the x-direction and be arranged to pass through the first circuit region PCA1b, the second circuit region PCA2b, and the third circuit region PCA3b. The first conductive line 300a may be a driving voltage line PL to which the driving voltage ELVDD is applied. The first conductive line 300a may include sub-lines 300as that are disconnected and separated from each other at specific intervals. The sub-lines 300as may be spaced apart from each other in the x-direction. In an embodiment, the sub-lines 300as may be spaced apart from each other at a specific distance SL in a plan view within the first circuit region PCA1b and the first semiconductor layer ACT1 (see...) Figure 26 The sub-lines 300as are located between the sub-lines 300as. Therefore, the sub-lines 300as can be located in the first circuit region PCA1b without overlapping with the first semiconductor layer ACT1.

[0196] Each sub-line 300as may include a main line 300am extending in the x-direction and a protrusion 300ap1 extending from the main line 300am in the -y-direction. The protrusion 300ap1 may overlap with the data line DL in each circuit region. The sub-line 300as may also include a protrusion 300ap2 extending in the +y-direction in the second circuit region PCA2b and the third circuit region PCA3b. In each of the second circuit region PCA2b and the third circuit region PCA3b, the main line 300am and the protrusion 300ap2 may overlap with the first semiconductor layer ACT1. In each of the second circuit region PCA2b and the third circuit region PCA3b, the main line 300am and the protrusion 300ap2 may overlap at least with the channel region of the first transistor T1. In an embodiment, the x-direction width w25 of the protrusion 300ap2 in the third circuit region PCA3b may be greater than the x-direction width w24 of the protrusion 300ap2 in the second circuit region PCA2b.

[0197] For each circuit region, the area of ​​the first conductive line 300a can be different. For example, the area of ​​the first conductive line 300a in the third circuit region PCA3b can be larger than the area of ​​the first conductive line 300a in the first circuit region PCA1b and the second circuit region PCA2b. The area of ​​the first conductive line 300a in the second circuit region PCA2b can be larger than the area of ​​the first conductive line 300a in the first circuit region PCA1b. In an embodiment, the y-direction width w23 of the main line 300am in the third circuit region PCA3b can be larger than the y-direction width w22 of the main line 300am in the second circuit region PCA2b and the y-direction width w21 of the main line 300am in the first circuit region PCA1b, and the y-direction width w21 of the main line 300am in the first circuit region PCA1b can be larger than the y-direction width w22 of the main line 300am in the second circuit region PCA2b.

[0198] The second conductive line 300b may extend in the x-direction and may be arranged to pass through the first circuit region PCA1b, the second circuit region PCA2b, and the third circuit region PCA3b. The second conductive line 300b may be the common voltage line EL to which the common voltage ELVSS is applied. In the following, the second conductive line 300b and the common voltage line EL may be used interchangeably. The second conductive line 300b may be arranged parallel to the first conductive line 300a. The second conductive line 300b may include a main line 300bm extending in the x-direction in each circuit region and a protrusion 300bp1 protruding from the main line 300bm in the -y direction. The main line 300bm may have bends and may extend in the x-direction. The protrusion 300bp1 may overlap with the data line DL in each circuit region. The second conductive line 300b may also include a protrusion 300bp2 protruding in the -y direction in the third circuit region PCA3b. In the third circuit region PCA3b, the protrusion 300bp2 can be spaced apart from the protrusion 300bp1 in the plan view, and the protrusion 300ap2 of the first conductive line 300a is between the protrusion 300bp2 and the protrusion 300bp1.

[0199] The repair line EL can extend in the x direction and can be arranged to pass through the first circuit region PCA1b, the second circuit region PCA2b and the third circuit region PCA3b.

[0200] The first insulating layer 111 may be disposed on the substrate 100 to cover or overlap the first conductive layer, and the second conductive layer may be disposed on the first insulating layer 111. Figure 25 As shown, the second conductive layer may include a second electrode 320, a lower first gate line GWLb, a reference voltage line VRL, and / or a first-second initialization voltage line VL12.

[0201] The second electrode 320 can be provided as an island. The second electrode 320 can partially overlap with the first conductive line 300a and the second conductive line 300b. In the first circuit region PCA1b and the second circuit region PCA2b, the second electrode 320 can overlap with the first electrode 310. In the third circuit region PCA3b, the second electrode 320 can overlap with a protrusion 300bp2 of the second conductive line 300b. The second electrode 320 can include the second gate electrode G12 and the source electrode of the first transistor T1. In the first circuit region PCA1b and the second circuit region PCA2b, the opening SOP overlapping with the first electrode 310 can be defined in the second electrode 320. The area of ​​the second electrode 320 can be different for each circuit region. In an embodiment, the area of ​​the second electrode 320 in the third circuit region PCA3b can be larger than the area of ​​the second electrode 320 in the first circuit region PCA1b, and the area of ​​the second electrode 320 in the first circuit region PCA1b can be larger than the area of ​​the second electrode 320 in the second circuit region PCA2b. In the second circuit region PCA2b, the area where the second electrode 320 overlaps with the first electrode 310 can be larger than the area where the second electrode 320 overlaps with the first electrode 310 in the first circuit region PCA1b.

[0202] The lower first gate line GWLb, the reference voltage line VRL, and the first-second initialization voltage line VL12 can extend in the x direction and can be arranged to pass through the first circuit region PCA1b, the second circuit region PCA2b, and the third circuit region PCA3b.

[0203] The second insulating layer 112 may be disposed on the first insulating layer 111 to cover the second conductive layer or overlap with the second conductive layer, and as follows: Figure 26 As shown, a semiconductor layer ACT, including an oxide semiconductor, can be disposed on the second insulating layer 112. The semiconductor layer ACT may include a first semiconductor layer ACT1, a second semiconductor layer ACT2, and / or a third semiconductor layer ACT3. The semiconductor layer ACT may include a source region, a drain region, and a channel region between the source and drain regions of each of the first transistor T1 to the sixth transistor T6. According to an embodiment, the source region or drain region may also be interpreted as the source electrode or drain electrode of the transistor.

[0204] Figure 28 The transistors in the first circuit region PCA1b are shown. (Reference) Figure 28The first semiconductor layer ACT1 may include the source region S1 and drain region D1 of the first transistor T1 and the source region S5 and drain region D5 of the fifth transistor T5. The second semiconductor layer ACT2 may include the source region S2 and drain region D2 of the second transistor T2 and the source region S3 and drain region D3 of the third transistor T3. The third semiconductor layer ACT3 may include the source region S4 and drain region D4 of the fourth transistor T4 and the source region S6 and drain region D6 of the sixth transistor T6.

[0205] The third insulating layer 113 may be disposed on the second insulating layer 112 to cover the semiconductor layer ACT or overlap with the semiconductor layer ACT, and the third conductive layer may be disposed on the third insulating layer 113. Figure 27 As shown, the third conductive layer may include a third electrode 330, a fourth electrode 340, connecting electrodes 350 and 360, an upper first gate line GWLt, a second gate line GIL, a third gate line GRL, a fourth gate line EML, a fifth gate line EMBL, and / or a first-first initialization voltage line VL11.

[0206] The third electrode 330, the fourth electrode 340, and the connecting electrodes 350 and 360 can be provided in an island configuration. The third electrode 330, the fourth electrode 340, and the connecting electrode 350 can be arranged in each of the first circuit regions PCA1b to the third circuit regions PCA3b. The connecting electrode 360 ​​can be arranged in some of the first circuit regions PCA1b, the second circuit region PCA2b, and the third circuit region PCA3b. For example, as... Figure 27 As shown, the connection electrode 360 ​​can be arranged between the second circuit region PCA2b and the third circuit region PCA3b. A portion of the connection electrode 360 ​​can overlap with the data line DL. A portion of the connection electrode 360 ​​can overlap with the first conductive line 300a.

[0207] The area of ​​the third electrode 330 in the first circuit region PCA1b and the third circuit region PCA3b can be larger than the area of ​​the third electrode 330 in the second circuit region PCA2b. The area where the third electrode 330 overlaps with the second electrode 320 in the first circuit region PCA1b and the third circuit region PCA3b can be larger than the area where the third electrode 330 overlaps with the second electrode 320 in the second circuit region PCA2b.

[0208] In the first circuit region PCA1b and the second circuit region PCA2b, the third electrode 330 can be electrically connected to the first electrode 310 through a contact hole 31b passing through the first insulating layer 111 to the third insulating layer 113. The contact hole 31b can be insulated from the opening SOP of the second electrode 320 and can be positioned within the opening SOP.

[0209] In the first circuit region PCA1b to the third circuit region PCA3b, the connecting electrode 350 can be electrically connected to the protruding portion 300ap1 of the first conductive line 300a through the contact hole 33b passing through the first insulating layer 111 to the third insulating layer 113.

[0210] Between the second circuit region PCA2b and the third circuit region PCA3b, the connecting electrode 360 ​​can be electrically connected to the protruding portion 300bp1 of the second conductive line 300b through the contact hole 34b passing through the first insulating layer 111 to the third insulating layer 113.

[0211] The upper first gate line GWLt, second gate line GIL, third gate line GRL, fourth gate line EML, fifth gate line EMBL and first initialization voltage line VL11 can extend in the x direction and can be arranged to pass through the first circuit region PCA1b to the third circuit region PCA3b.

[0212] The upper first gate line GWLt can overlap with the lower first gate line GWLb, and can be electrically connected to the lower first gate line GWLb through the contact hole 32b passing through the second insulating layer 112 and the third insulating layer 113.

[0213] like Figure 28 As shown, the third conductive layer may include the gate electrodes G1 to G6 of the first transistor T1 to the sixth transistor T6. The gate electrodes G1 to G6 may overlap with the channel region of the semiconductor layer ACT.

[0214] refer to Figure 28 The third electrode 330 may include the first gate electrode G11 of the first transistor T1. The first gate electrode G11 may overlap with the first semiconductor layer ACT1. The fourth electrode 340 may correspond to the gate electrode G2 of the second transistor T2. The fourth electrode 340 may overlap with the second semiconductor layer ACT2. The gate electrode G3 of the third transistor T3 may be the portion of the third gate line GRL that overlaps with the second semiconductor layer ACT2. The gate electrode G4 of the fourth transistor T4 may be the portion of the second gate line GIL that overlaps with the third semiconductor layer ACT3. The gate electrode G5 of the fifth transistor T5 may be the portion of the fourth gate line EML that overlaps with the first semiconductor layer ACT1. The gate electrode G6 of the sixth transistor T6 may be the portion of the fifth gate line EML that overlaps with the third semiconductor layer ACT3.

[0215] The fourth insulating layer 114 may be disposed on the third insulating layer 113 to cover the third conductive layer or overlap the third conductive layer, and the fourth conductive layer may be disposed on the fourth insulating layer 114. For example... Figure 29aAs shown, the fourth conductive layer may include a data line DL and connecting electrodes 370, 371, 372, 373, 374, 375, 376, 377 and 378.

[0216] For each circuit region, the data line DL can be arranged to extend in the y direction. The data line DL can be electrically connected to the drain region D2 of the second transistor T2 through the contact hole 43b passing through the third insulating layer 113 and the fourth insulating layer 114.

[0217] The connecting electrode 370 may include a first region 370a overlapping with the first electrode 310 to the third electrode 330 and a second region 370b protruding from the first region 370a in the -y direction. The connecting electrode 370 can electrically connect the source region S1 of the first transistor T1 to the second gate electrode G12 of the first transistor T1 and the sixth transistor T6.

[0218] The first region 370a of the connecting electrode 370 can be electrically connected to the source region S1 of the first transistor T1 through a contact hole 42b passing through the third insulating layer 113 and the fourth insulating layer 114. The first region 370a of the connecting electrode 370 can be electrically connected to the second electrode 320 through a contact hole 41b passing through the second insulating layer 112 to the fourth insulating layer 114. Therefore, the connecting electrode 370 can correspond to the source electrode electrically connected to the source region S1 of the first transistor T1. The second electrode 320 can correspond to the second gate electrode G12 of the first transistor T1, and the second gate electrode G12 can face the first gate electrode G11 of the first transistor T1 and overlap with the channel region of the first transistor T1. When the connecting electrode 370 is connected to the second electrode 320, the second gate electrode G12 of the first transistor T1 can be electrically connected to the source region S1 of the first transistor T1.

[0219] The second region 370b of the connecting electrode 370 can be electrically connected to the drain region D6 of the sixth transistor T6 through the contact hole 50b passing through the third insulating layer 113 and the fourth insulating layer 114.

[0220] The connection electrode 371 can be electrically connected to the gate electrode G2 of the second transistor T2 through the contact hole 45b passing through the fourth insulating layer 114. The connection electrode 371 can be electrically connected to the upper first gate line GWLt through the contact hole 44b passing through the fourth insulating layer 114.

[0221] The connecting electrode 372 can be electrically connected to the source region S3 of the third transistor T3 through the contact hole 46b passing through the third insulating layer 113 and the fourth insulating layer 114, and can be electrically connected to the reference voltage line VRL through the contact hole 47b passing through the second insulating layer 112 to the fourth insulating layer 114.

[0222] The connection electrode 373 can be electrically connected to the source region S2 of the second transistor T2 and the drain region D3 of the third transistor T3 through contact holes 48b passing through the third insulating layer 113 and the fourth insulating layer 114. The connection electrode 373 can be electrically connected to the third electrode 330 through contact holes 49b passing through the fourth insulating layer 114, and can also be electrically connected to the first gate electrode G11 of the first transistor T1. The connection electrode 373 can correspond to... Figure 22 The node electrode corresponding to the first node N1. The connection electrode 373 may correspond to a bridge electrode that electrically connects at least two transistors. For example, the connection electrode 373 may correspond to a bridge electrode that connects the first gate electrode G11 of the first transistor T1, the source region S2 of the second transistor T2, and the drain region D3 of the third transistor T3.

[0223] The connecting electrode 374 can be electrically connected to the protruding portion 300p1 of the first conductive line 300a through contact holes 51b passing through the first insulating layer 111 to the fourth insulating layer 114. The connecting electrode 374 can be electrically connected to the drain region D5 of the fifth transistor T5 through contact holes 52b passing through the third insulating layer 113 and the fourth insulating layer 114. Therefore, the drain region D5 of the fifth transistor T5 can be electrically connected to the first conductive line 300a.

[0224] In some of the first circuit regions PCA1b, such as Figure 29b As shown, the connecting electrode 374 may also have a protrusion 374p. For example, the protrusion 374p of the connecting electrode 374 may be formed only in the vertical drive voltage line PLv within the vertical conductive lines described below (see...). Figure 30 In the first circuit region PCA1b arranged therein.

[0225] The connecting electrode 375 can be electrically connected to the source region S6 of the sixth transistor T6 and the drain region D4 of the fourth transistor T4 through contact holes 53b passing through the third insulating layer 113 and the fourth insulating layer 114. The connecting electrode 375 can overlap with a portion of the repair line RL. The connecting electrode 375 can be insulated from the repair line RL, and can be electrically connected to the repair line RL later in the event of a defect in the pixel circuitry arranged in the circuit region.

[0226] In the first circuit region PCA1b, the connection electrode 376 can be electrically connected to the source region S4 of the fourth transistor T4 through the contact hole 54b passing through the third insulating layer 113 and the fourth insulating layer 114. The connection electrode 376 can be connected to the first-1 initialization voltage line VL11 through the contact hole 55b passing through the fourth insulating layer 114.

[0227] In the second circuit region PCA2b and the third circuit region PCA3b, the connection electrode 376 can be electrically connected to the source region S4 of the fourth transistor T4 through contact holes 54b passing through the third insulating layer 113 and the fourth insulating layer 114. The connection electrode 376 can be electrically connected to the first-second initialization voltage line VL12 through contact holes 56b passing through the second insulating layer 112 to the fourth insulating layer 114.

[0228] In some of the first circuit regions PCA1b, such as Figure 29c As shown, the connecting electrode 376 may also have a protrusion 376p. For example, the protrusion 376p of the connecting electrode 376 may be formed only in the first vertical initialization voltage line VL11v in the vertical conductive lines described below (see...). Figure 31 In the first circuit region PCA1b arranged therein.

[0229] In the first circuit region PCA1b, the connecting electrode 377 can be electrically connected to the first-second initialization voltage line VL12 through contact holes 57b passing through the second insulating layer 112 to the fourth insulating layer 114. The connecting electrode 377 can be arranged in some of the first circuit regions PCA1b. For example, the connecting electrode 377 can be arranged only in the second vertical initialization voltage line VL12v (see below) where the vertical conductive lines described below are arranged. Figure 32 In the first circuit region PCA1b of ).

[0230] In the second circuit region PCA2b, the connecting electrode 378 can be electrically connected to the connecting electrode 360 ​​through the contact hole 57b passing through the fourth insulating layer 114.

[0231] The fifth insulating layer 115 may be disposed above the fourth insulating layer 114 to cover the fourth conductive layer or overlap with the fourth conductive layer, and the fifth conductive layer may be disposed above the fifth insulating layer 115. For example... Figures 30 to 33 As shown, the fifth conductive layer may include a vertical conductive line VCL and connecting electrodes 381 and 383. For ease of illustration and explanation, Figures 30 to 32 Only a few of the lower conductive lines connected to the fifth conductive layer are shown.

[0232] The connecting electrode 381 can be electrically connected to the connecting electrode 375 through the contact hole 61b passing through the fifth insulating layer 115, and can also be electrically connected to the source region S6 of the sixth transistor T6.

[0233] The connecting electrode 383 can be electrically connected to the connecting electrode 370 through the contact hole 62b passing through the fifth insulating layer 115. The connecting electrode 383 can be arranged to cover and overlap the connecting electrode 373, which serves as a node electrode. The second electrode 320 can be arranged below the connecting electrode 373, and the connecting electrode 383 can be arranged above the connecting electrode 373. The connecting electrode 383 can completely cover the connecting electrode 373, and the second electrode 320 can completely cover the connecting electrode 373. The connecting electrode 383 can serve as an upper shielding layer for the connecting electrode 373, and the second electrode 320 can serve as a lower shielding layer for the connecting electrode 373.

[0234] The vertical conductor line VCL may include a vertical drive voltage line PLv, a first vertical initialization voltage line VL11v, a second vertical initialization voltage line VL12v, a vertical common voltage line ELv, and a vertical reference voltage line VRLv. Each of the vertical conductor lines VCL may extend in the y-direction and may be arranged to be spaced apart from each other in the x-direction within the first circuit region PCA1b to the third circuit region PCA3b.

[0235] Four vertical conductive lines can be arranged to be spaced apart from each other in the x-direction within the first circuit region PCA1b to the third circuit region PCA3b. For example, four vertical conductive lines among the first vertical initialization voltage line VL11v, the second vertical initialization voltage line VL12v, the vertical drive voltage line PLv, the vertical common voltage line ELv, and the vertical reference voltage line VRLv can be arranged to be spaced apart from each other in the x-direction. The vertical conductive line VCL can be electrically connected to a horizontal conductive line extending in the x-direction. The horizontal conductive line can include a first conductive line 300a as the drive voltage line PL, a second conductive line 300b as the common voltage line EL, a first-first initialization voltage line VL11, a first-second initialization voltage line VL12, and a reference voltage line VRL.

[0236] Figure 30 An example is shown where the vertical drive voltage line PLv, a pair of vertical common voltage lines ELv, and the vertical reference voltage line VRLv are arranged sequentially in the x-direction in the first circuit region PCA1b to the third circuit region PCA3b.

[0237] Figure 31 An example is shown where the first vertical initialization voltage line VL11v, a pair of vertical drive voltage lines PLv, and the vertical reference voltage line VRLv are arranged sequentially in the x-direction in the first circuit region PCA1b to the third circuit region PCA3b.

[0238] Figure 32An example is shown where the second vertical initialization voltage line VL12v, the vertical drive voltage line PLv, the vertical common voltage line ELv, and the vertical reference voltage line VRLv are arranged sequentially in the x-direction in the first circuit region PCA1b to the third circuit region PCA3b.

[0239] A pair of adjacent vertical drive voltage lines PLv can be connected via a connecting portion BR. The pair of vertical drive voltage lines PLv can be integrated as a single unit. In an embodiment, the connecting portions BR can be arranged in two rows. For example, as... Figure 31 As shown, a pair of vertical drive voltage lines PLv can be connected to each other via a connection portion BR in either odd or even rows, and can be spaced apart from each other in either even or odd rows without a connection portion BR.

[0240] In an embodiment, such as Figure 33 As shown, the first vertical conductive line VCL of the unit circuit region PCAu can be a first vertical initialization voltage line VL11v, a second vertical initialization voltage line VL12v, or a vertical drive voltage line PLv. The fourth vertical conductive line VCL of the unit circuit region PCAu can be a vertical reference voltage line VRLv. The second and third vertical conductive lines VCL of the unit circuit region PCAu can be a pair of vertical drive voltage lines PLv, a pair of vertical common voltage lines PLv, or a pair of vertical drive voltage lines PLv and a vertical common voltage line ELv.

[0241] like Figure 30 As shown, the vertical drive voltage line PLv can be electrically connected to the connection electrode 374 arranged in the first circuit region PCA1b through the contact hole 67b passing through the fifth insulating layer 115. Figure 31 As shown, the vertical drive voltage line PLv can be electrically connected to the connection electrode 374 arranged in the second circuit region PCA2b through the contact hole 64b passing through the fifth insulating layer 115. The connection electrode 374 is electrically connected to the first conductive line 300a, and the drive voltage line PL can have a mesh structure in the display region DA.

[0242] like Figure 31 As shown, the first vertical initialization voltage line VL11v can be electrically connected to the connection electrode 376 arranged in the first circuit region PCA1b through the contact hole 63b passing through the fifth insulating layer 115. The connection electrode 376 is electrically connected to the first initialization voltage line VL11, and the first initialization voltage line VL11 can have a mesh structure in the display region DA.

[0243] like Figure 32As shown, the second vertical initialization voltage line VL12v can be electrically connected to the connection electrode 377 arranged in the first circuit region PCA1b through the contact hole 66b passing through the fifth insulating layer 115. The connection electrode 377 is electrically connected to the first-second initialization voltage line VL12, and the first-second initialization voltage line VL12 can have a mesh structure in the display region DA.

[0244] like Figure 30 and Figure 32 As shown, the vertical common voltage line ELv can be electrically connected to the connection electrode 378 arranged in the second circuit region PCA2b through the contact hole 66b passing through the fifth insulating layer 115. The connection electrode 378 is electrically connected to the second conductive line 300b, which serves as the common voltage line EL, and the common voltage line EL can have a mesh structure in the display region DA. In an embodiment, the vertical common voltage line ELv can be electrically connected to the common voltage supply line 13 arranged in the peripheral region PA (see...). Figure 2 ).

[0245] like Figures 30 to 32 As shown, the vertical reference voltage line VRLv can be electrically connected to the connection electrode 372 arranged in the third circuit region PCA3b through the contact hole 65b passing through the fifth insulating layer 115. The connection electrode 372 can be electrically connected to the reference voltage line VRL, and the reference voltage line VRL can have a mesh structure in the display area DA.

[0246] Although not shown in the accompanying drawings, voltage supply lines electrically connected to the horizontal and / or vertical conductive lines may be further arranged in the peripheral area PA. The voltage supply lines may be arranged on at least one of the upper, lower, left, and right sides of the display area DA.

[0247] The connecting electrodes, which have essentially the same function and correspond to the first circuit region PCA1b to the third circuit region PCA3b, can have different shapes and positions depending on the position of the lines arranged in the first circuit region PCA1b to the third circuit region PCA3b.

[0248] Pixel electrode 511 can be electrically connected to connection electrode 381, which is a lower conductive pattern, through contact hole 71b of sixth insulating layer 116, and therefore can be electrically connected to first transistor T1. For example... Figure 34As shown, the pixel electrode 511 connected to the pixel circuit of the first pixel PX1 can be electrically connected to the connection electrode 581 arranged in the first circuit region PCA1b, and therefore can be electrically connected to the first transistor T1. The pixel electrode 511 connected to the pixel circuit of the second pixel PX2 can be electrically connected to the connection electrode 381 arranged in the second circuit region PCA2b, and therefore can be electrically connected to the first transistor T1. The pixel electrode 511 connected to the pixel circuit of the third pixel PX3 can be electrically connected to the connection electrode 381 arranged in the third circuit region PCA3b, and therefore can be electrically connected to the first transistor T1.

[0249] like Figure 3 As shown, the auxiliary electrode AE ​​can be further arranged on the same layer as the pixel electrode 511.

[0250] like Figures 35 to 37 As shown, a seventh insulating layer 117, serving as a pixel defining layer covering the edge of the pixel electrode 511, can be disposed above the pixel electrode 511. An opening 117OP exposing a portion of the pixel electrode 511 and defining an emission region can be defined in the seventh insulating layer 117. The seventh insulating layer 117 can be a single organic insulating layer or multiple organic insulating layers and / or a single inorganic insulating layer or multiple inorganic insulating layers. The intermediate layer can include an emission layer 513 and a first functional layer below the emission layer 513 and / or a second functional layer above the emission layer 513. The opposing electrodes 515 can be integrally formed with each other to correspond to an organic light-emitting diode (OLED) disposed in the display area DA.

[0251] refer to Figures 35 to 37 According to embodiments of this disclosure, since the first conductive line 300a is arranged or not arranged to at least correspond to the channel region CH1 of the first transistor T1, the disconnection of the channel region CH1 of the first transistor T1 can be minimized (prevented).

[0252] According to embodiments of this disclosure, the ratio of the first capacitor C1, the second capacitor C2, and the third capacitor C3 for each pixel can be optimized by adjusting the degree of overlap between the first conductive line 300a and the second electrode 320, the degree of overlap between the second conductive line 300b and the second electrode 320, the separation distance between the first conductive line 300a and the first electrode 310, and / or the size of the first conductive line 300a and / or the first electrode 310 and / or the width of the first conductive line 300a and / or the first electrode 310 in the y-direction.

[0253] Return to reference Figure 35 and Figure 36The first capacitor C1 of the first pixel PX1 and the second pixel PX2 may include a first electrode C11 and a second electrode C12. The first electrode C11 may include a lower first electrode C11b formed by the first electrode 310, an intermediate first electrode C11m formed by the third electrode 330, and an upper first electrode C11t formed by the connecting electrode 373. The lower first electrode C11b and the intermediate first electrode C11m may be electrically connected to each other through a contact hole 31b, and the intermediate first electrode C11m and the upper first electrode C11t may be electrically connected to each other through a contact hole 49b. The second electrode C12 may include a lower second electrode C12b formed by the second electrode 320, an intermediate second electrode C12m formed by the connecting electrode 370, and an upper second electrode C12t formed by the connecting electrode 383. The lower second electrode C12b and the intermediate second electrode C12m may be electrically connected to each other through a contact hole 41b, and the intermediate second electrode C12m and the upper second electrode C12t may be electrically connected to each other through a contact hole 62b.

[0254] The capacitance of the first capacitor C1 can be the sum of the capacitance formed by the lower first electrode C11b and the lower second electrode C12b, the capacitance formed by the lower second electrode C12b and the intermediate first electrode C11m, the capacitance formed by the intermediate first electrode C11m and the intermediate second electrode C12m, and the capacitance formed by the upper first electrode C11t and the upper second electrode C12t. The first capacitor C1 can have a structure in which sub-capacitors formed by conductive lines overlapping each other in the z-direction are connected in parallel, and thus can have (or obtain) increased capacitance without increasing the area in the x and y directions.

[0255] The y-direction width wc2 of the lower first electrode C11b of the first capacitor C1 of the second pixel PX2 can be greater than the y-direction width wc2 of the lower first electrode C11b of the first capacitor C1 of the first pixel PX1. The overlap area between the lower first electrode C11b and the lower second electrode C12b of the first capacitor C1 of the second pixel PX2 can be greater than the overlap area between the lower first electrode C11b and the lower second electrode C12b of the first capacitor C1 of the first pixel PX1. The sum of the overlap area between the lower second electrode C12b and the middle first electrode C11m of the first capacitor C1 of the first pixel PX1 and the overlap area between the middle first electrode C11m and the middle second electrode C12m of the first capacitor C1 of the first pixel PX1 can be greater than the sum of the overlap area between the lower second electrode C12b and the middle first electrode C11m of the first capacitor C1 of the second pixel PX2 and the overlap area between the middle first electrode C11m and the middle second electrode C12m of the first capacitor C1 of the second pixel PX2.

[0256] The second capacitor C2 of the first pixel PX1 and the second pixel PX2 may include a first electrode C21 formed by a first conductive line 300a and a second electrode C22 formed by a second electrode 320. The area of ​​overlap between the second electrode C22 and the first electrode C21 in the second pixel PX2 may be the same as or different from the area of ​​overlap between the second electrode C22 and the first electrode C21 in the first pixel PX1.

[0257] The third capacitor C3 of the first pixel PX1 and the second pixel PX2 may include a first electrode C31 formed by the second conductive line 300b and a second electrode C32 formed by a portion of the second electrode 320.

[0258] refer to Figure 37 The first capacitor C1 of the third pixel PX3 may include a first electrode C11 and a second electrode C12. The first electrode C11 may include an intermediate first electrode C11m formed by the third electrode 330 and an upper first electrode C11t formed by the connecting electrode 373. The second electrode C12 may include a lower second electrode C12b formed by the second electrode 320, an intermediate second electrode C12m formed by the connecting electrode 370, and an upper second electrode C12t formed by the connecting electrode 383. The capacitance of the first capacitor C1 may be the sum of the capacitance formed by the lower second electrode C12b and the intermediate first electrode C11m, the capacitance formed by the intermediate first electrode C11m and the intermediate second electrode C12m, and the capacitance formed by the upper first electrode C11t and the upper second electrode C12t. The first capacitor C1 may have a structure in which sub-capacitors formed by conductive lines overlapping each other in the z-direction are connected in parallel, and thus can have (obtain) increased capacitance without increasing the area in the x and y directions.

[0259] The sum of the overlapping area between the lower second electrode C12b and the middle first electrode C11m of the first capacitor C1 of the third pixel PX3 and the overlapping area between the middle first electrode C11m and the middle second electrode C12m of the first capacitor C1 of the third pixel PX3 can be greater than the sum of the overlapping area between the lower second electrode C12b and the middle first electrode C11m of the first capacitor C1 of the first pixel PX1 and the overlapping area between the middle first electrode C11m and the middle second electrode C12m of the first capacitor C1 of the first pixel PX1, and can be greater than the sum of the overlapping area between the lower second electrode C12b and the middle first electrode C11m of the first capacitor C1 of the second pixel PX2 and the overlapping area between the middle first electrode C11m and the middle second electrode C12m of the first capacitor C1 of the second pixel PX2.

[0260] The second capacitor C2 of the third pixel PX3 may include a first electrode C21 formed by a first conductive line 300a and a second electrode C22 formed by a portion of a second electrode 320. The area where the second electrode C22 overlaps with the first electrode C21 in the third pixel PX3 may be larger than the area where the second electrode C22 overlaps with the first electrode C21 in the first pixel PX1 and the second pixel PX2.

[0261] The third capacitor C3 of the third pixel PX3 may include a first electrode C31 formed by the second conductive line 300b and a second electrode C32 formed by a portion of the second electrode 320.

[0262] Figure 38 This is a schematic diagram of the equivalent circuit of pixel PXc according to an embodiment.

[0263] Apart from Figure 4 In addition to the pixel circuit PCa of pixel PXa shown in the figure, Figure 38 The pixel circuit PCc of pixel PXc shown may also include a seventh transistor T7.

[0264] refer to Figure 38 A seventh transistor T7 can be connected between the first transistor T1 and the second initialization voltage line VL2. The seventh transistor T7 may include a gate connected to the second gate line GIL, a first terminal connected to the second node N2, and a second terminal connected to the second initialization voltage line VL2. The first terminal of the seventh transistor T7 can be connected to the second terminal of the first transistor T1, the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The seventh transistor T7 can be turned on by a second gate signal GI transmitted through the second gate line GIL, and can be configured to transmit a second initialization voltage Vint2 transmitted through the second initialization voltage line VL2 to the second node N2. The voltage level of the second initialization voltage Vint2 can be lower than the voltage level of the initialization voltage Vint.

[0265] Figure 38 The fourth transistor T4 of the pixel circuit PCc shown in the figure is... Figure 4 The difference in the fourth transistor T4 of the pixel circuit PCa shown may be at least that the gate of the fourth transistor T4 of the pixel circuit PCc is connected to the sixth gate line GBL to receive the sixth gate signal GB. The gate of the fourth transistor T4 may be connected to the sixth gate line GBL, and the fourth transistor T4 may be configured to be turned on by the sixth gate signal GB transmitted through the sixth gate line GBL and to transmit the initialization voltage Vint transmitted through the initialization voltage line VL to the third node N3.

[0266] Figure 38The second capacitor C2 of the pixel circuit PCc shown in the figure is... Figure 4 The difference in the pixel circuit PCa shown may be at least that the second capacitor C2 of the pixel circuit PCc is connected between the reference voltage line VRL and the second node N2. The first electrode of the second capacitor C2 may be connected to the reference voltage line VRL. The second electrode of the second capacitor C2 may be connected to the second terminal and second gate of the first transistor T1, the second electrode of the first capacitor C1, the first terminal of the seventh transistor T7, and the first terminal of the sixth transistor T6. The capacitance of each of the first capacitor C1 and the second capacitor C2 may vary according to the color of the light emitted from the pixel PXc.

[0267] Figure 38 Other configurations of the pixel circuit PCc shown can be compared with... Figure 4 The pixel circuit PCa shown in the figure has the same configuration.

[0268] Figure 39 This is a schematic layout diagram showing the positions of the transistors and capacitors of the pixels according to an embodiment. Figures 40 to 50 This is a schematic layout diagram showing the elements for each pixel of each layer. Figure 49 This is a schematic diagram illustrating the arrangement of vertical conductive lines according to an embodiment. Figure 51 It is along Figure 39 and Figure 50 A schematic cross-sectional view of the pixel elements intercepted by lines VI-VI' and VII-VII'.

[0269] exist Figure 39 In the first circuit region PCA1c, the second circuit region PCA2c, and the third circuit region PCA3c, the pixel circuits can correspond to Figure 38 The pixel circuit PCc of the pixel is shown in the figure.

[0270] In this embodiment, the pixel circuit PCc of the first pixel PX1 can be connected to the first-1 initialization voltage line VL11, and the pixel circuit PCcs of the second pixel PX2 and the third pixel PX3 can be connected to the first-2 initialization voltage line VL12. The initialization voltage supplied to the first-1 initialization voltage line VL11 and the initialization voltage supplied to the first-2 initialization voltage line VL12 can be different from each other.

[0271] In the following description, for ease of illustration and explanation, reference numerals are assigned to devices of the pixel circuit PCc arranged in the first circuit region PCA1c, and the description is given based on the first circuit region PCA1c. However, this description can also be applied to the same elements in the second circuit region PCA2c and the third circuit region PCA3c. Reference will be made below to... Figures 39 to 51Provide a description.

[0272] The first conductive layer can be disposed on the substrate 100. For example... Figure 40 As shown, the first conductive layer may include a first conductive line 400a, a second conductive line 400b, a reference voltage line VRL, and / or a repair line RL. In an embodiment, a barrier layer may be further disposed between the substrate 100 and the first conductive layer.

[0273] The first conductive line 400a may extend in the x-direction and may be arranged to pass through the first circuit region PCA1c, the second circuit region PCA2c, and the third circuit region PCA3c. The first conductive line 400a may be the driving voltage line PL to which the driving voltage ELVDD is applied. The first conductive line 400a may include a main line 400am extending in the x-direction and a protruding portion 400ap extending from the main line 400am in the +y direction. The protruding portion 400ap may overlap with the data line DL in each circuit region.

[0274] The second conductive line 400b can extend in the x direction and can be arranged to pass through the first circuit region PCA1c, the second circuit region PCA2c and the third circuit region PCA3c.

[0275] The second conductive line 400b can be the driving voltage line PL applied by the reference voltage ELVDD. The second conductive line 400b can include a main line 400bm extending in the x-direction and a protruding portion 400bp extending from the main line 400bm in the -y direction. The protruding portion 400bp can overlap with the first semiconductor layer ACT1 in each circuit region. The protruding portion 400bp can overlap with the entire channel region of the first transistor T1. The second conductive line 400b can serve as the first electrode C21 of the second capacitor C2. For example, the first electrode C21 of the second capacitor C2 in the first pixel region PCA1c, the second pixel region PCA2c, and the third pixel region PCA3c can be connected to each other.

[0276] The reference voltage line VRL can be arranged parallel to the second conductive line 400b, extending in the x-direction, and arranged to pass through the first circuit region PCA1c, the second circuit region PCA2c, and the third circuit region PCA3c. The reference voltage line VRL can be connected to the second conductive line 400b via a connection portion CP. Therefore, the second conductive line 400b can be understood as part of the reference voltage line VRL. In an embodiment, the reference voltage line VRL, the second conductive line 400b, and the connection portion CP can be integrated as a whole and provided on the same layer. The connection portion CP can overlap with the data line DL.

[0277] The repair line RL can extend in the x direction and can be arranged to pass through the first circuit region PCA1c, the second circuit region PCA2c and the third circuit region PCA3c.

[0278] A first insulating layer 111 may be disposed on a substrate 100 to cover a first conductive layer, and a second conductive layer may be disposed on the first insulating layer 111. For example... Figure 41 As shown, the second conductive layer may include a first electrode 420, a lower first gate line GWLb, a second initialization voltage line VL2 and / or a first-second initialization voltage line VL12.

[0279] The first electrode 420 may be provided as an island. The first electrode 420 may overlap with the second conductive line 400b and the protrusion 400bp. The first electrode 420 may include the second gate electrode G12 and the source electrode of the first transistor T1.

[0280] The lower first gate line GWLb, the second initialization voltage line VL2, and the first-second initialization voltage line VL12 can extend in the x direction and can be arranged to pass through the first circuit region PCA1c, the second circuit region PCA2c, and the third circuit region PCA3c.

[0281] The second insulating layer 112 can be disposed on the first insulating layer 111 to cover the second conductive layer, and on the second insulating layer 112, as shown in the figure below, can be disposed on the second insulating layer 112. Figure 42 The diagram shows a semiconductor layer ACT comprising an oxide semiconductor. The semiconductor layer ACT may include a first semiconductor layer ACT1, a second semiconductor layer ACT2, a third semiconductor layer ACT3, a fourth semiconductor layer ACT4, and a fifth semiconductor layer ACT5. The semiconductor layer ACT may include a source region, a drain region, and a channel region between the source and drain regions of each of the first transistors T1 to the seventh transistor T7. According to embodiments, the source or drain region may also be interpreted as the source electrode or drain electrode of the transistor.

[0282] Figure 44 This is a schematic diagram showing the transistors in the first circuit region PCA1c. (Reference) Figure 44 The first semiconductor layer ACT1 may include the source region S1 and drain region D1 of the first transistor T1 and the source region S5 and drain region D5 of the fifth transistor T5. The second semiconductor layer ACT2 may include the source region S2 and drain region D2 of the second transistor T2 and the source region S3 and drain region D3 of the third transistor T3. The third semiconductor layer ACT3 may include the source region S6 and drain region D6 of the sixth transistor T6. The fourth semiconductor layer ACT4 may include the source region S4 and drain region D4 of the fourth transistor T4. The fifth semiconductor layer ACT5 may include the source region S7 and drain region D7 of the seventh transistor T7.

[0283] The third insulating layer 113 can be disposed on the second insulating layer 112 to cover the semiconductor layer ACT, and the third conductive layer can be disposed on the third insulating layer 113. For example... Figure 43 As shown, the third conductive layer may include a second electrode 430, a third electrode 440, connecting electrodes 450 and 460, an upper first gate line GWLt, a second gate line GIL, a third gate line GRL, a fourth gate line EML, a fifth gate line EMBL, a sixth gate line GBL, and / or a first-1 initialization voltage line VL11.

[0284] The second electrode 430, the third electrode 440, and the connecting electrodes 450 and 460 can be provided in an island shape. The second electrode 430, the third electrode 440, and the connecting electrodes 450 and 460 can be arranged in each of the first circuit region PCA1c, the second circuit region PCA2c, and the third circuit region PCA3c.

[0285] The connecting electrode 450 can be electrically connected to the protruding portion 400ap of the first conductive line 400a through the contact hole 33c passing through the first insulating layer 111, the second insulating layer 112 and the third insulating layer 113.

[0286] The connecting electrode 460 can be electrically connected to the reference voltage line VRL through the contact hole 35c passing through the first insulating layer 111, the second insulating layer 112 and the third insulating layer 113.

[0287] The upper first gate line GWLt, second gate line GIL, third gate line GRL, fourth gate line EML, fifth gate line EMBL, sixth gate line GBL and first initialization voltage line VL11 can extend in the x direction and can be arranged to pass through the first circuit region PCA1c, the second circuit region PCA2c and the third circuit region PCA3c.

[0288] The upper first gate line GWLt can overlap with the lower first gate line GWLb, and can be electrically connected to the lower first gate line GWLb through a contact hole 32c passing through the second insulating layer 112 and the third insulating layer 113. The first gate line GWL can have a two-layer structure including the lower first gate line GWLb and the upper first gate line GWLt arranged on different layers.

[0289] like Figure 44 As shown, the third conductive layer may include the gate electrodes G1 to G7 of the first transistor T1 to the seventh transistor T7. The gate electrodes G1 to G7 may overlap with the channel region of the semiconductor layer ACT.

[0290] refer to Figure 44The second electrode 430 may include the first gate electrode G11 of the first transistor T1. The first gate electrode G11 may overlap with the first semiconductor layer ACT1. The third electrode 440 may be the gate electrode G2 of the second transistor T2. The fourth electrode 440 may overlap with the second semiconductor layer ACT2. The gate electrode G3 of the third transistor T3 may be the portion of the third gate line GRL that overlaps with the second semiconductor layer ACT2. The gate electrode G4 of the fourth transistor T4 may be the portion of the sixth gate line GBL that overlaps with the fourth semiconductor layer ACT4. The gate electrode G5 of the fifth transistor T5 may be the portion of the fourth gate line EML that overlaps with the first semiconductor layer ACT1. The gate electrode G6 of the sixth transistor T6 may be the portion of the fifth gate line EML that overlaps with the third semiconductor layer ACT3. The gate electrode G7 of the seventh transistor T7 may be the portion of the second gate line GIL that overlaps with the fifth semiconductor layer ACT5.

[0291] A fourth insulating layer 114 may be disposed on the third insulating layer 113 to cover the third conductive layer, and a fourth conductive layer may be disposed on the fourth insulating layer 114. For example... Figure 45a As shown, the fourth conductive layer may include a data line DL and connecting electrodes 470, 471, 472, 473, 474, 475, 476, 477, 478 and 479.

[0292] For each circuit region, the data line DL can be arranged to extend in the y-direction. The data line DL can be electrically connected to the drain region D2 of the second transistor T2 through the contact hole 43c passing through the third insulating layer 113 and the fourth insulating layer 114.

[0293] The connecting electrode 470 may include a first region 470a overlapping the second conductive line 400b, the first electrode 420, and the second electrode 430, and a second region 470b protruding from the first region 470a in the -y direction. The connecting electrode 470 can electrically connect the source region S1 of the first transistor T1 to the second gate electrode G12 of the first transistor T1 and the sixth transistor T6.

[0294] The first region 470a of the connecting electrode 470 can be electrically connected to the source region S1 of the first transistor T1 through a contact hole 42c passing through the third insulating layer 113 and the fourth insulating layer 114. The first region 470a of the connecting electrode 470 can be electrically connected to the first electrode 420 through a contact hole 41c passing through the second insulating layer 112, the third insulating layer 113 and / or the fourth insulating layer 114. Therefore, the connecting electrode 470 can be the source electrode electrically connected to the source region S1 of the first transistor T1. The first electrode 420 can correspond to the second gate electrode G12 of the first transistor T1, and the second gate electrode G12 can face the first gate electrode G11 of the first transistor T1 and overlap with the channel region of the first transistor T1. When the connecting electrode 470 is connected to the first electrode 420, the second gate electrode G12 of the first transistor T1 can be electrically connected to the source region S1 of the first transistor T1.

[0295] The second region 470b of the connecting electrode 470 can be electrically connected to the drain region D6 of the sixth transistor T6 through the contact hole 50c passing through the third insulating layer 113 and the fourth insulating layer 114. The second region 470b of the connecting electrode 470 can be electrically connected to the drain region D7 of the seventh transistor T7 through the contact hole 58c passing through the third insulating layer 113 and the fourth insulating layer 114.

[0296] The connection electrode 471 can be electrically connected to the gate electrode G2 of the second transistor T2 through the contact hole 45c passing through the fourth insulating layer 114. The connection electrode 471 can be electrically connected to the upper first gate line GWLt through the contact hole 44c passing through the fourth insulating layer 114.

[0297] The connecting electrode 472 can be electrically connected to the source region S3 of the third transistor T3 through the contact hole 46c passing through the third insulating layer 113 and the fourth insulating layer 114, and can be electrically connected to the reference voltage line VRL through the contact hole 47c passing through the second insulating layer 112 to the fourth insulating layer 114.

[0298] The connecting electrode 473 can be electrically connected to the source region S2 of the second transistor T2 and the drain region D3 of the third transistor T3 through the contact hole 48c passing through the third insulating layer 113 and the fourth insulating layer 114. The connecting electrode 473 can be electrically connected to the second electrode 430 through the contact hole 49c passing through the fourth insulating layer 114, and can also be electrically connected to the first gate electrode G11 of the first transistor T1. The connecting electrode 473 can correspond to... Figure 38The node electrode corresponding to the first node N1. The connection electrode 473 may correspond to a bridge electrode that electrically connects at least two transistors. For example, the connection electrode 473 may correspond to a bridge electrode that connects the first gate electrode G11 of the first transistor T1, the source region S2 of the second transistor T2, and the drain region D3 of the third transistor T3.

[0299] The connecting electrode 474 can be electrically connected to the protruding portion 400ap of the first conductive line 400a through contact holes 51c passing through the first insulating layer 111 to the fourth insulating layer 114. The connecting electrode 474 can be electrically connected to the drain region D5 of the fifth transistor T5 through contact holes 52c passing through the third insulating layer 113 and the fourth insulating layer 114. Therefore, the drain region D5 of the fifth transistor T5 can be electrically connected to the first conductive line 400a.

[0300] The connecting electrode 475 can be electrically connected to the source region S6 of the sixth transistor T6 through the contact hole 53c passing through the third insulating layer 113 and the fourth insulating layer 114. The connecting electrode 475 can be electrically connected to the drain region D4 of the fourth transistor T4 through the contact hole 59c passing through the third insulating layer 113 and the fourth insulating layer 114. The connecting electrode 475 can overlap with a portion of the repair line RL. The connecting electrode 475 can be insulated from the repair line RL, and can be electrically connected to the repair line RL later in the event of a defect occurring in the pixel circuitry arranged in the circuit region.

[0301] In the first circuit region PCA1c, the connection electrode 476 can be electrically connected to the source region S4 of the fourth transistor T4 through the contact hole 54c passing through the third insulating layer 113 and the fourth insulating layer 114. The connection electrode 476 can be connected to the first-1 initialization voltage line VL11 through the contact hole 55c passing through the fourth insulating layer 114.

[0302] In the second circuit region PCA2c and the third circuit region PCA3c, the connecting electrode 476 can be electrically connected to the source region S4 of the fourth transistor T4 through the contact hole 54c passing through the third insulating layer 113 and the fourth insulating layer 114. The connecting electrode 476 can be electrically connected to the first-second initialization voltage line VL12 through the contact hole 56c passing through the second insulating layer 112 to the fourth insulating layer 114.

[0303] In some of the first circuit regions PCA1c, such as Figure 45b As shown, the connecting electrode 476 may also have a protrusion 476p. For example, the protrusion 476p of the connecting electrode 476 may be formed only in the first vertical initialization voltage line VL11v within the vertical conductive line VCL described below (see...). Figure 46 In the first circuit region PCA1c arranged by )

[0304] In the first circuit region PCA1c, the connecting electrode 477 can be electrically connected to the first-second initialization voltage line VL12 through the contact hole 57c passing through the second insulating layer 112 to the fourth insulating layer 114. The connecting electrode 477 can be arranged in some of the first circuit regions PCA1c. For example, the connecting electrode 477 can be arranged only in the second vertical initialization voltage line VL12v (see below) where the vertical conductive lines described below are arranged. Figure 47 In the first circuit region PCA1c.

[0305] The connecting electrode 478 can be electrically connected to the source region S7 of the seventh transistor T7 through the contact hole 60c passing through the third insulating layer 113 and the fourth insulating layer 114. The connecting electrode 478 can be electrically connected to the second initialization voltage line VL2 through the contact hole 68c passing through the second insulating layer 112, the third insulating layer 113 and the fourth insulating layer 114.

[0306] In the second circuit region PCA2c, the connecting electrode 479 can be electrically connected to the second initialization voltage line VL2 through the contact hole 69c passing through the second insulating layer 112 to the fourth insulating layer 114. The connecting electrode 479 can be arranged in only some of the second circuit regions PCA2c. For example, the connecting electrode 479 can be arranged only in the third vertical initialization voltage line VL2v (see below) among the vertical conductive lines. Figure 47 In the second circuit region PCA2c arranged therein.

[0307] The fifth insulating layer 115 may be disposed above the fourth insulating layer 114 to cover the fourth conductive layer or overlap with the fourth conductive layer, and the fifth conductive layer may be disposed above the fifth insulating layer 115. For example... Figures 46 to 49 As shown, the fifth conductive layer may include a vertical conductive line VCL and connecting electrodes 481 and 483. For ease of illustration and explanation, Figures 46 to 48 Only a few of the lower conductive lines connected to the fifth conductive layer are shown.

[0308] The connecting electrode 481 can be electrically connected to the connecting electrode 475 through the contact hole 61c passing through the fifth insulating layer 115, and can also be electrically connected to the source region S6 of the sixth transistor T6.

[0309] The connecting electrode 483 can be electrically connected to the connecting electrode 470 through the contact hole 62c passing through the fifth insulating layer 115. The connecting electrode 483 can be arranged to cover and overlap the connecting electrode 473, which serves as a node electrode. The first electrode 420 can be arranged below the connecting electrode 473, and the connecting electrode 483 can be arranged above the connecting electrode 473. The connecting electrode 483 can completely cover the connecting electrode 473, and the first electrode 420 can completely cover or completely overlap the connecting electrode 473. The connecting electrode 483 can serve as an upper shielding layer for the connecting electrode 473, and the first electrode 420 can serve as a lower shielding layer for the connecting electrode 473.

[0310] The vertical conductor line VCL may include a vertical drive voltage line PLv, a first vertical initialization voltage line VL11v, a second vertical initialization voltage line VL12v, a third vertical initialization voltage line VL2v, a vertical common voltage line ELv, and a vertical reference voltage line VRLv. Each of the vertical conductor lines VCL may extend in the y-direction and may be arranged to be spaced apart from each other in the x-direction within the first circuit region PCA1c to the third circuit region PCA3c.

[0311] Four vertical conductive lines can be arranged to be spaced apart from each other in the x-direction within the first circuit region PCA1c to the third circuit region PCA3c. For example, four vertical conductive lines among the first vertical initialization voltage line VL11v, the second vertical initialization voltage line VL12v, the third vertical initialization voltage line VL2v, the vertical drive voltage line PLv, the vertical common voltage line ELv, and the vertical reference voltage line VRLv can be arranged to be spaced apart from each other in the x-direction. The vertical conductive line VCL can be electrically connected to a horizontal conductive line extending in the x-direction. The horizontal conductive line can include a conductive line 400 as the drive voltage line PL, the first initialization voltage line VL11, the first initialization voltage line VL12, and the reference voltage line VRL.

[0312] Figure 46 An example is shown where the first vertical initialization voltage line VL11v, a pair of vertical drive voltage lines PLv, and a vertical reference voltage line VRLv are arranged sequentially in the x-direction in the first circuit region PCA1c to the third circuit region PCA3c.

[0313] Figure 47 An example is shown where the second vertical initialization voltage line VL12v, the third vertical initialization voltage line VL2v, and a pair of vertical reference voltage lines VRLv are arranged sequentially in the x-direction in the first circuit region PCA1c to the third circuit region PCA3c.

[0314] Figure 48An example is shown where the second vertical initialization voltage line VL12v, the vertical reference voltage line VRLv, the vertical common voltage line ELv, and the vertical reference voltage line VRLv are arranged sequentially in the x-direction in the first circuit region PCA1c to the third circuit region PCA3c.

[0315] A pair of adjacent vertical conductive lines VCL can be connected by a connecting section. A pair of vertical conductive lines VCL can also be integrated into one unit. For example, as... Figure 46 As shown, a pair of adjacent vertical drive voltage lines PLv can be connected via the connection portion BR1. The pair of vertical drive voltage lines PLv can also be integrated into one unit. For example... Figure 47 As shown, a pair of adjacent vertical reference voltage lines VRLv can be connected via a connecting portion BR2. The pair of vertical reference voltage lines VRLv can be integral with each other. In an embodiment, connecting portions BR1 and BR2 can be positioned every two rows. For example, as... Figure 46 As shown, a pair of vertical drive voltage lines PLv can be connected to each other via a connection portion BR1 in either odd or even rows, and can be spaced apart from each other in either even or odd rows without a connection portion BR1.

[0316] In an embodiment, such as Figure 49 As shown, the first vertical conductive line VCL of the unit circuit region PCAu can be either the first vertical initialization voltage line VL11v or the second vertical initialization voltage line VL12v. The fourth vertical conductive line VCL of the unit circuit region PCAu can be the vertical reference voltage line VRLv. The second and third vertical conductive lines VCL of the unit circuit region PCAu can be a pair of vertical drive voltage lines PLv, a pair of vertical drive voltage lines PLv and a vertical reference voltage line VRLv, or a pair of vertical reference voltage lines VRLv and a vertical common voltage line ELv.

[0317] like Figure 46 As shown, the vertical drive voltage line PLv can be electrically connected to the connection electrode 474 arranged in the second circuit region PCA2c through the contact hole 64c passing through the fifth insulating layer 115. The connection electrode 474 can be electrically connected to the first conductive line 400a, which is the drive voltage line PL, and the drive voltage line PL can have a mesh structure in the display region DA.

[0318] like Figure 46 As shown, the first vertical initialization voltage line VL11v can be electrically connected to the connection electrode 476 arranged in the first circuit region PCA1c through the contact hole 63c passing through the fifth insulating layer 115. The connection electrode 476 can be electrically connected to the first initialization voltage line VL11, and the first initialization voltage line VL11 can have a mesh structure in the display area DA.

[0319] like Figure 47 As shown, the second vertical initialization voltage line VL12v can be electrically connected to the connection electrode 477 arranged in the first circuit region PCA1c through the contact hole 66c passing through the fifth insulating layer 115. The connection electrode 477 can be electrically connected to the first-second initialization voltage line VL12, and the first-second initialization voltage line VL12 can have a mesh structure in the display area DA.

[0320] like Figure 47 As shown, the third vertical initialization voltage line VL2v can be electrically connected to the connection electrode 479 arranged in the second circuit region PCA2c through the contact hole 67c passing through the fifth insulating layer 115. The connection electrode 479 can be electrically connected to the second initialization voltage line VL2, and the second initialization voltage line VL2 can have a mesh structure in the display region DA.

[0321] like Figures 46 to 48 As shown, the vertical reference voltage line VRLv can be electrically connected to the connection electrode 472 arranged in the second circuit region PCA2c and / or the third circuit region PCA3c through the contact hole 65c passing through the fifth insulating layer 115. The connection electrode 472 can be electrically connected to the reference voltage line VRL, and the reference voltage line VRL can have a mesh structure in the display area DA.

[0322] The vertical common voltage line ELv can be electrically connected to the common voltage supply line 13 located in the peripheral area PA (see...). Figure 2 ).

[0323] Although not shown in the accompanying drawings, voltage supply lines electrically connected to the horizontal and / or vertical conductive lines may be further arranged in the peripheral area PA. The voltage supply lines may be arranged on at least one of the upper, lower, left, and right sides of the display area DA.

[0324] The connecting electrodes, which have the same function and correspond to the first circuit region PCA1a to the third circuit region PCA3a, can have different shapes and positions depending on the position of the lines arranged in the first circuit region PCA1c to the third circuit region PCA3c.

[0325] The sixth insulating layer 116 may be disposed above the fifth insulating layer 115 to cover the fifth conductive layer or overlap with the fifth conductive layer, and the organic light-emitting diode (OLED) may be disposed above the sixth insulating layer 116 as a display element. The OLED may include a pixel electrode 511, a counter electrode 515, and an intermediate layer between the pixel electrode 511 and the counter electrode 515.

[0326] Pixel electrode 511 can be electrically connected to connection electrode 481, which is a lower conductive pattern, through contact hole 71c of sixth insulating layer 116, and therefore can be electrically connected to first transistor T1. For example... Figure 50 As shown, the pixel electrode 511 connected to the pixel circuit of the first pixel PX1 can be electrically connected to the connection electrode 481 arranged in the first circuit region PCA1c, and therefore can be electrically connected to the first transistor T1. The pixel electrode 511 connected to the pixel circuit of the second pixel PX2 can be electrically connected to the connection electrode 481 arranged in the second circuit region PCA2c, and therefore can be electrically connected to the first transistor T1. The pixel electrode 511 connected to the pixel circuit of the third pixel PX3 can be electrically connected to the connection electrode 481 arranged in the third circuit region PCA3c, and therefore can be electrically connected to the first transistor T1.

[0327] like Figure 3 As shown, the auxiliary electrode AE ​​can be further arranged on the same layer as the pixel electrode 511.

[0328] like Figure 51 As shown, a seventh insulating layer 117, serving as a pixel defining layer covering the edge of the pixel electrode 511, can be disposed above the pixel electrode 511. An opening 117OP exposing a portion of the pixel electrode 511 and defining an emission region can be defined in the seventh insulating layer 117. The seventh insulating layer 117 can be a single organic insulating layer or multiple organic insulating layers and / or a single inorganic insulating layer or multiple inorganic insulating layers. The intermediate layer can include an emission layer 513 and a first functional layer below the emission layer 513 and / or a second functional layer above the emission layer 513. The opposing electrodes 515 can be integrally formed with each other to correspond to an organic light-emitting diode (OLED) disposed in the display area DA.

[0329] refer to Figure 51 The protruding portion 400bp of the second conductive line 400b can correspond to the entire channel region CH1 of the first transistor T1 in each circuit region. According to embodiments of the present disclosure, since the protruding portion 400bp of the second conductive line 400b is arranged to at least correspond to the channel region CH1 of the first transistor T1, the disconnection of the channel region CH1 of the first transistor T1 due to steps can be minimized (prevented).

[0330] The first capacitor C1 of the first pixel PX1, the second pixel PX2, and the third pixel PX3 may include a first electrode C11 and a second electrode C12. The first electrode C11 may include an intermediate first electrode C11m formed by the second electrode 430 and an upper first electrode C11t formed by the connecting electrode 473. The intermediate first electrode C11m and the upper first electrode C11t may be electrically connected to each other through a contact hole 49c. The second electrode C12 may include a lower second electrode C12b formed by the first electrode 420, an intermediate second electrode C12m formed by the connecting electrode 470, and / or an upper second electrode C12t formed by the connecting electrode 483. The lower second electrode C12b and the intermediate second electrode C12m may be electrically connected to each other through a contact hole 41c, and the intermediate second electrode C12m and the upper second electrode C12t may be electrically connected to each other through a contact hole 62c.

[0331] The capacitance of the first capacitor C1 can be the sum of the capacitance formed by the lower second electrode C12b and the intermediate first electrode C11m, the capacitance formed by the intermediate first electrode C11m and the intermediate second electrode C12m, and the capacitance formed by the upper first electrode C11t and the upper second electrode C12t. The first capacitor C1 can have a structure in which sub-capacitors formed by conductive lines overlapping each other in the z-direction are connected in parallel, and thus can have (obtain) increased capacitance without increasing the area in the x and y directions.

[0332] The second capacitor C2 may include a first electrode C21 formed by a second conductive line 400b connected to a reference voltage line VRL and a second electrode C22 formed by a first electrode 420. The capacitance of the second capacitor C2 for each pixel can be adjusted according to the y-direction width of the second conductive line 400b including the first electrode C21 and the area of ​​overlap between the second electrode C22 and the first electrode C21.

[0333] In the display device according to an embodiment of the present disclosure, since at least one conductive layer disposed below the semiconductor layer of the driving transistor corresponds at least to the channel region of the semiconductor layer of the driving transistor, disconnection of the semiconductor layer due to the lower step can be prevented.

[0334] Figures 52a to 53b This is a schematic cross-sectional view showing the structure of a display element according to an embodiment.

[0335] According to an embodiment, an organic light-emitting diode (OLED) as a display element may include a pixel electrode 511, a counter electrode 515, and an intermediate layer 513m between the pixel electrode 511 (first electrode, anode) and the counter electrode 515 (second electrode, cathode).

[0336] Pixel electrode 511 may include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or zinc aluminum oxide (AZO). Pixel electrode 511 may include a reflective layer comprising Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or compounds thereof. For example, pixel electrode 511 may have a three-layer structure of ITO / Ag / ITO.

[0337] The relative electrode 515 may be disposed on the intermediate layer 513m. The relative electrode 515 may comprise a metal, alloy, electrically conductive compound, or any combination thereof having a low work function. For example, the relative electrode 515 may comprise Li, Ag, Mg, Al, Al-Li, Ca, Mg-In, Mg-Ag, Yb, Ag-Yb, ITO, IZO, or any combination thereof. The relative electrode 515 may comprise a transmission electrode, a transmission-reflection electrode, or a reflection electrode.

[0338] The intermediate layer 513m may include high-molecular-weight organic materials or low-molecular-weight organic materials that emit light of a specific color. In addition to various organic materials, the intermediate layer 513m may also include metal-containing compounds such as organometallic compounds and inorganic materials such as quantum dots.

[0339] In an embodiment, the intermediate layer 513m may include an emitter layer and a first functional layer and a second functional layer located below and above the emitter layer, respectively. The first functional layer may include, for example, a hole transport layer (HTL) or a hole transport layer (HTL) and a hole injection layer (HIL). The second functional layer may include an electron transport layer (ETL) and / or an electron injection layer (EIL). The first or second functional layer may be omitted. The first and second functional layers may be integrated with each other to correspond to an organic light-emitting diode (OLED) included in the display area DA.

[0340] In an embodiment, the intermediate layer 513m may include at least two emitters and a charge generation layer CGL. The at least two emitters may be sequentially stacked between the pixel electrode 511 and the opposing electrode 515, and the charge generation layer CGL may be disposed between the at least two emitters. When the intermediate layer 513m includes emitters and a charge generation layer CGL, the organic light-emitting diode (OLED) can be a tandem light-emitting device. When the OLED has a stacked structure of emitters, it can have improved color purity and emission efficiency.

[0341] The emitting unit may include an emitting layer and a first functional layer and a second functional layer located below and above the emitting layer, respectively. The charge generation layer CGL may include a negative charge generation layer and a positive charge generation layer. Based on the negative charge generation layer and the positive charge generation layer, the emission efficiency of an organic light-emitting diode (OLED) as a tandem light-emitting device including an emitting layer can be further improved.

[0342] The negative charge generation layer can be an n-type charge generation layer. The negative charge generation layer can supply electrons. The negative charge generation layer can include a host material and a dopant. The host material can include an organic material. The dopant material can include a metallic material. The positive charge generation layer can be a p-type charge generation layer. The positive charge generation layer can supply holes. The positive charge generation layer can include a host material and a dopant. The host material can include an organic material. The dopant material can include a metallic material.

[0343] In an embodiment, such as Figure 52a As shown, an organic light-emitting diode (OLED) may include a first emitter EU1 containing a first emitter layer EML1 and a second emitter EU2 containing a second emitter layer EML2, and the first emitter EU1 and the second emitter EU2 may be stacked sequentially on top of each other. A charge-generating layer CGL may be provided between the first emitter EU1 and the second emitter EU2. For example, an OLED may include a pixel electrode 511, a first emitter layer EML1, a charge-generating layer CGL, a second emitter layer EML2, and a counter electrode 515 stacked sequentially on top of each other. A first functional layer and a second functional layer may be included below and above the first emitter layer EML1, respectively. The first functional layer and the second functional layer may be included below and above the second emitter layer EML2, respectively. The first emitter layer EML1 may be a blue emitter layer, and the second emitter layer EML2 may be a yellow emitter layer.

[0344] In an embodiment, such as Figure 52bAs shown, an organic light-emitting diode (OLED) may include a first emitter EU1 and a third emitter EU3 comprising a first emitter layer EML1, and a second emitter EU2 comprising a second emitter layer EML2. A first charge-generating layer CGL1 may be provided between the first emitter EU1 and the second emitter EU2, and a second charge-generating layer CGL2 may be provided between the second emitter EU2 and the third emitter EU3. For example, an OLED may include a pixel electrode 511, a first emitter EML1, a first charge-generating layer CGL1, a second emitter EML2, a second charge-generating layer CGL2, a first emitter EML1, and a counter electrode 515, stacked sequentially on top of each other. A first functional layer and a second functional layer may be included below and above the first emitter EML1, respectively. The first functional layer and the second functional layer may be included below and above the second emitter EML2, respectively. The first emitter EML1 may be a blue emitter layer, and the second emitter EML2 may be a yellow emitter layer.

[0345] In an embodiment, the organic light-emitting diode (OLED) may include a second emitting layer EU2. In addition to the second emitting layer EML2, the second emitting layer EU2 may also include a third emitting layer EML3 and / or a fourth emitting layer EML4 that are directly in contact with the second emitting layer EML2 below and / or above it. Here, "direct contact" can mean that no layer can be arranged between the second emitting layer EML2 and the third emitting layer EML3 and / or between the second emitting layer EML2 and the fourth emitting layer EML4. The third emitting layer EML3 may be a red emitting layer, and the fourth emitting layer EML4 may be a green emitting layer.

[0346] For example, such as Figure 52c As shown, an organic light-emitting diode (OLED) may include pixel electrodes 511, a first emission layer EML1, a first charge generation layer CGL1, a third emission layer EML3, a second emission layer EML2, a second charge generation layer CGL2, and a counter electrode 515, which are stacked sequentially on top of each other. As another example, such as... Figure 52d As shown, an organic light-emitting diode (OLED) may include a pixel electrode 511, a first emission layer EML1, a first charge generation layer CGL1, a third emission layer EML3, a second emission layer EML2, a fourth emission layer EML4, a second charge generation layer CGL2, a first emission layer EML1, and a counter electrode 515, which are stacked sequentially on top of each other.

[0347] Figure 53a It is shown Figure 52c A schematic cross-sectional view of an example of an organic light-emitting diode (OLED), and Figure 53b It is shown Figure 52dA schematic cross-sectional view of an example of an organic light-emitting diode (OLED).

[0348] refer to Figure 53a An organic light-emitting diode (OLED) may include a first emitter EU1, a second emitter EU2, and a third emitter EU3 stacked sequentially on top of each other. A first charge-generating layer CGL1 may be provided between the first emitter EU1 and the second emitter EU2, and a second charge-generating layer CGL2 may be provided between the second emitter EU2 and the third emitter EU3. Each of the first charge-generating layer CGL1 and the second charge-generating layer CGL2 may include a negative charge-generating layer nCGL and a positive charge-generating layer pCGL.

[0349] The first emitting unit EU1 may include a blue emitting layer BEML. The first emitting unit EU1 may also include a hole injection layer HIL and a hole transport layer HTL between the pixel electrode 511 and the blue emitting layer BEML. In an embodiment, a p-doped layer may be further included between the hole injection layer HIL and the hole transport layer HTL. The p-doped layer can be formed by doping the hole injection layer HIL with a p-type dopant material. In an embodiment, at least one of a blue light assist layer, an electron blocking layer, and a buffer layer may be further included between the blue emitting layer BEML and the hole transport layer HTL. The blue light assist layer can improve the emission efficiency of the blue emitting layer BEML. The blue light assist layer can improve the emission efficiency of the blue emitting layer BEML by adjusting the hole charge balance. The electron blocking layer can prevent electrons from being injected into the hole transport layer HTL. The buffer layer can compensate for the resonant distance according to the wavelength of the light emitted from the emitting layer.

[0350] The second emitter EU2 may include a yellow emitter layer YEML and a red emitter layer REML directly contacting the yellow emitter layer YEML below it. The second emitter EU2 may also include a hole transport layer HTL between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red emitter layer REML, and may further include an electron transport layer ETL between the yellow emitter layer YEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0351] The third emitting unit EU3 may include a blue emitting layer BEML. The third emitting unit EU3 may also include a hole transport layer HTL between the positive charge generation layer pCGL of the second charge generation layer CGL2 and the blue emitting layer BEML. The third emitting unit EU3 may also include an electron transport layer ETL and an electron injection layer EIL between the blue emitting layer BEML and the opposing electrode 515. The electron transport layer ETL may include a single layer or multiple layers. In an embodiment, at least one of a blue light assist layer, an electron blocking layer, and a buffer layer may be further included between the blue emitting layer BEML and the hole transport layer HTL. At least one of a hole blocking layer and a buffer layer may be further included between the blue emitting layer BEML and the electron transport layer ETL. The hole blocking layer prevents hole injection into the electron transport layer ETL.

[0352] Figure 53b The organic light-emitting diode (OLED) shown can be used with Figure 53a The organic light-emitting diode (OLED) shown has a stacked structure with different second emitter EU2, and apart from the stacked structure of the second emitter EU2, Figure 53b The organic light-emitting diode (OLED) shown can be used with Figure 53a The organic light-emitting diode (OLED) shown has the same structure. (Reference) Figure 53b The second emitting unit EU2 may include a yellow emitting layer YEML, a red emitting layer REML directly contacting the yellow emitting layer YEML below it, and a green emitting layer GEML directly contacting the yellow emitting layer YEML above it. The second emitting unit EU2 may also include a hole transport layer HTL between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red emitting layer REML, and may further include an electron transport layer ETL between the green emitting layer GEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0353] Figure 54 This is a schematic cross-sectional view showing the structure of the pixels of a display device according to an embodiment.

[0354] refer to Figure 54 The display device may include pixels. A pixel may include a first pixel PX1, a second pixel PX2, and a third pixel PX3. Each of the first pixel PX1 to the third pixel PX3 may include a pixel electrode 511, a counter electrode 515, and an intermediate layer 513m. In an embodiment, the first pixel PX1 may include a red pixel, the second pixel PX2 may include a green pixel, and the third pixel PX3 may include a blue pixel. Here, the pixel may include an organic light-emitting diode (OLED) as a display element, and the OLED of each pixel may be electrically connected to the pixel circuitry.

[0355] A pixel electrode 511 may be provided in each of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0356] The intermediate layer 513m of each of the first pixels PX1 to the third pixels PX3 in an organic light-emitting diode (OLED) may include a first emitter EU1 and a second emitter EU2 stacked sequentially on top of each other, and a charge generation layer CGL between the first emitter EU1 and the second emitter EU2. The charge generation layer CGL may include a negative charge generation layer nCGL and a positive charge generation layer pCGL. The charge generation layer CGL may be a common layer continuously formed throughout the first pixels PX1 to the third pixels PX3.

[0357] The first emitter EU1 of the first pixel PX1 may include a hole injection layer HIL, a hole transport layer HTL, a red emitter layer REML, and an electron transport layer ETL, which are sequentially stacked on the pixel electrode 511. The first emitter EU1 of the second pixel PX2 may include a hole injection layer HIL, a hole transport layer HTL, a green emitter layer GEML, and an electron transport layer ETL, which are sequentially stacked on the pixel electrode 511. The first emitter EU1 of the third pixel PX3 may include a hole injection layer HIL, a hole transport layer HTL, a blue emitter layer BEML, and an electron transport layer ETL, which are sequentially stacked on the pixel electrode 511. Each of the hole injection layer HIL, hole transport layer HTL, and electron transport layer ETL in each of the first emitter EU1 may be a common layer formed continuously throughout the first pixel PX1 to the third pixel PX3.

[0358] The second emitter EU2 of the first pixel PX1 may include a hole transport layer HTL, an auxiliary layer AXL, a red emitter layer REML, and an electron transport layer ETL, which are sequentially stacked on the charge generation layer CGL. The second emitter EU2 of the second pixel PX2 may include a hole transport layer HTL, a green emitter layer GEML, and an electron transport layer ETL, which are sequentially stacked on the charge generation layer CGL. The second emitter EU2 of the third pixel PX3 may include a hole transport layer HTL, a blue emitter layer BEML, and an electron transport layer ETL, which are sequentially stacked on the charge generation layer CGL. Each of the hole transport layer HTL and the electron transport layer ETL in each of the second emitter EU2 may be a common layer formed continuously throughout the first pixel PX1 to the third pixel PX3. In an embodiment, in the second emitter EU2 of the first pixel PX1 to the third pixel PX3, at least one of a hole blocking layer and a buffer layer may be further included between the emitter layer and the electron transport layer ETL.

[0359] The thicknesses H1 of the red emitter layer REML, H2 of the green emitter layer GEML, and H3 of the blue emitter layer BEML can be determined based on the resonant distance. The auxiliary layer AXL can be a region added to adjust the resonant distance and can include resonant auxiliary materials. For example, the auxiliary layer AXL can include the same material as the hole transport layer HTL.

[0360] Figure 54 It is shown that the auxiliary layer AXL can be included in only the first pixel PX1. However, embodiments of this disclosure are not limited thereto. For example, the auxiliary layer AXL can be provided in at least one of the first pixel PX1 to the third pixel PX3 to adjust the resonant distance of at least one of the first pixel PX1 to the third pixel PX3.

[0361] The display device may also include a capping layer 517 disposed outside the opposing electrode 515. The capping layer 517 can improve emission efficiency based on the principle of constructive interference. Therefore, because the light extraction efficiency of the organic light-emitting diode OLED is improved, the emission efficiency of the organic light-emitting diode OLED can be improved.

[0362] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure and as defined by the appended claims.

Claims

1. A display device comprising: a first conductive line; a first electrode disposed on and overlapping the first conductive line; a semiconductor layer disposed on and overlapping the first electrode; a second electrode disposed on and overlapping the first electrode; and a third electrode disposed on the second electrode, the third electrode overlapping the second electrode, and the third electrode electrically connected to the semiconductor layer and the first electrode, wherein a region of the semiconductor layer overlapping the second electrode overlaps the first conductive line.

2. The display device according to claim 1, further comprising: a fourth electrode electrically connected to the second electrode, the fourth electrode and the third electrode disposed on the same layer; and a fifth electrode disposed on the fourth electrode, the fifth electrode overlapping the fourth electrode, and the fifth electrode electrically connected to the third electrode.

3. The display device according to claim 1, further comprising: a sixth electrode, the sixth electrode and the first conductive line disposed on the same layer, wherein the first electrode, the second electrode, and the third electrode overlap the sixth electrode, and the second electrode is electrically connected to the sixth electrode.

4. The display device according to claim 3, wherein an opening overlapping the sixth electrode is defined in the first electrode, and the second electrode is electrically connected to the sixth electrode through the opening.

5. The display device according to claim 3, further comprising: a seventh electrode electrically connected to the second electrode, the seventh electrode and the third electrode disposed on the same layer; and an eighth electrode disposed on the seventh electrode, the eighth electrode overlapping the seventh electrode, and the eighth electrode electrically connected to the third electrode.

6. The display device according to claim 1, further comprising: a second conductive line spaced apart from the first conductive line, the second conductive line and the first conductive line provided on the same layer, wherein a voltage applied to the second conductive line is different from a voltage applied to the first conductive line. the first electrode overlaps the second conductive line.

8. A display device comprising: a first circuit region and a second circuit region, pixel circuits of first pixels being disposed in the first circuit region, pixel circuits of second pixels being disposed in the second circuit region; 7. The display device of claim 6, wherein, a first conductive line disposed in the first circuit region and the second circuit region; a first electrode disposed on and overlapping the first conductive line, the first electrode being disposed in each of the first circuit region and the second circuit region; a semiconductor layer disposed on and overlapping the first electrode, the semiconductor layer being disposed in each of the first circuit region and the second circuit region; a second electrode disposed on and overlapping the first electrode, the second electrode being disposed in each of the first circuit region and the second circuit region; and a third electrode disposed on the second electrode, the third electrode overlapping the second electrode, and the third electrode electrically connected to the semiconductor layer and the first electrode, wherein a region of the semiconductor layer overlapping the second electrode overlaps the first conductive line. ​ ​ a third electrode disposed on the second electrode, the third electrode overlapping the second electrode, and the third electrode electrically connected to the semiconductor layer and the first electrode, the third electrode disposed in each of the first circuit region and the second circuit region, wherein a region of the semiconductor layer overlapping the second electrode overlaps the first conductive line.

9. The display device according to claim 8, further comprising: a fourth electrode electrically connected to the second electrode, the fourth electrode disposed in each of the first circuit region and the second circuit region, the fourth electrode and the third electrode disposed on the same layer; and a fifth electrode disposed on the fourth electrode, the fifth electrode overlapping the fourth electrode, and the fifth electrode electrically connected to the third electrode, the fifth electrode disposed in each of the first circuit region and the second circuit region.

10. The display device according to claim 8, further comprising: a sixth electrode, the sixth electrode and the first conductive line disposed on the same layer in the first circuit region, wherein the first electrode, the second electrode, and the third electrode overlap the sixth electrode, and the second electrode is electrically connected to the sixth electrode.

11. The display device of claim 10, wherein, in the first circuit region, an opening overlapping the sixth electrode is defined in the first electrode, and the second electrode is electrically connected to the sixth electrode through the opening.

12. The display device according to claim 10, further comprising: a seventh electrode electrically connected to the second electrode, the seventh electrode disposed in each of the first circuit region and the second circuit region, the seventh electrode and the third electrode disposed on the same layer; and an eighth electrode disposed on the seventh electrode, the eighth electrode overlapping the seventh electrode, and the eighth electrode electrically connected to the third electrode, the eighth electrode disposed in each of the first circuit region and the second circuit region.

13. A display device comprising: a first circuit region and a second circuit region, pixel circuits of first pixels disposed in the first circuit region, pixel circuits of second pixels disposed in the second circuit region; a first conductive line disposed in the first circuit region and the second circuit region; a second conductive line spaced apart from the first conductive line, the second conductive line and the first conductive line disposed on the same layer in the first circuit region and the second circuit region; a first electrode disposed on and overlapping the first conductive line, the first electrode disposed in each of the first circuit region and the second circuit region; a semiconductor layer disposed on and overlapping the first electrode, the semiconductor layer disposed in each of the first circuit region and the second circuit region; a second electrode disposed on and overlapping the first electrode, the second electrode disposed in each of the first circuit region and the second circuit region; and a third electrode disposed on the second electrode, the third electrode overlapping the second electrode, and the third electrode electrically connected to the semiconductor layer and the first electrode, the third electrode disposed in each of the first circuit region and the second circuit region, wherein a region of the semiconductor layer overlapping the second electrode overlaps the first conductive line.

9. The display device according to claim 8, further comprising: a fourth electrode electrically connected to the second electrode, the fourth electrode disposed in each of the first circuit region and the second circuit region, the fourth electrode and the third electrode disposed on the same layer; and a fifth electrode disposed on the fourth electrode, the fifth electrode overlapping the fourth electrode, and the fifth electrode electrically connected to the third electrode, the fifth electrode disposed in each of the first circuit region and the second circuit region.

10. The display device according to claim 8, further comprising: a sixth electrode, the sixth electrode and the first conductive line disposed on the same layer in the first circuit region, wherein the first electrode, the second electrode, and the third electrode overlap the sixth electrode, and the second electrode is electrically connected to the sixth electrode. in the first circuit region, an opening overlapping the sixth electrode is defined in the first electrode, and the second electrode is electrically connected to the sixth electrode through the opening.

12. The display device according to claim 10, further comprising: a seventh electrode electrically connected to the second electrode, the seventh electrode disposed in each of the first circuit region and the second circuit region, the seventh electrode and the third electrode disposed on the same layer; and an eighth electrode disposed on the seventh electrode, the eighth electrode overlapping the seventh electrode, and the eighth electrode electrically connected to the third electrode, the eighth electrode disposed in each of the first circuit region and the second circuit region.

13. A display device comprising: a first circuit region and a second circuit region, pixel circuits of first pixels disposed in the first circuit region, pixel circuits of second pixels disposed in the second circuit region; a first conductive line disposed in the first circuit region and the second circuit region; a second conductive line spaced apart from the first conductive line, the second conductive line and the first conductive line disposed on the same layer in the first circuit region and the second circuit region; a first electrode disposed on and overlapping the first conductive line, the first electrode disposed in each of the first circuit region and the second circuit region; a semiconductor layer disposed on and overlapping the first electrode, the semiconductor layer disposed in each of the first circuit region and the second circuit region; a second electrode disposed on and overlapping the first electrode, the second electrode disposed in each of the first circuit region and the second circuit region; and a third electrode disposed on the second electrode, the third electrode overlapping the second electrode, and the third electrode electrically connected to the semiconductor layer and the first electrode, the third electrode disposed in each of the first circuit region and the second circuit region, wherein a region of the semiconductor layer overlapping the second electrode overlaps the first conductive line. a third electrode disposed on the second electrode, the third electrode overlapping the second electrode, and the third electrode electrically connected to the semiconductor layer and the first electrode, the third electrode disposed in each of the first circuit region and the second circuit region, wherein a region of the semiconductor layer overlapping the second electrode overlaps the first conductive line.

14. The display device according to claim 13, further comprising: a fourth electrode electrically connected to the second electrode, the fourth electrode disposed in each of the first circuit region and the second circuit region, the fourth electrode and the third electrode disposed on the same layer; and a fifth electrode disposed on the fourth electrode, the fifth electrode overlapping the fourth electrode, and the fifth electrode electrically connected to the third electrode, the fifth electrode disposed in each of the first circuit region and the second circuit region.

15. The display device according to claim 13, further comprising: a sixth electrode, the sixth electrode and the first conductive line disposed on the same layer in the first circuit region, wherein the first electrode, the second electrode, and the third electrode overlap the sixth electrode, and the second electrode is electrically connected to the sixth electrode.

16. The display device of claim 15, wherein, in the first circuit region, an opening overlapping the sixth electrode is defined in the first electrode, and the second electrode is electrically connected to the sixth electrode through the opening.

17. The display device according to claim 15, further comprising: a seventh electrode electrically connected to the second electrode, the seventh electrode disposed in each of the first circuit region and the second circuit region, the seventh electrode and the third electrode disposed on the same layer; and an eighth electrode disposed on the seventh electrode, the eighth electrode overlapping the seventh electrode, and the eighth electrode electrically connected to the third electrode, the eighth electrode disposed in each of the first circuit region and the second circuit region.

18. The display device according to claim 17, further comprising: a third circuit region in which pixel circuits of third pixels are disposed, wherein the first conductive line and the second conductive line extend into the third circuit region, the first conductive line includes a plurality of sub-conductive lines spaced apart from each other, and a region of the semiconductor layer overlapping the second electrode, which is disposed in the third circuit region, is positioned between the sub-conductive lines.

19. The display device of claim 13, wherein, the first electrode overlaps the second conductive line.

20. The display device of claim 19, wherein, an area in which the first electrode disposed in the first circuit region overlaps the second conductive line is different from an area in which the first electrode disposed in the second circuit region overlaps the second conductive line. the first electrode overlaps the second conductive line. an area in which the first electrode disposed in the first circuit region overlaps the second conductive line is different from an area in which the first electrode disposed in the second circuit region overlaps the second conductive line.

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