A method and apparatus for scanning chip voltage current turnover points

Abstract

This application relates to the field of integrated circuit testing technology and discloses a method and device for scanning the voltage and current inversion points of a chip. The method includes the following steps: after the host computer completes parameter configuration and wavetable loading, it issues a start command; a global synchronization unit generates a synchronization signal; an arbitrary waveform generator is started in parallel for scanning; a trigger unit monitors the signal; and an internal counter keeps track of the time. When the trigger unit detects an inversion, it sends a stop signal; the global synchronization unit immediately latches the count value; finally, the host computer reads the count value and calculates the inversion point value by combining the wavetable rate and clock cycle. This invention uses a global synchronization unit to coordinate the parallel hardware architecture of the arbitrary waveform generator and the trigger unit, realizing the continuous scanning of the excitation signal and the real-time monitoring of the response signal at the hardware level, which greatly shortens the overall time of a single inversion point test.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit testing technology, specifically to a method and apparatus for scanning the voltage and current inversion points of a chip. Background Technology

[0002] Integrated circuits (chips) are the core of modern electronic devices. Their internal communication and interaction with other chips rely on the precise discrimination of high and low level signals. In digital logic, there exists a specific voltage or current threshold. When an input signal crosses this threshold, the chip's internal logic state flips, for example, from logic 0 to logic 1. This critical threshold point is called a turnover point. These turnover points, such as the input high-level threshold (VIH) and input low-level threshold (VIL), directly determine the chip's anti-interference capability and signal compatibility. Therefore, rigorous quality inspection of chips before they leave the factory, and the rapid and accurate identification of these turnover points, are crucial for ensuring the stability and reliability of the final product.

[0003] Currently, the mature technologies used in the industry for this type of testing generally rely on a precision instrument called a Per-Pin Measurement Unit (PPMU). The PPMU is powerful and flexible, capable of precisely applying a set voltage to a single chip pin and measuring the resulting current, or applying a current and measuring the voltage on the pin. This capability allows test engineers to perform detailed static DC characteristic analysis of the chip. By writing test sequences using host computer software, engineers can have complete control over every action of the PPMU, thereby achieving high-precision single-point measurement and characterization of specific chip parameters.

[0004] However, when using this point-by-point control scheme for flip-point scanning, its inherent working mode reveals some fundamental shortcomings. First, the testing efficiency is extremely low because each voltage step requires a complete instruction communication and data return between the host computer and the test hardware. A high-precision scanning task may involve hundreds or thousands of test points, which means that the same number of communication handshakes are required, resulting in a huge cumulative time overhead. Second, testing accuracy and efficiency become mutually restrictive contradictions. To obtain higher measurement resolution, the only way is to encrypt the scan points, but this inevitably leads to a significant increase in testing time, making high-precision testing almost impossible in mass production. Finally, the timing start point of the entire testing process is determined by the host computer software, but the execution of software instructions is affected by the operating system scheduling, resulting in random timing jitter, which directly impairs the stability and repeatability of the measurement results. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a method and apparatus for scanning the voltage and current reversal points of a chip, thereby solving the technical problems of low testing efficiency and the mutual constraint between measurement accuracy and testing time caused by relying on a host computer for point-by-point control of scanning in existing technologies.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a method for scanning the voltage-current inversion point of a chip, comprising the following steps:

[0007] S1. The host computer writes configuration parameters to the arbitrary waveform generator and the trigger unit respectively, and loads the generated wavetable data sequence into the storage space of the arbitrary waveform generator;

[0008] S2. The global synchronization unit receives the start command issued by the host computer, converts the start command into a global start signal that is phase-aligned with the system clock based on the system clock, and sends the global start signal in parallel to the arbitrary waveform generator, the trigger unit, and the counter inside the global synchronization unit.

[0009] S3. The arbitrary waveform generator responds to the global start signal and outputs the wavetable data sequence to the chip under test sequentially based on the wavetable output rate in the configuration parameters. At the same time, the counter responds to the global start signal and starts to accumulate the count value based on the system clock. The trigger unit responds to the global start signal and starts to monitor the follower pin status of the chip under test in real time.

[0010] S4. When the triggering unit detects that the status of the following pin meets the triggering condition in the configuration parameters, it generates a stop signal. The global synchronization unit receives the stop signal and controls the counter to stop the accumulation operation to latch the current count value.

[0011] S5. The host computer reads the latched count value, calculates the theoretical index position corresponding to the flip event based on the count value, the period of the system clock and the wavetable output rate, and extracts the flip point value of the chip under test from the wavetable data sequence using the theoretical index position.

[0012] Preferably, step S1 specifically includes:

[0013] The host computer writes the target trigger level, trigger judgment logic, and measurement range to the register inside the trigger unit through the system bus. The trigger unit controls the internal digital-to-analog converter to generate an analog reference voltage based on the target trigger level and inputs it to the reference terminal of the hardware comparator.

[0014] The host computer writes the output drive mode, output range and wavetable output rate into the register inside the arbitrary waveform generator, wherein the wavetable output rate defines the physical time length during which two adjacent data points in the wavetable data sequence are maintained at the output end.

[0015] The host computer generates the wavetable data sequence containing continuously linearly increasing or decreasing digital codes in its local memory according to the scanning range and scanning step accuracy set by the test task, and transmits the wavetable data sequence to the arbitrary waveform generator through direct memory access.

[0016] Preferably, step S2 specifically includes:

[0017] The global synchronization unit receives the start command from the host computer in the asynchronous clock domain, and latches the start command to generate a pre-trigger signal;

[0018] The global synchronization unit utilizes its internally integrated synchronization circuit to shape the pre-trigger signal into a global start pulse signal that is strictly aligned with the phase of the system clock when a valid transition edge of the system clock is detected.

[0019] The global synchronization unit transmits the global start pulse signal simultaneously to the hardware enable terminal of the arbitrary waveform generator, the hardware enable terminal of the trigger unit, and the counting enable terminal of the counter through a hardware signal transmission network, and controls the propagation delay difference of each signal transmission path to be less than one system clock cycle.

[0020] Preferably, step S3 specifically includes:

[0021] The waveform control logic inside the arbitrary waveform generator is reset and enabled. Using the wavetable output rate as the timing reference, the internal digital-to-analog converter is driven to read data point by point from the starting address of the wavetable data sequence and convert it into an analog excitation signal to be applied to the chip under test.

[0022] The hardware comparator inside the trigger unit is de-shielded, the real-time signal of the follow pin is connected to one input of the hardware comparator, and the preset analog reference voltage is connected to the other input of the hardware comparator.

[0023] The hardware comparator performs continuous analog voltage comparisons on the signals at the two input terminals and outputs a digital level signal representing the comparison result.

[0024] Preferably, step S4 specifically includes:

[0025] When the follow pin signal of the chip under test crosses the analog reference voltage, the output state of the hardware comparator flips to form a hardware stop signal.

[0026] The triggering unit sends the hardware stop signal to the stop signal input terminal of the global synchronization unit through a dedicated signal path;

[0027] The global synchronization unit receives the hardware stop signal and converts the hardware stop signal into a synchronization stop signal aligned with the system clock through a synchronizer.

[0028] The global synchronization unit uses the synchronization stop signal to invalidate the counter's count enable pin, so that the counter retains the last valid count value before the stop response as the latched count value.

[0029] Preferably, the calculation of the theoretical index position corresponding to the flip event in step S5 includes:

[0030] The host computer obtains the count value latched by the counter through the bus, and retrieves the wavetable output rate and the fixed clock period of the system clock stored locally.

[0031] The host computer multiplies the count value by the fixed clock period to obtain the total measurement time from the time the global start signal is issued to the time the stop signal is latched.

[0032] The host computer divides the total measurement time by the wavetable output rate to obtain the theoretical index position, wherein the theoretical index position represents the position coordinate in the wavetable data sequence corresponding to the time when the flip event occurs.

[0033] Preferably, the calculation of the theoretical index position corresponding to the flip event in step S5 further includes the process of removing the inherent system delay:

[0034] Before performing the test, the output of the arbitrary waveform generator is shorted to the input of the trigger unit and a step signal capture test is performed to obtain the inherent delay parameters of the system.

[0035] The host computer subtracts the inherent delay parameter of the system from the total measurement time to obtain the effective time of the actual waveform operation;

[0036] The host computer divides the effective time by the wavetable output rate to obtain the corrected theoretical index position.

[0037] Preferably, step S5, extracting the flip point value of the chip under test from the wavetable data sequence, includes:

[0038] The host computer determines whether the theoretical index position is not an integer;

[0039] When the theoretical index position is not an integer, the host computer performs a floor operation on the theoretical index position to obtain a first integer index, and performs a floor operation on the theoretical index position to obtain a second integer index;

[0040] The host computer addresses the wavetable data sequence stored locally and reads the first waveform value corresponding to the first integer index and the second waveform value corresponding to the second integer index.

[0041] Preferably, step S5, extracting the flip point value of the chip under test from the wavetable data sequence, further includes:

[0042] The host computer performs linear interpolation calculations based on the first waveform value, the second waveform value, and the decimal part of the theoretical index position.

[0043] The host computer uses the first waveform value as a reference and adds the product of the decimal part and the difference between the first waveform value and the second waveform value to obtain the accurate flip point value.

[0044] The host computer stores or displays the calculated flip point value as the final measurement result of the chip under test under the test conditions.

[0045] An apparatus for scanning the voltage-current switching points of a chip, comprising:

[0046] The host computer is used to generate configuration parameters and wavetable data sequences, and to issue start commands;

[0047] An arbitrary waveform generator is provided, wherein the input terminal of the arbitrary waveform generator is connected to the host computer to receive the configuration parameters and the wavetable data sequence, and the output terminal of the arbitrary waveform generator is connected to the excitation input pin of the chip under test to provide a continuously changing excitation signal to the chip under test.

[0048] A trigger unit, the input terminal of which is connected to the follower pin of the chip under test, is used to monitor the signal status of the follower pin in real time and generate a stop signal according to the triggering conditions;

[0049] A global synchronization unit is connected to the host computer, the arbitrary waveform generator, and the triggering unit, respectively. The global synchronization unit contains a counter.

[0050] The global synchronization unit is used to respond to the start command by sending a phase-aligned global start signal in parallel to the arbitrary waveform generator, the trigger unit, and the counter based on the system clock. When the stop signal sent by the trigger unit is received, the unit controls the counter to latch the current count value so that the host computer can read and calculate the flip-flop value of the chip under test.

[0051] This invention provides a method and apparatus for scanning the voltage-current switching points of a chip. It has the following beneficial effects:

[0052] 1. This invention adopts a parallel hardware architecture that coordinates the arbitrary waveform generator and the triggering unit with a global synchronization unit, realizing the continuous scanning of the excitation signal and the real-time monitoring of the response signal at the hardware level, which greatly shortens the overall time of a single flip point test. Compared with the step-by-step cycle of setting and measuring point by point by the host computer and the parameter measurement unit in the existing technology, this invention eliminates a large amount of communication handshake and software waiting overhead in the testing process, and solves the problem of low testing efficiency caused by communication bottlenecks in traditional solutions.

[0053] 2. This invention introduces a computational model based on time-domain mapping. It uses a high-frequency counter to accurately latch the physical moment of the flip event and performs interpolation calculations in conjunction with the wavetable output rate to deduce the accurate flip point value. This decouples the measurement accuracy from the density of wavetable points, changing the existing technology where the measurement resolution is completely equivalent to the scanning step and the accuracy must be improved by increasing the number of scanning points. This solves the technical contradiction that high accuracy and high efficiency cannot be achieved simultaneously.

[0054] 3. The global synchronization unit of the present invention constitutes the core of the system's timing reference. The generated hardware start signal is strictly aligned with the starting point of excitation output, response monitoring and timing on a nanosecond time scale, thereby establishing a deterministic and repeatable hardware-level measurement timing. Compared with the existing technology that relies on host computer software instructions to start the test, the present invention avoids the random timing error introduced by operating system scheduling and bus transmission delay, and solves the fundamental defects of uncertain measurement starting point and poor repeatability in traditional schemes. Attached Figure Description

[0055] Figure 1 This is a schematic diagram of the device structure according to an embodiment of the present invention;

[0056] Figure 2 This is a schematic diagram of the method flow according to an embodiment of the present invention;

[0057] Figure 3 This is a schematic diagram comparing the technical solutions of the present invention with existing technical solutions.

[0058] in:

[0059] 1. Arbitrary waveform generator; 2. Wavetable; 3. AWG parameter register; 4. Trigger unit; 5. Trigger parameter register; 6. Global synchronization unit; 7. Counter; 8. System clock; 9. Host computer; 10. Chip under test. Detailed Implementation

[0060] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0061] See attached document Figure 1 , Figure 1 This is a schematic diagram of a device for scanning chip voltage and current switching points according to an embodiment of the present invention. The present invention provides a device for scanning chip voltage and current switching points, which is applied to an integrated circuit automatic test system for testing a chip under test (DUT) 10.

[0062] The device may include: an arbitrary waveform generator (AWG) 1, a trigger unit 4, and a global synchronization unit 6.

[0063] The output of arbitrary waveform generator 1 is connected to the excitation input pin of chip under test 10. The input of trigger unit 4 is connected to the follow pin of chip under test 10. The control signal output of global synchronization unit 6 is connected to arbitrary waveform generator 1 and trigger unit 4 respectively, and its stop signal input is connected to the signal output of trigger unit 4.

[0064] The device may also include a host computer (PC) 9 for configuring the parameters of each functional unit before the test begins and issuing test start commands to the global synchronization unit 6. The device may also include a system clock (CLK) 8, which provides a unified clock reference for the global synchronization unit 6.

[0065] In the above structure, the arbitrary waveform generator 1 serves as the excitation source, providing continuously varying voltage or current signals to the chip under test 10. The arbitrary waveform generator 1 integrates a wavetable 2 and an AWG parameter register 3. The wavetable 2 stores a preset signal sequence consisting of a series of data points. The AWG parameter register 3 stores configuration parameters written by the host computer 9, which define the output mode, range, and wavetable output rate of the arbitrary waveform generator 1.

[0066] Trigger unit 4, acting as a response detection unit, is used to monitor the signal status of the follow pins of the chip under test 10 in real time. Trigger unit 4 integrates a trigger parameter register 5. Trigger parameter register 5 stores configuration parameters written by the host computer 9, which define the target trigger level, sampling rate, and range. When the signal monitored by trigger unit 4 meets the preset conditions in trigger parameter register 5, trigger unit 4 sends a stop signal to global synchronization unit 6.

[0067] The global synchronization unit 6, acting as a timing control unit, coordinates the synchronous operation of the arbitrary waveform generator 1 and the trigger unit 4. Internally, the global synchronization unit 6 contains a timer 7. The timer 7 is connected to the system clock 8, using the period of the system clock 8 as the counting reference. Upon receiving a start command from the host computer 9, the global synchronization unit 6 broadcasts a start signal to both the arbitrary waveform generator 1 and the trigger unit 4, and simultaneously starts its internal timer 7. When the global synchronization unit 6 receives a stop signal from the trigger unit 4, it responds to the stop signal, controls the timer 7, and latches the current count value.

[0068] See attached document Figure 2 , Figure 2 This is a flowchart illustrating a method for scanning the voltage-current inversion point of a chip according to an embodiment of the present invention. The present invention provides a method for scanning the voltage-current inversion point of a chip, comprising the following steps:

[0069] S1, Initialization configuration: The host computer 9 writes configuration parameters to the arbitrary waveform generator 1 and the trigger unit 4 respectively, and loads the generated wave table 2 into the arbitrary waveform generator 1;

[0070] S2, Synchronous Start: The global synchronization unit 6 responds to the start command of the host computer 9, broadcasts a start signal to the arbitrary waveform generator 1 and the trigger unit 4, and simultaneously controls the internal counter 7 to start timing based on the system clock 8;

[0071] S3, Parallel scanning and monitoring: Arbitrary waveform generator 1 responds to the start signal and outputs the signal sequence in wavetable 2 to the chip under test 10 in sequence according to the preset wavetable output rate. At the same time, trigger unit 4 responds to the start signal and monitors the signal status of the follow pins of chip under test 10 in real time.

[0072] S4, Trigger Locking: When the signal state monitored by the triggering unit 4 meets the preset triggering conditions, a stop signal is sent to the global synchronization unit 6. The global synchronization unit 6 responds to the stop signal and controls the counter 7 to stop counting in order to latch the current count value.

[0073] S5, Flip point calculation: Read the count value latched by counter 7, and calculate the wavetable index corresponding to the flip point based on the count value, the period of system clock 8 and wavetable output rate, and then obtain the flip point value of the chip under test 10 from wavetable 2.

[0074] The technical details and principles of each of the above steps will be explained in detail below, taking into account the specific implementation process.

[0075] In step S1, initialization configuration is performed. This step is completed by the host computer 9, which mainly includes setting parameters for the trigger unit 4 and the arbitrary waveform generator 1, and loading the wave table 2 for scanning.

[0076] S101, the host computer 9 writes configuration parameters to the trigger parameter register 5 inside the trigger unit 4 via the test system bus to configure the operating state of the comparison circuit inside the trigger unit 4. Specifically, this includes:

[0077] Target trigger level: Sets the voltage or current threshold used to determine the flip-flop. This digital parameter is converted into an analog reference voltage by the digital-to-analog converter inside trigger unit 4 and input to the reference terminal of the hardware comparator.

[0078] Triggering conditions: Define the valid judgment logic for signal crossing the threshold, including rising edge triggering, falling edge triggering, or level transition triggering, to adapt to the flip-flop characteristics of the follow pin of the chip under test 10 under different test vectors.

[0079] Measurement range: Select the corresponding range circuit according to the expected signal amplitude of the follower pin of the chip under test 10 to ensure that the input signal is within the linear measurement range.

[0080] Monitoring clock frequency: Sets the operating clock of the internal comparison logic circuit of trigger unit 4. This parameter determines the time resolution of trigger signal detection.

[0081] S102, the host computer 9 writes configuration parameters to the AWG parameter register 3 inside the arbitrary waveform generator 1 to control the output logic of the digital-to-analog converter (DAC) in the arbitrary waveform generator 1. Specifically, this includes:

[0082] Output mode: Configure the output drive stage of arbitrary waveform generator 1 to work in constant voltage source mode or constant current source mode.

[0083] Output range: Sets the full-scale range of the output signal of arbitrary waveform generator 1.

[0084] Waveform output rate ( ): Defines the period during which the arbitrary waveform generator 1 updates its output voltage or current value. At the hardware level, this parameter controls the clock division factor for data conversion by the DAC, i.e., the physical duration for which two adjacent data points in the wavetable 2 are maintained at the output. This rate This determines the slope of the scanning signal change and serves as an indispensable time reference parameter for calculating the flip point in the subsequent step S5.

[0085] S103, the host computer 9 generates the data sequence of wavetable 2 in its local memory according to the scanning range and scanning accuracy required by the test task. For example, if it is necessary to scan the range of 2.0V to 3.0V with a scanning step size of 1mV, the host computer 9 generates a digitally encoded sequence containing {2.000, 2.001, 2.002, ..., 3.000}. This data sequence is then loaded into the high-speed waveform memory inside the arbitrary waveform generator 1.

[0086] For the specific data transmission method of loading the data sequence from the host computer 9 to the wave table 2, those skilled in the art can use direct memory access (DMA) or register polling, etc. The specific implementation is a well-known technology in the field and will not be described in detail here.

[0087] In step S2, a timing synchronization reference for the system is established and a hardware-level startup is performed. This step is executed by the global synchronization unit 6 according to the system clock 8, aiming to eliminate random delays in the transmission of instructions from the host computer 9 and ensure that the issuance of the excitation signal and the establishment of the timing start point are strictly aligned on a nanosecond time scale.

[0088] S201, the global synchronization unit 6 receives the start command from the host computer 9 through the communication interface. At this time, the instruction decoding logic inside the global synchronization unit 6 does not immediately output the start signal, but instead latches the start command into the internal register, generating a pre-trigger signal in the asynchronous clock domain.

[0089] S202, Global Synchronization Unit 6 performs cross-clock domain signal synchronization processing. Global Synchronization Unit 6 integrates a synchronization circuit based on cascaded D flip-flops, which uses system clock 8 (CLK) as its time base signal. When the synchronization circuit detects a valid transition edge (e.g., rising edge) of system clock 8, it shapes the aforementioned pre-trigger signal into a global start pulse signal that is strictly phase-aligned with system clock 8. This global start pulse signal physically manifests as a level step of a specific width, with a fixed delay between its transition time and the edge of system clock 8.

[0090] S203, the global synchronization unit 6 transmits the aforementioned global start pulse signal in parallel to the hardware enable terminal of the arbitrary waveform generator 1, the hardware enable terminal of the trigger unit 4, and the counting enable terminal of the internal counter 7 through a hardware signal transmission network. In terms of circuit layout, the propagation delay of each signal transmission path is controlled by PCB equal-length trace design or global clock network buffering inside the logic device, ensuring that the time difference between the arrival of the global start pulse signal at the arbitrary waveform generator 1, the trigger unit 4, and the counter 7 is less than one system clock cycle 8.

[0091] S204, in response to the received global startup pulse signal, the various functional modules of the system execute the following hardware actions within the same system clock cycle:

[0092] The waveform reading logic inside the arbitrary waveform generator 1 is reset and enabled by hardware, which points the reading pointer of the waveform table 2 to the starting address and drives the digital-to-analog converter to output the first data point.

[0093] The comparator circuit inside the trigger unit 4 is deshielded and begins to compare the input level of the follower pin of the chip under test 10 in real time.

[0094] The gate of counter 7 inside global synchronization unit 6 is enabled, and counter 7 starts accumulating the count value based on system clock 8. .

[0095] Through the steps S201 to S204 described above, the system achieves strict synchronization between "excitation source startup" and "timer startup" at the hardware level. The action of the arbitrary waveform generator 1 outputting the first waveform point and the action of the counter 7 recording the start clock cycle are physically locked within the same system clock cycle, thereby eliminating the uncertainty errors caused by operating system scheduling or bus transmission in the software control method.

[0096] For the specific implementation of the above-mentioned synchronization circuit, those skilled in the art can use a dual D flip-flop beat circuit or a handshake synchronization state machine to realize the conversion of asynchronous signals to the synchronous clock domain. The specific circuit topology is a well-known technology in the field of digital logic circuit design, and will not be described in detail here.

[0097] In step S3, the system enters the parallel scanning and real-time monitoring stage. During this stage, the arbitrary waveform generator 1, the trigger unit 4, and the global synchronization unit 6 are all active and execute their respective hardware logic.

[0098] S301, the arbitrary waveform generator 1 responds to the global start signal received in step S2 and begins autonomous scanning. The waveform control logic inside the arbitrary waveform generator 1 operates at the wavetable output rate set in the AWG parameter register 3. This serves as a timing reference, controlling the data updates of its internal digital-to-analog converter (DAC). This rate... The output time interval between adjacent data points in wavetable 2 is defined. Each time interval... Within the defined time period, the waveform control logic automatically reads the data point of the next address from the memory of wavetable 2 and feeds it to the digital-to-analog converter. This process is independently controlled by the hardware timing circuit of arbitrary waveform generator 1, without the intervention of host computer 9. Therefore, arbitrary waveform generator 1 provides a voltage or current signal that changes continuously with time to the excitation input pin of the chip under test 10.

[0099] In step S302, while the arbitrary waveform generator 1 is scanning, the trigger unit 4 also responds to the global start signal and enters the real-time monitoring state. The hardware comparator inside the trigger unit 4 continues to run continuously. One input of the hardware comparator is connected to the follow pin of the chip under test 10 to receive the real-time response signal; the other input is connected to the output of the internal digital-to-analog converter (DAC) corresponding to the trigger parameter register 5 to receive the target trigger level (analog reference voltage) set in step S1. The hardware comparator performs a real-time analog voltage comparison of the signals at its two inputs and outputs a high-level or low-level digital signal representing the comparison result.

[0100] S303, throughout the parallel execution of steps S301 and S302 described above, the counter 7 inside the global synchronization unit 6 remains enabled. The counter 7 takes the system clock 8 as input and increments its count value at each valid clock edge (e.g., the rising edge) of the system clock 8. Increment by one. At this point, the count value... It grows linearly over time, accurately tracking the total number of system clock cycles elapsed since the start of step S2.

[0101] In step S4, a trigger response and counter latch are performed. This step is completed collaboratively by the trigger unit 4 and the global synchronization unit 6, aiming to reliably capture the precise moment when the flip event occurs.

[0102] S401, during the parallel monitoring process in step S3, when the signal level of the follow pin of the chip under test 10 crosses the target trigger level set in step S1 (for example, the signal voltage drops from high level and falls below the threshold), the output state of the hardware comparator (such as S302) inside the trigger unit 4 is flipped (for example, it jumps from low level to high level).

[0103] The toggling of the comparator output state (S402) constitutes a hardware stop signal. The output logic of trigger unit 4 sends this hardware stop signal to the stop signal input of global synchronization unit 6 via a dedicated high-speed signal path. This signal transmission is purely hardware-driven, bypassing the software stack of host computer 9, ensuring low latency.

[0104] In S403, since the flip-flop timing of the chip under test 10 is based on its internal physical characteristics and is excited by the continuous signal from the arbitrary waveform generator 1, the phase of this flip-flop event relative to the system clock 8 is asynchronous. The hardware stop signal generated in S402 also arrives at the global synchronization unit 6 asynchronously.

[0105] S404, the timing control logic inside global synchronization unit 6, is designed to respond to this asynchronous hardware stop signal. In one specific implementation, global synchronization unit 6 uses this hardware stop signal to control the clock gating logic of counter 7, or to drive the count enable (CE) pin of counter 7.

[0106] In step S405, to address the potential metastability issue caused by the asynchronous hardware stop signal, the global synchronization unit 6 first synchronizes the signal. Taking the counter enable (CE) pin as an example: after step S2, the CE pin of counter 7 is set to a high-level active state. When the asynchronous hardware stop signal arrives in S402, this signal is sent to one or more D flip-flops (synchronizers) driven by the system clock 8, generating a synchronous stop signal aligned with the system clock 8. This synchronous stop signal then passes through logic gates to invalidate the CE pin of counter 7 (e.g., pull it low).

[0107] In S406, when the CE pin becomes invalid, counter 7 stops responding to system clock 8 at the next valid edge of system clock 8, and its internal register group no longer increments. The value of counter 7 is held at the last valid count value before it stopped responding. The count value This value is locked in counter 7, awaiting reading and calculation in subsequent step S5. In this way, the system reliably maps asynchronous toggle events to a synchronous system clock count value. superior.

[0108] In step S5, the flip point calculation based on time-domain mapping is performed. This step is implemented by the host computer 9 after the hardware trigger is completed, by reading the hardware status and performing data processing.

[0109] S501, the host computer 9 initiates a read operation to the global synchronization unit 6 through the test system bus to obtain the final count value of the counter 7 that was latched in step S406. .

[0110] S502, the host computer 9 retrieves the known parameters used in this test from the local configuration storage, specifically including: the wavetable output rate set in step S102. (Unit: seconds / point), and the fixed clock period of system clock 8. (Unit: seconds).

[0111] S503, host computer 9 based on the above three parameters ( , , ) Calculate the time when the flip event occurs, as well as the pre-stored inherent system delay parameters. Calculate the theoretical index position of wave table 2 output by arbitrary waveform generator 1 when the flip event occurs. .

[0112] Specifically, the system's inherent delay The acquisition method may include: before system testing, directly shorting the output of arbitrary waveform generator 1 to the input of trigger unit 4; configuring arbitrary waveform generator 1 to output a step signal with a steep edge, and configuring trigger unit 4 to capture the edge; starting the test and acquiring the count value of counter 7. At this time, since there is no delay from the tested chip 10, the count value... Multiply by the system clock cycle It mainly consists of cable transmission delay, comparator response delay, and logic gate delay, which are considered as inherent system delays. Stored in host computer 9 for subsequent testing and correction.

[0113] The computational model is based on the following logic:

[0114] First, based on the latched count value... and system clock cycle Calculate the total measurement time from step S2 (synchronous startup) to step S4 (triggered latch). :

[0115] ;

[0116] Next, considering the inherent physical delays in signal transmission via cable, hardware comparator response, and internal logic gate transmission, in order to improve calculation accuracy, it is necessary to subtract these inherent delays from the total measurement time. Thus, the effective time of the actual waveform operation is obtained. :

[0117] ;

[0118] in, The system can be pre-acquired and configured in the host computer 9 through methods such as system short-circuit self-calibration test.

[0119] S504, due to the arbitrary waveform generator 1 using The time interval outputs a wavetable point; therefore, the effective time... Corresponding wave table index (Assuming the starting index of the wavetable is 0) it can be calculated using the following formula:

[0120] ;

[0121] in, The calculated wavetable index value (dimensionless). The total number of system clock cycles (dimensionless) latched by counter 7. The period of the system clock 8 (in seconds). Waveform output rate (unit: seconds / point). The inherent system delay (unit: seconds).

[0122] S505, due to the count value The resolution is limited by the system clock. Furthermore, the flip event occurs asynchronously, and the index calculated in S504... This is typically a non-integer (i.e., a floating-point number). This non-integer index... It precisely indicates the location of the flip event in the wavetable.

[0123] S506, to obtain the non-integer index The corresponding precise flip point value The host computer 9 needs to perform interpolation calculations on the discrete data points in wavetable 2. The host computer 9 obtains adjacent integer index values ​​by addressing the local wavetable data array generated in S103. and Corresponding waveform values and A linear interpolation algorithm can be used, and its calculation formula is as follows:

[0124] ;

[0125] in, Indicates to The integer index obtained by rounding down. Indicates to The integer index obtained by rounding up. This indicates the number stored in wave table 2. The value at each index position. This indicates the number stored in wave table 2. The value at each index position.

[0126] S507. To simplify the calculation process, a simplified value selection method can also be used, such as directly rounding down. Alternatively, use the nearest neighbor value with rounding. .in, Indicates to The value corresponding to the nearest integer index after rounding.

[0127] S508 is ultimately calculated using S506 or S507. The numerical value is the precise flip point (voltage or current value) of the chip 10 under test under the specified test conditions. The host computer 9 stores or displays this value.

[0128] To further clarify the collaborative working process of the technical solution of this invention, a specific working scenario example will be used below. This example aims to demonstrate how, in actual testing applications, the various hardware modules work collaboratively based on a unified timing architecture to accurately measure the input threshold voltage of the device under test (DUT).

[0129] Suppose the test task is to measure the high-level toggling threshold of a general-purpose input / output (GPIO) pin of a chip under test (CUT) 10. The expected toggling voltage is between 1.2V and 1.8V.

[0130] During the test preparation phase, the host computer 9 constructs wavetable 2 according to the test requirements. The scan start voltage is set to 1.0V, the stop voltage to 2.0V, and the voltage step accuracy to 1mV. The host computer 9 generates a linearly increasing digital sequence {1.000V, 1.001V, ..., 2.000V} containing 1001 voltage points in its memory. Simultaneously, the system clock 8 is set to a frequency of 100MHz, i.e., the clock period... Configure the hardware parameters on the host computer 9. Set the wavetable output rate. The frequency is set to 100 ns / point. This means that the arbitrary waveform generator 1 updates its output voltage every 100 ns, and the entire scan process, if completed, will take approximately 100.1 µs. The target trigger level of trigger unit 4 is set to a logic high-level determination threshold (e.g., setting the comparator reference voltage to the characteristic voltage when the output of the chip under test 10 flips), and the trigger mode is configured as level transition trigger. Furthermore, the system is calibrated to confirm the inherent delay from signal output to trigger response. It is 20ns.

[0131] Subsequently, the system performs a synchronous startup. The host computer 9 issues a command, and the global synchronization unit 6 generates a global startup pulse upon detecting the rising edge of the system clock 8. Within the same 10ns clock cycle:

[0132] Counter 7 is reset to zero and begins accumulating the count value at a rate of 100MHz. ;

[0133] Arbitrary waveform generator 1 starts outputting the first point (1.000V) in the wavetable.

[0134] Trigger unit 4 releases the lockout and begins monitoring the feedback signal of the chip under test 10.

[0135] The system then enters the scanning and monitoring phase. Arbitrary waveform generator 1, with a period of 100ns, drives the digital-to-analog converter to sequentially output voltage values ​​of 1.001V and 1.002V, forming a stepped linear ramp excitation signal at the input of the chip under test 10. Simultaneously, counter 7 continuously counts, and its count value... It increases linearly over time. During this period, the host computer 9 does not participate in any real-time control, thus freeing up bus resources.

[0136] When a flip event is detected, for example, when the output of arbitrary waveform generator 1 is sent to a certain point, causing the actual voltage at the input terminal of the chip under test 10 to reach its physical flip threshold (assuming the actual threshold is 1.5425V), the output pin state of the chip under test 10 flips. The hardware comparator of trigger unit 4 detects this flip within a nanosecond time and sends a stop signal to global synchronization unit 6.

[0137] During the hardware latching phase, after synchronizing the stop signal, global synchronization unit 6 disables the enable pin of counter 7. Assume that the final count value latched by counter 7 is at this point. The value is 5427. This means that the system took 5427 clock cycles from startup to latch flip-flop.

[0138] Finally, the host computer performs the calculation. Host computer 9 reads the latch value. And calculate using known parameters:

[0139] Total measurement time .

[0140] Effective running time .

[0141] Corresponding wave table index position .

[0142] Due to index The voltage is 542.5. The host computer 9 reads data point 542 (corresponding to 1.542V) and data point 543 (corresponding to 1.543V) from wavetable 2. Using the linear interpolation formula:

[0143] ;

[0144] The calculated result of 1.5425V is the accurate threshold voltage measured in this study.

[0145] As can be seen from this embodiment, the present invention uses a high-frequency counter (100MHz) as the system time reference and further subdivides the resolution of voltage measurement (step 1mV) through time domain interpolation, thereby achieving measurement results higher than the step accuracy of wavetable without using a high bit-width analog-to-digital converter.

[0146] To verify the significant advantages of the device and method of this invention in terms of testing efficiency and accuracy compared to existing technologies, the following is in conjunction with the appendix. Figure 3 The specific comparative test experiments are explained.

[0147] See attached document Figure 3 , Figure 3 This is a schematic diagram comparing the test times of the technical solution according to an embodiment of the present invention and existing technical solutions under different scanning accuracies. To visually illustrate the data differences, an appendix is ​​attached. Figure 3 The test data trend of the prior art solution is represented by a solid line with circular marker nodes, and the test data trend of the present invention solution is represented by a dashed line with triangular marker nodes.

[0148] Experimental conditions set:

[0149] Select the same chip under test 10 and perform input toggle point (VIH) testing on the same GPIO pin. The scan voltage range is set to 1.0V to 2.0V (spanning 1.0V).

[0150] Existing technical solution: Testing is performed using a traditional power parameter measurement unit (PPMU). The PPMU operates in a step-by-step cycle of "setting voltage - waiting for stabilization - measuring current - determining flip-flop". Each voltage step requires a command communication between the host PC and the tester.

[0151] The technical solution of this invention adopts the hardware synchronous scanning mode of arbitrary waveform generator 1 and trigger unit 4 in the aforementioned embodiments. Arbitrary waveform generator 1 generates continuous waveforms, and trigger unit 4 is triggered in real time by hardware, requiring only one start command from the host computer 9.

[0152] Experimental data analysis:

[0153] like Figure 3As shown, the horizontal axis represents the scanning accuracy (unit: mV), with a smaller value indicating higher accuracy (closer step size); the vertical axis represents the total time required to complete one full scan test (unit: ms).

[0154] 1. Comparison of test time magnitudes: In a typical test scenario with a scanning accuracy of 5mV (i.e., a step size of 5mV, for a total of 200 points):

[0155] Existing technical solutions have a long testing time due to the large amount of communication handshake between the PC and the Tester and the PPMU establishment time (estimated to be around 830ms based on the optimization ratio).

[0156] By employing the technical solution of this invention, the intermediate communication process is eliminated, and the arbitrary waveform generator 1 outputs a continuous waveform, requiring a total test time of only 54ms. Compared to existing technical solutions, this invention significantly reduces the test time by approximately 93.5%, greatly improving the throughput of production line testing.

[0157] 2. Comparison of the correlation between accuracy and time: Observation of the appendix Figure 3 The solid line trend (existing technology) shows that as the scanning accuracy increases from 15mV to 1mV (i.e., the horizontal axis value decreases), the number of points that need to be scanned increases exponentially (from approximately 67 points to 1000 points). Since the time cost of the PPMU solution is linearly positively correlated with the number of points, its testing time shows a sharp upward trend, even reaching several seconds at 1mV high accuracy, making it difficult to meet the real-time requirements of mass production testing.

[0158] Comparative observation appendix Figure 3 The dotted line trend (in this invention) shows that the testing time remained stable without a significant increase as the scanning accuracy improved. This is because this invention is based on the time-domain mapping principle, where the accuracy of the flip point depends primarily on the system clock frequency and the interpolation algorithm, rather than simply on the density of wavetable points. Even when using a relatively sparse wavetable (such as a 5mV step), extremely high measurement resolution can still be obtained through time interpolation calculation in step S5. Therefore, this invention achieves decoupling of testing speed and accuracy while ensuring high precision, resolving the technical contradiction of high precision leading to low efficiency in existing technologies.

[0159] In summary, this invention utilizes a global synchronization unit to coordinate the hardware-level parallel operation of the arbitrary waveform generator 1 and the trigger unit 4. This not only improves the real-time performance of the measurement by using continuous signals, but also achieves an order-of-magnitude improvement in testing efficiency by eliminating redundant communication commands, while ensuring or even surpassing the measurement accuracy of existing technologies.

[0160] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for scanning the voltage-current reversal point of a chip, characterized in that, Includes the following steps: S1. The host computer writes configuration parameters to the arbitrary waveform generator and the trigger unit respectively, and loads the generated wavetable data sequence into the storage space of the arbitrary waveform generator; S2. The global synchronization unit receives the start command issued by the host computer, converts the start command into a global start signal that is phase-aligned with the system clock based on the system clock, and sends the global start signal in parallel to the arbitrary waveform generator, the trigger unit, and the counter inside the global synchronization unit. S3. The arbitrary waveform generator responds to the global start signal and outputs the wavetable data sequence to the chip under test sequentially based on the wavetable output rate in the configuration parameters. At the same time, the counter responds to the global start signal and starts to accumulate the count value based on the system clock. The trigger unit responds to the global start signal and starts to monitor the follower pin status of the chip under test in real time. S4. When the triggering unit detects that the status of the following pin meets the triggering condition in the configuration parameters, it generates a stop signal. The global synchronization unit receives the stop signal and controls the counter to stop the accumulation operation to latch the current count value. S5. The host computer reads the latched count value, calculates the theoretical index position corresponding to the flip event based on the count value, the period of the system clock and the wavetable output rate, and extracts the flip point value of the chip under test from the wavetable data sequence using the theoretical index position.

2. The method for scanning the voltage-current reversal point of a chip according to claim 1, characterized in that, The S1 step specifically includes: The host computer writes the target trigger level, trigger judgment logic, and measurement range to the register inside the trigger unit through the system bus. The trigger unit controls the internal digital-to-analog converter to generate an analog reference voltage based on the target trigger level and inputs it to the reference terminal of the hardware comparator. The host computer writes the output drive mode, output range and wavetable output rate into the register inside the arbitrary waveform generator, wherein the wavetable output rate defines the physical time length during which two adjacent data points in the wavetable data sequence are maintained at the output end. The host computer generates the wavetable data sequence containing continuously linearly increasing or decreasing digital codes in its local memory according to the scanning range and scanning step accuracy set by the test task, and transmits the wavetable data sequence to the arbitrary waveform generator through direct memory access.

3. The method for scanning the voltage-current reversal point of a chip according to claim 1, characterized in that, The S2 step specifically includes: The global synchronization unit receives the start command from the host computer in the asynchronous clock domain, and latches the start command to generate a pre-trigger signal; The global synchronization unit utilizes its internally integrated synchronization circuit to shape the pre-trigger signal into a global start pulse signal that is strictly aligned with the phase of the system clock when a valid transition edge of the system clock is detected. The global synchronization unit transmits the global start pulse signal simultaneously to the hardware enable terminal of the arbitrary waveform generator, the hardware enable terminal of the trigger unit, and the counting enable terminal of the counter through a hardware signal transmission network, and controls the propagation delay difference of each signal transmission path to be less than one system clock cycle.

4. The method for scanning the voltage-current reversal point of a chip according to claim 1, characterized in that, The S3 step specifically includes: The waveform control logic inside the arbitrary waveform generator is reset and enabled. Using the wavetable output rate as the timing reference, the internal digital-to-analog converter is driven to read data point by point from the starting address of the wavetable data sequence and convert it into an analog excitation signal to be applied to the chip under test. The hardware comparator inside the trigger unit is de-shielded, the real-time signal of the follow pin is connected to one input of the hardware comparator, and the preset analog reference voltage is connected to the other input of the hardware comparator. The hardware comparator continuously compares the analog voltages of the signals at the two input terminals and outputs a digital level signal representing the comparison result.

5. The method for scanning the voltage-current reversal point of a chip according to claim 1, characterized in that, The S4 step specifically includes: When the follow pin signal of the chip under test crosses the analog reference voltage, the output state of the hardware comparator flips to form a hardware stop signal. The triggering unit sends the hardware stop signal to the stop signal input terminal of the global synchronization unit through a dedicated signal path; The global synchronization unit receives the hardware stop signal and converts the hardware stop signal into a synchronization stop signal aligned with the system clock through a synchronizer. The global synchronization unit uses the synchronization stop signal to invalidate the counter's count enable pin, so that the counter retains the last valid count value before the stop response as the latched count value.

6. The method for scanning the voltage-current reversal point of a chip according to claim 1, characterized in that, The calculation of the theoretical index position corresponding to the flip event in step S5 includes: The host computer obtains the count value latched by the counter through the bus, and retrieves the wavetable output rate and the fixed clock period of the system clock stored locally. The host computer multiplies the count value by the fixed clock period to obtain the total measurement time from the time the global start signal is issued to the time the stop signal is latched. The host computer divides the total measurement time by the wavetable output rate to obtain the theoretical index position, wherein the theoretical index position represents the position coordinate in the wavetable data sequence corresponding to the time when the flip event occurs.

7. The method for scanning the voltage-current reversal point of a chip according to claim 6, characterized in that, The calculation of the theoretical index position corresponding to the flip event in step S5 also includes the process of removing the inherent system delay: Before performing the test, the output of the arbitrary waveform generator is shorted to the input of the trigger unit and a step signal capture test is performed to obtain the inherent delay parameters of the system. The host computer subtracts the inherent delay parameter of the system from the total measurement time to obtain the effective time of the actual waveform operation; The host computer divides the effective time by the wavetable output rate to obtain the corrected theoretical index position.

8. The method for scanning the voltage-current reversal point of a chip according to claim 7, characterized in that, Step S5, which involves extracting the flip-point value of the chip under test from the wavetable data sequence, includes: The host computer determines whether the theoretical index position is not an integer; When the theoretical index position is not an integer, the host computer performs a floor operation on the theoretical index position to obtain a first integer index, and performs a floor operation on the theoretical index position to obtain a second integer index; The host computer addresses the wavetable data sequence stored locally and reads the first waveform value corresponding to the first integer index and the second waveform value corresponding to the second integer index.

9. The method for scanning the voltage-current reversal point of a chip according to claim 8, characterized in that, The step S5, which involves extracting the flip-point value of the chip under test from the wavetable data sequence, further includes: The host computer performs linear interpolation calculations based on the first waveform value, the second waveform value, and the decimal part of the theoretical index position. The host computer uses the first waveform value as a reference and adds the product of the decimal part and the difference between the first waveform value and the second waveform value to obtain the accurate flip point value. The host computer stores or displays the calculated flip point value as the final measurement result of the chip under test.

10. An apparatus for scanning the voltage-current reversal point of a chip, applied to the method for scanning the voltage-current reversal point of a chip as described in any one of claims 1-9, characterized in that, include: The host computer is used to generate configuration parameters and wavetable data sequences, and to issue start commands; An arbitrary waveform generator is provided, wherein the input terminal of the arbitrary waveform generator is connected to the host computer to receive the configuration parameters and the wavetable data sequence, and the output terminal of the arbitrary waveform generator is connected to the excitation input pin of the chip under test to provide a continuously changing excitation signal to the chip under test. A trigger unit, the input terminal of which is connected to the follower pin of the chip under test, is used to monitor the signal status of the follower pin in real time and generate a stop signal according to the triggering conditions; A global synchronization unit is connected to the host computer, the arbitrary waveform generator, and the triggering unit, respectively. The global synchronization unit contains a counter. The global synchronization unit is used to respond to the start command by sending a phase-aligned global start signal in parallel to the arbitrary waveform generator, the trigger unit, and the counter based on the system clock. When the stop signal sent by the trigger unit is received, the unit controls the counter to latch the current count value so that the host computer can read and calculate the flip-flop value of the chip under test.

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