A monomer battery internal resistance measurement method, device and storage medium

Abstract

A kind of monomer battery resistance measurement method, device and storage medium, including steps: by external power supply 48V DC voltage drives DBN battery sampling special chip work, battery monitoring edge computing terminal is transmitted to DBN battery sampling special chip by daisy chain communication unit with instruction;By DBN battery sampling special chip generates positive and negative square wave signal and drives battery excitation unit work;Battery excitation unit is discharged according to required frequency drive excitation resistance to battery;Signal amplification circuit provides battery voltage sampling unit after real-time voltage of battery is conditioned, again by the signal conversion of ADC digital-analog conversion unit of DBN battery sampling special chip, and according to the voltage Vm when excitation resistance is accessed to battery and the voltage Vb when battery is separated, the internal resistance is obtained by calculation.This application can not affect the consistency of single battery by battery pack or external power supply, using DBN special chip can fully consider the characteristics and monitoring requirements of battery, with higher performance.

Description

Technical Field

[0001] This invention belongs to the field of energy storage components and batteries, and particularly relates to a method, device and storage medium for measuring the internal resistance of a single battery cell. Background Technology

[0002] With the development of battery technology, drawing power from the battery will increase the battery load, accelerate self-discharge and cause poor battery consistency. DC pulse discharge below 1A has a large current, which is not good for small capacity batteries, such as 10AH batteries, where the current has reached 0.1C10.

[0003] However, existing power measurement strategies employ DC pulse discharge technology at a certain frequency, around 1kHz, resulting in a limited frequency range. Furthermore, the configuration integrating an MCU, bandpass filter, load drive, operational amplifier, and voltage sampling offers no cost advantage and does not involve temperature acquisition, failing to meet the requirements for flexible, efficient, and low-cost battery internal resistance testing.

[0004] Therefore, how to design a method that can improve operational safety and ensure stable measurement performance is an urgent problem to be solved in current battery internal resistance measurement technology. Summary of the Invention

[0005] To address the shortcomings of the existing technology, the present invention provides a method for measuring the internal resistance of a single battery cell, the method comprising the following steps:

[0006] The DBN battery sampling chip is driven by an external power supply with a 48V DC voltage. The battery monitoring edge computing terminal sends an internal resistance test command, which is transmitted to the DBN battery sampling chip through a daisy-chain communication unit.

[0007] A daisy-chain topology is formed by cascading DBN battery sampling dedicated chips through serial communication interfaces. The battery monitoring edge computing terminal is connected to the first DBN battery sampling dedicated chip through a serial communication interface. The serial communication interfaces of each DBN battery sampling dedicated chip are connected to the previous and next DBN battery sampling dedicated chips respectively. The serial communication interface of the last DBN battery sampling dedicated chip is left floating or connected to a resistor.

[0008] The DBN battery sampling chip integrates a high-speed PWM generator, which generates positive and negative square wave signals to drive the battery excitation unit according to the instructions issued by the battery monitoring edge computing terminal of the main device. The frequency of the square wave signal is preset by the battery monitoring edge computing terminal.

[0009] The battery excitation unit drives the excitation resistor to discharge the battery at the required frequency, wherein the maximum discharge current is less than or equal to 150mA;

[0010] The signal amplification circuit conditions the real-time voltage of the battery and provides it to the battery voltage sampling unit. The ADC digital-to-analog converter built into the DBN battery sampling chip performs signal conversion. Based on the voltage divider law, the internal resistance Ri = (Rext*(Vb-Vm)) / Vm is obtained according to the voltage sampled when the excitation resistor is connected to the battery (Vm) and the voltage sampled when the battery is disconnected (Vb). Here, Rext is the resistance value of the externally applied excitation resistor.

[0011] The internal resistance test instruction includes an internal resistance test strategy, which includes:

[0012] Define the test state space, including the frequency state space, amplitude state space, and duration state space;

[0013] Establish a dynamic model of battery internal resistance and temperature: simulate the changes in battery internal resistance and temperature under different operating conditions, and integrate the internal resistance and temperature model into the test environment to generate actual internal resistance and temperature data during the test process.

[0014] The optimal testing strategy is learned using the Q-Learning algorithm: Initialize Q(s, a) to 0, where s is the state and a is the behavior; at each time step, select the optimal behavior a in the current state s, and observe the environmental feedback reward r, the next state s', and the optimal behavior a'; update the Q value according to the Q-Learning update rule:

[0015] Q(s,a)=Q(s,a)+α*(r+γ*max_a'Q(s',a')-Q(s,a))

[0016] Where r is the reward function after performing action a in the current state s; α is the learning rate, ranging from [0, 1], representing the degree of learning of new information; γ is a factor, ranging from [0, 1]; max_a'Q(s', a') represents the value corresponding to the optimal action a' selected in the next state s';

[0017] Repeated iterations converge to the optimal test strategy.

[0018] Among them, the internal resistance calculation model based on machine learning includes:

[0019] Determine the input characteristics of the model: external resistance Rext, battery voltage Vb, and battery internal voltage Vm;

[0020] Collect historical internal resistance calculation data and train the model to learn the formula coefficients: establish a dataset containing internal resistance calculation samples, preprocess the dataset, and train a machine learning model to fit the internal resistance calculation formula based on the gradient descent optimization algorithm.

[0021] The trained model is deployed to the battery monitoring edge computing terminal to collect the battery's Rext, Vb, and Vm data in real time, and input into the deployed model for internal resistance calculation.

[0022] The system employs a distributed computing architecture, configuring multiple battery monitoring edge computing terminals to collaboratively complete internal resistance analysis, including:

[0023] The master-slave distributed architecture is adopted, and the internal resistance calculation task is divided into multiple sub-tasks, including data acquisition, feature calculation and model inference. The sub-tasks are dynamically allocated according to the computing resources of the battery monitoring edge computing terminal of each slave node, and the computing load of each node is balanced based on the load balancing algorithm.

[0024] Establish a distributed data storage system to manage the computational data of each node, and configure the master node to obtain the latest internal resistance calculation results in a timely manner based on the real-time data synchronization mechanism.

[0025] The voltage sampling unit performs voltage sampling based on compressed sensing, including:

[0026] Establish a state-space model for the battery voltage time-series signal: Analyze the battery voltage time-series signal to determine its time correlation and spectral characteristics, select a state-space model to describe the battery voltage signal, and determine the parameters of the state-space model, including the state transition matrix and the observation matrix;

[0027] Design a compressed sensing sampling matrix to reduce the ADC sampling rate: Based on the sparsity of the battery voltage signal, a random sampling matrix Φ is selected, the coherence of the sampling matrix is ​​calculated, and the ADC sampling rate is compressed by adjusting the dimension of the sampling matrix.

[0028] The original voltage signal is reconstructed using the orthogonal matching pursuit (OMP) algorithm: the voltage data y = Φx obtained by compressed sensing is used to reconstruct the original voltage signal x based on y and Φ using the OMP algorithm.

[0029] Estimating the true value of battery voltage based on Kalman filter: Using a state-space model, the actual value of battery voltage is estimated based on a Kalman filter;

[0030] The compressed sensing sampling matrix Φ and the OMP reconstruction algorithm are deployed on the voltage sampling unit for voltage sampling.

[0031] Among them, Fourier transform or discrete wavelet transform is performed on the sampled battery voltage signal to obtain the voltage signal in the frequency domain or time-frequency domain;

[0032] Extract time-frequency domain features, calculate power spectral density (PSD) based on the transformed voltage signal, and analyze the energy distribution characteristics of the signal in different frequency bands;

[0033] Principal Component Analysis (PCA) is used to reduce dimensionality and remove redundant information, resulting in an optimized feature set. The Recursive Feature Selection (RFE) algorithm is then employed to optimize the feature set by iteratively eliminating irrelevant features to obtain the optimal feature subset.

[0034] The optimized feature set is used as input to the internal resistance calculation model.

[0035] The DBN battery sampling chip integrates a 0.5Hz-7.5kHz frequency adjustment unit, a positive and negative square wave generator, a multi-channel voltage sampling circuit, and a daisy-chain communication unit.

[0036] The 0.5Hz-7.5kHz frequency band is divided into four sub-bands: 0.5Hz-10Hz, 10Hz-100Hz, 100Hz-1kHz, and 1kHz-7.5kHz.

[0037] The sampled signals in the four sub-frequency bands are acquired respectively and sent to the edge computing terminal for internal resistance analysis and calculation based on the communication interface.

[0038] This invention utilizes a 48V DC power supply from an external power source to drive a dedicated DBN battery sampling chip. A battery monitoring edge computing terminal issues an internal resistance test command, which is transmitted to the DBN battery sampling chip via a daisy-chain communication unit. The DBN battery sampling chip generates positive and negative square wave signals to drive a battery excitation unit, the frequency of which is preset by the battery monitoring edge computing terminal. The battery excitation unit drives an excitation resistor to discharge the battery at the required frequency, with a maximum discharge current less than or equal to 150mA. A signal amplification circuit conditions the real-time battery voltage and provides it to the battery voltage sampling unit. The DBN battery sampling chip's ADC (digital-to-analog converter) then performs signal conversion. Based on the voltage divider law, and using the voltage Vm collected when the excitation resistor is connected to the battery and Vb collected when the battery is disconnected, the internal resistance Ri = (Rext*(Vb-Vm)) / Vm is obtained, where Rext is the resistance value of the externally applied excitation resistor. This invention, powered by a battery pack or external power source, does not affect the consistency of individual cells. Using a dedicated DBN chip, it fully considers the characteristics and monitoring requirements of the battery, has high performance, and can meet the needs of flexible, efficient, and low-cost battery internal resistance testing. Attached Figure Description

[0039] The above and other objects, features, and advantages of exemplary embodiments of the present disclosure will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of the present disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:

[0040] Figure 1 This is a flowchart illustrating a method for measuring the internal resistance of a single-cell battery according to an embodiment of the present invention.

[0041] Figure 2 This illustrates the circuit structure of a single-cell battery internal resistance measuring device according to an embodiment of the present invention. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0043] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms, and “multiple” generally includes at least two unless the context clearly indicates otherwise.

[0044] It should be understood that although the terms first, second, third, etc., may be used to describe... in the embodiments of the present invention, these... should not be limited to these terms. These terms are only used to distinguish... For example, first... may also be referred to as second... without departing from the scope of the embodiments of the present invention, and similarly, second... may also be referred to as first...

[0045] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0046] Depending on the context, the words “if” or “suppose” as used here can be interpreted as “when” or “in response to determination” or “in response to detection.” Similarly, depending on the context, the phrases “if determination” or “if detection (of the stated condition or event)” can be interpreted as “when determination” or “in response to determination” or “when detection (of the stated condition or event)” or “in response to detection (of the stated condition or event).”

[0047] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device that includes said element.

[0048] Existing battery internal resistance measurement technologies have certain limitations. Common methods such as voltage drop and resistance testing both have inherent errors, especially when the battery is low in charge or aging, leading to inaccurate measurement accuracy and potentially inaccurate battery condition assessments. Measuring internal resistance using discharge current or AC impedance methods requires a certain current to flow through the battery, consuming some of its capacity. For some small portable devices, this power consumption can affect normal operating time.

[0049] Many internal resistance measurement methods can only be performed offline, failing to provide real-time, continuous monitoring of the battery. This makes it impossible to detect internal battery problems in a timely manner, missing the optimal maintenance window. Furthermore, battery internal resistance measurement results reflect the combined effects of the positive and negative electrode materials and the electrolyte, unable to distinguish the characteristics of each component individually, limiting in-depth analysis of battery performance. On the other hand, some precise internal resistance measurement methods require specialized testing equipment, which is costly and limits their application in small and medium-sized equipment.

[0050] like Figure 1 As shown, this invention discloses a method for measuring the internal resistance of a single-cell storage battery, the method comprising:

[0051] The DBN battery sampling chip is powered by an external 48V DC power supply. The battery monitoring edge computing terminal sends an internal resistance test command, which is transmitted to the DBN battery sampling chip through a daisy-chain communication unit.

[0052] In one embodiment, since drawing power from a single battery cell would strain the battery and cause imbalances, an external battery pack is used to supply 48V DC power to drive the DBN. Using an external 48V DC power supply provides sufficient voltage and current to ensure stable and reliable chip operation. Compared to relying on the battery itself for power, this method is unaffected by battery capacity and voltage fluctuations, ensuring long-term stable system operation.

[0053] A 48V power supply can provide a higher operating voltage for the DBN chip, thereby improving the resolution and sampling accuracy of its internal A / D converter. Precise battery voltage and current sampling helps to more accurately assess the battery's state and performance.

[0054] In one embodiment, the daisy-chain topology has high redundancy, meaning that even if one node or link fails, other nodes can continue to transmit data, improving the reliability of the entire system. When a node fails, rapid recovery can be achieved by reconfiguring the routing, ensuring that critical information can be delivered in a timely manner.

[0055] Nodes in a daisy-chain network typically operate in low-power mode, significantly reducing the overall system's energy consumption. This is highly beneficial for battery-powered embedded applications, extending device lifespan. Adding new nodes easily expands the coverage and number of connected devices within the daisy-chain network. The addition of new nodes does not significantly interfere with the existing network, demonstrating excellent plug-and-play characteristics.

[0056] A daisy-chain topology is formed by cascading DBN battery sampling dedicated chips through serial communication interfaces. The battery monitoring edge computing terminal is connected to the first DBN battery sampling dedicated chip through a serial communication interface. The serial communication interfaces of each DBN battery sampling dedicated chip are connected to the previous and next DBN battery sampling dedicated chips respectively. The serial communication interface of the last DBN battery sampling dedicated chip is left floating or connected to a resistor.

[0057] The connection method between the battery monitoring edge computing terminal and the DBN battery sampling dedicated chip fully leverages the advantages of daisy-chain communication, offering significant advantages in scalability, wiring simplicity, cost-effectiveness, and reliability. It is highly suitable for large-scale battery pack internal resistance measurement and condition monitoring applications. Data processing is centralized at the battery monitoring edge computing terminal, while the DBN battery sampling dedicated chip is only responsible for acquiring and executing instructions, reducing the cost of a single chip. Furthermore, centralized data processing and control also facilitates system maintenance and upgrades.

[0058] The internal resistance test instruction includes an internal resistance test strategy, which includes:

[0059] Define the test state space, including the frequency state space, amplitude state space, and duration state space;

[0060] Establish a dynamic model of battery internal resistance and temperature: simulate the changes in battery internal resistance and temperature under different operating conditions, and integrate the internal resistance and temperature model into the test environment to generate actual internal resistance and temperature data during the test process.

[0061] The optimal testing strategy is learned using the Q-Learning algorithm: Initialize Q(s, a) to 0, where s is the state and a is the behavior; at each time step, select the optimal behavior a in the current state s, and observe the environmental feedback reward r, the next state s', and the optimal behavior a'; update the Q value according to the Q-Learning update rule:

[0062] Q(s,a)=Q(s,a)+α*(r+γ*max_a'Q(s',a')-Q(s,a))

[0063] Where r is the reward function after performing action a in the current state s; α is the learning rate, ranging from [0, 1], representing the degree of learning of new information; γ is a factor, ranging from [0, 1]; max_a'Q(s', a') represents the value corresponding to the optimal action a' selected in the next state s';

[0064] Repeated iterations converge to the optimal test strategy.

[0065] The DBN battery sampling chip integrates a high-speed PWM generator, which generates positive and negative square wave signals to drive the battery excitation unit according to the instructions issued by the battery monitoring edge computing terminal of the main device. The frequency of the square wave signal is preset by the battery monitoring edge computing terminal.

[0066] The battery excitation unit drives the excitation resistor to discharge the battery at the required frequency, wherein the maximum discharge current is less than or equal to 150mA.

[0067] Among them, a relatively mild discharge current of less than 150mA can prevent the battery from being over-discharged, reduce the rapid aging of electrode materials and electrolytes, extend the battery's lifespan, and improve the reliability and stability of the entire system.

[0068] In one embodiment, the low discharge current design makes it easier to integrate with other modules such as the battery management system and battery charging, expanding the applicability of the battery excitation unit and improving the overall system compatibility.

[0069] The signal amplification circuit conditions the real-time voltage of the battery and provides it to the battery voltage sampling unit. The ADC digital-to-analog converter built into the DBN battery sampling chip performs signal conversion. Based on the voltage divider law, the internal resistance Ri = (Rext*(Vb-Vm)) / Vm is obtained according to the voltage sampled when the excitation resistor is connected to the battery (Vm) and the voltage sampled when the battery is disconnected (Vb). Here, Rext is the resistance value of the externally applied excitation resistor.

[0070] In one embodiment, an internal resistance calculation model is established based on machine learning, including:

[0071] Determine the input characteristics of the model: external resistance Rext, battery voltage Vb, and battery internal voltage Vm;

[0072] Collect historical internal resistance calculation data and train the model to learn the formula coefficients: establish a dataset containing internal resistance calculation samples, preprocess the dataset, and train a machine learning model to fit the internal resistance calculation formula based on the gradient descent optimization algorithm.

[0073] The trained model is deployed to the battery monitoring edge computing terminal to collect the battery's Rext, Vb, and Vm data in real time, and input into the deployed model for internal resistance calculation.

[0074] In one embodiment, a distributed computing architecture is adopted, configuring multiple battery monitoring edge computing terminals to collaboratively complete internal resistance analysis, including:

[0075] The master-slave distributed architecture is adopted, and the internal resistance calculation task is divided into multiple sub-tasks, including data acquisition, feature calculation and model inference. The sub-tasks are dynamically allocated according to the computing resources of the battery monitoring edge computing terminal of each slave node, and the computing load of each node is balanced based on the load balancing algorithm.

[0076] Establish a distributed data storage system to manage the computational data of each node, and configure the master node to obtain the latest internal resistance calculation results in a timely manner based on the real-time data synchronization mechanism.

[0077] In one embodiment, the voltage sampling unit performs voltage sampling based on compressed sensing, including:

[0078] Establish a state-space model for the battery voltage time-series signal: Analyze the battery voltage time-series signal to determine its time correlation and spectral characteristics, select a state-space model to describe the battery voltage signal, and determine the parameters of the state-space model, including the state transition matrix and the observation matrix;

[0079] Design a compressed sensing sampling matrix to reduce the ADC sampling rate: Based on the sparsity of the battery voltage signal, a random sampling matrix Φ is selected, the coherence of the sampling matrix is ​​calculated, and the ADC sampling rate is compressed by adjusting the dimension of the sampling matrix.

[0080] The original voltage signal is reconstructed using the orthogonal matching pursuit (OMP) algorithm: the voltage data y = Φx obtained by compressed sensing is used to reconstruct the original voltage signal x based on y and Φ using the OMP algorithm.

[0081] Estimating the true value of battery voltage based on Kalman filter: Using a state-space model, the actual value of battery voltage is estimated based on a Kalman filter;

[0082] The compressed sensing sampling matrix Φ and the OMP reconstruction algorithm are deployed on the voltage sampling unit for voltage sampling.

[0083] In one embodiment, the sampled battery voltage signal is subjected to Fourier transform or discrete wavelet transform to obtain a representation of the voltage signal in the frequency domain or time-frequency domain.

[0084] Extract time-frequency domain features, calculate power spectral density (PSD) based on the transformed voltage signal, and analyze the energy distribution characteristics of the signal in different frequency bands;

[0085] Principal Component Analysis (PCA) is used to reduce dimensionality and remove redundant information, resulting in an optimized feature set. The Recursive Feature Selection (RFE) algorithm is then employed to optimize the feature set by iteratively eliminating irrelevant features to obtain the optimal feature subset.

[0086] The optimized feature set is used as input to the internal resistance calculation model.

[0087] In one embodiment, the DBN battery sampling chip integrates a 0.5Hz-7.5kHz frequency adjustment unit, a positive and negative square wave generator, a multi-channel voltage sampling circuit, and a daisy-chain communication unit.

[0088] The DBN chip employs a high-precision analog-to-digital converter and signal processing circuitry, enabling high-accuracy sampling and measurement of parameters such as battery voltage and current. Compared to general-purpose microcontrollers, the DBN chip provides more precise battery state monitoring data. Specifically designed and optimized for battery applications, the DBN chip offers enhanced anti-interference capabilities and stability. Compared to general-purpose chips, the DBN chip is better suited for harsh environments, improving the reliability of the entire battery management system.

[0089] In one embodiment, the 0.5Hz-7.5kHz frequency band is divided into four sub-bands: 0.5Hz-10Hz, 10Hz-100Hz, 100Hz-1kHz, and 1kHz-7.5kHz.

[0090] The sampled signals in the four sub-frequency bands are acquired respectively and sent to the edge computing terminal for internal resistance analysis and calculation based on the communication interface.

[0091] The electrochemical processes and performance characteristics of batteries may differ significantly across different sub-frequency bands. This segmentation approach allows for targeted analysis of battery behavior within each band, leading to a better understanding of battery performance. Measurement results across different frequency bands can reflect state information at different levels of the battery. By comparing and analyzing data from each frequency band, battery problems can be quickly located, improving fault diagnosis efficiency.

[0092] Dividing the 0.5Hz-7.5kHz frequency band into four sub-bands can improve measurement accuracy, quickly diagnose battery status, optimize battery management strategies, and better meet the needs of different application scenarios.

[0093] This invention utilizes a 48V DC power supply from an external power source to drive a dedicated DBN battery sampling chip. A battery monitoring edge computing terminal issues an internal resistance test command, which is transmitted to the DBN battery sampling chip via a daisy-chain communication unit. The DBN battery sampling chip generates positive and negative square wave signals to drive a battery excitation unit, the frequency of which is preset by the battery monitoring edge computing terminal. The battery excitation unit drives an excitation resistor to discharge the battery at the required frequency, with a maximum discharge current less than or equal to 150mA. A signal amplification circuit conditions the real-time battery voltage and provides it to the battery voltage sampling unit. The DBN battery sampling chip's ADC (digital-to-analog converter) then performs signal conversion. Based on the voltage divider law, and using the voltage Vm collected when the excitation resistor is connected to the battery and Vb collected when the battery is disconnected, the internal resistance Ri = (Rext*(Vb-Vm)) / Vm is obtained, where Rext is the resistance value of the externally applied excitation resistor. This invention, powered by a battery pack or external power source, does not affect the consistency of individual cells. Using a dedicated DBN chip, it fully considers the characteristics and monitoring requirements of the battery, has high performance, and can meet the needs of flexible, efficient, and low-cost battery internal resistance testing.

[0094] It should be noted that the computer-readable medium described in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0095] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0096] Computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0097] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0098] The units described in the embodiments of this disclosure can be implemented in software or hardware. The names of the units are not, in some cases, intended to limit the specific unit.

[0099] The preferred embodiments of the present invention have been described above to make the spirit of the present invention clearer and easier to understand, and are not intended to limit the present invention. All modifications, substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope summarized by the appended claims.

Claims

1. A method for measuring the internal resistance of a single-cell storage battery, characterized in that: The DBN battery sampling chip is driven by an external power supply with a 48V DC voltage. The battery monitoring edge computing terminal sends an internal resistance test command, which is transmitted to the DBN battery sampling chip through a daisy-chain communication unit. A daisy-chain topology is formed by cascading DBN battery sampling dedicated chips through serial communication interfaces. The battery monitoring edge computing terminal is connected to the first DBN battery sampling dedicated chip through a serial communication interface. The serial communication interfaces of each DBN battery sampling dedicated chip are connected to the previous and next DBN battery sampling dedicated chips respectively. The serial communication interface of the last DBN battery sampling dedicated chip is left floating or connected to a resistor. The DBN battery sampling chip integrates a high-speed PWM generator, which generates positive and negative square wave signals to drive the battery excitation unit according to the instructions issued by the battery monitoring edge computing terminal of the main device. The frequency of the square wave signal is preset by the battery monitoring edge computing terminal. The battery excitation unit drives the excitation resistor to discharge the battery at the required frequency, wherein the maximum discharge current is less than or equal to 150mA; The signal amplification circuit conditions the real-time voltage of the battery and provides it to the battery voltage sampling unit. The ADC digital-to-analog converter built into the DBN battery sampling chip performs signal conversion. Based on the voltage divider law, the internal resistance Ri is obtained by taking the voltage Vm when the excitation resistor is connected to the battery and the voltage Vb when the battery is disconnected. Here, Rext is the resistance value of the externally applied excitation resistor. The internal resistance test command includes an internal resistance test strategy, which includes: Define the test state space, including the frequency state space, amplitude state space, and duration state space; Establish a dynamic model of battery internal resistance and temperature: simulate the changes in battery internal resistance and temperature under different operating conditions, and integrate the internal resistance and temperature model into the test environment to generate actual internal resistance and temperature data during the test process. The optimal testing strategy is learned using the Q-Learning algorithm: Initialize Q(s, a) to 0, where s is the state and a is the behavior; at each time step, select the optimal behavior a in the current state s, and observe the environmental feedback reward r, the next state s', and the optimal behavior a'; update the Q value according to the Q-Learning update rule: Q(s, a) = Q(s, a) + α * (r + γ * max_a' Q(s', a') - Q(s, a)); Where r is the reward function after performing action a in the current state s; α is the learning rate, ranging from [0, 1], representing the degree of learning of new information; γ is a factor, ranging from [0, 1]; max_a' Q(s', a') represents the value corresponding to the optimal action a' selected in the next state s'; Repeated iterations converge to the optimal test strategy.

2. The method for measuring the internal resistance of a single-cell storage battery as described in claim 1, characterized in that, A machine learning-based model for calculating internal resistance is established, including: Determine the input characteristics of the model: external resistance Rext, battery voltage Vb, and battery internal voltage Vm; Collect historical internal resistance calculation data and train the model to learn the formula coefficients: establish a dataset containing internal resistance calculation samples, preprocess the dataset, and train a machine learning model to fit the internal resistance calculation formula based on the gradient descent optimization algorithm. The trained model is deployed to the battery monitoring edge computing terminal to collect the battery's Rext, Vb, and Vm data in real time, and input into the deployed model for internal resistance calculation.

3. The method for measuring the internal resistance of a single-cell storage battery as described in claim 2, characterized in that, A distributed computing architecture is adopted, configuring multiple battery monitoring edge computing terminals to collaboratively complete internal resistance analysis, including: The master-slave distributed architecture is adopted, and the internal resistance calculation task is divided into multiple sub-tasks, including data acquisition, feature calculation and model inference. The sub-tasks are dynamically allocated according to the computing resources of the battery monitoring edge computing terminal of each slave node, and the computing load of each node is balanced based on the load balancing algorithm. Establish a distributed data storage system to manage the computational data of each node, and configure the master node to obtain the latest internal resistance calculation results in a timely manner based on the real-time data synchronization mechanism.

4. The method for measuring the internal resistance of a single-cell storage battery as described in claim 1, characterized in that, The voltage sampling unit performs voltage sampling based on compressed sensing, including: Establish a state-space model for the battery voltage time-series signal: Analyze the battery voltage time-series signal to determine its time correlation and spectral characteristics, select a state-space model to describe the battery voltage signal, and determine the parameters of the state-space model, including the state transition matrix and the observation matrix; Design a compressed sensing sampling matrix to reduce the ADC sampling rate: Based on the sparsity of the battery voltage signal, a random sampling matrix Φ is selected, the coherence of the sampling matrix is ​​calculated, and the ADC sampling rate is compressed by adjusting the dimension of the sampling matrix. The original voltage signal is reconstructed using the orthogonal matching pursuit (OMP) algorithm: the voltage data y = Φx obtained by compressed sensing is used to reconstruct the original voltage signal x based on y and Φ using the OMP algorithm. Estimating the actual battery voltage based on Kalman filtering: Using a state-space model, the actual battery voltage is estimated based on a Kalman filter. The compressed sensing sampling matrix Φ and the OMP reconstruction algorithm are deployed on the voltage sampling unit for voltage sampling.

5. The method for measuring the internal resistance of a single-cell storage battery as described in claim 4, characterized in that: Perform Fourier transform or discrete wavelet transform on the sampled battery voltage signal to obtain the voltage signal in the frequency domain or time-frequency domain; Extract time-frequency domain features, calculate power spectral density (PSD) based on the transformed voltage signal, and analyze the energy distribution characteristics of the signal in different frequency bands; Principal component analysis (PCA) is used to reduce dimensionality and remove redundant information, which is then used as the optimized feature set. The RFE recursive feature selection algorithm is used to optimize the feature set, iteratively eliminating irrelevant features to obtain the optimal feature subset; The optimized feature set is used as input to the internal resistance calculation model.

6. The method for measuring the internal resistance of a single-cell storage battery as described in claim 1, characterized in that: The DBN battery sampling chip integrates a 0.5Hz-7.5kHz frequency adjustment unit, a positive and negative square wave generator, a multi-channel voltage sampling circuit, and a daisy-chain communication unit.

7. The method for measuring the internal resistance of a single-cell storage battery as described in claim 6, characterized in that: The 0.5Hz-7.5kHz frequency band is divided into 4 sub-bands: 0.5Hz-10Hz, 10Hz-100Hz, 100Hz-1kHz, and 1kHz-7.5kHz. The sampled signals in the four sub-frequency bands are acquired respectively and sent to the edge computing terminal for internal resistance analysis and calculation based on the communication interface.

8. An apparatus for measuring the internal resistance of a single-cell storage battery, comprising: At least one processor; as well as At least one memory including computer program code, The at least one memory and the computer program code are configured, together with the at least one processor, to cause the device to perform the method according to any one of claims 1-7.

9. A computer-readable storage medium having a computer program stored thereon, the computer program, when executed by a processor, implementing the method of any one of claims 1-7.

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