An active temperature control method and system for a chip aging tester

Abstract

This invention relates to the field of chip test engineering control technology, and particularly to an active temperature control method and system for a chip aging tester. The method includes: analyzing the test process based on test task parameters and evaluating the expected rate of change of thermal load on the test chip to dynamically generate a target junction temperature control curve; obtaining the theoretical furnace temperature through a junction temperature closed-loop control algorithm based on the target junction temperature control curve, the actual chip junction temperature, and the current actual furnace temperature, and calculating the furnace temperature compensation amount through a feedforward compensation algorithm in conjunction with test state parameters; obtaining the ideal furnace temperature based on the theoretical furnace temperature and the furnace temperature compensation amount; and obtaining the actual temperature control amount based on the basic temperature adjustment amount and the temperature control compensation amount. This invention can more accurately track the preset target junction temperature control curve and more effectively suppress transient and steady-state errors caused by test program switching and environmental fluctuations, achieving higher precision and faster response control of the chip junction temperature.

Description

Technical Field

[0001] This invention relates to the field of chip testing engineering control technology, and in particular to an active temperature control method and system for a chip aging tester. Background Technology

[0002] In existing high and low temperature aging test chambers, temperature control generally uses the furnace temperature as a feedback variable. This approach is based on an implicit assumption: there is a stable and predictable mapping relationship between the furnace temperature and the chip junction temperature.

[0003] However, in actual aging tests, differences in chip type, package form, test vector, and power supply conditions can lead to significant variations in chip junction temperature at the same furnace temperature. More importantly, when the test program switches from standby to high load, chip power consumption can increase dramatically within milliseconds. Due to the thermal resistance and capacitance between the chip package and the test board, the chip junction temperature exhibits a significant time delay and inertia in response to power consumption changes. If the test continues at the original furnace temperature setting, the chip junction temperature will rise lagging and may overshoot; conversely, as power consumption decreases, the chip junction temperature will slowly fall back, causing the chip junction temperature to deviate from the preset curve throughout the test. While existing technologies incorporate feedforward compensation, they do not consider the rate of change of power consumption and its coupling relationship with the chip's own thermal dynamic characteristics, making it difficult to cope with transient thermal disturbances. Summary of the Invention

[0004] The main objective of this invention is to provide an active temperature control method and system for a chip aging tester, aiming to solve the technical problems mentioned in the background section.

[0005] This invention proposes an active temperature control method for a chip aging tester, comprising:

[0006] Obtain the operating parameters and test task parameters of the chip aging tester;

[0007] The test process is analyzed based on the test task parameters, and the expected thermal load change rate of the test chip is evaluated to dynamically generate the target junction temperature control curve of the chip.

[0008] The actual junction temperature of the chip and the current actual furnace temperature are obtained based on the operating parameters. Based on the target junction temperature control curve of the chip, the actual chip junction temperature and the current actual furnace temperature, the theoretical furnace temperature is obtained through the junction temperature closed-loop control algorithm. The furnace temperature compensation amount is calculated through the feedforward compensation algorithm in combination with the test state parameters. The ideal furnace temperature is obtained based on the theoretical furnace temperature and the furnace temperature compensation amount.

[0009] Obtain environmental parameters, obtain a basic temperature adjustment amount based on the ideal furnace temperature and the current actual furnace temperature, and obtain a temperature control compensation amount through a feedforward compensation algorithm in combination with the environmental parameters. Obtain the actual temperature control amount based on the basic temperature adjustment amount and the temperature control compensation amount.

[0010] The actual temperature control value is converted into a control signal for the actuator to control the energy output value of the heating and cooling systems.

[0011] The system monitors the operating parameters of the chip aging tester in real time and executes safety protection actions according to the graded alarm strategy.

[0012] Preferably, the steps of obtaining the test task parameters of the chip aging tester, analyzing the test process based on the test task parameters, and evaluating the expected thermal load change rate of the test chip to dynamically generate the target junction temperature control curve of the chip include:

[0013] Based on the test task parameters, obtain the preset temperature curve for chip aging test, chip type, chip manufacturing batch, and test items;

[0014] Based on the preset temperature curve of chip aging test, chip type, chip manufacturing batch, and test items, the test process is analyzed to obtain the expected power consumption of the chip at each test moment.

[0015] Obtain the type and number of chips to be tested, obtain the thermal load assessment value based on the chip type, number of chips and expected power consumption of the chips, and calculate the expected thermal load change rate based on the thermal load assessment value within a preset time window;

[0016] The cumulative test duration is obtained, and the preset temperature curve is dynamically corrected based on the expected thermal load change rate and the cumulative test duration to obtain the target junction temperature control curve of the chip.

[0017] When the absolute value of the expected rate of change of thermal load is detected to be greater than the preset change threshold, the target junction temperature control curve of the chip is dynamically updated.

[0018] Preferably, the steps of obtaining the actual junction temperature of the chip and the current actual furnace temperature based on the operating parameters, obtaining the theoretical furnace temperature based on the target junction temperature control curve of the chip, the actual chip junction temperature, and the current actual furnace temperature through a junction temperature closed-loop control algorithm, and calculating the furnace temperature compensation amount through a feedforward compensation algorithm in combination with the test state parameters, and obtaining the ideal furnace temperature based on the theoretical furnace temperature and the furnace temperature compensation amount include:

[0019] The target junction temperature of the chip is obtained according to the target junction temperature control curve of the chip, and the actual chip junction temperature and the current actual furnace temperature are obtained according to the real-time operating parameters.

[0020] Calculate the deviation between the actual chip junction temperature and the target chip junction temperature, and obtain a first dynamic thermal time constant. Based on the first dynamic thermal time constant and the deviation, obtain a second dynamic thermal time constant.

[0021] The theoretical furnace temperature is calculated by inverse solving the model prediction algorithm based on the first-order inertial element, according to the deviation value, the second dynamic thermal time constant, and the current actual furnace temperature.

[0022] Obtain the actual power consumption of the chip and calculate the rate of change of the actual power consumption of the chip based on the actual power consumption of the chip within a preset time window;

[0023] The test program switching timing is obtained based on the test status parameters. The furnace temperature compensation amount is calculated using a feedforward compensation algorithm based on the current actual furnace temperature, the actual power consumption change rate of the chip, and the test program switching timing.

[0024] The ideal furnace temperature is obtained by superimposing the theoretical furnace temperature with the furnace temperature compensation amount.

[0025] Preferably, the steps of obtaining environmental parameters, obtaining a basic temperature adjustment amount based on the ideal furnace temperature and the current actual furnace temperature, obtaining a temperature control compensation amount through a feedforward compensation algorithm in conjunction with the environmental parameters, and obtaining the actual temperature control amount based on the basic temperature adjustment amount and the temperature control compensation amount include:

[0026] Calculate the deviation between the current actual furnace temperature and the ideal furnace temperature;

[0027] The basic temperature adjustment amount is obtained based on the deviation value using a segmented PID control algorithm.

[0028] Collect environmental parameters and compare them with the corresponding rated reference data to obtain several deviation parameters. The environmental parameters include ambient temperature, cooling water temperature, power supply voltage, operating status of heating system and cooling system, and wind speed and wind pressure in the circulating air duct.

[0029] The feedforward compensation algorithm is used to fuse and calculate the several deviation parameters, and output the temperature control compensation amount.

[0030] The base temperature adjustment amount is superimposed with the feedforward temperature compensation amount to obtain the unlimited control amount;

[0031] The unlimited control quantity is limited to obtain the actual temperature control quantity.

[0032] Preferably, the step of converting the actual temperature control quantity into a control signal for the actuator to control the energy output value of the heating system and the cooling system is as follows:

[0033] The actual temperature control value is converted into the control signal required by the actuator;

[0034] A corresponding drive signal is generated based on the type of control signal, wherein the drive signal includes control signals for the heating system and control signals for the refrigeration system;

[0035] The energy output values ​​of the heating and cooling systems are coordinated based on the sign and magnitude of the actual temperature control quantity.

[0036] Preferably, the steps of real-time monitoring of the chip aging tester's operating parameters and executing safety protection actions according to the graded alarm strategy include:

[0037] The real-time monitoring parameters of the chip aging tester are obtained, including the actual chip junction temperature, ideal furnace temperature, current actual furnace temperature, actual temperature control value, and actual chip power consumption.

[0038] Based on the target junction temperature control curve of the chip and the actual power consumption of the chip, the junction temperature protection threshold and the furnace temperature protection threshold are dynamically generated.

[0039] Determine whether the real-time monitoring parameter exceeds the corresponding junction temperature protection threshold or furnace temperature protection threshold;

[0040] If the threshold is exceeded, a tiered alarm strategy will be adopted to perform corresponding processing actions. The tiered alarm strategy includes a level 1 alarm: automatically filtering out abnormal data and maintaining the previous normal state data to continue running; a level 2 alarm: recording the state data and providing prompt information; and a level 3 alarm: automatically terminating the test.

[0041] The present invention also provides an active temperature control system for a chip aging tester, comprising multiple modules, which are used to implement the steps of an active temperature control method for a chip aging tester.

[0042] Preferably, the module includes multiple units, which are used to implement the steps of an active temperature control method for a chip aging tester.

[0043] The present invention also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of an active temperature control method for a chip aging tester.

[0044] The present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of an active temperature control method for a chip aging tester.

[0045] The beneficial effects of this invention are as follows: This invention dynamically corrects the target junction temperature based on prior knowledge of the test task, predicts and reverse-solves the theoretical furnace temperature based on the physical model, and performs real-time feedforward compensation by fusing multi-source disturbance information at the bottom layer. This enables more accurate tracking of the preset chip target junction temperature control curve and more effective suppression of transient and steady-state errors caused by test program switching and environmental fluctuations, thereby achieving higher precision and faster response control of the chip junction temperature. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of a method flow according to an embodiment of this application.

[0047] Figure 2 This is a schematic diagram of the system structure according to an embodiment of this application.

[0048] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0049] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0050] like Figure 1 As shown, this application provides an active temperature control method for a chip aging tester, comprising:

[0051] S1, obtain the operating parameters and test task parameters of the chip aging tester;

[0052] S2, Analyze the test process according to the test task parameters and evaluate the expected thermal load change rate of the test chip to dynamically generate the target junction temperature control curve of the chip;

[0053] S3. Obtain the actual junction temperature of the chip and the current actual furnace temperature according to the operating parameters. Based on the target junction temperature control curve of the chip, the actual junction temperature of the chip and the current actual furnace temperature, obtain the theoretical furnace temperature through the junction temperature closed-loop control algorithm. Combine the test state parameters and calculate the furnace temperature compensation amount through the feedforward compensation algorithm. Obtain the ideal furnace temperature according to the theoretical furnace temperature and the furnace temperature compensation amount.

[0054] S4, obtain environmental parameters, obtain the basic temperature adjustment amount based on the ideal furnace temperature and the current actual furnace temperature, and obtain the temperature control compensation amount through the feedforward compensation algorithm in combination with the environmental parameters, and obtain the actual temperature control amount based on the basic temperature adjustment amount and the temperature control compensation amount.

[0055] S5, convert the actual temperature control quantity into a control signal for the actuator to control the energy output value of the heating system and the cooling system;

[0056] S6 monitors the operating parameters of the chip aging tester in real time and executes safety protection actions according to the graded alarm strategy.

[0057] As described in steps S1-S6 above, due to differences in chip type, packaging, test vector, and power supply conditions during actual aging tests, the junction temperature may vary significantly under the same furnace temperature. When the test program switches from standby to high load, the chip power consumption can increase dramatically within milliseconds (e.g., from 1W to 10W). Due to the thermal resistance and thermal capacitance between the chip package and the test board, the junction temperature response to power consumption changes has a significant time delay and inertia. If the test continues to run at the original furnace temperature setting, the junction temperature will rise lagging and may overshoot. Conversely, when the power consumption decreases, the junction temperature will slowly fall back, causing the junction temperature to deviate from the preset curve throughout the test. In existing high and low temperature aging test chambers, temperature control generally uses the furnace temperature as a feedback variable. This is based on the assumption that there is a stable and predictable mapping relationship between the furnace temperature and the chip junction temperature. Although feedforward compensation is introduced (e.g., adjusting the furnace temperature according to steady-state power consumption), the rate of change of power consumption and its coupling relationship with the chip's own thermal dynamic characteristics are not considered, making it difficult to cope with transient thermal disturbances. Therefore, this invention can more accurately track the preset target junction temperature control curve of the chip by dynamically correcting the target junction temperature based on the prior knowledge of the test task, predicting and solving the theoretical furnace temperature based on the physical model, and performing real-time feedforward compensation by fusing multi-source disturbance information at the bottom layer. It can also more effectively suppress transient and steady-state errors caused by test program switching and environmental fluctuations, and achieve higher precision and faster response control of the chip junction temperature.

[0058] Specifically, the operating parameters and test task parameters of the chip aging tester are obtained. The operating parameters include the actual junction temperature of the chip, the current actual furnace temperature, and the actual power consumption of the chip. These parameters are obtained based on the temperature sensor, furnace temperature probe, and power measurement unit (PMU) built into the tester. The furnace temperature is obtained by collecting raw data from multiple PT100 platinum resistance sensors near the test rack and calculating the current actual furnace temperature through temperature field weighting. The test task parameters include the preset temperature curve for chip aging test, chip type, chip manufacturing batch, and test items.

[0059] Because the thermal characteristics of a chip drift with time and temperature during aging, and the power consumption patterns vary significantly across different testing stages, a fixed preset temperature curve is insufficient for precise junction temperature control. Therefore, this invention analyzes the test process based on the test task parameters and evaluates the expected rate of change of thermal load on the test chip to dynamically generate a target junction temperature control curve. This curve adapts to the chip aging process and solves the long-term tracking error problem caused by thermal characteristic drift. Since directly controlling the furnace temperature cannot guarantee precise junction temperature tracking, this invention obtains the actual junction temperature of the chip and the current actual furnace temperature based on the operating parameters. Based on the target junction temperature control curve, the actual chip junction temperature, and the current actual furnace temperature, a closed-loop junction temperature control algorithm is used to obtain the theoretical furnace temperature. Combined with test state parameters, a feedforward compensation algorithm is used to calculate the furnace temperature compensation amount. The ideal furnace temperature is obtained based on the theoretical furnace temperature and the furnace temperature compensation amount. This allows for a more accurate response to upcoming thermal disturbances, effectively suppressing overshoot and hysteresis in the actual chip junction temperature. In addition, environmental parameters are acquired, a basic temperature adjustment amount is obtained based on the ideal furnace temperature and the current actual furnace temperature, and a temperature control compensation amount is obtained through a feedforward compensation algorithm in combination with the environmental parameters. Based on the basic temperature adjustment amount and the temperature control compensation amount, an actual temperature control amount that can resist environmental disturbances is obtained, which can improve the robustness of temperature control.

[0060] To ensure the execution and safety of the entire control scheme, the actual temperature control quantity is converted into control signals for the actuators, controlling the energy output values ​​of the heating and cooling systems, thus physically realizing the control commands. Real-time monitoring of the chip aging tester's operating parameters and execution of safety protection actions based on a tiered alarm strategy ensures test safety while minimizing accidental shutdowns due to occasional interference, thereby improving test continuity and efficiency.

[0061] In one embodiment, the steps of obtaining the test task parameters of the chip aging tester, parsing the test process based on the test task parameters, and evaluating the expected thermal load change rate of the test chip to dynamically generate the target junction temperature control curve of the chip include:

[0062] S21, obtain the chip aging test preset temperature curve, chip type, chip manufacturing batch and test items according to the test task parameters;

[0063] S22: Based on the preset temperature curve of chip aging test, chip type, chip manufacturing batch, and test items, analyze the test process to obtain the expected power consumption of the chip at each test moment.

[0064] S23, obtain the type and number of chips to be tested, obtain the thermal load assessment value based on the chip type, number of chips and expected power consumption of the chips, and calculate the expected thermal load change rate based on the thermal load assessment value within a preset time window;

[0065] The formula for calculating the heat load assessment value is:

[0066]

[0067] In the formula, This represents the heat load assessment value. Indicates the number of chips. express The expected power consumption of the chip at any given time. Indicates and (Actual chip junction temperature) Related chip leakage power consumption (different chip types have different chip leakage power consumption).

[0068] The formula for calculating the expected rate of change of heat load is:

[0069]

[0070] In the formula, Indicates the expected rate of change of heat load. express The heat load assessment value at any given time. express The heat load assessment value at any given time. Indicates the preset time window;

[0071] S24, obtain the cumulative test duration, and dynamically correct the preset temperature curve based on the expected thermal load change rate and the cumulative test duration to obtain the target junction temperature control curve for the chip. The correction formula is:

[0072]

[0073] In the formula, express The target junction temperature after real-time correction. express Preset temperature curve values ​​at all times. This represents the first dynamic thermal time constant that changes with the cumulative duration of the test. This represents the dynamic compensation coefficient that changes with the cumulative test duration. The parameters in this formula are normalized before calculation.

[0074]

[0075] In the formula, This represents the first dynamic thermal time constant that changes with the cumulative duration of the test. This represents the initial dynamic thermal time constant (obtained from a pre-stored thermal characteristic database based on the chip type). This represents the first thermal characteristic drift coefficient (obtained from a pre-stored aging model database based on the chip type and test temperature range). Indicates the start time of the current test. This indicates the preset total test duration. Indicates the current time;

[0076]

[0077] In the formula, This represents the dynamic compensation coefficient that changes with the cumulative test duration. This represents the initial dynamic compensation coefficient (obtained from the pre-stored thermal characteristics database based on the chip type). The second thermal characteristic drift coefficient is (obtained from a pre-stored aging model database based on the chip type and test temperature range).

[0078] S25, when the absolute value of the expected thermal load change rate is detected to be greater than the preset change threshold, the target junction temperature control curve of the chip is dynamically updated.

[0079] As described in steps S21-S25 above, in chip aging tests, the chip junction temperature is a core indicator determining test accuracy and chip safety. The junction temperature is directly affected by the chip's thermal load, which is closely related to the chip's power consumption during the test process. Differences in test vectors and power supply conditions at different test stages can lead to changes in the chip's expected power consumption. Furthermore, differences in chip type and manufacturing batch can result in variations in leakage power consumption. The number of chips directly determines the total thermal load. In addition, increased test duration can cause chip thermal characteristic drift, further affecting junction temperature stability. Therefore, this invention analyzes test task parameters to dynamically evaluate the expected thermal load change trend of the chip during the test process. Combined with a chip aging model, it performs real-time and adaptive correction of the preset temperature curve, generating a target junction temperature control curve that can actively compensate for thermal characteristic drift and transient thermal disturbances, thereby improving the accuracy of active temperature control.

[0080] Specifically, the test task parameters are obtained by communicating with the host computer server of the test machine through the communication port. The host computer server stores the configuration information of all test tasks. Among them, the preset temperature curve of chip aging test is preset by the test engineer according to the test standard or chip specification, such as the -40 degrees Celsius to 125 degrees Celsius cycle curve. The test items include high and low temperature cycle aging and high temperature long-term aging, which determines the switching logic of the test program. The test process, based on the preset temperature curve for chip aging tests, chip type, chip manufacturing batch, and test items, is as follows: Combining the temperature nodes of the preset temperature curve for chip aging tests (such as low-temperature holding, heating, high-temperature holding, and cooling stages) with the requirements of the test items (such as the high-temperature holding stage requiring 8 hours), the test stages are divided, and the test procedures for each stage are defined. Then, based on the chip type and test procedures, the expected power consumption of the chip at each test moment is queried from a pre-stored test procedure-power consumption mapping database. This database is constructed as follows: For different chip types, power consumption data for different test procedures is measured using a power analyzer in a laboratory environment. Simultaneously, the measured data is adjusted using correction factors for the chip manufacturing batch, ultimately forming a correlation mapping table of "chip type-manufacturing batch-test procedure-power consumption".

[0081] Because different test items correspond to different test vectors, and the chip's working modules (such as CPU cores and peripheral interfaces) and operating frequencies differ, power consumption exhibits phased changes. For example, during the chip functional testing phase, the test vectors primarily involve low-speed I / O interactions, and the expected power consumption may remain stable at 2W; however, during the performance stress testing phase, the test vectors switch to high-frequency data operations, and the expected power consumption jumps to 8W. This step uses a pre-stored test program-power consumption mapping database to associate the parsed test process with historically verified power consumption data, directly querying the expected power consumption P_expected(t) at each moment without real-time calculation. This ensures the accuracy of power consumption data while reducing the computational power requirements for real-time control.

[0082] In the formula for calculating the thermal load assessment, chip leakage power is strongly correlated with the actual chip junction temperature. It needs to be looked up from a pre-stored leakage power model based on the chip type. For example, a CMOS chip might have a leakage power of 0.5W at an actual junction temperature of 85℃, but this increases to 1.2W when the junction temperature rises to 125℃. Introducing chip leakage power makes the thermal load assessment more closely reflect the actual heat generation patterns of the chip. The expected rate of change of thermal load quantifies the speed of change; a larger value indicates more drastic fluctuations in the junction temperature, requiring more timely adjustments to the target curve.

[0083] During long-term aging tests, the thermal characteristics of the chip will slowly drift over time (e.g., the thermal resistance increases due to the aging of the thermal grease on the test board). At the same time, the expected rate of change of thermal load directly determines the fluctuation trend of the actual chip junction temperature. Therefore, the correction formula introduces the first dynamic thermal time constant and the dynamic compensation coefficient. The initial dynamic thermal time constant of the first dynamic thermal time constant is obtained from the pre-stored thermal characteristic database based on the chip type (e.g., the initial dynamic thermal time constant of a certain BGA packaged chip is 8s). The first thermal characteristic drift coefficient is obtained from the pre-stored aging model database based on the chip type and test temperature range (e.g., the first thermal characteristic drift coefficient α=0.02 in the test range of -40℃ to 150℃). The first dynamic thermal time constant is dynamically adjusted by the ratio of the cumulative test duration to the preset total test duration to adapt to the thermal characteristic drift in long-term testing. The initial dynamic compensation coefficient is also obtained from the pre-stored thermal characteristic database based on the chip type (e.g., the initial dynamic compensation coefficient k0=0.05). The second thermal characteristic drift coefficient β is obtained from the pre-stored aging model database based on the chip type and test temperature range (e.g., the second thermal characteristic drift coefficient is 0.01). Its adjustment with the cumulative test duration is to balance the stability and response speed of the control in long-term testing, so that the target junction temperature control curve of the chip can rise in advance when the thermal load steps, avoiding the actual chip junction temperature lag overshoot.

[0084] During testing, switching test programs (such as switching from standby to high-load programs) can cause the expected thermal load change rate to change drastically in a short period of time. If the target junction temperature curve is not updated in time, the actual junction temperature will deviate significantly from the target junction temperature. For example, if the target junction temperature is not adjusted in time when the thermal load increases suddenly, the actual junction temperature will rise with a lag, or even overshoot. In this solution, the preset change threshold is determined according to the chip type, packaging form and test safety requirements. Through experimental calibration, the junction temperature control effect is tested under various thermal load change scenarios for different chip types. The maximum change rate that keeps the junction temperature overshoot within the allowable range (such as ±2 degrees Celsius) is selected as the preset change threshold. The system monitors the expected thermal load change rate in real time. When its absolute value is detected to be greater than the preset change threshold, the dynamic update of the chip target junction temperature control curve is immediately triggered. The calculation process of S23-S24 is re-executed to obtain the chip's expected power consumption at the current moment, calculate the thermal load evaluation value and the expected thermal load change rate, update the first dynamic thermal time constant and the dynamic compensation coefficient, and correct and obtain a new chip target junction temperature control curve. This allows it to adapt to sudden increases in heat load, avoid lag and overshoot in the actual junction temperature, and enable the target junction temperature curve to respond quickly to drastic changes in heat load, maintaining junction temperature control accuracy.

[0085] In one embodiment, the steps of obtaining the actual junction temperature of the chip and the current actual furnace temperature based on the operating parameters, obtaining the theoretical furnace temperature based on the target junction temperature control curve of the chip, the actual chip junction temperature, and the current actual furnace temperature through a junction temperature closed-loop control algorithm, and calculating the furnace temperature compensation amount through a feedforward compensation algorithm in combination with the test state parameters, and obtaining the ideal furnace temperature based on the theoretical furnace temperature and the furnace temperature compensation amount include:

[0086] S31, obtain the target junction temperature of the chip according to the target junction temperature control curve of the chip, and obtain the actual chip junction temperature and the current actual furnace temperature according to the real-time operating parameters;

[0087] S32, calculate the deviation between the actual chip junction temperature and the target chip junction temperature, and obtain a first dynamic thermal time constant. Based on the first dynamic thermal time constant and the deviation, obtain a second dynamic thermal time constant. The calculation formula is as follows:

[0088]

[0089] In the formula, This represents the second dynamic thermal time constant. Represents the first dynamic thermal time constant. Indicates the deviation value. This represents the adaptive coefficient (set according to the chip type, with a value range of 0.01 to 0.1).

[0090] S33, the theoretical furnace temperature is calculated by inverse solving based on the deviation value, the second dynamic thermal time constant and the current actual furnace temperature using a model prediction algorithm based on a first-order inertial element;

[0091] The formula for the model prediction algorithm is:

[0092]

[0093] In the formula, Indicates the predicted future junction temperature, Indicates the prediction time step. This indicates the current actual furnace temperature. express The actual chip junction temperature at any given time. Indicates the second dynamic thermal time constant;

[0094] Inverse solution calculation formula:

[0095]

[0096] In the formula, This indicates the theoretical furnace temperature (referring to the temperature at which the actual chip junction temperature will be determined in the future). Precisely reaching the predicted future junction temperature (The theoretically achievable temperature of the furnace cavity).

[0097] S34, obtain the actual power consumption of the chip, and calculate the rate of change of the actual power consumption of the chip based on the actual power consumption of the chip within a preset time window;

[0098] S35, obtain the test program switching timing according to the test status parameters, and calculate the furnace temperature compensation amount through the feedforward compensation algorithm based on the current actual furnace temperature, the actual power consumption change rate of the chip and the test program switching timing.

[0099] S36, the ideal furnace temperature is obtained by superimposing the theoretical furnace temperature with the furnace temperature compensation amount.

[0100] As described in steps S31-S36 above, in chip aging tests, furnace temperature is the direct means of adjusting the chip junction temperature. However, there is a complex heat transfer process between the chip junction temperature and the furnace temperature. The thermal resistance and thermal capacity formed by the chip packaging, test board, and cavity environment will cause a delay of hundreds of milliseconds to several seconds in the response of the chip junction temperature to changes in furnace temperature. At the same time, the transient changes in chip power consumption caused by test program switching will further exacerbate the dynamic imbalance between junction temperature and furnace temperature. If the control strategy is adjusted only based on the current furnace temperature, the lag response of the junction temperature will lead to overshoot or undershoot. If the influence of test state parameters (such as test program switching timing and power consumption change rate) is ignored, static feedforward compensation cannot cope with transient thermal disturbances. Therefore, this invention obtains the actual chip junction temperature and the current actual furnace temperature in real time, quantifies the junction temperature deviation, and predicts thermal disturbances in combination with the test state to calculate an ideal furnace temperature that can eliminate the current junction temperature deviation and respond to transient changes in advance, ensuring that the chip junction temperature is stable within the target range and guaranteeing the accuracy of temperature control in chip aging tests.

[0101] Specifically, the target junction temperature of the chip is obtained by calling the target junction temperature control curve of the chip; the actual junction temperature of the chip is obtained by collecting the case temperature through temperature sensors located near the chip test board socket, combined with the temperature sensor data of the internal diode of the chip read through communication, and converted according to the pre-stored chip junction temperature algorithm (such as thermal resistance model); the current actual furnace temperature is obtained by collecting raw data through multiple temperature sensors distributed near the high and low temperature inner cavity test frame of the test machine, and calculating the weighted average value according to the temperature field distribution weight.

[0102] The calculation of the second dynamic thermal time constant integrates the chip's thermal dynamic characteristics and the deviation between the chip's actual junction temperature and the target junction temperature. The deviation reflects the degree of deviation of the current junction temperature control. The adaptive coefficient is obtained from the pre-stored thermal characteristic database according to the chip type (the value range is 0.01 to 0.1, such as 0.05 for automotive-grade chips). By incorporating the deviation value into the thermal time constant, the thermal dynamic model is made to better fit the current thermal response characteristics of the chip, thereby improving the accuracy of subsequent theoretical furnace temperature calculations.

[0103] The model prediction algorithm based on the first-order inertial element can accurately simulate the dynamic characteristics of the chip's thermal system. By inversely solving the formula, the theoretical furnace temperature that will enable the future junction temperature to accurately reach the target junction temperature of the chip can be obtained. In this scheme, the calculation of the theoretical furnace temperature takes into account the current junction temperature deviation and incorporates the delay characteristics of the chip's thermal response through the second dynamic thermal time constant, ensuring that the furnace temperature setting can gradually eliminate the junction temperature deviation and avoid overshoot.

[0104] The actual power consumption of the chip is calculated by communicating with the test motherboard through the communication port to obtain the real-time current and voltage parameters of the test chip. The actual power consumption data of the chip within the preset time window is retrieved from the system cache. The change rate of the actual power consumption of the chip is calculated by formula to quantify the intensity of the transient change in power consumption, which provides a quantitative basis for the calculation of the furnace temperature compensation amount and avoids the feedforward compensation lag caused by ignoring the change rate of power consumption.

[0105] The core of calculating furnace temperature compensation based on test state parameters is to proactively address transient thermal disturbances. The test program switching timing in the test state parameters is obtained through communication with the host computer server of the test machine (e.g., predicting a switch to a high-load test vector after 200ms). The feedforward compensation algorithm adopts a multi-input single-output linear weighted model. The weight coefficients are dynamically called from a preset lookup table of "actual chip power consumption change rate - furnace temperature compensation amount" according to the temperature range. This lookup table is calibrated through system identification experiments and combined with the test program switching look-ahead period (e.g., 200ms) to calculate the furnace temperature compensation amount. By calculating the furnace temperature compensation amount, the furnace temperature can be fine-tuned in advance before the power consumption step change, effectively suppressing junction temperature overshoot, especially in millisecond-level power consumption transient scenarios.

[0106] The ideal furnace temperature is generated by superimposing the theoretical furnace temperature with the furnace temperature compensation amount, which enables the synergy of steady-state control and transient compensation. This ideal furnace temperature includes both the steady-state control requirement to eliminate the current junction temperature deviation and the transient compensation to cope with future power consumption steps. This allows the furnace temperature setting to gradually correct the actual junction temperature of the chip to the target junction temperature, and to respond to transient thermal disturbances in advance, avoiding junction temperature lag overshoot. At the same time, to ensure control stability, the furnace temperature compensation amount is limited during the generation of the ideal furnace temperature (e.g., limited to ±2% of the theoretical furnace temperature) to avoid control oscillation due to excessive compensation.

[0107] In one embodiment, the steps of acquiring environmental parameters, obtaining a base temperature adjustment amount based on the ideal furnace temperature and the current actual furnace temperature, obtaining a temperature control compensation amount through a feedforward compensation algorithm in conjunction with the environmental parameters, and obtaining an actual temperature control amount based on the base temperature adjustment amount and the temperature control compensation amount include:

[0108] S41, Calculate the deviation between the current actual furnace temperature and the ideal furnace temperature;

[0109] S42, the basic temperature adjustment amount is obtained based on the deviation value through a segmented PID control algorithm;

[0110] S43, collect environmental parameters, compare the environmental parameters with the corresponding rated reference data to obtain several deviation parameters, the environmental parameters include ambient temperature, cooling water temperature, power supply voltage, operating status of heating system and cooling system, and wind speed and wind pressure in the circulating air duct;

[0111] S44, the several deviation parameters are fused and calculated using a feedforward compensation algorithm to output the temperature control compensation amount;

[0112] S45, the basic temperature adjustment amount is superimposed with the feedforward temperature compensation amount to obtain the unlimited control amount;

[0113] S46, the unlimited control quantity is limited to obtain the actual temperature control quantity.

[0114] As described in steps S41-S46 above, the furnace temperature is the direct external environment of the chip junction temperature. The stability of the furnace temperature directly determines the control accuracy of the junction temperature. However, the furnace temperature is easily affected by multiple external factors during the adjustment process. Changes in ambient temperature will alter the heat exchange efficiency between the cavity and the outside world, an increase in cooling water temperature will reduce the cooling capacity of the refrigeration system, and fluctuations in power supply voltage will affect the power output of the heating tube. These factors can all cause the furnace temperature to deviate from the ideal value. At the same time, the furnace temperature adjustment system has nonlinear characteristics, and the dynamic response speed varies within different deviation ranges (e.g., rapid heating is required for large deviations, while precise temperature maintenance is required for small deviations). Simple fixed parameter control cannot adapt to this characteristic. Therefore, this invention focuses on precise control of the ideal furnace temperature. First, the deviation benchmark of the furnace temperature adjustment is defined. Then, a piecewise PID control algorithm is used to obtain the basic adjustment amount. At the same time, environmental parameter feedforward compensation is introduced to offset the influence of external disturbances. Finally, the actual temperature control amount is obtained through superposition and amplitude limiting processing. This provides precise execution instructions for the coordinated operation of the heating and refrigeration systems, solving the problems of furnace temperature fluctuation and lag caused by external environmental disturbances and differences in system dynamic characteristics in actual testing, and ensuring that the furnace temperature stably follows the ideal furnace temperature.

[0115] The essence of furnace temperature regulation is to reduce the deviation between the actual furnace temperature and the ideal furnace temperature. Only by accurately calculating the deviation value can a clear adjustment direction and magnitude be provided for the subsequent control algorithm. If the deviation value is not calculated accurately, it will cause the control algorithm to output incorrect instructions, causing the furnace temperature to deviate from the ideal value, thus affecting the actual chip junction temperature control accuracy. In this step, the current actual furnace temperature is obtained by collecting data from multiple temperature sensors distributed near the high and low temperature cavity test frame of the test machine, and calculating a weighted average value according to the temperature field distribution weight. The temperature field distribution weight needs to be determined based on the thermal field simulation results or experimental calibration of the sensor installation location.

[0116] The basic temperature adjustment is obtained based on the deviation value using a piecewise PID control algorithm. Specifically, different PID parameter sets are automatically switched according to the absolute value of the deviation. For example, when the absolute value of the deviation is greater than 5°C, a set of parameters with high integral gain is activated to accelerate convergence under large deviations; when the absolute value of the deviation is less than 1°C, a set of parameters with low proportional gain and no integral is switched to avoid oscillations near the steady state. The above parameter sets are calibrated through step response experiments before the system leaves the factory.

[0117] Based on feedback control, environmental parameters are further collected to construct the input for feedforward compensation. These environmental parameters include ambient temperature, cooling water temperature, power supply voltage, operating status of the heating and cooling systems, and air velocity and pressure within the circulating air duct. Ambient temperature is acquired by a temperature and humidity sensor installed externally to the equipment; cooling water temperature is measured by a temperature sensor within the water circuit; power supply voltage is sampled by the power monitoring module; the operating status of the heating / cooling systems (such as compressor start / stop and heating element on / off) is fed back from the PLC's I / O status; and air velocity and pressure are monitored in real-time by an anemometer and pressure sensor installed within the circulating air duct. By comparing these environmental parameters with corresponding rated reference data (e.g., rated ambient temperature 25℃, rated cooling water temperature 20℃, rated power supply voltage 220V, etc., these reference values ​​are set and stored in the configuration file during equipment installation and commissioning), several deviation parameters are obtained.

[0118] The temperature control compensation step involves fusing several deviation parameters using a feedforward compensation algorithm. Specifically, a weighted summation formula is used for calculation, where the weighting coefficients are dynamically obtained from a pre-stored "temperature range-weighting coefficient" lookup table based on the current ideal furnace temperature range (e.g., -55℃~0℃, 0℃~125℃, 125℃~150℃). This lookup table is calibrated through system identification experiments under different combinations of environmental disturbances to ensure the physical rationality of the compensation amount. For example, when the cooling water temperature increases by 5℃, the impact on cooling efficiency in the high-temperature range (>125℃) is much greater than in the low-temperature range; therefore, its corresponding weight is set larger in the high-temperature range.

[0119] The base temperature regulation value and the temperature control compensation value are algebraically superimposed to obtain the unlimited control value. This achieves an organic integration of feedback and feedforward, enabling the controller to both correct existing deviations and preemptively offset the effects of measurable disturbances. The unlimited control value is then limited to obtain the actual temperature control value. The upper and lower limits of the limit are set based on the maximum power capacity of the heating and cooling systems to prevent control commands from exceeding the physical limits of the actuators and ensure system safety.

[0120] In one embodiment, the step of converting the actual temperature control quantity into a control signal for the actuator to control the energy output value of the heating system and the refrigeration system is as follows:

[0121] S51, convert the actual temperature control quantity into the control signal required by the actuator;

[0122] S52, Generate a corresponding drive signal according to the control signal type, wherein the drive signal includes the control signal of the heating system and the control signal of the refrigeration system;

[0123] S53, based on the sign and magnitude of the actual temperature control quantity, coordinate the energy output values ​​of the heating system and the cooling system.

[0124] As described in steps S51-S53 above, the present invention converts the actual temperature control quantity into a physical signal that can be recognized and executed by the actuator. At the same time, it establishes a collaborative control logic between the heating system and the cooling system to ensure that both output energy accurately according to the actual temperature control requirements. This enables stable adjustment of the test chamber temperature and provides a reliable physical execution guarantee for precise control of the chip junction temperature.

[0125] The actual temperature control quantity is converted into the control signal required by the actuator. The actual temperature control quantity is a value representing the required net heat power after amplitude limiting. Its value range is [-100%, +100%]. A positive value indicates that net heat needs to be input into the cavity, and a negative value indicates that net heat needs to be removed from the cavity. The conversion process is completed by table lookup or linear mapping. The normalized quantity is converted into an analog quantity (such as 0-10V) or a digital quantity (such as PWM duty cycle, Modbus register value) that conforms to the actuator interface protocol.

[0126] The corresponding drive signal is generated according to the control signal type. For heating systems, the drive signal is usually the firing angle control signal of the silicon controlled rectifier (SCR) or the PWM signal of the solid-state relay (SSR). For refrigeration systems, the drive signal can be the frequency setpoint of the compressor inverter, the opening command of the solenoid valve, or the target flow of the liquid nitrogen flow controller. The specific form of the drive signal is determined by the hardware interface of the actuator.

[0127] The energy output values ​​of the heating and cooling systems are coordinated based on the sign and magnitude of the actual temperature control quantity. Specifically: when the actual temperature control quantity is positive, only the heating system is activated, and its output power is proportional to the magnitude of the control quantity, while the cooling system remains off. When the actual temperature control quantity is negative, only the cooling system is activated, and its output power is proportional to the absolute value of the control quantity, while the heating system remains off. In the steady-state region where the control quantity is zero or at a very low value (e.g., ±1%), both systems maintain a low-power standby state. This design improves unidirectional activation and proportional output, avoiding energy offsetting phenomena caused by simultaneous heating and cooling operations, and improving energy utilization efficiency. Furthermore, since the control quantity itself has been smoothed and limited by the upper-level algorithm, the output of the actuator is continuous and stepless, thus ensuring the stability of furnace temperature changes.

[0128] In one embodiment, the step of real-time monitoring of the operating parameters of the chip aging tester and executing safety protection actions according to a graded alarm strategy includes:

[0129] S61. Obtain the real-time monitoring parameters of the chip aging tester, including the actual chip junction temperature, ideal furnace temperature, current actual furnace temperature, actual temperature control quantity, and actual chip power consumption.

[0130] S62. Dynamically generate junction temperature protection threshold and furnace temperature protection threshold based on the target junction temperature control curve of the chip and the actual power consumption of the chip;

[0131] Junction temperature protection threshold formula:

[0132]

[0133] In the formula, express Junction temperature protection threshold at any given time. for The target junction temperature at any given time, For the junction temperature basic protection tolerance, for The actual power consumption of the chip at any given time. The power consumption impact coefficient is related to chip packaging and heat dissipation conditions, where each parameter is calculated after normalization.

[0134] Furnace temperature protection threshold formula:

[0135]

[0136] In the formula, express The furnace temperature protection threshold at any given time. for Ideal furnace temperature at all times For the basic protection tolerance of furnace temperature, for Dynamic furnace temperature protection tolerance at any time ( ,in, and (These are calibration coefficients, where each parameter is calculated after normalization).

[0137] S63, determine whether the real-time monitoring parameter exceeds the corresponding junction temperature protection threshold or furnace temperature protection threshold;

[0138] If the threshold is exceeded, a tiered alarm strategy will be adopted to perform corresponding processing actions. The tiered alarm strategy includes a level 1 alarm: automatically filtering out abnormal data and maintaining the previous normal state data to continue running; a level 2 alarm: recording the state data and providing prompt information; and a level 3 alarm: automatically terminating the test.

[0139] As described in steps S61-S63 above, this invention monitors key operating parameters in real time and dynamically generates junction temperature protection thresholds and furnace temperature protection thresholds based on the chip target junction temperature control curve and the chip's actual power consumption. It constructs a graded alarm strategy that adaptively matches the current test status, thereby maximizing test continuity while ensuring test safety and avoiding accidental shutdowns caused by occasional interference or sensor noise.

[0140] Based on the target junction temperature control curve of the chip and the actual power consumption of the chip, the junction temperature protection threshold and the furnace temperature protection threshold are dynamically generated. The basic junction temperature protection tolerance is a fixed offset (e.g., +10°C) set according to the chip process reliability window. The power consumption impact coefficient related to chip packaging and heat dissipation conditions is determined during the system configuration phase based on the chip package type (e.g., FCBGA, QFN) and heat dissipation scheme (air cooling / liquid cooling) from the pre-stored "packaging-heat dissipation-" parameters. The coefficients were obtained from the database. This solution allows the junction temperature protection threshold and furnace temperature protection threshold to dynamically increase based on the target junction temperature and current power consumption; the higher the power consumption, the higher the allowable upper limit of the junction temperature. The basic furnace temperature protection tolerance is a preset value (e.g., +15℃); the dynamic furnace temperature protection tolerance formula is as follows: and Based on the thermal inertia of the cavity and the characteristics of the actuator, the design allows the furnace temperature protection threshold to be adaptively relaxed according to the control intensity, avoiding false triggering due to furnace temperature response lag during large adjustment phases.

[0141] The system compares real-time monitoring parameters with corresponding dynamic protection thresholds. If any parameter exceeds its threshold, a tiered alarm strategy is activated: Level 1 alarms handle brief, minor over-limits (e.g., duration <100ms). The system automatically filters out the abnormal data point and continues operation with the data from the previous normal state, suitable for scenarios such as sensor glitches; Level 2 alarms handle continuous but non-dangerous deviations (e.g., over-limits lasting 500ms but not reaching the hardware limit). The system records complete status data (including all monitoring parameters and timestamps) and provides operation prompts for engineers to evaluate; Level 3 alarms handle severe over-limits (e.g., junction temperature exceeding the threshold by 20°C or exceeding the limit for more than 1 second). The system immediately and automatically terminates the test, cuts off the power supply to the chip under test, and initiates a safety cooling program to prevent device burnout or equipment damage.

[0142] like Figure 2 As shown, the present invention also provides an active temperature control system for a chip aging test machine, comprising:

[0143] The parameter acquisition module is used to acquire the operating parameters and test task parameters of the chip aging tester.

[0144] The target generation module is used to parse the test process according to the test task parameters and evaluate the expected thermal load change rate of the test chip in order to dynamically generate the target junction temperature control curve of the chip.

[0145] The furnace temperature planning module is used to obtain the actual junction temperature of the chip and the current actual furnace temperature according to the operating parameters. Based on the target junction temperature control curve of the chip, the actual chip junction temperature and the current actual furnace temperature, the theoretical furnace temperature is obtained through the junction temperature closed-loop control algorithm. The furnace temperature compensation amount is calculated through the feedforward compensation algorithm in combination with the test state parameters. The ideal furnace temperature is obtained according to the theoretical furnace temperature and the furnace temperature compensation amount.

[0146] The disturbance compensation module is used to acquire environmental parameters, obtain a basic temperature adjustment amount based on the ideal furnace temperature and the current actual furnace temperature, and obtain a temperature control compensation amount through a feedforward compensation algorithm in combination with the environmental parameters. The actual temperature control amount is obtained based on the basic temperature adjustment amount and the temperature control compensation amount.

[0147] The execution control module is used to convert the actual temperature control quantity into a control signal for the actuator, and control the energy output value of the heating system and the refrigeration system.

[0148] The safety protection module is used to monitor the operating parameters of the chip aging tester in real time and execute safety protection actions according to the graded alarm strategy.

[0149] The target generation module includes:

[0150] Task parameter parsing is used to obtain the chip aging test preset temperature curve, chip type, chip manufacturing batch and test items based on the test task parameters;

[0151] Power consumption flow mapping is used to analyze the test flow based on the preset temperature curve of chip aging test, chip type, chip manufacturing batch, and test items, and obtain the expected power consumption of the chip at each test moment.

[0152] Thermal load assessment is used to obtain the type and number of chips to be tested, obtain thermal load assessment values ​​based on the chip type, number of chips and expected power consumption of the chips, and calculate the expected thermal load change rate based on the thermal load assessment values ​​within a preset time window.

[0153] The correction unit is used to obtain the cumulative test duration and dynamically correct the preset temperature curve according to the expected thermal load change rate and the cumulative test duration to obtain the target junction temperature control curve of the chip.

[0154] The target curve update is used to dynamically update the target junction temperature control curve of the chip when the absolute value of the expected rate of change of thermal load is detected to be greater than a preset change threshold.

[0155] The present invention also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of an active temperature control method for a chip aging tester.

[0156] The present invention also provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of an active temperature control method for a chip aging tester.

[0157] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, apparatus, article, or method. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, apparatus, article, or method that includes that element.

[0158] The above description is merely a preferred embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structural or procedural transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for active temperature control of a chip burn-in tester, comprising: The method comprises the following steps: acquiring the operating parameters and test task parameters of a chip aging test machine; analyzing the test process according to the test task parameters and evaluating the expected heat load change rate of the test chip to dynamically generate a chip target junction temperature control curve; acquiring the actual junction temperature of the chip and the current actual furnace temperature according to the operating parameters, obtaining a theoretical furnace temperature based on the chip target junction temperature control curve, the actual chip junction temperature and the current actual furnace temperature through a junction temperature closed-loop control algorithm, calculating a furnace temperature compensation amount through a feedforward compensation algorithm in combination with the test state parameters, and obtaining an ideal furnace temperature according to the theoretical furnace temperature and the furnace temperature compensation amount; acquiring environmental parameters, obtaining a basic temperature adjustment amount according to the ideal furnace temperature and the current actual furnace temperature, obtaining a temperature control compensation amount through a feedforward compensation algorithm in combination with the environmental parameters, and obtaining an actual temperature control amount according to the basic temperature adjustment amount and the temperature control compensation amount; converting the actual temperature control amount into a control signal of an actuator to control the energy output values of a heating system and a refrigeration system; monitoring the operating parameters of the chip aging test machine in real time and performing a safety protection action according to a hierarchical alarm strategy.

2. The method of claim 1, wherein the temperature of the plurality of temperature-controlled zones is controlled by a plurality of temperature-controlled zones. The step of acquiring the test task parameters of the chip aging test machine, analyzing the test process according to the test task parameters and evaluating the expected heat load change rate of the test chip to dynamically generate a chip target junction temperature control curve comprises the following steps: acquiring a chip aging test preset temperature curve, a chip type, a chip manufacturing batch and a test item according to the test task parameters; analyzing the test process according to the chip aging test preset temperature curve, the chip type, the chip manufacturing batch and the test item to obtain the chip expected power consumption corresponding to each test time; acquiring the chip type and the chip quantity to be tested, obtaining a heat load evaluation value according to the chip type, the chip quantity and the chip expected power consumption, and calculating the expected heat load change rate based on the heat load evaluation value within a preset time window; acquiring a test cumulative duration, dynamically modifying the preset temperature curve according to the expected heat load change rate and the test cumulative duration to obtain a chip target junction temperature control curve; when it is detected that the absolute value of the expected heat load change rate is greater than a preset change threshold, dynamically updating the chip target junction temperature control curve.

3. The method of claim 2, wherein the temperature of the plurality of temperature-controlled probes is actively controlled by a temperature controller. The step of acquiring the actual junction temperature of the chip and the current actual furnace temperature according to the operating parameters, obtaining a theoretical furnace temperature based on the chip target junction temperature control curve, the actual chip junction temperature and the current actual furnace temperature through a junction temperature closed-loop control algorithm, calculating a furnace temperature compensation amount through a feedforward compensation algorithm in combination with the test state parameters, and obtaining an ideal furnace temperature according to the theoretical furnace temperature and the furnace temperature compensation amount comprises the following steps: acquiring the chip target junction temperature according to the chip target junction temperature control curve, and acquiring the actual chip junction temperature and the current actual furnace temperature according to real-time operating parameters; calculating the deviation value of the actual chip junction temperature and the chip target junction temperature, and acquiring a first dynamic thermal time constant, obtaining a second dynamic thermal time constant according to the first dynamic thermal time constant and the deviation value; calculating a theoretical furnace temperature according to the deviation value, the second dynamic thermal time constant and the current actual furnace temperature by a first-order inertia element based model prediction algorithm; acquiring a chip actual power consumption, calculating a chip actual power consumption change rate based on the chip actual power consumption within a preset time window; calculating a furnace temperature compensation amount according to the current actual furnace temperature, the chip actual power consumption change rate and the test program switching timing by a feedforward compensation algorithm; superimposing the theoretical furnace temperature and the furnace temperature compensation amount to obtain an ideal furnace temperature.

4. The method of claim 3, wherein the temperature of the plurality of temperature-controlled probes is actively controlled by a temperature controller. The step of acquiring an environment parameter, acquiring a basic temperature adjustment amount according to the ideal furnace temperature and the current actual furnace temperature, and acquiring a temperature control compensation amount by a feedforward compensation algorithm in combination with the environment parameter, and acquiring an actual temperature control amount according to the basic temperature adjustment amount and the temperature control compensation amount comprises: calculating a deviation value of the current actual furnace temperature and the ideal furnace temperature; acquiring a basic temperature adjustment amount according to the deviation value by a piecewise PID control algorithm; acquiring an environment parameter, comparing the environment parameter with corresponding rated reference data to obtain a plurality of deviation parameters, wherein the environment parameter comprises an environment temperature, a cooling water temperature, a power supply voltage, a heating system and a refrigeration system operating state, and a wind speed and a wind pressure in a circulating air duct; fusing and calculating the plurality of deviation parameters by a feedforward compensation algorithm to output a temperature control compensation amount; superimposing the basic temperature adjustment amount and the feedforward temperature compensation amount to obtain an unclipped control amount; clipping the unclipped control amount to obtain an actual temperature control amount.

5. The active temperature control method for a chip aging tester according to claim 1, characterized in that, The step of converting the actual temperature control amount into a control signal of an actuator and controlling an energy output value of the heating system and the refrigeration system comprises: converting the actual temperature control amount into a control signal required by the actuator; generating a corresponding driving signal according to a control signal type, wherein the driving signal comprises a control signal of the heating system and a control signal of the refrigeration system; controlling the energy output value of the heating system and the refrigeration system based on the sign and size of the actual temperature control amount.

6. The method of claim 4, wherein the temperature of the plurality of temperature-controlled probes is actively controlled by a temperature controller. The step of real-time monitoring an operating parameter of the chip burn-in tester and executing a safety protection action according to a hierarchical alarm strategy comprises: acquiring a real-time monitoring parameter of the chip burn-in tester, wherein the real-time monitoring parameter comprises an actual chip junction temperature, an ideal furnace temperature, a current actual furnace temperature, an actual temperature control amount and a chip actual power consumption; dynamically generating a junction temperature protection threshold and a furnace temperature protection threshold based on the chip target junction temperature control curve and the chip actual power consumption; judging whether the real-time monitoring parameter exceeds a corresponding junction temperature protection threshold or furnace temperature protection threshold; if so, executing a corresponding processing action by a hierarchical alarm strategy, wherein the hierarchical alarm strategy comprises a first-level alarm: automatically filtering out abnormal data and maintaining the last normal state data to continue running, a second-level alarm: recording state data and giving a prompt information, and a third-level alarm: automatically terminating the test.

7. An active temperature control system for a chip burn-in tester, comprising: The chip burn-in tester comprises a plurality of modules, and the plurality of modules are used to implement the steps of the method according to any one of claims 1 to 6.

8. The active temperature control system of claim 7, wherein the temperature control system is configured to control the temperature of the plurality of dies to a temperature of about 125 °C. The module comprises a plurality of units for implementing the steps of the method of any one of claims 1 to 6. 9.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is configured to perform the method according to any one of claims 1-8 when the computer program is executed by the processor. The processor implements the steps of the method of any one of claims 1 to 6 when executing the computer program.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program, which when executed by a processor implements the steps of the method of any one of claims 1 to 6.

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