Test card and host

Abstract

The invention discloses a test card and a host, and relates to the technical field of test.According to the technical scheme, firstly, after a plurality of different test interfaces are arranged on the test card, when the host comprises a plurality of different slots, the slots can be tested through the different test interfaces of the test card; in this way, the problem that part of the slots cannot be tested can be avoided, and then the test coverage rate can be increased. Secondly, the test interface comprises an identification pin, and the controller can determine a target test interface connected with the host based on the voltage of the identification pin of each test interface. Thus, in the testing process, different testing interfaces can be sequentially connected with the host, and the testing flexibility is improved. And finally, the test card supports loopback test and card function test, and test mode selection can be carried out through a configuration end of the information loading circuit. Therefore, each slot of the host can be tested according to a plurality of different test modes, so that the test coverage rate is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of testing, in particular to a test card and a host. BACKGROUND

[0002] The host refers to any computer device capable of running programs or providing services, including but not limited to servers, tablets, laptops, etc. In order to ensure the stability and reliability of each PCIe (Peripheral Component Interconnect Express) slot on the host, the PCIe slot of the host is usually tested for functions, performance, etc. before the host is shipped.

[0003] At present, in some technologies, when testing the PCIe slot, a single interface form of PCIe standard card is usually used for testing. The test coverage of this test method is not high. SUMMARY

[0004] The present application provides a test card and a host to at least solve the problem of low test coverage in the related art.

[0005] The present application provides a test card, which comprises: a plurality of different test interfaces, the test interface comprising a communication pin and an identification pin, the voltage of the identification pin of the test interface being a first voltage when the test interface is connected to the host, and the voltage of the identification pin of the test interface being a second voltage when the test interface is disconnected from the host; an information loading circuit comprising a configuration end and a detection end, the detection end being connected to the identification pin, and the configuration end being configured to receive a configuration signal representing a test mode; a controller connected to the detection end, the configuration end and the communication pin of each test interface, configured to detect the voltage of the identification pin of each test interface through the detection end, and based on the detected voltage of the identification pin, determine a target test interface connected to the host, and when the configuration signal received by the configuration end represents a first test mode, perform loopback test with the host through the communication pin of the target test interface, and when the configuration signal received by the configuration end represents a second test mode, perform card function test with the host through the communication pin of the target test interface.

[0006] The present application also provides a host, wherein the test card described in any of the above is used to test the host.

[0007] In the technical solutions of some embodiments of the present application, first, after the test card is provided with a plurality of different test interfaces, when the host includes a plurality of different slots, each slot can be tested through the different test interfaces of the test card. In this way, the problem that some slots cannot be tested can be avoided, and thus the test coverage can be improved. Second, the test interface includes an identification pin, and when the test interface is connected to the host, the voltage of the identification pin of the test interface is a first voltage, and when the test interface is disconnected from the host, the voltage of the identification pin of the test interface is a second voltage. The controller can determine the target test interface connected to the host based on the voltage of the identification pin of each test interface. In this way, during the test process, different test interfaces can be sequentially connected to the host according to actual needs, and the test flexibility can be improved. Finally, the test card supports loopback testing and card function testing, and the configuration end of the information loading circuit can be used to select a test mode. In this way, each slot of the host can be tested according to a plurality of different test modes, and thus the test coverage can be further improved. BRIEF DESCRIPTION OF DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0009] Figure 1 A top view of the test card provided by some embodiments of the present application; Figure 2 A size schematic diagram of the test card provided by some embodiments of the present application; Figure 3 A schematic diagram of the docking relationship between the second test interface and the host slot corresponding to the first test interface provided by some embodiments of the present application; Figure 4 A size schematic diagram of the test card provided by some embodiments of the present application; Figure 5 A schematic diagram of the test card provided by some embodiments of the present application; Figure 6 A schematic diagram of the first positional relationship between the first fixing assembly and the baffle provided by some embodiments of the present application; Figure 7 A schematic diagram of the second positional relationship between the first fixing assembly and the baffle provided by some embodiments of the present application; Figure 8 A schematic diagram of the third positional relationship between the first fixing assembly and the baffle provided by some embodiments of the present application; Figure 9A fourth position relationship between the first fixed assembly and the baffle provided for some embodiments of the present application is shown schematically; Figure 10 A top view size of the first baffle corresponding to the first test interface provided for some embodiments of the present application is shown schematically; Figure 11 A side view size of the first baffle corresponding to the first test interface provided for some embodiments of the present application is shown schematically; Figure 12 A top view size of the second baffle corresponding to the first test interface provided for some embodiments of the present application is shown schematically; Figure 13 A side view size of the second baffle corresponding to the first test interface provided for some embodiments of the present application is shown schematically; Figure 14 A top view size of the first baffle corresponding to the second test interface provided for some embodiments of the present application is shown schematically; Figure 15 A side view size of the first baffle corresponding to the second test interface provided for some embodiments of the present application is shown schematically; Figure 16 A top view size of the second baffle corresponding to the second test interface provided for some embodiments of the present application is shown schematically; Figure 17 A side view size of the second baffle corresponding to the second test interface provided for some embodiments of the present application is shown schematically; Figure 18 An assembly schematic of the test card connected with the host computer provided for a first embodiment of the present application is shown schematically; Figure 19 An assembly schematic of the test card connected with the host computer provided for a second embodiment of the present application is shown schematically; Figure 20 An assembly schematic of the test card connected with the host computer provided for a third embodiment of the present application is shown schematically; Figure 21 An assembly schematic of the test card connected with the host computer provided for a fourth embodiment of the present application is shown schematically; Figure 22 An assembly schematic of the test card connected with the host computer provided for a fifth embodiment of the present application is shown schematically; Figure 23 A partial module schematic of the test card provided for some embodiments of the present application is shown schematically; Figure 24 A module schematic of the controller provided for some embodiments of the present application is shown schematically; Figure 25 A module schematic of the test interface provided for some embodiments of the present application is shown schematically; Figure 26 An interaction schematic of the controller and other components of the test card provided for some embodiments of the present application is shown schematically; Figure 27 A schematic diagram of a test card provided for some embodiments of the present application; Figure 28 A schematic diagram of a module of a host provided for some embodiments of the present application. DETAILED DESCRIPTION

[0010] The technical solutions in the embodiments of the present application will be apparently and completely described below with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without any creative work fall within the protection scope of the present application.

[0011] It should be noted that, in the description of the present application, the terms “comprise”, “contain” or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. The terms “first”, “second” and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0012] In order for those skilled in the art to better understand the technical solutions of the present application, the present application will be further described in detail below with the accompanying drawings and specific embodiments.

[0013] The PCIe standard card refers to a PCIe device used to implement a single function, such as a standalone network card, a GPU (Graphics Processing Unit), a PCIe solid state disk, etc. When some technologies use PCIe standard cards to test the PCIe slots of a host, the following problems exist: 1) Each PCIe standard card only supports a single PCIe version or a specified number of channels, and when a host includes multiple generations of PCIe slots, there is a problem of low test coverage. For example, when a host includes PCIe X8 and PCIe X16 slots, if a standard card supporting PCIe X8 is used for testing, the PCIe X16 slot cannot be covered. If a standard card supporting PCIe X16 is used for testing, the PCIe X18 slot cannot be covered. If a standard card supporting PCIe X8 and a standard card supporting PCIe X16 are used for testing respectively, multiple standard cards are needed, and the testing cost is high.

[0014] 2) In order to reduce the test cost, the PCIe slot supporting high speed is tested by using the standard card supporting low speed. For example, the standard card of PCIe 5.0 version supports high speed, and the standard card of PCIe 3.0 version only supports low speed, but due to the high cost of the standard card of PCIe 5.0 version, the standard card of PCIe 3.0 version is used to test the PCIe slot of PCIe 5.0 version. This test method cannot comprehensively test the PCIe slot of PCIe 5.0 version, thereby having the problem of low test coverage.

[0015] 3) During the test process, the PCIe standard card needs to be frequently plugged in and out between different PCIe slots, resulting in a high loss rate of the PCIe standard card, and the PCIe standard card needs to be frequently replaced, thereby increasing the test cost.

[0016] 4) It is not suitable for loopback test. The so-called loopback test refers to that the PCIe standard card needs to directly return the original data signal issued by the host, so as to verify the communication signal quality and protocol compliance of the PCIe slot and the PCIe link by the host. For example, in the loopback test, after the host issues the original data signal A to the PCIe standard card, the PCIe standard card needs to return the original data signal A to the host, and the host compares the data signal issued and the data signal returned by the PCIe standard card. If the signals are small, it proves that the communication signal quality of the PCIe slot and the PCIe link is good, and if the signals are large, it proves that the communication signal quality of the PCIe slot and the PCIe link is poor. At present, the firmware and circuit design of the PCIe standard card are mainly used for actual business, and there is no firmware and circuit design related to loopback test. Therefore, when the PCIe standard card is used to test the PCIe slot, the loopback test cannot be performed, thereby causing the problem of low test coverage.

[0017] In view of this, the application provides a test card which can solve the above problems. In combination with Figure 1 The top view of the test card 100 provided by some embodiments of the application is shown. Figure 1In the embodiment, the test card 100 comprises a plurality of different test interfaces 11, an information loading circuit 12 and a controller 13. The test interface 11 comprises a communication pin 111 and an identification pin 112. When the test interface 11 is connected with the host, the voltage of the identification pin 112 of the test interface 11 is a first voltage. When the test interface 11 is disconnected with the host, the voltage of the identification pin 112 of the test interface 11 is a second voltage. The information loading circuit 12 comprises a configuration end 122 and a detection end 121. The detection end 121 is connected with the identification pin 112. The configuration end 122 is configured to receive a configuration signal representing a test mode. The controller 13 is connected with the detection end 121, the configuration end 122 and the communication pin 111 of each test interface 11. The controller 13 is configured to detect the voltage of the identification pin 112 of each test interface 11 through the detection end 121, determine a target test interface 11 connected with the host based on the detected voltage of the identification pin 112, and perform a loopback test with the host through the communication pin 111 of the target test interface 11 when the configuration signal received by the configuration end 122 represents a first test mode, and perform a card function test with the host through the communication pin 111 of the target test interface 11 when the configuration signal received by the configuration end 122 represents a second test mode.

[0018] Specifically, in the embodiment, the plurality of test interfaces 11 comprise a PCIe X4 interface, a PCIe X8 interface and a PCIe X16 interface. For example, Figure 1 In the embodiment, the test interface 11 marked as A can be a PCIe X8 interface, the test interface 11 marked as B can be a PCIe X4 interface, and the test interface 11 marked as C can be a PCIe X16 interface. Different test interfaces 11 can support different protocols, or the plurality of test interfaces 11 all support the same protocol, but different test interfaces 11 support different protocol versions.

[0019] In the embodiment, the information loading circuit 12 can comprise a power supply end. Each test interface 11 can be connected with the power supply end of the information loading circuit 12. A pull-up resistor is arranged between the power supply end and the test interface 11. When the test interface 11 is connected with the host, the identification pin 112 of the test interface 11 can be connected with a ground end of the host, so that the voltage of the identification pin 112 is a first voltage, i.e. a ground voltage. When the test interface 11 is disconnected with the host, due to the existence of the pull-up resistor, the voltage of the identification pin 112 can be a second voltage, i.e. a power supply voltage. The controller 13 can detect the voltage of the identification pin of each test interface 11 through the detection end 121. For any test interface 11, if the voltage of the identification pin of the test interface 11 is the ground voltage, it indicates that the test interface 11 is connected with the host. If the voltage of the identification pin of the test interface 11 is the power supply voltage, it indicates that the test interface 11 is disconnected with the host.

[0020] In some embodiments, the information loading circuit 12 can also include a ground terminal. Each test interface 11 can be connected to the ground terminal of the information loading circuit 12. In the case that the test interface 11 is connected to the host, the identification pin 112 of the test interface 11 can be connected to the power terminal of the host, so that the voltage of the identification pin 112 is the first voltage, i.e., the power voltage. In the case that the test interface 11 is disconnected from the host, the identification pin 112 is grounded, and the voltage of the identification pin 112 can be the second voltage, i.e., the ground voltage. The controller 13 can detect the voltage of the identification pin of each test interface 11 through the detection terminal 121. For any test interface 11, if the voltage of the identification pin of the test interface 11 is the power voltage, it indicates that the test interface 11 is connected to the host, and if the voltage of the identification pin of the test interface 11 is the ground voltage, it indicates that the test interface 11 is disconnected from the host.

[0021] After determining the target test interface 11 connected to the host, the controller 13 can determine the test mode based on the configuration signal received by the configuration terminal 122, and communicate with the host through the communication pin 111 of the target test interface 11.

[0022] Specifically, in the firmware and circuit design of the test card 100, the following two aspects of firmware and circuit design can be included: 1) firmware and circuit design related to loopback test; and 2) firmware and circuit design related to the service function of the test card 100.

[0023] The configuration terminal 122 of the information loading circuit 12 can be connected to a host computer or the like, and the test personnel can select the test mode based on the host computer or the like. For example, if the test personnel needs to perform loopback test, the test personnel can issue a first configuration signal (such as high level) to the configuration terminal 122 through the host computer or the like. When the configuration signal received by the configuration terminal 122 is the first configuration signal, the controller 13 can communicate with the host through the firmware and circuit design related to the loopback test to complete the loopback test. Conversely, if the test personnel needs to complete the related test of the PCIe slot of the host through the function test of the test card 100, the test personnel can issue a second configuration signal (such as low level) to the configuration terminal 122 through the host computer or the like. When the configuration signal received by the configuration terminal 122 is the second configuration signal, the controller 13 can communicate with the host through the firmware and circuit design related to the service function of the test card 100 to complete the function test of the test card 100.

[0024] In conclusion, in the technical solutions of some embodiments of the present application, first, after multiple different test interfaces 11 are arranged on the test card 100, when the host includes multiple different slots, each slot can be tested through the different test interfaces 11 of the test card 100. In this way, the problem that some slots cannot be tested can be avoided, and the test coverage can be improved. Second, the test interface 11 includes an identification pin 112, and when the test interface 11 is connected to the host, the voltage of the identification pin of the test interface 11 is the first voltage, and when the test interface 11 is disconnected from the host, the voltage of the identification pin of the test interface 11 is the second voltage. The controller 13 can determine the target test interface 11 connected to the host based on the voltage of the identification pin of each test interface 11. In this way, during the test process, different test interfaces 11 can be connected to the host in turn according to actual needs, improving the test flexibility. Finally, the test card 100 supports loopback testing and card function testing, and through the configuration end 122 of the information loading circuit 12, the test mode can be selected. In this way, each slot of the host can be tested according to multiple different test modes, thereby further improving the test coverage.

[0025] In addition, the identification pin 112 arranged on each test interface 11 can be understood as an improved scheme adapted to multiple different test interfaces 11, because in some technologies, each standard card only includes one test interface, and the controller does not need to determine the target test interface connected to the host among multiple test interfaces. Therefore, the standard card in some technologies does not have the problem of determining the target test interface. However, the test card 100 of the present application includes multiple different test interfaces 11, and the controller 13 necessarily needs to determine the target test interface 11 connected to the host among the multiple test interfaces 11, and communicate with the host through the communication pin 111 of the target test interface 11. Therefore, the test card 100 of the present application has the problem of needing to determine the target test interface, and the identification pin 112 arranged on each test interface 11 is used to solve this problem.

[0026] Further, taking the PCIe protocol as an example. In a host designed based on the PCIe protocol, PCIe X4, PCIe X8, and PCIe X16 slots can have various corresponding widths, for example, the width of a PCIe X16 slot is greater than the width of a PCIe X8 slot, so that the PCIe X16 slot can support a larger number of channels. At the same time, the external space size of the PCIe X16 slot and the PCIe X8 slot is the same, and the external space size of the PCIe X4 slot is different from the external space size of the PCIe X8 and PCIe X16 slots. Among them, the external space size refers to the space area reserved outside the PCIe slot for accommodating PCIe standard cards and test cards.

[0027] When the test card 100 simultaneously includes the three types of test interfaces 11 of PCIe X4, PCIe X8 and PCIe X16, the size of the test card 100 can be reasonably designed to ensure that these test interfaces 11 can be docked with the corresponding PCIe slots. For ease of understanding, refer to Figure 2 The size of the test card 100 provided for some embodiments of the present application is shown in the figure. Figure 2 In the figure, the test card 100 includes a first end EF, a second end GH, a third end FH and a fourth end EG, the first end EF and the second end GH are oppositely arranged, and the third end FH and the fourth end EG are oppositely arranged. A plurality of different test interfaces 11 include a first test interface and a second test interface, the first test interface and the second test interface are used to connect the host slot, the first test interface is arranged at the first end EF, the second test interface is arranged at the second end GH, the distance between the first test interface and the third end FH is a first distance, the distance between the second test interface and the fourth end EG is a second distance, and the first distance is equal to the second distance.

[0028] Specifically, the first test interface can be a PCIe X16 interface, and the second test interface can be a PCIe X8 interface. The first distance and the second distance are 56.2 millimeters specified by the PCIe protocol.

[0029] Since in the PCIe protocol, the PCIe X16 slot corresponding to the first test interface and the PCIe X8 slot corresponding to the second test interface have the same external space size, when the first test interface and the second test interface are arranged at opposite ends of the test card 100, and the first distance between the first test interface and the third end FH is equal to the second distance between the second test interface and the fourth end EG, the first test interface can adapt to the external space size of the PCIe X16 slot, and the second test interface can adapt to the external space size of the PCIe X8 slot. In short, after the PCIe X16 interface is connected with the PCIe X16 slot of the host, the test card 100 is counterclockwise rotated, and the PCIe X8 interface can also be connected with the PCIe X8 slot of the host, or after the PCIe X8 interface is connected with the PCIe X8 slot of the host, the test card 100 is clockwise rotated, and the PCIe X16 interface can also be connected with the PCIe X16 slot of the host. That is, with the counterclockwise or clockwise rotation of the test card 100, the PCIe X16 interface and the PCIe X8 interface can adapt to the same external space size.

[0030] Further, continue to refer to Figure 2In some embodiments, the second test interface (i.e., the PCIe X8 interface) can be docked with the host slot corresponding to the first test interface (i.e., the PCIe X16 interface), but since the width of the first test interface is greater than the width of the second test interface, if the second test interface is flush with the third end FH, the second test interface cannot be inserted into the host slot corresponding to the first test interface. In view of this, the second test interface and the third end include a recessed area DH, which takes the end of the second test interface closest to the third end FH as the starting point and extends towards the third end FH, the extension length L of the recessed area DH is greater than or equal to the difference between the width of the first test interface and the width of the second test interface, and the height h1 of the recessed area DH is greater than or equal to the height h2 of the first test interface. In this way, after the test card 100 in Figure 2 is rotated in the counterclockwise direction, the recessed area DH can be used to accommodate part of the host slot corresponding to the first test interface (i.e., the PCIe X16 interface). For ease of understanding, refer to Figure 3 for the docking relationship between the second test interface provided by some embodiments of the present application and the host slot corresponding to the first test interface. Figure 3 In , the thick-line rectangular area can be regarded as the host slot corresponding to the first test interface. The second test interface can be docked with the shadow area of the host slot, and at the same time, the non-shaded area of the host slot is located in the recessed area of the test card 10. In this way, it is ensured that the second test interface (i.e., the PCIe X8 interface) can be inserted into the host slot corresponding to the first test interface (i.e., the PCIe X16 interface).

[0031] Continue to refer to Figure 2 In some embodiments, the plurality of different test interfaces 11 further include a third test interface for connecting the hard disk backplane of the host, and the third test interface is arranged at the third end FH or the fourth end EG. Specifically, the third test interface can be a PCIe X4 interface. When the test card 100 is connected to the host through the third test interface, the test card 100 can serve as a hard disk device of the host and communicate with the host. Since in the PCIe protocol, the external space size of the PCIe X4 slot is different from that of the PCIe X8 and X16 slots, the third test interface can be arranged at the third end FH or the fourth end EG. In this way, the width of the third end FH or the fourth end EG can be set according to the external space requirement of the PCIe X4 slot. Specifically, based on the PCIe protocol, the width of the third end FH and the fourth end EG can be 68.9 millimeters.

[0032] Refer to Figure 4 for the size diagram of the test card 100 provided by some other embodiments of the present application. Figure 4In this design, the thickness of test card 100 is equal to the second thickness, which refers to the card thickness specified by the communication protocol between test interface 11 and the host. Specifically, when the communication protocol between test interface 11 and the host is the PCIe protocol, the second thickness is 1.57 mm. Thus, the design of test card 100 conforms to the communication protocol specification, making test card 100 suitable for testing host slots designed according to the communication protocol.

[0033] The above Figure 2 and Figure 4 In the illustrated embodiment, by rationally designing the size of the test card 100, each test interface 11 of the test card 100 can be adapted to the slot size requirements and external space size requirements specified by the communication protocol, thereby improving the applicability of the test card 100.

[0034] In some embodiments, at least a portion of the test interface 11 includes gold fingers for contacting the host to connect the test interface 11 to the host. For example, see [reference needed]. Figure 5 This is a schematic diagram of a test card 100 provided in some embodiments of this application. Figure 5 In the diagram, the areas marked 'a' and 'b' can be the areas for setting the gold fingers. The gold plating thickness of the gold fingers can be specified in the communication protocol. For example, in the PCIe protocol, the gold plating thickness can be specified as 0.8 micrometers.

[0035] In some embodiments of this application, considering that the test card 100 needs to be frequently plugged and unplugged between various hosts, resulting in significant wear and tear on the test interface 11, the gold plating thickness of the gold fingers can be greater than or equal to a first thickness, where the first thickness refers to the gold plating thickness specified by the communication protocol between the test interface 11 and the host. For example, in the PCIe protocol, the specified gold plating thickness of the gold fingers is 0.8 micrometers. Therefore, in the test card 100 of this application, the gold plating thickness of the gold fingers can be 1.25 micrometers. This increases the durability of the test card 100 and extends its service life.

[0036] Furthermore, in conjunction with reference Figures 6 to 9 In some embodiments, the third end FH of the test card 100 is provided with a first fixing component 141, and the fourth end GE is provided with a second fixing component 143. At least one of the first fixing component 141 and the second fixing component 143 is used to fix the first end of the baffle 142. When the first test interface or the second test interface is connected to the host slot, the second end of the baffle 142 is fixed to the host. The baffle 142 is used to keep the first test interface or the second test interface in contact with the host slot.

[0037] Specifically, when the second test interface (i.e., the PCIe X8 interface) is connected with the host, the first fixing assembly 141 can be used to fix the baffle 142. When the first test interface (i.e., the PCIe X16 interface) is connected with the host, the second fixing assembly 143 can be used to fix the baffle 142. Of course, it can be understood that in actual application, the fixing assembly used can also be dynamically adjusted. For example, when the first test interface (i.e., the PCIe X16 interface) is connected with the host, the first fixing assembly 141 can be used to fix the baffle 142. When the second test interface (i.e., the PCIe X8 interface) is connected with the host, the second fixing assembly 143 can be used to fix the baffle 142. For example, when the first test interface (i.e., the PCIe X16 interface) and the second test interface (i.e., the PCIe X8 interface) are connected with the host, the first fixing assembly 141 or the second fixing assembly 143 is used to fix the baffle 142. The present application does not limit this.

[0038] By setting the first fixing assembly 141 and the second fixing assembly 143 for fixing the baffle on the test card 100, when the test interface 11 is connected with the host slot, the test interface 11 and the host slot can maintain a good contact state, thereby improving the communication reliability and avoiding the problem of communication interruption caused by poor contact between the test interface 11 and the host slot.

[0039] In some embodiments, the baffle includes a first baffle and a second baffle, the first baffle is used to adapt to a first height of the host, and the second baffle is used to adapt to a second height of the host. The first height of the host refers to a half-height host, and the second height of the host refers to a full-height host. In other words, when the test card 100 is used to test the host slot of the half-height host, if the host is a half-height host, the first fixing assembly 141 or the second fixing assembly 143 is used to fix the first baffle, and if the host is a full-height host, the first fixing assembly 141 or the second fixing assembly 143 is used to fix the second baffle. That is, according to the height of the host to be tested, the first fixing assembly 141 can be used to fix either of the first baffle and the second baffle. Similarly, the second fixing assembly 143 can also be used to fix either of the first baffle and the second baffle.

[0040] In some embodiments, according to the PCIe protocol, the first baffle corresponding to the first test interface (i.e., the PCIe X16 interface) and the second test interface (i.e., the PCIe X8 interface) has different sizes, and the second baffle corresponding to the first test interface (i.e., the PCIe X16 interface) and the second test interface (i.e., the PCIe X8 interface) also has different sizes.

[0041] For the convenience of understanding, reference can be made to Figures 10 to 17 . Figure 10The top view size of the first baffle corresponding to the first test interface provided for some embodiments of the present application. Figure 11 The side view size of the first baffle corresponding to the first test interface provided for some embodiments of the present application. Figure 12 The top view size of the second baffle corresponding to the first test interface provided for some embodiments of the present application. Figure 13 The side view size of the second baffle corresponding to the first test interface provided for some embodiments of the present application. Figure 14 The top view size of the first baffle corresponding to the second test interface provided for some embodiments of the present application. Figure 15 The side view size of the first baffle corresponding to the second test interface provided for some embodiments of the present application. Figure 16 The top view size of the second baffle corresponding to the second test interface provided for some embodiments of the present application. Figure 17 The side view size of the second baffle corresponding to the second test interface provided for some embodiments of the present application. Figures 10 to 17 The baffle size in the above-mentioned embodiments conforms to the PCIe protocol, and thus can be applied to any host slot test based on PCIe design, and is more applicable.

[0042] In the above-mentioned embodiments, the first baffle and the second baffle of different sizes are designed according to the height of the host and the type of the test interface, which can make the test card 100 applicable to hosts of different heights, and is more applicable.

[0043] The following gives a partial assembly diagram of the test card 100 connected with the host, for better understanding.

[0044] For reference, Figure 18 The assembly diagram of the test card 100 connected with the host provided for the first embodiment of the present application. Figure 18 In the above-mentioned embodiment, a plurality of test cards 100 are connected with the host board slot (i.e. the host slot on the host board) of the half-height host. The height of the host board slot is half the height of the standard PCIe slot, so as to adapt to the half-height host. Specifically, the test card 100 is connected with the host slot through one of the first test interface (i.e. the PCIe X16 interface) and the second test interface (i.e. the PCIe X8 interface), and the baffle of the test card 100 is the first baffle.

[0045] For reference, Figure 19 The assembly diagram of the test card 100 connected with the host provided for the second embodiment of the present application. Figure 19In the third embodiment of the present application, the plurality of test cards 100 are connected to the host slots of a full-height host. The height of the host slots is the same as the height of the standard PCIe slots, so as to adapt to the full-height host. Specifically, the test card 100 is connected to the host slot through one of the first test interface (i.e., the PCIe X16 interface) and the second test interface (i.e., the PCIe X8 interface), and the baffle of the test card 100 is the second baffle.

[0046] For reference Figure 20 The assembly schematic diagram of the test card 100 connected to the host provided by the third embodiment of the present application is shown in FIG. 3. Figure 20 In the third embodiment of the present application, the plurality of test cards 100 are connected to the host slots of a full-height host. The height of the host slots is the same as the height of the standard PCIe slots, so as to adapt to the full-height host. Specifically, the test card 100 is connected to the host slot through one of the first test interface (i.e., the PCIe X16 interface) and the second test interface (i.e., the PCIe X8 interface), and the baffle of the test card 100 is the second baffle.

[0047] For reference Figure 21 The assembly schematic diagram of the test card 100 connected to the host provided by the fourth embodiment of the present application is shown in FIG. 4. Figure 21 In the third embodiment of the present application, the plurality of test cards 100 are connected to the host slots of a full-height host. The height of the host slots is the same as the height of the standard PCIe slots, so as to adapt to the full-height host. Specifically, the test card 100 is connected to the host slot through one of the first test interface (i.e., the PCIe X16 interface) and the second test interface (i.e., the PCIe X8 interface), and the baffle of the test card 100 is the second baffle.

[0048] For reference Figure 22 The assembly schematic diagram of the test card 100 connected to the host provided by the fifth embodiment of the present application is shown in FIG. 5. Figure 22 In the third embodiment of the present application, the plurality of test cards 100 are connected to the host slots of a full-height host. The height of the host slots is the same as the height of the standard PCIe slots, so as to adapt to the full-height host. Specifically, the test card 100 is connected to the host slot through one of the first test interface (i.e., the PCIe X16 interface) and the second test interface (i.e., the PCIe X8 interface), and the baffle of the test card 100 is the second baffle.

[0049] The hardware design of the test card 100 is described below.

[0050] For reference Figure 23 The schematic diagram of some modules of the test card 100 provided by some embodiments of the present application is shown in FIG. 6. Figure 23In some embodiments, the test card 100 comprises a test interface 11, a controller 13, a clock source 191, a power supply 193, a storage medium 18, a sensor 192, an indicator 194, and an auxiliary component 17. The test interface 11 comprises a first test interface, a second test interface, and a third test interface. The auxiliary component 17 comprises, but is not limited to, a UART (Universal Asynchronous Receiver / Transmitter), a TAP_SEL (Test Access Port Selector), a reset button, an I2C (Inter-Integrated Circuit), and the like. The clock source 191 is configured to generate a clock signal. The controller 13 operates according to the clock signal generated by the clock source 191. The power supply 193 is configured to output a voltage, such as 12V or 5V, to power the components on the test card 100, such as the controller 13. The indicator 194 is configured to show the working status of the test card 100, which can include, but is not limited to, working, standby, and abnormal working. The sensor 192 is configured to collect data of the test card 100, such as the temperature of the test card 100. The sensor 192 is connected to the controller 13. The controller 13 can receive the data collected by the sensor 192.

[0051] The storage medium 18 is configured to store test parameters. The controller 13 communicates with the host based on the test parameters. Specifically, the test parameters refer to the communication parameters in the process of communication between the controller 13 and the host, including, but not limited to, clock frequency and communication rate. When the controller 13 detects that one of the test interfaces is connected to the host, the controller 13 reads the test parameters from the storage medium 18 and communicates with the host based on the test parameters.

[0052] In some embodiments, different test modes correspond to different test parameters. The controller 13 reads the configuration parameters corresponding to the target test mode from the storage medium 18 according to the target test mode corresponding to the configuration signal, and communicates with the host according to the read configuration parameters. For example, in the storage medium 18, a first set of test parameters corresponding to a first test mode and a second set of test parameters corresponding to a second test mode can be stored. The first set of test parameters and the second set of test parameters can be the same or different. Figure 1 When the configuration signal received by the configuration end represents the first test mode, the controller 13 reads the first set of test parameters from the storage medium 18 and communicates with the host according to the first set of test parameters. When the configuration signal received by the configuration end represents the second test mode, the controller 13 reads the second set of test parameters from the storage medium 18 and communicates with the host according to the second set of test parameters. Figure 1 When the configuration signal received by the configuration end represents the second test mode, the controller 13 reads the second set of test parameters from the storage medium 18 and communicates with the host according to the second set of test parameters.

[0053] The test parameters are divided according to the test modes, and the test parameters corresponding to different test modes are stored in the storage medium 18 of the test card 100. In this way, different test parameters can be set for different test modes, improving the test flexibility.

[0054] Similarly, in some embodiments, different test interfaces 11 correspond to different test parameters, the controller 13 reads the configuration parameters corresponding to the target test interface 11 from the storage medium 18, and communicates with the host according to the read configuration parameters. For example, in the storage medium 18, a third set of test parameters corresponding to the first test interface, a fourth set of test parameters corresponding to the second test interface, and a fifth set of test parameters corresponding to the third test interface can be stored. The third set of test parameters, the fourth set of test parameters, and the fifth set of test parameters can be the same or different. In the case where the controller 13 detects that the first test interface is connected to the host, the third set of test parameters corresponding to the first test interface can be read from the storage medium 18, and the host can be communicated according to the third set of test parameters. In the case where the controller 13 detects that the second test interface is connected to the host, the fourth set of test parameters corresponding to the second test interface can be read from the storage medium 18, and the host can be communicated according to the fourth set of test parameters. The same applies to the third test interface.

[0055] The test parameters are divided according to the test interfaces, and the test parameters corresponding to different test interfaces are stored in the storage medium of the test card 100. In this way, different test parameters can be set for different test interfaces, improving the test flexibility.

[0056] Continuing to refer to Figure 23In some embodiments, the controller 13 includes a plurality of physical lanes, which are divided into at least two logical ports based on the number of test interfaces of the test card 100 and the number of communication pins of each test interface 11, and each logical port corresponds to a test interface, and the physical lanes of each logical port are used to connect the corresponding test interface 11. For example, when the first test interface is a PCIe X16 interface, the second test interface is a PCIe X8 interface, and the third test interface is a PCIe X4 interface, the controller 13 can include 28 physical lanes, the first to sixteenth physical lanes are divided into the logical port P1, the seventeenth to twenty-fourth physical lanes are divided into the logical port P2, and the twenty-fifth to twenty-eighth physical lanes are divided into the logical port P3. The physical lanes of the logical port P1 are connected to the communication pins 111 of the first test interface, the physical lanes of the logical port P2 are connected to the communication pins 111 of the second test interface, and the physical lanes of the logical port P3 are connected to the communication pins 111 of the third test interface. In addition, in the PCIe protocol, since each physical lane includes two signal lines, the number of communication pins of each test interface 11 is equal to four times the number of physical lanes supported by the corresponding test interface 11. For example, the PCIe X16 interface has 62 communication pins.

[0057] In this way, the physical lanes between the test interfaces 11 can be independent of each other, improving the test flexibility.

[0058] In some embodiments, the physical lane division logic can be pre-burned in the storage medium 18. The controller 13 divides the physical lanes into a plurality of logical ports based on the physical lane division logic in the storage medium 18. The physical lane division logic includes, but is not limited to, the binding relationship between the physical lanes and the logical ports, the correspondence between the logical ports and the physical lanes, etc. By pre-burning the physical lane division logic in the storage medium 18, the physical lanes can be divided as needed, thereby improving the flexibility of lane division.

[0059] For reference Figure 24 The module schematic diagram of the controller 13 provided for some embodiments of the present application. Figure 24In some embodiments, the controller 13 further comprises an uplink clock pin 131, which is used to connect a host clock source. In the case that the logical ports of the controller 13 comprise uplink ports, the physical layer of the uplink ports is time-sequenced matched with the clock signal generated by the host clock source. For example, the logical ports of the controller 13 used to connect with the PCIe X16 interface can be uplink ports. The controller core 132 controls the physical layer of the logical ports to be time-sequenced matched with the clock signal generated by the host clock source. In this way, it can be ensured that the controller 13 and the host have the same clock source, and the problem of communication error caused by the clock inconsistency between the controller 13 and the host can be avoided.

[0060] With reference to Figure 23 In some embodiments, the clock source 191 located on the test card 100 can also be referred to as a local clock source. The controller 13 further comprises a local clock pin 133. The local clock pin 133 is connected with the local clock source 191, and the controller 13 performs data processing operations other than data uploading according to the clock signal generated by the local clock source 191. For example, the controller 13 performs operations such as data packet routing, register configuration, and cache management according to the clock signal generated by the local clock pin 133. The local clock source 191 and the host clock source can be independent of each other. In the case of host failure, the controller 13 can perform operations according to the clock signal generated by the local clock source 191, thereby improving the fault tolerance.

[0061] With reference to Figure 25 A module schematic diagram of the test interface 11 provided for some embodiments of the present application is shown in FIG. 3. Figure 24 In some embodiments, the test interface 11 comprises an I2C pin in addition to the communication pin 111 and the identification pin 112. The sensor 192 can be connected with the I2C pin of the test interface 11 through the controller 13. The BMC (Baseboard Management Controller) in the host can obtain the data collected by the sensor 192 (such as the temperature of the test card 100) through the I2C pin of the test interface 11, and manage the test card 100 based on the data collected by the sensor 192. For example, the test card 100 is controlled to stop working when the temperature of the test card 100 is too high. At the same time, the host can also burn data (such as channel division logic) into the storage medium 18 of the test card 100 through the I2C pin of the test interface 11, thereby realizing the management of the test card 100.

[0062] Further, Figure 24In some embodiments, the I2C pin of the test interface 11 can be connected to the sensor 192 and the storage medium 18 through the voltage conversion module 195. In this way, voltage matching between the test interface 11 and the sensor 192 and the storage medium 18 is achieved.

[0063] Further, Figure 24 In some embodiments, a switch 196 can be further included between the voltage conversion module 195 and the storage medium 18. The switch 196 is used to control the on-off between the voltage conversion module 195 and the storage medium 18, so as to avoid misoperation on the storage medium 18.

[0064] For reference Figure 26 The schematic diagram of the interaction between the controller 13 and other components of the test card 100 is provided for some embodiments of the present application. Figure 26 In some embodiments, the auxiliary port can include, but is not limited to, a GPIO port, an I2C port, and an SPI (Serial Peripheral Interface). The working principle of the controller 13 can be referred to the above description, which is not repeated here.

[0065] Based on the above description, for reference Figure 27 The schematic diagram of the test card 100 is provided for some embodiments of the present application. Figure 27 In some embodiments, the components marked as 16 are other chip components of the test card 100 except the controller 13. The other components can be referred to the above description, which is not repeated here.

[0066] For reference Figure 28 The module schematic diagram of the host 200 is provided for some embodiments of the present application. The test card 100 described above is used to test the host 200.

[0067] Specifically, the host 200 includes a hard disk backboard. In the case that a plurality of test cards 100 are connected to the hard disk backboard, the plurality of test cards 100 are arranged in the same accommodating container, which is used to keep the hard disk backboard and the plurality of test cards 100 in contact. In this way, the communication reliability between the test card 100 and the host 200 is ensured.

[0068] The test card and the host provided by the present application are described in detail above. The principles and implementation manners of the present application are described by applying specific examples. The above description of the embodiments is only used to help understand the method of the present application and its core idea. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, some improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A test card, characterized in that, The test card includes: Multiple different test interfaces, each test interface including a communication pin and an identification pin. When the test interface is connected to the host, the voltage of the identification pin of the test interface is a first voltage. When the test interface is disconnected from the host, the voltage of the identification pin of the test interface is a second voltage. The information loading circuit includes a configuration terminal and a detection terminal. The detection terminal is connected to the identification pin, and the configuration terminal is used to receive a configuration signal that characterizes the test mode. The controller is connected to the detection terminal, the configuration terminal, and the communication pins of each of the test interfaces. It is used to detect the identification pin voltage of each of the test interfaces through the detection terminal, and determine the target test interface connected to the host based on the detected identification pin voltage. When the configuration signal received by the configuration terminal represents a first test mode, it performs a loopback test with the host through the communication pin of the target test interface. When the configuration signal received by the configuration terminal represents a second test mode, it performs a card function test with the host through the communication pin of the target test interface.

2. The test card according to claim 1, characterized in that, The test card includes a first end, a second end, a third end, and a fourth end, wherein the first end and the second end are positioned opposite each other, and the third end and the fourth end are positioned opposite each other. The plurality of different test interfaces include a first test interface and a second test interface. The first test interface and the second test interface are used to connect to the host slot. The first test interface is located at the first end, and the second test interface is located at the second end. The distance between the first test interface and the third end is a first distance, and the distance between the second test interface and the fourth end is a second distance. The first distance is equal to the second distance.

3. The test card according to claim 2, characterized in that, The plurality of different test interfaces also include a third test interface, which is used to connect to the hard drive backplane of the host, and the third test interface is located at the third end or the fourth end.

4. The test card according to claim 2, characterized in that, The width of the first test interface is greater than the width of the second test interface. The second test interface and the third end include a recessed area. The recessed area extends from the end of the second test interface closest to the third end to the third end. The extension length of the recessed area is greater than or equal to the difference between the widths of the first test interface and the second test interface, and the height of the recessed area is greater than or equal to the height of the first test interface.

5. The test card according to claim 2, characterized in that, The test card is provided with a first fixing component at its third end and a second fixing component at its fourth end. At least one of the first fixing component and the second fixing component is used to fix the first end of the baffle. When the first test interface or the second test interface is connected to the host slot, the second end of the baffle is fixed to the host. The baffle is used to keep the first test interface or the second test interface in contact with the host slot. Furthermore, the baffle includes a first baffle and a second baffle, the first baffle being adapted to a host of a first height, and the second baffle being adapted to a host of a second height.

6. The test card according to any one of claims 1 to 5, characterized in that, At least a portion of the test interface includes gold fingers for contacting the host to connect the test interface to the host. The gold plating thickness of the gold fingers is greater than or equal to a first thickness, which refers to the gold plating thickness specified by the communication protocol between the test interface and the host.

7. The test card according to any one of claims 1 to 5, characterized in that, The thickness of the test card is equal to the second thickness, which refers to the card thickness specified by the communication protocol between the test interface and the host.

8. The test card according to claim 1, characterized in that, The controller includes multiple physical channels. Based on the number of test interfaces of the test card and the number of communication pins of each test interface, the multiple physical channels are divided into at least two logical ports. Each logical port corresponds one-to-one with a test interface, and the physical channel of each logical port is used to connect to the corresponding test interface.

9. The test card according to claim 8, characterized in that, The controller also includes an uplink clock pin, which is used to connect to the host clock source. When the logic port of the controller includes an uplink port, the physical layer of the uplink port performs timing matching with the host based on the clock signal generated by the host clock source.

10. The test card according to claim 9, characterized in that, The controller also includes a local clock pin, and the test card also includes a local clock source. The local clock pin is connected to the local clock source, and the controller performs data processing operations other than data uploading based on the clock signal generated by the local clock source.

11. The test card according to claim 1, characterized in that, The test card also includes a storage medium for storing test parameters, and the controller communicates with the host based on the test parameters.

12. The test card according to claim 11, characterized in that, Different test modes correspond to different test parameters. The controller reads the configuration parameters corresponding to the target test mode from the storage medium according to the target test mode corresponding to the configuration signal, and communicates with the host according to the read configuration parameters.

13. The test card according to claim 11, characterized in that, Different test interfaces correspond to different test parameters. The controller reads the configuration parameters corresponding to the target test interface from the storage medium and communicates with the host according to the read configuration parameters.

14. A host computer, characterized in that, The test card as described in any one of claims 1 to 13 is used to test the host.

15. The host computer according to claim 14, characterized in that, The host includes a hard disk backplane. When multiple test cards are connected to the hard disk backplane, the multiple test cards are placed in the same receiving container. The receiving container is used to keep the hard disk backplane in contact with the multiple test cards.

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