PCIe device link training control method and electronic device
By adjusting the training latency of the PCIe device through the control component, the problem of the PCIe device not being able to enter the link training at an appropriate time after the reset signal is solved, and a reliable connection between the PCIe device and the processor system is achieved.
Patent Information
- Application Number
- CN202511432794.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-09-30
- Publication Date
- 2026-01-02
AI Technical Summary
In the prior art, PCIe devices cannot enter the link training phase at an appropriate time after the power reset signal is released, resulting in link training failure and inability to establish a communication connection with the CPU.
The control unit controls the PCIe devices to start link training based on the stored correspondence between PCIe devices and training latency. When link training failure is detected, the training latency is adjusted and the processor system is restarted to restart link training.
This effectively reduces the number of PCIe device link training failures and ensures that PCIe devices can establish connections with the processor system.
Smart Images
Figure CN121255705A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of computer technology, and in particular to a control method and electronic device for PCIe device link training. Background Technology
[0002] Peripheral Component Interconnect Express (PCIe) is a high-speed serial computer expansion bus characterized by high transmission speed and reliable end-to-end transmission. PCIe devices are those connected to the processor system of electronic devices via PCIe ports. Examples of PCIe devices connected to the processor system in electronic devices include, but are not limited to, solid-state drives (SSDs) and network interface cards (NICs).
[0003] To ensure reliable communication between PCIe devices and the processor system, PCIe devices perform link training after the power reset signal is deactivated. However, currently, individual PCIe devices in electronic devices may not enter the link training phase at the appropriate time, leading to link training failure and preventing the PCIe device from establishing a communication connection with the CPU. Summary of the Invention
[0004] On the one hand, this application provides a control method for PCIe device link training, including:
[0005] According to the correspondence between at least one PCIe device and training latency stored in the control unit, the control unit controls the PCIe device to start link training;
[0006] If the system boot firmware confirms that there is a target PCIe device with a failed link training, it determines the target duration to which the training latency of the target PCIe device needs to be adjusted, and the target PCIe device belongs to the at least one PCIe device.
[0007] The system boot firmware adjusts the training latency corresponding to the target PCIe device in the control component to the target latency, triggering a processor system restart to restart the link training for the PCIe device.
[0008] In one possible implementation, the control method for training the PCIe device link further includes: detecting that a reset signal in the processor system has been deactivated, and the control component determining the current time as a reference time;
[0009] The step of controlling the PCIe device to start link training according to the correspondence between at least one PCIe device and training latency stored in the control unit includes:
[0010] According to the correspondence between at least one PCIe device and training latency stored in the control unit, when the time from the current time to the reference time reaches the training latency corresponding to the PCIe device, the control unit instructs the PCIe device to start link training.
[0011] In another possible implementation, the control method for training the PCIe device link also includes:
[0012] In response to the processor system's first boot, the system boot firmware sends an initial configuration command to the control unit. The initial configuration command is used to instruct that the training latency duration corresponding to each PCIe device be set to the set initial duration.
[0013] In response to the initial configuration command, the control unit sets and stores the training latency duration corresponding to each PCIe device as the initial duration.
[0014] In another possible implementation, determining the target duration to which the training latency of the target PCIe device needs to be adjusted includes:
[0015] From a set number of candidate delay durations, determine a target candidate delay duration that is different from the current training delay duration corresponding to the target PCIe device;
[0016] The target candidate latency duration is determined as the target duration to which the training latency duration of the target PCIe device needs to be adjusted.
[0017] In another possible implementation, determining a target candidate latency duration that differs from the current training latency duration of the target PCIe device from a set plurality of candidate latency durations includes:
[0018] Based on the time length order of the multiple candidate latency durations, the target candidate latency duration that has not yet been used as the training latency duration corresponding to the target PCIe device and is the first in the order is determined.
[0019] In another possible implementation, the control method for training the PCIe device link further includes: the system boot firmware confirming at least one PCIe device connected to the processor system through the control component;
[0020] The system boot firmware confirms the existence of a target PCIe device where link training has failed, including:
[0021] The system boot firmware uses the CPU to confirm the PCIe device information that has been successfully trained via link verification;
[0022] Based on the PCIe device information that has successfully trained the link, determine the target PCIe device among the at least one PCIe devices that has failed the link training.
[0023] In another possible implementation, the control method for training the PCIe device link also includes:
[0024] If there is no target PCIe device where the link training failed, the system boot firmware obtains the training latency duration corresponding to each of at least one PCIe device stored in the control unit.
[0025] The system boot firmware stores the training latency duration corresponding to each PCIe device in a target memory outside the control unit.
[0026] After detecting that the electronic device is powered on, the system boot firmware obtains the training latency duration corresponding to each PCIe device in the target memory and configures it into the control unit.
[0027] In yet another possible implementation, the control unit is a field-programmable gate array in the processor system.
[0028] In another aspect, this application also provides an electronic device, comprising:
[0029] A processor system and system boot firmware, the processor system including control components;
[0030] The control component is used to control the PCIe device to start link training according to the stored correspondence between at least one PCIe device and the training latency duration.
[0031] The system boot firmware is used to, if it is confirmed that there is a target PCIe device whose link training has failed, determine the target duration to which the training latency of the target PCIe device needs to be adjusted, wherein the target PCIe device belongs to the at least one PCIe device; adjust the training latency of the control unit corresponding to the target PCIe device to the target duration, and trigger a restart of the processor system to restart the link training of the PCIe device.
[0032] In one possible implementation, the control unit is further configured to detect that the reset signal in the processor system has been deactivated and determine the current time as a reference time;
[0033] Specifically, the control component is configured to, according to the correspondence between at least one PCIe device and training latency stored in the control component, instruct the PCIe device to start link training when the time from the current time to the reference time reaches the training latency corresponding to the PCIe device. Attached Figure Description
[0034] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.
[0035] Figure 1 A flowchart illustrating the control method for PCIe device link training provided in this application;
[0036] Figure 2 Another flowchart illustrating the control method for PCIe device link training provided in this application;
[0037] Figure 3 A flowchart illustrating the control method for PCIe device link training provided in this application in one application scenario;
[0038] Figure 4 A schematic diagram of the component architecture of the electronic device provided in this application. Detailed Implementation
[0039] The solution presented in this application can be applied to any electronic device having a processor system and system boot firmware. The processor system can be a processor module (also called a processor platform) that includes at least a Central Processing Unit (CPU) and control components. Of course, this processor module may also include a Graphics Processing Unit (GPU) and chipsets, etc., without limitation. The processor system is capable of establishing a connection with Peripheral Component Interconnect Express (PCIe) devices. For example, the electronic device can be a server or a mainframe with a processor system, and the specific processor system is not limited.
[0040] PCIe devices refer to devices that connect to the processor system of electronic devices through PCIe ports (interfaces) or slots. For example, PCIe devices can be solid-state drives and network cards, etc., without specific restrictions.
[0041] In this application, the system boot firmware is firmware used to boot an electronic device. It can be responsible for the electronic device's power-on self-test, hardware initialization, and loading the operating system loader. For example, the system boot firmware can be a Unified Extensible Firmware Interface (UEFI), or a Basic Input / Output System (BIOS), or other firmware that can be used to replace the BIOS or UEFI in subsequent upgrades. There are no restrictions on this.
[0042] The embodiments of this application are described below with reference to the accompanying drawings. The terminology used in the implementation section of this application is only for explaining specific embodiments and is not intended to limit the application. Those skilled in the art will recognize that, with technological advancements and the emergence of new scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.
[0043] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms are interchangeable where appropriate; this is merely a way of distinguishing objects with the same attributes in the embodiments of this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion, so that a process, method, system, product, or apparatus that comprises a series of elements is not necessarily limited to those elements, but may include other elements not explicitly listed or inherent to those processes, methods, products, or apparatuses.
[0044] like Figure 1 This illustration shows a flowchart of a control method for PCIe device link training provided in this application. The method of this embodiment is applied to electronic devices and may include:
[0045] S101, according to the correspondence between at least one PCIe device and training latency stored in the control unit, the control unit controls the PCIe device to start link training.
[0046] The control unit can be a component within the processor system, and its specific configuration can be determined according to actual needs without restriction. For example, in one possible scenario, the control unit could be a Field Programmable Gate Array (FPGA) within the processor system.
[0047] The training latency durations for each PCIe device stored in the control unit can be those sent to the control unit by the system boot firmware after the current processor system startup. For example, during the first startup of the processor system, the system boot firmware sends the initial training latency durations for each PCIe device, and the control unit saves these durations. Of course, the training latency durations for each PCIe device may be adjusted subsequently. Correspondingly, the correspondence between each PCIe device and its training latency duration stored in the control unit can also be the correspondence stored and maintained by the control unit after the last processor system startup; there are no specific restrictions.
[0048] In this application, the training latency for a PCIe device refers to the delay in initiating link training from the moment the reset signal in the processor system is deactivated. The training latency may differ for different PCIe devices.
[0049] Based on this, the control unit, according to the training latency duration corresponding to the PCIe device, can control the PCIe device to start link training by delaying the training latency duration corresponding to the PCIe device in response to the deactivation of the reset signal in the processor system, thereby instructing the PCIe device to start link training. For example, the control unit sends an indication signal to the PCIe device to indicate that the reset signal has been deactivated, and the PCIe device will start link training in response to the indication signal.
[0050] Link training for PCIe devices refers to the process of information calibration and parameter negotiation between the PCIe device and the processor system (such as the CPU in the processor system). Its purpose is to ensure the reliability and efficiency of physical signal transmission between the PCIe device and the connected processor system. This application does not impose any restrictions on the specific implementation of link training for PCIe devices.
[0051] It is understandable that the reset signal in a processor system is the signal that triggers the power-on of each PCIe device connected to the processor system. For example, the CPU can generate a reset signal before starting instruction execution to reset its internal power management controller and related logic. Of course, there are other situations where a reset signal can be generated, and there are no restrictions on this. When the reset signal is activated, the internal logic of the PCIe device is reset to prepare for entering the link training phase. When the reset signal is deactivated (e.g., from low to high), it indicates that the PCIe device can begin entering the link training phase.
[0052] S102, if the system boot firmware confirms that there is a target PCIe device with a failed link training, determine the target duration to which the training latency of the target PCIe device needs to be adjusted.
[0053] Among them, PCIe device link training failure refers to the inability of a PCIe device to establish a connection with the processor system (such as CPU), resulting in the loss of the PCIe device.
[0054] In this application, for ease of distinction, the PCIe device that failed to train the link is referred to as the target PCIe device. Based on this, it can be known that the target PCIe device belongs to at least one of the PCIe devices mentioned above.
[0055] The inventors of this application discovered that if the timing of initiating link training for a PCIe device is inappropriate after the reset signal is deactivated, it can lead to the PCIe device losing its link training capability. Therefore, in this application, the system boot firmware, upon confirming the failure of link training for the target PCIe device, will re-determine the appropriate target delay duration for initiating link training for that target PCIe device, in order to subsequently adjust the corresponding training delay duration for that target PCIe device.
[0056] There may be one or more target PCIe devices that fail in link training, but the processing procedure is the same for each target PCIe device.
[0057] S103, the system boot firmware adjusts the training latency corresponding to the target PCIe device in the control unit to the target latency, triggering a processor system restart to restart the link training for the PCIe device.
[0058] For example, the system boot firmware can send a duration adjustment command to the control unit. This command indicates the target duration for the target PCIe device. For instance, the command might include the port number of the port or the slot number of the slot to which each target PCIe device is connected, as well as the target duration for each device. Accordingly, in response to the command, the control unit will adjust its stored training latency for the target PCIe device to the target duration.
[0059] Understandably, after the system boot firmware adjusts the training latency of the target PCIe device stored in the control unit to the target latency, the training latency of that PCIe device in the correspondence stored in the control unit will be updated to the target latency. Based on this, after the system boot firmware triggers a processor system restart, the control unit will control the target PCIe device to start link training according to the target latency, thus reducing the likelihood of link training failures.
[0060] As can be seen from the above, in this application, the control unit controls the PCIe devices to start link training according to the correspondence between each PCIe device and the training latency. After the system boot firmware confirms that there is a target PCIe device with link training failure, the system boot firmware will re-determine the target latency of the target PCIe device and adjust the training latency of the target PCIe device in the control unit to the target latency. Based on this, after the system boot firmware restarts the processor system, the control unit can restart the link training of the target PCIe device according to the adjusted training latency of the target PCIe device. This can reduce the situation where PCIe device link training fails due to an inappropriate latency of the target PCIe device, and naturally reduce the situation where a connection cannot be established with the processor system (such as the CPU) due to PCIe device link training failure.
[0061] It is understood that in this application, if the processor system is a first-time system, the system boot firmware also needs to configure the initial training time corresponding to each PCIe device in the control unit.
[0062] For example, in one possible implementation, in response to the processor system's initial boot, the system boot firmware sends an initial configuration command to the control unit. This initial configuration command instructs that the training latency for each PCIe device be set to a predetermined initial latency. Accordingly, in response to this initial configuration command, the control unit can set and store the training latency for each PCIe device as the initial latency.
[0063] The initial duration can be set according to actual needs. For example, if the initial duration is 1 second, then when the processor system starts up for the first time, the training latency duration corresponding to each PCIe device that can be stored in the control unit will be the same, which is 1 second.
[0064] It is understandable that, since different PCIe devices are suited to different timings for initiating link training, if the control unit controls each PCIe device to initiate link training with the same training delay duration, it may cause some PCIe devices to fail to complete link training. Based on the solution in this application, the system boot firmware adjusts the training delay duration corresponding to the PCIe devices whose link training failed in the control unit. Therefore, after the system boot firmware restarts the processor system, the training delay durations corresponding to each PCIe device stored in the control unit will not be exactly the same.
[0065] It is understood that the control unit can only control the PCIe device to start link training when the reset signal is deactivated. Therefore, in this application, the control unit can control each PCIe device to start link training according to the corresponding delay training duration of each PCIe device in response to the reset signal being deactivated. The following is in conjunction with... Figure 2 Please provide an explanation.
[0066] like Figure 2 This illustration shows another flowchart of the control method for PCIe device link training provided in this application. The method in this embodiment may include:
[0067] S201, the reset signal in the processor system is detected to be deactivated, and the control unit determines the current time as the reference time.
[0068] The control unit can detect that the processor system's reset signal has been deactivated through the system boot firmware. For example, if the system boot firmware detects that the reset signal has been deactivated, it will send a deactivation instruction to the control unit, which indicates that the reset signal in the processor system has been deactivated.
[0069] Of course, the control unit can also detect that the reset signal has been deactivated in other ways, and there are no restrictions on the specific implementation method.
[0070] S202, according to the correspondence between at least one PCIe device and training latency stored in the control unit, when the time from the current time to the reference time reaches the training latency corresponding to the PCIe device, the control unit instructs the PCIe device to start link training.
[0071] Understandably, if the current stage is the initial startup of the processor system, the system boot firmware will send an initial configuration command to the control unit before step S201 or S202. Since the initial configuration command indicates that the training latency for each PCIe device is set to an initial duration, in this case, the control unit stores the same initial training latency for each PCIe device. Therefore, when the time remaining from the reference time reaches the initial duration, the control unit will control each PCIe device to simultaneously start link training.
[0072] If this is not the processor system's first boot, the mapping between PCIe devices and training latency in the control unit has already been adjusted. Therefore, the training latency for each PCIe device may differ. For each PCIe device, the control unit only needs to initiate link training when the time remaining since the reference time reaches the corresponding training latency. In this case, the start time for link training for each PCIe device may vary.
[0073] S203, if the system boot firmware confirms that there is a target PCIe device with a failed link training, determine the target duration to which the training latency of the target PCIe device needs to be adjusted.
[0074] The target PCIe device belongs to the at least one PCIe device.
[0075] S204, the system boot firmware adjusts the training latency corresponding to the target PCIe device in the control unit to the target latency, triggering a processor system restart to restart the link training for the PCIe device.
[0076] As can be seen, the solution proposed in this application can continuously adjust the training latency of each PCIe device in the control device, thereby ultimately finding the appropriate training latency for each PCIe device, so that each PCIe device can start link training at the appropriate time, which naturally reduces the situation where PCIe devices cannot establish a connection with the processor system (such as CPU).
[0077] In any of the above embodiments of this application, the system boot firmware can determine the target duration to which the training latency of the target PCIe device corresponding to the link training failure needs to be adjusted in a variety of ways, without limitation.
[0078] In one possible implementation, in order to determine the appropriate training latency for each PCIe device as quickly as possible and reduce the number of processor system restarts, this application may pre-set multiple candidate latency durations. These multiple candidate latency durations can be set based on experience and are not specifically limited.
[0079] Accordingly, the system boot firmware can determine a target candidate latency duration that differs from the current training latency duration of the target PCIe device from a set of multiple candidate latency durations. This target candidate latency duration is then determined as the target duration to which the training latency duration of the target PCIe device needs to be adjusted.
[0080] For example, suppose the system boot firmware is configured with 8 candidate delay durations. These 8 candidate delay durations can be stored sequentially in 8-bit order according to their time length, as shown in the table below:
[0081]
[0082] For example, suppose the initial training latency for each PCIe device is set to 1 second.
[0083] When the processor system boots for the first time, the system boot firmware configures the training latency for each PCIe device stored in the control unit to be 1 second. Based on this, assuming that after the control unit initiates link training for each PCIe device, and PCIe device 1 experiences a link training failure, the system boot firmware can select a candidate latency other than 1 second from the table above as the target latency. For example, selecting 0.95 seconds will allow the system boot firmware to adjust the training latency for PCIe device 1 in the control unit to 0.95 seconds.
[0084] Based on this, after restarting the processor system, the control unit detects that the reset signal has been deactivated and can control PCIe device 1 to start link training after a delay of 0.95s. If the link training of PCIe device 1 still fails, a candidate latency duration that has not yet been configured for PCIe device 1 can be selected from the table above as the target duration. For example, the target duration can be 1.05s. This process is repeated until the link training of PCIe device 1 is successful.
[0085] In particular, these multiple candidate latency durations can also be sorted according to their time length. Based on this, the system boot firmware can determine the target candidate latency duration that is not yet used as the training latency duration corresponding to the target PCIe device and is ranked first, according to the time length order of the multiple candidate latency durations.
[0086] Using the table above as an example, to enable the system boot firmware to quickly determine which candidate latency durations in the table have not yet been used as the training latency durations corresponding to the target PCIe device, the system boot firmware can sequentially set the candidate latency durations in each bit to the training latency duration corresponding to the target PCIe device, from bit 7 to bit 0 (since the 1 second corresponding to bit 3 is the initially set training latency duration, the 1 second stored in bit 3 can be skipped). For example, after PCIe device 1 fails to train the link for the first time, the system boot firmware will adjust the latency training duration corresponding to PCIe device 1 in the control unit to 0 seconds; after PCIe device 1 fails to train the link for the second time, the system boot firmware will adjust the latency training duration corresponding to PCIe device 1 in the control unit to 0.85 seconds, and so on, until PCIe device 1 successfully trains the link.
[0087] In any of the above embodiments of this application, the system boot firmware can confirm the existence of a target PCIe device that has failed link training after detecting that the reset signal has been deactivated for a target duration. The target duration can be set by combining the training latency suitable for most types of PCIe devices and the duration required for link training, and is not specifically limited. For example, the target duration can be 3 seconds.
[0088] There are several possible implementations for the system boot firmware to determine whether the PCIe device's link training has been successful, and no restrictions are imposed on this.
[0089] For example, in one possible implementation, a control unit in the processor system can manage the device connections of the various sockets and ports of the processor system. For instance, the control unit could be an FPGA, which could determine whether a PCIe device is connected to any PCIe port or slot in the processor system. Based on this, the system boot firmware can use the control unit to confirm at least one PCIe device connected to the processor system. For example, the system boot firmware obtains the port identifier of each PCIe port connected to a PCIe device through the control unit, and uses the port identifier to indicate the PCIe device connected to that PCIe port.
[0090] Furthermore, since the CPU in the processor system can confirm whether each PCIe device has established a connection with the processor system, it can also determine whether the link training for each PCIe device has been successful. Based on this, the system boot firmware can use the CPU to confirm the information of PCIe devices that have successfully completed link training. Correspondingly, based on the information of PCIe devices that have successfully completed link training, the system boot firmware can determine whether the target PCIe device among the at least one PCIe device belongs to the category of target PCIe devices whose link training failed.
[0091] To facilitate understanding of the solution presented in this application, the following description uses UEFI as the system boot firmware and an FPGA in the processor system as the control component. Figure 3 This illustration shows another flowchart of the control method for PCIe device link training provided in this application. The method in this embodiment may include:
[0092] S301, after the processor system starts up, UEFI uses the FPGA to verify at least one PCIe device connected to the processor system.
[0093] S302, the FPGA confirms that the reset signal in the processor system has been deactivated through UEFI and determines the current time as the reference time.
[0094] It is understandable that, prior to step S302, a reset signal (such as a CPU-activated reset signal) can be generated and activated in the processor system. Under certain conditions, the processor system can deactivate the reset signal, and the specific process is not limited.
[0095] S303, according to the correspondence between at least one PCIe device and training delay stored in the FPGA, when the time from the current time to the reference time reaches the training delay time corresponding to the PCIe device, the FPGA instructs the PCIe device to start link training.
[0096] S304, UEFI confirms the PCIe device information that the link training was successful through the CPU in the processor system.
[0097] For example, if the PCIe device's link training is successful, then the connection between the PCIe device and the CPU is successfully established.
[0098] Understandably, UEFI can confirm the PCIe device information that the link has been successfully trained via the CPU after the target time for which the reset signal has been deactivated is detected.
[0099] The PCIe device information for which the link training was successful may include the device identifier of the PCIe device or the port identifier of the corresponding PCIe port, etc., without any specific restrictions.
[0100] S305, UEFI, based on the PCIe device information of successfully trained links, identifies at least one target PCIe device among at least one PCIe device whose link training has failed.
[0101] The target PCIe device belongs to at least one PCIe device determined in step S301.
[0102] S306, For each target PCIe device, UEFI determines the target duration to which the training latency of the target PCIe device needs to be adjusted.
[0103] This step can be found in the previous detailed introduction, and will not be repeated here.
[0104] S307, UEFI adjusts the training latency corresponding to the target PCIe device in the FPGA to the target latency, triggering a processor system restart to restart the link training for the PCIe device.
[0105] Understandably, after the UEFI restarts the processor system, it will re-trigger the execution of step S301 and subsequent related operations until the link training of each PCIe device is successful.
[0106] Understandably, if the system boot firmware confirms that there are no target PCIe devices that have failed to train the link, it means that the link training of each PCIe device has been successful, which means that the initialization phase is over and the processing flow of this application can be exited without restarting the processor system.
[0107] Specifically, considering the limited storage space of control components such as FPGAs, to reduce the excessive storage space occupied by storing the training latency times corresponding to each PCIe device, if the system boot firmware determines that there is no target PCIe device with failed link training, the system boot firmware can also obtain the training latency times corresponding to at least one PCIe device stored in the control component and store the training latency times corresponding to each PCIe device in a target memory outside the control component. At this time, the control component can delete the correspondence between each PCIe device and its training latency time.
[0108] The target memory can be non-volatile random access memory (NVRAM) or complementary metal-oxide-semiconductor (CMOS) memory in the processor system, etc., without any specific restrictions.
[0109] Accordingly, after storing the training latency durations corresponding to each PCIe device in the target memory outside the control unit, the training latency durations corresponding to each PCIe device can be obtained from the target memory upon the next processor system restart. Specifically, after detecting that the electronic device has been powered on, the system boot firmware can obtain the training latency durations corresponding to each PCIe device in the target memory and configure them in the control unit.
[0110] On the other hand, this application also provides an electronic device. For example... Figure 4 This diagram illustrates a component architecture of the electronic device provided in this application.
[0111] Depend on Figure 4 As can be seen, the electronic device includes: a processor system 401 and system boot firmware 402, the processor system including a control component 403.
[0112] The control unit 403 is used to control the PCIe device to start link training according to the stored correspondence between at least one PCIe device and training latency duration.
[0113] The system boot firmware 402 is used to, if it is confirmed that there is a target PCIe device with failed link training, determine the target duration to which the training latency of the target PCIe device needs to be adjusted, wherein the target PCIe device belongs to the at least one PCIe device; adjust the training latency of the control unit corresponding to the target PCIe device to the target duration, and trigger a restart of the processor system to restart the link training of the PCIe device.
[0114] like Figure 4 It is understood that the processor system may also include a Central Processing Unit (CPU) 404. Of course, the processor system may also include other components, without limitation.
[0115] It is understood that the electronic device may also include a display unit 405 and other components, without limitation.
[0116] In one possible implementation, the control unit is further configured to detect that the reset signal in the processor system has been deactivated and determine the current time as the reference time;
[0117] Accordingly, the control component is specifically configured to, according to the correspondence between at least one PCIe device and training latency stored in the control component, instruct the PCIe device to start link training when the time from the current time to the reference time reaches the training latency corresponding to the PCIe device.
[0118] For details on the specific functions of the control components and system guidance components, please refer to the relevant descriptions in the preceding embodiments, which will not be repeated here.
[0119] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. In addition, in the device embodiment drawings provided in this application, the connection relationship between modules indicates that they have a communication connection, which can be implemented as one or more communication buses or signal lines.
[0120] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware, or it can be implemented by special-purpose hardware including application-specific integrated circuits, special-purpose CPUs, special-purpose memory, special-purpose components, etc. Generally, any function performed by a computer program can be easily implemented by corresponding hardware, and the specific hardware structure used to implement the same function can also be diverse, such as analog circuits, digital circuits, or special-purpose circuits. However, for this application, software program implementation is more often the preferred implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium, such as a computer floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk, or optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, training equipment, or network device, etc.) to execute the methods described in the various embodiments of this application.
[0121] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, as a computer program product.
[0122] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from one website, computer, training device, or data center to another website, computer, training device, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a training device or data center that integrates one or more available media. The available media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid-state drives (SSDs)).
Claims
1. A control method for PCIe device link training, comprising: According to the correspondence between at least one PCIe device and training latency stored in the control unit, the control unit controls the PCIe device to start link training; If the system boot firmware confirms that there is a target PCIe device with a failed link training, it determines the target duration to which the training latency of the target PCIe device needs to be adjusted, and the target PCIe device belongs to the at least one PCIe device. The system boot firmware adjusts the training latency corresponding to the target PCIe device in the control component to the target latency, triggering a processor system restart to restart the link training for the PCIe device.
2. The control method for PCIe device link training according to claim 1 further includes: Upon detecting that the reset signal in the processor system has been deactivated, the control unit determines the current time as the reference time. The step of controlling the PCIe device to start link training according to the correspondence between at least one PCIe device and training latency stored in the control unit includes: According to the correspondence between at least one PCIe device and training latency stored in the control unit, when the time from the current time to the reference time reaches the training latency corresponding to the PCIe device, the control unit instructs the PCIe device to start link training.
3. The control method for PCIe device link training according to claim 1 further includes: In response to the processor system's first boot, the system boot firmware sends an initial configuration command to the control unit. The initial configuration command is used to instruct that the training latency duration corresponding to each PCIe device be set to the set initial duration. In response to the initial configuration command, the control unit sets and stores the training latency duration corresponding to each PCIe device as the initial duration.
4. The control method for PCIe device link training according to claim 1, wherein determining the target duration to which the training latency of the target PCIe device needs to be adjusted includes: From a set number of candidate delay durations, determine a target candidate delay duration that is different from the current training delay duration corresponding to the target PCIe device; The target candidate latency duration is determined as the target duration to which the training latency duration of the target PCIe device needs to be adjusted.
5. The control method for PCIe device link training according to claim 4, wherein determining a target candidate delay duration that is different from the current training delay duration corresponding to the target PCIe device from a set plurality of candidate delay durations includes: Based on the time length order of the multiple candidate latency durations, the target candidate latency duration that has not yet been used as the training latency duration corresponding to the target PCIe device and is the first in the order is determined.
6. The control method for PCIe device link training according to claim 1 further includes: The system boot firmware uses the control component to confirm at least one PCIe device connected to the processor system; The system boot firmware confirms the existence of a target PCIe device where link training has failed, including: The system boot firmware uses the CPU to confirm the PCIe device information that has been successfully trained via link verification; Based on the PCIe device information that has successfully trained the link, determine the target PCIe device among the at least one PCIe devices that has failed the link training.
7. The control method for PCIe device link training according to claim 1 further includes: If there is no target PCIe device where the link training failed, the system boot firmware obtains the training latency duration corresponding to each of at least one PCIe device stored in the control unit. The system boot firmware stores the training latency duration corresponding to each PCIe device in a target memory outside the control unit. After detecting that the electronic device is powered on, the system boot firmware obtains the training latency duration corresponding to each PCIe device in the target memory and configures it into the control unit.
8. The control method for PCIe device link training according to claim 1, wherein the control component is a field-programmable gate array in the processor system.
9. An electronic device, comprising: A processor system and system boot firmware, the processor system including control components; The control component is used to control the PCIe device to start link training according to the stored correspondence between at least one PCIe device and the training latency duration. The system boot firmware is used to, if it is confirmed that there is a target PCIe device whose link training has failed, determine the target duration to which the training latency of the target PCIe device needs to be adjusted, wherein the target PCIe device belongs to the at least one PCIe device; adjust the training latency of the control unit corresponding to the target PCIe device to the target duration, and trigger a restart of the processor system to restart the link training of the PCIe device.
10. The electronic device according to claim 9, wherein the control component is further configured to detect that a reset signal in the processor system has been deactivated and determine the current time as a reference time; Specifically, the control component is configured to, according to the correspondence between at least one PCIe device and training latency stored in the control component, instruct the PCIe device to start link training when the time from the current time to the reference time reaches the training latency corresponding to the PCIe device.