Switch board, control method of switch board, electronic equipment and storage medium

Abstract

The invention provides a switch board, a control method of the switch board, an electronic device and a storage medium, the switch board is connected with a main control board in the same device, the main control board is provided with a programmable logic chip, and the switch board comprises a first shift register, a second shift register and a third shift register, an input port of the first shift register is connected with a switch chip on the switch board, and an output port of the first shift register is connected with the programmable logic chip. And each switching chip is connected with a plurality of ROM (Read Only Memory) modules in the same equipment through a multiplexer. And an input port of the second shift register is connected with the programmable logic chip, and an output port of the second shift register is connected with the multiplexer.

Description

TECHNICAL FIELD

[0001] The present specification relates to the technical field of computer hardware systems, and particularly relates to a switching board, a control method of the switching board, an electronic device and a storage medium. BACKGROUND

[0002] The switching board inside the server is the core hub of the internal data communication of the server, and is responsible for coordinating the data exchange between various components (such as CPU, memory, storage, network interface) inside the server. The switching chip inside the switching board usually needs to switch different working modes according to the load demand.

[0003] The conventional solution is to configure a CPLD (Complex Programmable logic device) or MCU (Microcontroller Unit) and the like expensive control chip on the switching board to control the mode switching of the switching chip.

[0004] However, in order to only realize the mode switching of the switching chip, the CPLD or MCU is assembled on the switching board, which is high in cost and not suitable for enterprise mass production scenarios. SUMMARY

[0005] In order to overcome the problems in the related art, the present specification provides a switching board, a control method of the switching board, an electronic device and a storage medium.

[0006] According to a first aspect of an embodiment of the present specification, a switching board is provided, the switching board is connected with a main control board inside the same device, the main control board is installed with a programmable logic chip, and the switching board comprises:

[0007] A first shift register, an input port of the first shift register is connected with a switching chip on the switching board, and an output port is connected with the programmable logic chip; the first shift register is used for collecting an in-place signal of an output port of the switching chip, and transmitting the in-place signal to the programmable logic chip, so that the programmable logic chip determines the working mode of the switching chip according to the in-place signal;

[0008] At least one switching chip, each switching chip is connected with a plurality of ROM modules inside the same device through a multiplexer, the ROM module stores a firmware program, and in response to the chip selection signal sent by the programmable logic chip being received by the multiplexer, the line of the selected ROM module and the switching chip is communicated, so that the firmware program of the selected ROM module is loaded to the switching chip, so as to execute the corresponding working mode through the firmware program;

[0009] A second shift register, an input port of the second shift register is connected with the programmable logic chip, and an output port of the second shift register is connected with the multiplexer; the second shift register is used for sending the chip selection signal to the multiplexer.

[0010] According to a second aspect of the embodiments of the present specification, a control method of a switching board is provided, the method is applied to the programmable logic chip as described in the first aspect, and the method comprises:

[0011] receiving a firmware program loading instruction issued by a baseboard management controller (BMC);

[0012] converting the firmware program loading instruction into a chip selection signal and sending the chip selection signal to the second shift register;

[0013] The second shift register outputs the chip selection signal from the output port to the multiplexer connected with the second shift register, and the multiplexer is responsive to the chip selection signal to connect the selected ROM module with the line of the switching chip, so that the firmware program of the selected ROM module is loaded to the switching chip to execute the corresponding working mode through the firmware program.

[0014] According to a third aspect of the embodiments of the present specification, an electronic device is provided, the electronic device comprises the master control board and the switching board as described in the first aspect.

[0015] According to a fourth aspect of the embodiments of the present specification, a computer readable storage medium is provided, the computer readable storage medium stores a computer program, and the program is executed by a processor to implement the steps of the method as described in the second aspect.

[0016] The technical solutions provided by the embodiments of the present specification can include the following beneficial effects:

[0017] In the embodiments of the present specification, the first shift register is added to the switching board, the in-situ signal of the output port of the switching chip is collected by the first shift register, and the programmable logic chip on the master control board can monitor the working mode of each switching chip on the switching board according to the collection result. The second shift register is added to the switching board, the firmware program loading instruction sent by the programmable logic chip is received by the second shift register, and the multiplexer between different ROM modules and the line of the switching chip is controlled in the form of a chip selection signal, so as to control the signal on-off between the ROM module and the line of the switching chip through the multiplexer, thereby realizing the loading of the firmware program stored in the specified ROM module to the connected switching chip, and executing the corresponding working mode through the firmware program.

[0018] It can be seen that the scheme only needs to add a first shift register and a second shift register on the switching board to reuse the programmable logic chip on the main control board to realize the monitoring and control of the working mode of the switching chip. The cost of the shift register is lower than that of the CPLD or MCU, but the same function can also be realized, so the production cost of the switching board can be saved.

[0019] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present specification. BRIEF DESCRIPTION OF DRAWINGS

[0020] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present specification and serve to explain the principles of the present specification, together with the description.

[0021] Figure 1 is a schematic diagram of a switching board architecture according to an exemplary embodiment of the present specification.

[0022] Figure 2 is a schematic diagram of another switching board architecture according to an exemplary embodiment of the present specification.

[0023] Figure 3 is a flowchart of a control method of a switching board according to an exemplary embodiment of the present specification.

[0024] Figure 4 is a chip select schematic diagram of a serial-in-parallel-out shift register and a programmable logic chip according to an exemplary embodiment of the present specification.

[0025] Figure 5 is a schematic diagram of an electronic device architecture according to an exemplary embodiment of the present specification. DETAILED DESCRIPTION

[0026] The exemplary embodiments will be described in detail hereinafter with reference to the attached drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present specification. Instead, they are merely examples of apparatuses and methods consistent with some aspects of the present specification as detailed in the appended claims.

[0027] The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of this specification. As used in this specification, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "and / or", as used herein, refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0028] It should be understood that, although the terms first, second, third, etc. can be used herein to describe various information, these terms are not intended to denote a particular order of the information. These terms are used merely to distinguish one type of information from another. For example, a first information can be termed a second information, and similarly, a second information can be termed a first information, without departing from the scope of this specification. Depending on the context, the word "if' as used herein can be interpreted to mean "when" or "in response to determining" or "in response to a determination".

[0029] The switchboard inside the server is the core hub of the internal data communication of the server, responsible for coordinating the data exchange between the internal components of the server (such as CPU, memory, storage, network interface). The switch chip inside the switchboard usually needs to switch different working modes according to the load demand.

[0030] The conventional solution is to configure a CPLD (Complex Programmable logic device) or MCU (Microcontroller Unit) and other expensive control chips on the switchboard to control the mode switching of the switch chip.

[0031] However, in order to only realize the mode switching of the switch chip, the CPLD or MCU is assembled on the switchboard, which is high in cost and not suitable for enterprise mass production scenarios.

[0032] In view of the above technical problems, the present specification provides a switchboard to reduce the cost of developing the working mode switching function of the switchboard.

[0033] Figure 1 is a schematic diagram of the architecture of a switchboard according to an exemplary embodiment of the present specification. As shown in Figure 1 The switchboard 12 is connected to the main control board 11 inside the same device. The programmable logic chip 111 is installed on the main control board 11.

[0034] Figure 1 Two switch chips are configured on the switchboard in the main control board 11, which are switch chip 122 and switch chip 123. Figure 1This is merely an illustrative example. Those skilled in the art can easily implement configurations of more than two switching chips or only one switching chip on the switching board 12. This solution is applicable to both situations and does not impose any restrictions on the number of switching chips on the switching board 12.

[0035] The operating modes of a switching chip can include, but are not limited to, serial mode, parallel mode, and hybrid mode. It should be noted that the operating mode of the switching chip addressed in this solution specifically refers to the data transmission method of the switching chip. For example, the switching chip may transmit data through a single channel in serial mode, through multiple channels in parallel mode, or through a mixture of channels in hybrid mode.

[0036] Each switching chip is connected to several ROM modules within the same device via a multiplexer. These ROM modules can specifically be read-only memories. For example, switching chip 122 is connected to ROM1 and ROM2 via multiplexer 125, while switching chip 123 is connected to ROM1 and ROM2 via multiplexer 126. The multiplexer can load firmware programs stored on designated ROM modules into the switching chip by controlling the on / off state of the SPI (Serial Peripheral Interface) signal between the ROM modules and the switching chip.

[0037] The ROM module stores firmware programs. When these firmware programs are loaded into the connected switch chip, the corresponding operating mode can be executed through the firmware programs. For example, different ROM modules store different firmware programs. Figure 1 ROM1 stores firmware for switching between serial and parallel modes, while ROM2 stores firmware for switching between parallel and non-serial modes. Each switching chip has its own ROM module for storing the firmware required to switch its operating mode. For example, suppose ROM1 stores firmware for switching between serial and parallel modes, and ROM2 stores firmware for switching between parallel and non-serial modes. When the firmware in ROM1 is loaded into the switching chip, the switching chip switches from its current operating mode to serial mode. When the firmware in ROM2 is loaded into the switching chip, the switching chip switches from its current operating mode to parallel mode.

[0038] In order to realize the current working mode of the device monitoring switch chip, the scheme adds a first shift register 121 in the conventional switch board 12. The input port of the first shift register 121 is connected with the switch chip 122 on the switch board 12, and the output port is connected with the programmable logic chip 111. The first shift register 121 is used to collect the in-place signals of the output ports of the switch chip, and transmit the in-place signals to the programmable logic chip 111, so that the programmable logic chip 111 determines the working mode of the switch chip according to the in-place signals. For example, Figure 1 The output port 1 and the output port 3 in the output port 3 are bound with the switch chip 122, and the output port 7 and the output port 9 are bound with the switch chip 123. The input port of the first shift register 121 is connected with the output ports of the switch chip 122 and the switch chip 123, and can be used to collect the in-place signals of the output ports of the two switch chips.

[0039] The type of these output ports can be MCIO (MiniCoolEdge O, multi-channel input / output) port, which is used to connect with PCIE (PCI Express, Peripheral Component Interconnect Express) card.

[0040] The MCIO port can generate in-place signals, which are high level by default without the cable of the PCIE card, and low level with the cable of the PCIE card. The scheme can collect the in-place signals of the MCIO port by using the first shift register 121, and determine whether the MCIO port of each switch chip has a cable according to the high and low levels of the levels, so as to determine the current working mode of the switch chip according to the corresponding relationship between the wiring rules of the cable and the working mode of the switch chip.

[0041] For example, it is assumed that the first shift register 121 records the high level of the MCIO port as 1 and the low level as 0. It is assumed that in the current device working scene, as shown in Figure 2 MCIO port 3, MCIO port 7 and MCIO port 9 are all without cable, and MCIO port 1 has a cable. Then, the data of the in-place signals fed back to the first shift register 121 can be represented as 1110, and then the first shift register 121 can send the data to the programmable logic chip 111, and the programmable logic chip 111 can determine the wiring state of the MCIO port of each switch chip according to the data, so as to determine the working mode of the switch chip according to the wiring rules of the cable. For example, according to 1110, it can be judged that only one MCIO port of the switch chip 122 is in the wiring state, as shown in Figure 2 It is connected with a PCIE card, so it can be judged that the current working mode of the switch chip 122 is serial mode, and all MCIO ports of the switch chip 123 are not connected with the cable, so it is in the non-working state.

[0042] In addition Figure 1 The switching chip 122 and the switching chip 123 are shown. The switching board 12 can also have more switching chips, and the first shift register 121 can also collect the in-place signals of the MCIO ports of the more switching chips in a cascaded manner, so as to send the in-place signals of the MCIO ports of the switching chips to the programmable logic chip 111, so that the programmable logic chip 111 can identify the working mode of each switching chip according to the in-place signals of the MCIO ports of each switching chip.

[0043] In the preferred hardware architecture design, as Figure 2 shown, the first shift register 121 can be a shift-in shift-out register 221, and the input port of the shift-in shift-out register 221 can be a parallel input pin, and the output port can be a serial output pin. Each parallel input pin can be connected with the MCIO port to collect the in-place signal on the MCIO port.

[0044] It can be seen that, by adding the first shift register 121 on the switching board 12, the in-place signal of the output port of the switching chip 122 is monitored by the first shift register 121, and the monitoring result is transmitted to the programmable logic chip 111 on the main control board, so as to realize the monitoring of the working mode of the switching chip.

[0045] Finally, the main control board can also be deployed with a BMC, and the programmable logic chip 111 can be implemented by a CPLD 212. Figure 2 The programmable logic chip 111 can upload the identification result to the BMC 211 (Baseboard Management Controller, bottom plate management controller), and then the BMC uploads the identification result to the user's out-of-band management system for the user to view, so that the user can remotely monitor the working mode of the switching chip on the device.

[0046] In order to realize that the device can manage the working mode of the switching chip. Continue to refer to Figure 1 , the second shift register 124 is designed in the switching board 12. The input port of the second shift register 124 is connected with the programmable logic chip 111, and the output port is connected with the multiplexer, and the second shift register 124 is used to send the chip selection signal to the multiplexer.

[0047] Chip select signal (also known as "CS signal") is a control signal commonly used in digital circuits to select a specific device for communication. The pin of the multiplexer can be connected to the output pin of the second shift register, and the chip select signal on the pin of the multiplexer can be represented by low active or high active, that is, in the case where the level of a certain pin of the multiplexer connected to the second shift register is pulled low, it indicates that the ROM module corresponding to the pin is selected, and by connecting the exchange chip to the circuit of the ROM module, the firmware program stored in the ROM module is loaded into the corresponding exchange chip. For example, assuming that the output ports of the second shift register are Q0 to Q7, each output port is connected to a pin of a different multiplexer. For example, the chip select signals output by Q0 to Q7 are 11001111, indicating that Q3 and Q4 send the specified chip select signal, and the ROM modules corresponding to the Q3 and Q4 pins are selected. The firmware programs on the two ROM modules can be loaded into the corresponding exchange chips in response to the pins of the multiplexers corresponding to the two ROM modules being pulled low or high, so as to execute the corresponding working mode through the firmware programs.

[0048] As shown in Figure 2 The second shift register 124 can be a serial-in-parallel-out shift register 224, the input port of the serial-in-parallel-out shift register 224 can be a serial input pin, and the output port can be a parallel output pin.

[0049] In an exemplary application scenario, assuming that the working mode of the exchange chip of the exchange board after power-on initialization is the serial mode by default, and the user wants to switch the current working mode to the parallel mode. On the basis of Figure 1 The BMC can also be deployed on the host board.

[0050] The user can remotely control the BMC on the host board through the out-of-band management system to issue a firmware program loading instruction to the programmable logic chip 111, and the programmable logic chip 111 can generate a chip select signal corresponding to the firmware program loading instruction and send the chip select signal to the second shift register 124, so that the second shift register 124 outputs the chip select signal from the parallel output port. The exchange chip loads the firmware program stored in the specified ROM module. For example, a signal of 0 is regarded as a specified chip select signal, which is used to instruct the multiplexer to load the firmware program on the ROM module corresponding to the pin receiving the chip select signal into the exchange chip.

[0051] In the case where the exchange board 12 is configured with multiple exchange chips, the multiplexers connected to different exchange chips can all receive the chip select signal. Any exchange chip loads the firmware program stored in the ROM module of the exchange chip into the exchange chip in response to the ROM module being selected.

[0052] It can be seen that, by adding the second shift register 124 on the switching board 12, the programmable logic chip 111 on the main control board 11 can be reused to manage the working modes of different switching chips on the switching board 12.

[0053] In an embodiment, one parallel output pin in the serial-in-parallel-out shift register only controls the chip select pin of one multiplexer.

[0054] In the embodiment, the working modes of the switching chips can be individually controlled through the respective parallel output pins, so that the control strategies of the working modes of different switching chips do not affect each other.

[0055] As shown in Figure 2 The present specification provides an exemplary switching board 22 connected with a main control board 21 inside the same device, and the main control board 21 is installed with a CPLD 212. The switching board 21 comprises:

[0056] a serial-in-parallel-out shift register 221, an input port of the serial-in-parallel-out shift register 221 is connected with the MCIO port of the switching chip 222 and the switching chip 223 and other switching chips on the switching board 22, and an output port is connected with the CPLD 212. The serial-in-parallel-out shift register 221 is used to collect the in-place signals of the MCIO ports of the connected switching chips, and transmit the in-place signals to the CPLD 212, so that the CPLD 212 determines the working mode of the switching chip according to the in-place signals.

[0057] The switching chip 222 is connected with the ROM1 and the ROM2 through the multiplexer 225, and the switching chip 223 is connected with the ROM1 and the ROM2 through the multiplexer 226.

[0058] a serial-in-parallel-out shift register 224, an input port of the serial-in-parallel-out shift register 224 is connected with the CPLD 212, and output ports are respectively connected with the multiplexer 225 and the multiplexer 226.

[0059] The main control board 21 can also be deployed with a BMC 211, which is used to upload the working mode monitored by the CPLD 212 to the out-of-band management system for the user to view, and receive the mode switching instruction issued by the user to the CPLD 212 through the BMC 211 to switch the working mode of the switching chip on the switching board 22.

[0060] Figure 3 is a flowchart of a control method of a switching board according to an exemplary embodiment of the present specification. As shown in Figure 3 The control method can be applied to Figure 1 the programmable logic chip 111, comprising steps 301-302:

[0061] Step 301: receiving a firmware program loading instruction issued by a baseboard management controller (BMC).

[0062] Step 302: converting the firmware program loading instruction into a chip select signal and sending the chip select signal to a second shift register.

[0063] The second shift register outputs the chip select signal from an output port to a multiplexer connected to the second shift register. The multiplexer is responsive to receiving the chip select signal to communicate the ROM module selected by the chip select signal with a line of the switching chip, so that the firmware program of the selected ROM module is loaded to the switching chip to execute a corresponding working mode through the firmware program.

[0064] In the application scenario, a user can manage the working modes of each switching chip on the switching board through an out-of-band management system. For example, assuming that the user wants to switch the current serial mode of the switching chip 122 to a parallel mode, the user can control the BMC to issue a firmware program loading instruction for switching the specified working mode of the specified switching chip through the out-of-band management system. For example, a firmware program loading instruction for instructing the switching chip 122 to load the firmware program stored in the ROM1 can be issued separately, that is, the switching chip 122 is notified to switch the current working mode to a serial mode. A firmware program loading instruction for instructing the switching chip 123 to load the firmware program stored in the ROM2 can be issued separately, that is, the switching chip 123 is notified to switch the current working mode to a parallel mode. A firmware program loading instruction for instructing the switching chip 122 to load the firmware program stored in the ROM1 and the switching chip 123 to load the firmware program stored in the ROM2 can be issued simultaneously, that is, based on one firmware program loading instruction, multiple switching chips are controlled to switch the current working mode to a specified working mode.

[0065] It can be seen that, by adding a second shift register on the switching board, the programmable logic chip on the main control board can be reused to manage the working modes of different switching chips on the switching board.

[0066] The BMC sends the firmware program loading instruction issued by the user to the programmable logic chip. The programmable logic chip can convert the firmware program loading instruction into a chip select signal and send the chip select signal to the second shift register. The programmable logic chip can send the chip select signal to the second shift register in a serial data format.

[0067] For example, as shown in FIG. 6, the BMC sends the firmware program loading instruction to the programmable logic chip 601. Figure 4As shown, assuming that the serial-in-parallel-out shift register has 8 parallel output pins Q0-Q7, it can control 8 IOs simultaneously, and each chip select is connected to at least one multiplexer. For example, if the serial data sent by the programmable logic chip is 0xCF, the chip select signal received by the serial-in-parallel-out shift register is 11001111, and assuming that the chip select signal corresponding to the two 00s corresponds to the ROM1 of the switching chip 122 and the switching chip 123, it indicates that the level of the specified chip select pin on the multiplexer 125 and the multiplexer 126 changes to low, and the firmware program of the ROM1 corresponding to the chip select pin is loaded into the switching chip. Assuming that the chip select signal corresponding to the two 00s corresponds to the ROM1 of the switching chip 122 and the ROM2 of the switching chip 123, it indicates that the level of the specified chip select pin on the multiplexer 125 changes to low, and the firmware program of the corresponding ROM1 is loaded into the switching chip 122. The level of the specified chip select pin on the multiplexer 126 changes to low, and the firmware program of the corresponding ROM2 is loaded into the switching chip 123.

[0068] In an embodiment, when the firmware program loading instruction is converted into a chip select signal and sent to the second shift register, if the firmware program loading instruction is a new instruction, the firmware program loading instruction is converted into a chip select signal and then sent to the second shift register. After the chip select signal is sent, the current level of the output port of the second shift register remains unchanged.

[0069] For example, the programmable logic chip can determine whether the firmware program loading instruction input into the module is a new instruction every 1 ms. If it is a new instruction, the flag bit is changed (the change of the flag bit indicates that the data has changed). The firmware program loading instruction can be issued by the BMC or determined by the programmable logic chip according to the monitored cable connection status of the switching chip.

[0070] The programmable logic chip can flip the CP signal (i.e., the clock signal) of the downstream port every 1 us.

[0071] The programmable logic chip counts with the CP signal, and the count value can be increased by 1 every other CP signal high level until it counts to 8. If it is found that the flag bit is high, it indicates that the current data is not new data, and the count value can be cleared to zero.

[0072] When the CP signal changes, the level of the output of the parallel output pin is set to 0 when the MR reset signal is low. The programmable logic chip can send 1 bit of data to the serial DSA signal line at the rising edge of each CP signal until 8 bits of data are completely sent.

[0073] When the CP signal does not change, the programmable logic chip can maintain the high and low levels of the output port of the second shift register, so as to achieve the purpose of data latching, thereby reducing the interference of the always-changing CP signal to other sensitive signals of the system.

[0074] Suppose that the default firmware program loading instruction is 0x00, and the new firmware program loading instruction issued by the BMC to the programmable logic chip is 0xCF. The working process of the programmable logic chip is as follows: first, it judges that the data is new data, and sets the flag bit to 0. Every 1us, the programmable logic chip flips the CP signal once, and at the same time, one bit of the serial data is sent to the DSA signal line. Therefore, at the first CP signal high level, the data on the output port of the second shift register is 00000001; at the second CP signal high level, the data on the output port is 00000011; at the third CP signal high level, the data on the output port is 00000110; at the fourth CP signal high level, the data on the output port is 00001100; at the fifth CP signal high level, the data on the output port is 00011001; at the sixth CP signal high level, the data on the output port is 00110011; at the seventh CP signal high level, the data on the output port is 01100111; and at the eighth CP signal high level, the data on the output port is 11001111. At this time, the count value reaches 8, and the programmable logic chip can pull down the CP signal, and at the same time, set the flag bit to 1, indicating that no new data is added. For the second shift register, since the CP signal is always low, the data on the output port will always be maintained as 11001111. For the switching board, the CS signals of the two multiplexers are set to 0, so that the firmware is selected to the corresponding ROM1, and the two switching chips work in the parallel mode.

[0075] In an embodiment, the programmable logic chip can also receive the in-place data sent by the first shift register, and determine the in-place state of the output port corresponding to each bit in the in-place data according to the number on each bit. The number on each bit is determined according to the high and low levels of the output port corresponding to the bit collected by the first shift register.

[0076] For example, assuming that the in-situ data is 1110, the first bit corresponds to output port 9, the second bit corresponds to output port 7, the third bit corresponds to output port 3, and the fourth bit corresponds to output port 1. It can be determined that the bit is 1, and the output port corresponding to the bit has no cable, and the bit is 0, and the output port corresponding to the bit has a cable. According to the number of each bit in the in-situ data, it can be determined that output port 3, output port 7 and output port 9 have no cable, and output port 1 has a cable. Output port 1 and output port 3 are bound to switch chip 122, and output port 7 and output port 9 are bound to switch chip 123. The working mode of the switch chip can be determined according to the correspondence between the cable rule and the working mode of the switch chip.

[0077] In the embodiment, by adding a first shift register on the switching board, the in-situ signal of the output port of the switch chip is monitored through the first shift register, and the monitoring result is uploaded to the programmable logic chip on the main control board, thereby realizing the monitoring of the working mode of the switch chip.

[0078] As shown in Figure 5 The present specification also provides an electronic device 5, which comprises a main control board 51 and a switching board 52. The internal architecture of the main control board 51 can refer to the design of the main control board 11 in Figure 1 , and the internal architecture of the switching board 52 can refer to the design of the switching board 12 in Figure 1 . The present specification will not be repeated here.

[0079] The present specification also provides a computer readable storage medium, which stores a computer program. The program is executed by a processor to implement the steps of the control method of the switching board provided in the present application.

[0080] Specifically, the computer readable medium suitable for storing computer program instructions and data includes all forms of non-volatile memory, media and memory devices, such as semiconductor memory devices (e.g. EPROM, EEPROM and flash memory devices), magnetic disks (e.g. internal hard disks or removable disks), magneto-optical disks, and CD ROM and DVD-ROM disks.

Claims

1. A switching board connected to a main control board inside the same device, the main control board having a programmable logic chip mounted thereon, characterized in that, The switching board comprises: A first shift register, an input port of the first shift register is connected with a switching chip on the switching board, and an output port is connected with the programmable logic chip; the first shift register is used for collecting a bit signal of an output port of the switching chip and transmitting the bit signal to the programmable logic chip, so that the programmable logic chip determines a working mode of the switching chip according to the bit signal; At least one switching chip, each switching chip is connected with several ROM modules in the same device through a multiplexer, the ROM modules store a firmware program, and in response to a chip selection signal received by the multiplexer and sent by the programmable logic chip, the ROM module selected by the chip selection signal is connected with a line of the switching chip, so that the firmware program of the selected ROM module is loaded to the switching chip to execute a corresponding working mode through the firmware program; A second shift register, an input port of the second shift register is connected with the programmable logic chip, and an output port is connected with the multiplexer; the second shift register is used for sending the chip selection signal to the multiplexer.

2. The switching board according to claim 1, wherein: The first shift register is a parallel-in-serial-out shift register, An input port of the parallel-in-serial-out shift register is a parallel input pin, and an output port is a serial output pin.

3. The switching board according to claim 1, wherein: The second shift register is a serial-in-parallel-out shift register, An input port of the serial-in-parallel-out shift register is a serial input pin, and an output port is a parallel output pin.

4. The switching board according to claim 3, wherein: One parallel output pin in the serial-in-parallel-out shift register controls a chip selection pin of only one multiplexer.

5. A control method of a switching board, characterized by, The method is applied to the programmable logic chip as claimed in claim 1, and the method comprises: Receiving a firmware program loading instruction issued by a baseboard management controller (BMC); Converting the firmware program loading instruction into a chip selection signal and then sending the chip selection signal to the second shift register; Wherein, the second shift register outputs the chip selection signal from an output port to a multiplexer connected therewith, and the multiplexer responds to the chip selection signal to connect a ROM module selected by the chip selection signal with a line of the switching chip, so that the firmware program of the selected ROM module is loaded to the switching chip to execute a corresponding working mode through the firmware program.

6. The method of claim 5, wherein, The method further comprises: Receiving bit data sent by the first shift register and determining a bit state of an output port corresponding to each bit in the bit data according to a number of the bit; wherein the number of the bit is determined according to a level of an output port corresponding to the bit collected by the first shift register; Determining a working mode of a switching chip bound with the output port according to the bit state.

7. The method of claim 5, wherein, The conversion of the firmware program loading instruction into the chip selection signal and then the sending of the chip selection signal to the second shift register comprises: In the case that the firmware program loading instruction is a new instruction, the firmware program loading instruction is converted into a chip selection signal and then sent to the second shift register; After the chip selection signal is sent, the current level of the output port of the second shift register is kept unchanged.

8. The method of claim 5, wherein, The working mode includes a serial mode, a parallel mode or a mixed mode.

9. An electronic device comprising the master board and the switch board according to any one of claims 1-4.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that, The program, when executed by a processor, implements the steps of the method according to any one of claims 5-8.

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